2010 Microchip Technology Inc. DS39622L-page 1
PIC18F2XXX/4XXX FAMILY
1.0 DEVICE OVERVIEW
This docume nt includes the program ming sp ecifications
for the following devices :
2.0 PROGRAMMING OVERVIEW
PIC18F2XXX/4XXX family devices can be
programmed using either the high-voltage In-Circuit
Serial Programming™ (ICSP™) method or the
low-voltage ICSP method. Both methods can be done
with the device in the user’s system. The low-voltage
ICSP method is slightly different than the high-voltage
method and these differences are noted where
applicable.
This programming specification applies to the
PIC18F2XXX/4XXX family devices in all package
types.
2.1 Hardware Requirements
In High-Voltage ICSP mode, PIC18F2XXX/4XXX
f am il y devices require two programmable power sup-
plies: one for VDD and one for MCLR/VPP/RE3. Both
supplies should have a minimum resolution of 0.25V.
Refer to Section 6.0 “AC/DC Character istics Timing
Requirements for Program/Verify Test Mode” for
additional hardware parameters.
2.1.1 LOW-VOLTAGE ICSP
PROGRAMMING
In Low-Voltage ICSP mode, PIC18F2XXX/4XXX
family devices can be programmed using a VDD
source in the operating range. The MCLR/VPP/RE3
does not have to be brought to a different voltage, but
can instead be left at the normal operating voltage.
Refer to Section 6.0 “AC/DC Characteristics Timing
Requirements for Program/Verify Test Mode” for
additional hardware parameters.
2.2 Pin Diagrams
The pin diagrams for the PIC18F2XXX/4XXX family
are shown in Figure 2-1 and Figure 2-2.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F2XXX/4XXX FAMILY
• PIC18F2221 • PIC18F2580 • PIC18F4480
• PIC18F2321 • PIC18F2585 • PIC18F4510
• PIC18F2410 • PIC18F2610 • PIC18F4515
• PIC18F2420 • PIC18F2620 • PIC18F4520
• PIC18F2423 • PIC18F2680 • PIC18F4523
• PIC18F2450 • PIC18F2682 • PIC18F4525
• PIC18F2455 • PIC18F2685 • PIC18F4550
• PIC18F2458 • PIC18F4221 • PIC18F4553
• PIC18F2480 • PIC18F4321 • PIC18F4580
• PIC18F2510 • PIC18F4410 • PIC18F4585
• PIC18F2515 • PIC18F4420 • PIC18F4610
• PIC18F2520 • PIC18F4423 • PIC18F4620
• PIC18F2523 • PIC18F4450 • PIC18F4680
• PIC18F2525 • PIC18F4455 • PIC18F4682
• PIC18F2550 • PIC18F4458 • PIC18F4685
•PIC18F2553
Pin Name During Programming
Pin Name Pin Type Pin Description
MCLR/VPP/RE3 VPP P Programming Enable
VDD(2) VDD P Power Supply
VSS(2) VSS P Ground
RB5 PGM I Low-Voltage ICSP™ Input when LVP Configuration bit equals ‘1’(1)
RB6 PGC I Serial Clock
RB7 PGD I/O Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: See Figure 5-1 for more information.
2: All power supply (VDD) and ground (VSS) pins must be connected.
Flash Microcontroller Programming Specification
PIC18F2XXX/4XXX FAMILY
DS39622L-page 2 2010 Microchip Technology Inc.
FIGURE 2-1: PIC18F2XXX/4 XXX FAMILY PIN DIAGRAMS
40-Pin PDIP
28-Pin SPDIP, PDIP, SOIC and SSOP
The following devices are included in
28-pin SPDIP, PDIP and SOIC parts:
• PIC18F2221 • PIC18F2523
• PIC18F2321 • PIC18F2525
• PIC18F2410 • PIC18F2550
• PIC18F2420 • PIC18F2553
• PIC18F2423 • PIC18F2580
• PIC18F2450 • PIC18F2585
• PIC18F2455 • PIC18F2610
• PIC18F2458 • PIC18F2620
• PIC18F2480 • PIC18F2680
• PIC18F2510 • PIC18F2682
• PIC18F2515 • PIC18F2685
• PIC18F2520
The following devices are included in
28-pin SSOP parts:
• PIC18F2221 • PIC18F2321
The following devices are included in
40-pin PDIP parts:
• PIC18F4221 • PIC18F4523
• PIC18F4321 • PIC18F4525
• PIC18F4410 • PIC18F4550
• PIC18F4420 • PIC18F4553
• PIC18F4423 • PIC18F4580
• PIC18F4450 • PIC18F4585
• PIC18F4455 • PIC18F4610
• PIC18F4458 • PIC18F4620
• PIC18F4480 • PIC18F4680
• PIC18F4510 • PIC18F4682
• PIC18F4515 • PIC18F4685
• PIC18F4520
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
RA4
RA5
VSS
OSC1
OSC2
RC0
RC1
RC2
RC3
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC6
RC5
RC4
PIC18F2XXX
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RD7
RD6
RD5
RD4
RC7
RC6
RC5
RC4
RD3
RD2
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RE0
RE1
RE2
VDD
VSS
OSC1
OSC2
RC0
RC1
RC2
RC3
RD0
RD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F4XXX
28-Pin QFN
1011
2
3
6
1
18
19
20
21
22
121314 15
8
716
17
232425262728
9
PIC18F2XXX
RC0
5
4
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC6
RC5
RC4
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
RA4
RA5
VSS
OSC1
OSC2
RC1
RC2
RC3
The following devices are included in
28-pin QFN parts:
• PIC18F2221 • PIC18F2510
• PIC18F2321 • PIC18F2520
• PIC18F2410 • PIC18F2523
• PIC18F2420 • PIC18F2580
• PIC18F2423 • PIC18F2682
• PIC18F2450 • PIC18F2685
• PIC18F2480
2010 Microchip Technology Inc. DS39622L-page 3
PIC18F2XXX/4XXX FAMILY
FIGURE 2-2: PIC18F2XXX/4 XXX FAMILY PIN DIAGRAMS
44-Pin TQFP
44-Pin QFN
The following devices are included in
40-pin TQFP parts:
• PIC18F4221 • PIC18F4523
• PIC18F4321 • PIC18F4525
• PIC18F4410 • PIC18F4550
• PIC18F4420 • PIC18F4553
• PIC18F4423 • PIC18F4580
• PIC18F4450 • PIC18F4585
• PIC18F4455 • PIC18F4610
• PIC18F4458 • PIC18F4620
• PIC18F4480 • PIC18F4680
• PIC18F4510 • PIC18F4682
• PIC18F4520 • PIC18F4685
• PIC18F4515
The following devices are included in
44-pin QFN parts:
• PIC18F4221 • PIC18F4523
• PIC18F4321 • PIC18F4525
• PIC18F4410 • PIC18F4550
• PIC18F4420 • PIC18F4553
• PIC18F4423 • PIC18F4580
• PIC18F4450 • PIC18F4585
• PIC18F4455 • PIC18F4610
• PIC18F4458 • PIC18F4620
• PIC18F4480 • PIC18F4680
• PIC18F4510 • PIC18F4682
• PIC18F4520 • PIC18F4685
• PIC18F4515
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F4XXX
37
RA3
RA2
RA1
RA0
MCLR/VPP/RE3
RB7/PGD
RB6/PGC
RB5/PGM
NC RC6
D+/VP
D-/VM
RD3
RD2
RD1
RD0
VUSB
RC2
RC1
RC0
OSC2
OSC1
VSS
AVDD
RA5
RA4
RC7
RD4
RD5
RD6
VSS
VDD
RB0
RB1
RB2
RB3
RD7 5
4AVSS
VDD
AVDD
RB4
RE0
RE1
RE2
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F4XXX
37
RA3
RA2
RA1
RA0
MCLR/VPP/RE3
NC(1)/ICPGC
RB7/PGD
RB6/PGC
RB5/PGM
RB4
NC(1)/ICPGD RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC(1)/ICPORTS
NC(1)/ICVPP
RC0
OSC2
OSC1
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
VSS
VDD
RB0
RB1
RB2
RB3
RD7 5
4
Note 1: These pins are NC (No Connect) for all devices
listed above with the exception of the PIC18F4450,
PIC18F4455, PIC18F4458 and the PIC18F4553
device s (see Section 2.8 “De d icated ICSP/ I CD
Port (44-Pin TQFP Only)” fo r mo re i nf ormation on
programming these pins in these devices).
PIC18F2XXX/4XXX FAMILY
DS39622L-page 4 2010 Microchip Technology Inc.
2.3 Memory Map s
For PIC18FX6X0 devices, the code memory space
extends from 0000h to 0FFFFh (64 Kbytes) in four
16-Kbyte blocks. For PIC18FX5X5 devices, the code
memory space extends from 0000h to 0BFFFFh
(48 Kbytes) in three 16-Kbyte blocks. Addresses,
0000h through 07FFh, however, define a “Boot Block”
region that is treated separately from Block 0. All of
these blocks define code protection boundaries within
the code memory space.
The size of the Boot Block in PIC18F2585/2680/4585/
4680 devices can be configured as 1, 2 or 4K words
(see Figure 2-3). This is done th roug h th e BBSI Z<1:0>
bits in the Configuration register, CONFIG4L. It is
important to note that increasing the size of the Boot
Block decreases the size of Block 0.
TABLE 2-2: IMPLEMENTATION OF CODE
MEMORY
FIGURE 2-3: MEM ORY MAP AND THE CODE MEMORY S P ACE FOR PIC18FX5X5/X6X0 DEVICES
Device Code Memory Size (Bytes)
PIC18F2515
000000h-00BFFFh (48K)
PIC18F2525
PIC18F2585
PIC18F4515
PIC18F4525
PIC18F4585
PIC18F2610
000000h-00FFFFh (64K)
PIC18F2620
PIC18F2680
PIC18F4610
PIC18F4620
PIC18F4680
000000h
200000h
3FFFFFh
01FFFFh
Note: Sizes of memory areas are not to sca le.
* Boot Block size is determined by the BBSIZ<1:0> bits in the CONFIG4L register.
Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
MEMORY SIZE/DEVICE Address
Range
64 Kbytes
(PIC18FX6X0)
BBSIZ<1:0>
11/10 01 00
Boot
Boot
000000h
0007FFh
Block 0
000800h
000FFFh
Block 0
001000h
001FFFh
Block 0
002000h
003FFFh
Block 1
004000h
00FFFFh
Unimplemented
Reads all ‘0’s 01FFFFh
Block*
Block*
11/10 01 00
48 Kbytes
(PIC18FX5X5)
Boot
Block*
Boot
Block* Boot
Block*
Boot
Block*
Block 0
Block 0
Block 0
Unimplemented
Reads all ‘0’s
Block 2
Block 3
Block 2
Block 1
007FFFh
008000h
00BFFFh
00C000h
2010 Microchip Technology Inc. DS39622L-page 5
PIC18F2XXX/4XXX FAMILY
For PIC18F2685/4685 devices, the code memory
space extends from 0000h to 017FFFh (96 Kbytes) in
five 16-Kbyte blocks. For PIC18F2682/4682 devices,
the code memory space extends from 0000h to
0013FFFh (80 Kbytes) in four 16-Kbyte blocks.
Addresses, 0000h through 0FFFh, however, define a
“Boot Block” region that is treated separately from
Block 0. All of these blocks define code protection
boundaries within the code memory space.
The size of the Boot Block in PIC18F2685/4685 and
PIC18F2 682/4682 dev ices can be c onfigured as 1, 2 or
4K words (see Figure 2-4 ). This is done through the
BBSIZ<2:1> bits in the Configuration register,
CONFIG4L. It is important to note that increasing the
size of th e Boot Block decrease s the size o f Bloc k 0.
TABLE 2-3: IMPLEMENTATION OF CODE
MEMORY
FIGURE 2-4: MEMORY MAP AND THE CODE MEMORY SPACE
FOR PIC18F2685/4685 AND PIC18F2682/4682 DEVICES
Device Code Memory Size (Bytes)
PIC18F2682 000000h-013FFFh (80K)
PIC18F4682
PIC18F2685 000000h-017FFFh (96K)
PIC18F4685
000000h
200000h
3FFFFFh
01FFFFh
Note: Sizes of memory areas are not to scale.
* Boot Block size is determined by the BBSIZ<1:2> bits in the CONFIG4L register.
Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
MEMORY SIZE/DE VI CE Address
Range
96 Kbytes
(PIC18F2685/4685)
BBSIZ1:BBSIZ2
11/10 01 00
Boot
Boot
000000h
0007FFh
Block 0
000800h
000FFFh
Block 0
001000h
001FFFh
Block 0
002000h
003FFFh
Block 1 004000h
017FFFh
Unimplemented
Reads all ‘0’s 01FFFFh
Block*
Block*
11/10 01 00
80 Kbytes
(PIC18F2682/4682)
Boot
Block*
Boot
Block* Boot
Block*
Boot
Block*
Block 0
Block 0
Block 0
Unimplemented
Reads all ‘0’s
Block 2
Block 3
Block 2
Block 1
007FFFh
008000h
013FFFh
014000h
Block 4
Block 3
Block 5
Block 4
00FFFFh
010000h
00BFFFh
00C000h
PIC18F2XXX/4XXX FAMILY
DS39622L-page 6 2010 Microchip Technology Inc.
For PIC18FX5X0/X5X3 devices, the code memory
space extends from 000000h to 007FFFh (32 Kbytes)
in four 8-Kbyte blocks. For PIC18FX4X5/X4X8
devices, the code memory space extends from
000000h to 005FFFh (24 Kbytes) in three 8-Kbyte
blocks. Addresses, 000000h through 0007FFh,
however, define a “Boot Block” region that is treated
separately from Block 0. All of these blocks define code
protection boundaries within the code memory space.
TABLE 2-4: IMPLEMENTATION OF CODE
MEMORY
FIGURE 2-5: MEMORY MAP AND THE CODE MEMORY SPACE
FOR PIC18FX4X5/X4X8/X5X0/X5X3 DEVICES
Device Code Memory Size (Bytes)
PIC18F2455
000000h-005FFFh (24K)
PIC18F2458
PIC18F4455
PIC18F4458
PIC18F2510
000000h-007FFFh (32K)
PIC18F2520
PIC18F2523
PIC18F2550
PIC18F2553
PIC18F4510
PIC18F4520
PIC18F4523
PIC18F4550
PIC18F4553
000000h
200000h
3FFFFFh
1FFFFFh
Note: Sizes of memory areas are not to sca le.
Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
MEMORY SIZE/DEVIC E
32 Kbytes
(PIC18FX5X0/X5X3) 24 Kbytes
(PIC18FX4X5/X4X8) Address
Range
Boot Block Boot Block 000000h
0007FFh
Block 0 Block 0 000800h
001FFFh
Block 1 Block 1 002000h
003FFFh
Block 2 Block 2 004000h
005FFFh
Block 3
Unimplemented
Reads all ‘0’s
006000h
007FFFh
Unimplemented
Reads all ‘0’s
1FFFFFh
008000h
2010 Microchip Technology Inc. DS39622L-page 7
PIC18F2XXX/4XXX FAMILY
For PIC18FX4X0/X4X3 devices, the code memory
space extends from 000000h to 003FFFh (16 Kbytes)
in two 8-Kbyte blocks. Addresses, 000000h through
0003FFh, how e ve r, define a “Boot Bl oc k” re gio n th at i s
treated separately from Block 0. All of these blocks
define code protection boundaries within the code
memory space.
TABLE 2-5: IMPLEMENTATION OF CODE
MEMORY
FIGURE 2-6: MEMORY MAP AND THE CODE MEMORY SPACE
FOR PIC18FX4X0/X4X3 DEVICES
Device Code Memory Size (Bytes)
PIC18F2410
000000h-003FFFh (16K)
PIC18F2420
PIC18F2423
PIC18F2450
PIC18F4410
PIC18F4420
PIC18F4450
000000h
200000h
3FFFFFh
1FFFFFh
Note: Sizes of memory areas are not to scale.
Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
MEMORY SIZE/
DEVICE
16 Kbytes
(PIC18FX4X0/X4X3) Address
Range
Boot Block 000000h
0007FFh
Block 0 000800h
001FFFh
Block 1 002000h
003FFFh
Unimplemented
Reads all ‘0’s
004000h
005FFFh
006000h
007FFFh
1FFFFFh
008000h
PIC18F2XXX/4XXX FAMILY
DS39622L-page 8 2010 Microchip Technology Inc.
For PIC18F2480/4480 devices, the code memory
space extends from 0000h to 03FFFh (16 Kbytes) in
one 16-Kbyte block. For PIC18F2580/4580 devices,
the code memory space extends from 0000h to
07FFFh (32 Kbytes) in two 16-Kbyte blocks.
Addresses, 0000h through 07FFh, however, define a
“Boot Block” region that is treated separately from
Block 0. All of these blocks define code protection
boundaries within the code memory space.
The size of the Boot Block in PIC18F2480/2580/4480/
4580 dev ic es can be c onf igu r ed a s 1 o r 2K w ords (se e
Figure 2-7). This is done through the BBSIZ<0> bit in
the Con figuration regi ster , CONFIG4L . It is import ant to
note that increasing the size of the Boot Block
decreases the size of Block 0.
TABLE 2-6: IMPLEMENTATION OF CODE
MEMORY
FIGURE 2-7: MEMORY MAP AND THE CODE MEMORY SPACE
FOR PIC18F2480/2580/4480/4580 DEVICES
Device Code Memory Size (Bytes)
PIC18F2480 000000h-003FFFh (16K)
PIC18F4480
PIC18F2580 000000h-007FFFh (32K)
PIC18F4580
000000h
200000h
3FFFFFh
01FFFFh
Note: Sizes of memory areas are not to scale.
* Boot Block size is determined by the BBSIZ<0> bit in the CONFIG4L register.
Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
MEMORY SIZE/DE VI CE Address
Range
32 Kbytes
(PIC18FX580) 16 Kbytes
(PIC18FX480)
BBSIZ<0>
10 1 0
Boot Block * Boot Block* Boot Block* Boot Block* 000000h
0007FFh
Block 0 Block 0
000800h
000FFFh
Block 0 Block 0
001000h
001FFFh
Block 1
002000h
003FFFh
Block 2
004000h
Unimplemented
Reads all ‘0’s
01FFFFh
Unimplemented
Reads all ‘0’s
Block 3
005FFFh
006000h
007FFFh
2010 Microchip Technology Inc. DS39622L-page 9
PIC18F2XXX/4XXX FAMILY
For PIC18F2221/4221 devices, the code memory
space extends from 0000h to 00FFFh (4 Kbytes) in one
4-Kbyte block. For PIC18F2321/4321 devices, the
code memory space extends from 0000h to 01FFFh
(8 Kbytes) in two 4-Kbyte blocks. Addresses, 0000h
through 07 FFh, however , define a variable “Boot Block”
region that is treated separately from Block 0. All of
these blocks define code protection boundaries within
the code memory space.
The size of the Boot Block in PIC18F2221/2321/4221/
4321 devices can be configured as 256, 512 or
1024 words (see Figure 2-8). This is done through the
BBSIZ<1:0> bits in the Configuration register,
CONFIG4L (see Figure 2-8). It is im port ant to no te that
increasing the size of the Boot Block decreases the
size of Block 0.
TABLE 2-7: IMPLEMENTATION OF CODE
MEMORY
FIGURE 2-8: MEMORY MAP AND THE CODE MEMORY SPACE
FOR PIC18F2221/2321/4221/4321 DEVICES
Device Code Memory Size (Bytes)
PIC18F2221 000000h-000FFFh (4K)
PIC18F4221
PIC18F2321 000000h-001FFFh (8K)
PIC18F4321
000000h
200000h
3FFFFFh
01FFFFh
Note: Sizes of memory areas are not to scale.
* Boot Block size is determined by the BBSIZ<1:0> bits in the CONFIG4L regist er.
Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
MEMORY SIZE /DEVICE Address
Range
8 Kbytes
(PIC18FX321) 4 Kbytes
(PIC18FX221)
BBSIZ<1:0>
11/10 01 00 11/10/01 00
Boot Block*
1K word
Boot Block*
512 words
Boot Block*
256 words Boot Block*
512 words
Boot Block *
256 words
000000h
0001FFh
Block 0
1.75K words
Block 0
0.75K words
000200h
0003FFh
Block 0
1.5K words
Block 0
0.5K words
000400h
0007FFh
Block 0
1K word Block 1
1K word
000800h
000FFFh
Block 1
2K words
001000h
001FFFh
Unimplemented
Reads all ‘0’s
002000h
1FFFFFh
Unimplemented
Reads all ‘0’s
PIC18F2XXX/4XXX FAMILY
DS39622L-page 10 2010 Microchip Technology Inc.
In addition to the code memory space, there are three
blocks that are accessible to the user through Table
Reads and Table Wr ites. Their l ocations in t he me mo ry
map are shown in Figure 2-9 .
Users may store identification information (ID) in eight ID
registers. These ID registers are mapped in addresses,
200000h through 200007h. The ID locations read out
normally, even after cod e protection is applied.
Locatio ns, 300000h through 30000Dh , are reserved for
the Confi guratio n bits . These bi ts se lect va rious dev ice
options and are described in Section 5.0 “Configura-
tion Word”. These Configuration bits read out
normally, even after code protection.
Locations, 3FFFFEh and 3FFFFFh, are reserved for
the Device ID bits. These bits may be used by the
programmer to identify what device type is being
programmed and are described in Section 5.0 “Con-
figuration Word”. These Device ID bits read out
normally, even after code protection.
2.3.1 MEMOR Y ADDRESS POINTER
Memory in the address space, 0000000h to 3FFFFFh,
is addressed via the Table Pointer register, which is
comprised of three pointer registers:
• TBLPTRU at RAM address 0FF8h
• TBLPTRH at RAM address 0FF7h
• TBLPTRL at RAM address 0FF6h
The 4-bit command, ‘0000’ (core instruction), is used to
load the Table Poin ter prio r to usi ng man y read or wri te
operations.
FIGURE 2-9: CONFIGURATION AND ID LOCATIONS FOR PIC18F2XXX/4XXX FAMILY DEVICES
TBLPTRU TBLPTRH TBLPTRL
Addr[21:16] Addr[15:8] Addr[7:0]
ID Location 1 200000h
ID Location 2 200001h
ID Location 3 200002h
ID Location 4 200003h
ID Location 5 200004h
ID Location 6 200005h
ID Location 7 200006h
ID Location 8 200007h
CONFIG1L 300000h
CONFIG1H 300001h
CONFIG2L 300002h
CONFIG2H 300003h
CONFIG3L 300004h
CONFIG3H 300005h
CONFIG4L 300006h
CONFIG4H 300007h
CONFIG5L 300008h
CONFIG5H 300009h
CONFIG6L 30000Ah
CONFIG6H 30000Bh
CONFIG7L 30000Ch
CONFIG7H 30000Dh
Device ID1 3FFFFEh
Device ID2 3FFFFFh
Note: Sizes of memory areas are not to scale.
000000h
1FFFFFh
3FFFFFh
01FFFFh Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
2FFFFFh
2010 Microchip Technology Inc. DS39622L-page 11
PIC18F2XXX/4XXX FAMILY
2.4 High-Level Overview of the
Programming Process
Figure 2-10 shows the high-level overview of the
progr amming pr ocess. First, a Bulk Eras e is perf ormed.
Next, the code memory, ID locations and data EEPROM
are programmed (selected devices only , see Section 3. 3
“Data EEPROM Programming”). These memories are
then verified to ensure that programming was successful.
If no err ors ar e detec ted, th e Conf igu ratio n bits are th en
programmed and verified.
FIGURE 2-10: HIGH-LEVEL
PROGRAMMING FLOW
2.5 Entering and Exiting High-Voltage
ICSP Program/Verify Mode
As shown in Fig ure 2-11, the High-Voltage ICSP
Program/Verify mode is entered by holding PGC and
PGD low and then raising MCLR/VPP/RE3 to VIHH
(high voltage). Once in this mode, the code memory,
data EEPROM (sele cted devices only, see Section 3.3
“Data EEPROM Programming”), ID locations and
Configuration bits can be access ed and programmed in
serial fashi on. Figure 2-12 shows the exit sequence.
The sequence that enters the device into the Program/
V erify mode places all unused I/Os in the high-impedance
state.
FIGURE 2-11: ENTERING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
FIGURE 2-12: EXITING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
Start
Program Memory
Program IDs
Program Data EE(1)
Verify Program
Veri fy IDs
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
Perform Bulk
Erase
Note 1: Selected devices only, see Section 3.3
“Data EEPRO M Programm ing ”.
P12
PGD
PGD = Input
PGC
VDD
D110
P13
P1
MCLR/VPP/RE3
MCLR/VPP/RE3
P16
PGD
PGD = Input
PGC
VDD
D110
P17
P1
PIC18F2XXX/4XXX FAMILY
DS39622L-page 12 2010 Microchip Technology Inc.
2.6 Entering and Exiting Low-Voltage
ICSP Program/Verify Mode
When the LVP Configuration bit is ‘1’ (see Section 5.3
“Single-Supply ICSP Programming”), the
Low-Voltage ICSP mode is enabled. As shown in
Figure 2-13, Low-Voltage ICSP Program/Verify mode
is entered by holding PGC and PGD low , placing a logic
high on PGM and then raising MCLR/VPP/RE3 to VIH.
In this mode, the RB5/PGM pin is dedicated to the
programming function and ceases to be a general
purpose I/O pin. Figure 2-14 shows the exit sequence.
The sequence that enters the device into the Program/
V erify mode places all unused I/Os in the high-impedance
state.
FIGURE 2-13: ENTERING LOW-VOLTAGE
PROGRAM/VERIFY MODE
FIGU RE 2 -1 4: EXITING LOW-VOLTAGE
PROGRAM/VERIFY MODE
2.7 Serial Program/Verify Operation
The PGC pin is used as a clock input pin and the PGD
pin is used for entering command bits and data input/
output during serial operation. Comman ds and data a re
transmitted on the rising edge of PGC, latched on the
falling edge of PGC and are Least Significant bit (LSb)
first.
2.7.1 4-BIT COMMANDS
All instructions are 20 bits, consisting of a leading 4-bit
command followed by a 16-bit operand, which depends
on the type of command being executed. To input a
command, PGC is cycled four times. The commands
needed for programming and verification are shown in
Table 2-8.
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data or 8 bits of input data
and 8 bits of output data.
Throughout this specification, commands and data are
presented as illustrated in Table 2-9. The 4-bit command
is shown Most Significant bit (MSb) first. The command
operand, or “Dat a Payload”, is shown as <MSB><LSB>.
Figure 2-15 demonstrates how to serially present a
20-bit command/operand to the dev ice.
2.7.2 CORE INSTRUCTION
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to set up
registers as approp riate for us e with other co mmand s.
TABLE 2-8: COMMANDS FOR
PROGRAMMING
TABLE 2-9: SAMPLE COMMAND
SEQUENCE
MCLR/VPP/RE3
P12
PGD
PGD = Input
PGC
PGM
P15
VDD
VIH
VIH
MCLR/VPP/RE3
P16
PGD
PGD = Input
PGC
PGM
P18
VDD
VIH
VIH
Description 4-Bit
Command
Core Instruction
(Shift in16-b it i nst r uct i on) 0000
Shift Out TABLAT Register 0010
Ta ble R ead 1000
Ta ble R ead, P ost-Increme nt 1001
Ta ble R ead, P ost-Decrement 1010
Ta ble R ead, P re-Inc re m ent 1011
Ta ble Write 1100
Table Write, Post-Increment by 2 1101
Ta ble Write, Start Programming,
Post-Inc re m ent by 2 1110
Ta ble Write, Start Programming 1111
4-Bit
Command Data
Payload Core Instruction
1101 3C 40 Table Write,
post-increment by 2
2010 Microchip Technology Inc. DS39622L-page 13
PIC18F2XXX/4XXX FAMILY
FIGURE 2-15: TABLE WRITE, POST-INCREMENT TIMING (1101)
2.8 Dedicated ICSP/ICD Port
(44-Pin TQFP Only)
The PIC18F4455/4458/4550/4553 44-pin TQFP
devices are designed to support an alternate
programming input: the dedicated ICSP/ICD port. The
primary purpose of this port is to provide an alternate
In-Circuit Debugging (ICD) option and free the pins
(RB6, RB7 and MCLR) that would no rmally be u sed for
debugging the application. In conjunction with ICD
capability, however, the dedicated ICSP/ICD port also
provides an alternate port for ICSP.
Setting the ICPRT Configuration bit enables the
dedicated ICSP/ICD port. The dedicated ICSP/ICD
port functions the same as the default ICSP/ICD port;
however, alternate pins are used instead of the default
pins. Table 2-10 identifies the functionally equivalent
pins for ICSP purposes:
The dedicated ICSP/ICD port is an a lternate port. Thus,
ICSP is still available through the default port even
though the ICPRT Configuration bit is set. When the
VIH is seen on the MCLR/VPP/RE3 pin p rior to appl ying
VIH to the ICRST/ICVPP pin, then the state of the
ICRST/ICVPP pin is ignor ed. Likewise , wh en the VIH is
seen on ICRST/ICVPP prior to applying VIH to MCLR/
VPP/RE3, then the state of the MCLR/VPP/RE3 pin is
ignored.
TABLE 2-10: ICSP™ EQUIV ALEN T PINS
1234
PGC P5
PGD
PGD = Input
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4-Bit Command
1011
1234
nnnn
P3
P2 P2A
000000 010001111 0
04C3
P4
4-Bit Command 16-Bit Data Payload
P2B
Note: The ICPRT Configuration bit can only be
programmed through the default ICSP
port. Chip Erase functions through the
dedicat ed IC SP/ICD p ort do not af fect this
bit.
When the ICPRT Configuration bit is set
(dedicated ICSP/ICD port enabled), the
NC/ICPORTS pin must be tied to either
VDD or VSS.
The ICPRT Configuration bit must be
maintained clear for all 28-pin and 40-pin
devices; otherwi se , unex pe cted operation
may occur.
Pin Name During Programming
Pin Name Pin Type Dedicated Pins Pin Description
MCLR/VPP/RE3 VPP P NC/ICRST/ICVPP Programming Enable
RB6 PGC I NC/ICCK/ICPGC Serial Clock
RB7 PGD I/O NC/ICDT/ICPGD Serial Data
Legend: I = Input, O = Output, P = Power
PIC18F2XXX/4XXX FAMILY
DS39622L-page 14 2010 Microchip Technology Inc.
3.0 DEVICE PROGRAMMING
Programming includes the ability to erase or write the
various memory regions within the device.
In all cases, except high-voltage ICSP Bulk Erase, the
EECON1 register must be configured in order to
operate on a particular memory region.
When using the EECON1 register to act on code
memory , the EEPGD bit must be set (EECON1<7> = 1)
and the CFGS bit must be cleared (EECON1<6> = 0).
The WREN bit must be set (EECON1<2> = 1) to
enable writes of any sort (e.g., erases) and this must be
done prior to initiating a write sequence. The FREE bit
must be set (EECON1<4> = 1) in order to erase the
program space being pointed to by the Table Pointer.
The erase or write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongl y rec om mende d
that the WREN bit only be set immediately prior to a
program eras e.
3.1 ICSP Erase
3.1.1 HIGH-VOLTAGE ICSP BULK ERASE
Erasing code or data EEPROM is accomplished by
configuring two Bulk Erase Control registers located at
3C0004h an d 3C000 5h. Code memo ry may be erased ,
portions at a time, or the user may erase the entire
device in one action. Bulk Erase operations will also
clear any code-protect settings associated with the
memory block being erased. Erase optio ns are det ailed
in Table 3-1. If data EEPROM is code-protected
(CPD = 0), the user must request an erase of data
EEPROM (e.g., 0084h as shown in Table 3-1).
TABLE 3-1: BULK ERASE OPTIONS
The actual Bulk Erase function is a self-timed
operation. Once the erase has started (falling edge of
the 4th PGC after the NOP command), serial execution
will cease until the erase completes (Parameter P11).
During this time, PGC may con tin ue to tog gle but PG D
must be held low.
The code s equence to eras e the entire devic e is shown
in Table 3-2 and the flowchart is shown in Figure 3-1.
TABLE 3-2: BULK ERASE COMMAND
SEQUENCE
FIGURE 3-1: BULK ERASE FLOW
Description Data
(3C0005h:3C0004h)
Chip Erase 3F8Fh
Erase Data EEPROM(1) 0084h
Erase Boot Block 0081h
Erase Configuration Bits 0082h
Erase Code EEPROM Block 0 0180h
Erase Code EEPROM Block 1 0280h
Erase Code EEPROM Block 2 0480h
Erase Code EEPROM Block 3 0880h
Erase Code EEPROM Block 4 1080h
Erase Code EEPROM Block 5 2080h
Note 1: Selected devices only, see Section 3.3
“Data EEPROM Programming”.
Note: A Bulk Erase is t he onl y way to rep rogram
code-protect bits from an ON state to an
OFF sta t e.
4-Bit
Command Data
Payload Core Instruction
0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
1100
0000
0000
0E 3C
6E F8
0E 00
6E F7
0E 05
6E F6
3F 3F
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
8F 8F
00 00
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 05h
MOVWF TBLPTRL
Write 3F3Fh to 3C0005h
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 8F8Fh TO 3C0004h
to erase entire
device.
NOP
Hold PGD low until
erase completes.
Start
Done
Write 8F8Fh to
3C0004h to Erase
Entire Device
Write 3F3Fh
Delay P11 + P10
Time
to 3C0005h
2010 Microchip Technology Inc. DS39622L-page 15
PIC18F2XXX/4XXX FAMILY
3.1.2 LOW-VOLTAGE ICSP BULK ERASE
When using low-voltage ICSP, the part must be
supplied by the voltage specified in Parameter D111 if
a Bulk Erase is to be executed. All other Bulk Erase
details, as described above, apply.
If it is determined that a program memory erase must
be perform ed at a sup ply vo lta ge below the Bul k Erase
limit, refer to the erase methodology described in
Section 3.1.3 “ICSP Row Erase” and Section 3.2.1
“Modify ing Code Me mory”.
If it is determined that a data EEPROM erase
(selected devices only, see Section 3.3 “D ata
EEPROM Programming”) must be performed at a
supply voltage below the Bulk Erase limit, follow the
methodology described in Section 3.3 “Data
EEPROM Programming” and write ‘1’s to the array.
FIGURE 3-2: BULK ERASE TIMING
3.1.3 ICSP ROW ERASE
Rega rdless of w hether hi gh or low-vo ltag e ICSP is used ,
it is possible to erase one row (64 bytes of data), provided
the block is not code or write-protected. Rows are located
at static boundaries, beginning at program memory
address, 000000h, extending to the internal program
memory limit (see Section 2.3 “Memory Maps”).
The Row Erase duration is externally timed and is
controlled by PGC. After the WR bit in EECON1 is set,
a NOP is issue d, wher e the 4th PGC is he ld high for the
duration of the program mi ng tim e, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time
specified by Parameter P10 to allow high-voltage
discharge of the memory array.
The code sequence to Row Erase a PIC18F2XXX/
4XXX family device is shown in Table 3-3. The
flowchart, shown in Figure 3-3, depicts the logic
necessary to completely erase a PIC18F2XXX/4XXX
family device. The timing diagram that details the Start
Programming command and Parameters P9 and P10
is shown i n Figure 3-5.
n
1234 121516 123
PGC
P5 P5A
PGD
PGD = Input
0
0011
P11
P10
Erase Time
0000
00
12
00
4
0
1 2 15 16
P5
123
P5A
4
0000
n
4-Bit Com man d 4-Bit Command 4-Bit Command
16-Bit
Data Payload
16-Bit
Data Payload 16-Bit
Data Payload
11
Note: The TBLPTR register can point to any
byte within the row intended for erase.
PIC18F2XXX/4XXX FAMILY
DS39622L-page 16 2010 Microchip Technology Inc.
TABLE 3-3: ERASE CODE ME MORY CODE SEQUENCE
FIGURE 3-3: SINGLE ROW ERASE CODE MEMORY FLOW
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to code memory and enable writes.
0000
0000
0000
8E A6
9C A6
84 A6
BSF EECON1, EEPGD
BCF EECON1, CFGS
BSF EECON1, WREN
Step 2: Point to first row in code memory.
0000
0000
0000
6A F8
6A F7
6A F6
CLRF TBLPTRU
CLRF TBLPTRH
CLRF TBLPTRL
Step 3: Enable erase and erase single row.
0000
0000
0000
88 A6
82 A6
00 00
BSF EECON1, FREE
BSF EECON1, WR
NOP – hold PGC high for time P9 and low for time P10.
Step 4: Repeat Step 3, with the Address Pointer incremented by 64 until all rows are erased.
Done
Start
Hold PGC Low
for Time P10
All
rows
done?
No
Yes
Addr = 0
Configure
Device for
Row Erases
Addr = Addr + 64
Start Erase Sequence
and Hold PGC High
for Time P9
2010 Microchip Technology Inc. DS39622L-page 17
PIC18F2XXX/4XXX FAMILY
3.2 Code Memory Programming
Programming code memory is accomplished by first
loading data into the write buffer and then initiating a
programming sequence. The write and erase buffer
sizes, shown in Table 3-4, can be mapped to any
location of the same size, beginning at 000000h. The
actual memory write sequence takes the contents of
this buffer and programs the proper amount of code
memory that contains the Table Pointer.
The programming duration is externally timed and is
controlled by PGC. After a Start Programming
command is issued (4-bit command, ‘1111’), a NOP is
issued , where th e 4 th PGC is he ld high fo r the dur ation
of the programming time, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time
specified by Parameter P10 to allow high-voltage
discharge of the memory array.
The code sequence to program a PIC18F2XXX/4XXX
family device is shown in Table 3-5. The flowchart,
shown in Figure 3-4, depicts the logic necessary to
c o m pl e t el y w r it e a PIC18F2XXX/4XXX family d ev i c e .
The timing diagram that details the Start Programming
command and Parameters P9 and P10 is shown in
Figure 3-5.
TABLE 3-5: WRITE CODE MEMORY CODE SEQUENCE
Note: The TBLPTR register must point to the
same region when initiating the program-
ming sequence as it did when the write
buffers were loaded.
TABLE 3-4: WRITE AND ERASE BUFFER SIZES
Devices (Arranged by Family) Write Buffer S ize (Bytes) Erase Bu ffer S ize (Bytes)
PIC18F22 21, PI C 18 F2321, PIC18 F 42 21, PI C18F4321 8 64
PIC18F2450, PIC18 F4450 16 64
PIC18F24 10, PI C 18 F2510, PIC18 F 44 10, PI C18F4510
32 64
PIC18F24 20, PI C 18 F2520, PIC18 F 44 20, PI C18F4520
PIC18F24 23, PI C 18 F2523, PIC18 F 44 23, PI C18F4523
PIC18F24 80, PI C 18 F2580, PIC18 F 44 80, PI C18F4580
PIC18F24 55, PI C 18 F2550, PIC18 F 44 55, PI C18F4550
PIC18F24 58, PI C 18 F2553, PIC18 F 44 58, PI C18F4553
PIC18F25 15, PI C 18 F2610, PIC18 F 45 15, PI C18F4610
64 64
PIC18F25 25, PI C 18 F2620, PIC18 F 45 25, PI C18F4620
PIC18F25 85, PI C 18 F2680, PIC18 F 45 85, PI C18F4680
PIC18F26 82, PI C 18 F2685, PIC18 F 46 82, PI C18F4685
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to code memory and enable writes.
0000
0000 8E A6
9C A6 BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Load write buffer.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 3: Repeat for all but the last two bytes.
1101 <MSB><LSB> Write 2 bytes and post-increment address by 2.
Step 4: Load write buffer for last two bytes.
1111
0000 <MSB><LSB>
00 00 Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
To continue writing data, repeat Steps 2 through 4, where the Address Pointer is incremented by 2 at each iteration of the loop.
PIC18F2XXX/4XXX FAMILY
DS39622L-page 18 2010 Microchip Technology Inc.
FIGURE 3-4: PROGRAM CODE MEMORY FLOW
FIGURE 3-5: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111)
Start Write Sequence
All
locations
done?
No
Done
Start
Yes
Hold PGC Low
for Time P10
Load 2 Bytes
to Write
Buffer at <Addr>
All
bytes
written?
No
Yes
and Hold PGC
High until Done
N = 1
LoopCount = 0
Configure
Device for
Writes
N = 1
LoopCount =
LoopCount + 1
N = N + 1
and Wait P9
1234 12 1516 123 4
PGC
P5A
PGD
PGD = Input
n
1111
34 65
P9
P10
Progra mm i ng Time
nnn nn n n
00
12
000
16-Bit
Data Payload
0
3
0
P5
4-Bit Command 16-Bit Data Paylo ad 4-Bit Command
2010 Microchip Technology Inc. DS39622L-page 19
PIC18F2XXX/4XXX FAMILY
3.2.1 MODIFYING CODE MEMORY
The previous programming example assumed that the
device had been Bulk Erased prior to programming
(see Section 3.1.1 “High-V ol tage ICSP Bulk Erase”).
It may be the case, however, that the user wishes to
modify only a section of an already programmed
device.
The appro priate num ber of byte s required for the eras e
buffer must be read out of code memory (as described
in Section 4.2 “Verify Code Memory and ID
Locations”) and buffered. Modifications can be made
on this b uffer . Then, the bloc k of code memory that wa s
read out must be erased and rewritten with the
modified data.
The WREN bit must be set if the WR bit in EECON1 is
used to initiate a write sequence.
TABLE 3-6: MODIFYING CODE MEMORY
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to code memory.
Step 2: Read and modify code memory (see Secti on 4.1 “ R ead C o de M emory, ID Lo c a t i ons an d C onfiguration Bits”).
0000
0000 8E A6
9C A6 BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 3: Set the Table Pointer for the block to be erased.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 4: Enable memory writes and set up an erase.
0000
0000 84 A6
88 A6 BSF EECON1, WREN
BSF EECON1, FREE
Step 5: Initiate erase.
0000
0000 82 A6
00 00 BSF EECON1, WR
NOP - hold PGC high for time P9 and low for time P10.
Step 6: Load write buffer. The correct bytes will be selected based on the Table Pointer.
0000
0000
0000
0000
0000
0000
1101
.
.
.
1111
0000
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<MSB><LSB>
.
.
.
<MSB><LSB>
00 00
MOVLW <Addr[21:16]>
MOVWF TBLPTRU
MOVLW <Addr[8:15]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2.
Repeat as many times as necessary to fill the write buffer
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
To continue modifying data, repeat S t eps 2 through 6, where the Address Pointer is incremented by the appropriate number of bytes
(see Table 3-4) at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of
the erase buffer.
Step 7: Disable writes.
0000 94 A6 BCF EECON1, WREN
PIC18F2XXX/4XXX FAMILY
DS39622L-page 20 2010 Microchip Technology Inc.
3.3 Data EEPROM Programming
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair: EEADRH:EEADR) and
a data latch (EEDATA). Data EEPROM is written by
loading EEADRH:EEADR with the desired memory
location, EEDATA, with the data to be written and initi-
ating a memory write by appropriately configuring the
EECON1 register . A byte write automatically erases the
location and writes the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1< 2> = 1) to enable writes of any sort
and this must be done prior to initiating a write
sequen ce. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1).
The write begins on the falling edge of the 4th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming se quence terminates , PGC must
still be held low for the time sp ecified by Parameter P10
to allow high-volt age dis charge of the m emory array.
FIGURE 3-6: PROG RAM DATA FLOW
FIGURE 3-7: DATA EEPROM WRITE TIMING
Note: Data EEPROM programming is not
ava ilable on the the following devi ces:
PIC18F2410 PIC18F4410
PIC18F2450 PIC18F4450
PIC18F2510 PIC18F4510
PIC18F2515 PIC18F4515
PIC18F2610 PIC18F4610
Start
St art Write
Set D a ta
Done
No
Yes
Done?
Enable Write
Sequence
Set Address
WR bit
clear? No
Yes
n
PGC
PGD
PGD = Input
0000
BSF EECON1, WR4-Bit Command
1234 121516
P5 P5A
P10 12
n
Poll WR bit, Repe at until Clear 16-Bit Data
Payload
1234 121516 123
P5 P5A
41 2 15 16
P5 P5A
0000
MOVF EECON1, W, 0
4-Bit Command
0000
4-Bit Command Shift Out Data
MOVWF TABLAT
PGC
PGD
(see below)
(see Figure 4-4)
PGD = Input PGD = Output
Poll WR bit
P11A
2010 Microchip Technology Inc. DS39622L-page 21
PIC18F2XXX/4XXX FAMILY
TABLE 3-7: PROGRAMMING DATA MEMORY
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to data EEPROM .
0000
0000 9E A6
9C A6 BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000
0000
0000
0000
0E <Addr>
6E A9
OE <AddrH>
6E AA
MOVLW <Addr>
MOVWF EEADR
MOVLW <AddrH>
MOVWF EEADRH
Step 3: Load the data to be written.
0000
0000 0E <Data>
6E A8 MOVLW <Data>
MOVWF EEDATA
Step 4: Enable memory writes.
0000 84 A6 BSF EECON1, WREN
Step 5: Initiate write.
0000 82 A6 BSF EECON1, WR
Step 6: Poll WR bit, repeat until the bit is clear.
0000
0000
0000
0010
50 A6
6E F5
00 00
<MSB><LSB>
MOVF EECON1, W, 0
MOVWF TABLAT
NOP
Shift out data(1)
Step 7: Hold PGC low for time P10.
Step 8: Disable writes.
0000 94 A6 BCF EECON1, WREN
Repeat Steps 2 through 8 to write more data.
Note 1: See Figure 4-4 for details on shift out data timing.
PIC18F2XXX/4XXX FAMILY
DS39622L-page 22 2010 Microchip Technology Inc.
3.4 ID Location Programming
The ID locations are programmed much like the code
memory. The ID registers are mapped in addresses,
200000h through 200007h. These locations read out
normally even after code protection.
Table 3-8 demonstrates the code se quence requ ired to
write the ID locations.
In order to modif y the ID l ocations , refer to the me thod-
ology described in Sec t ion 3.2 .1 “Modi fying Code
Memory”. As with code memory, the ID locati ons mus t
be erased before being modified.
TABLE 3-8: WRITE ID SEQUENCE
Note: The us er on ly nee ds to fill the first 8 byt es
of the write buffer in order to write the ID
locations.
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to code memory and enable writes.
0000
0000 8E A6
9C A6 BSF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Load write buffer with 8 bytes and write.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
0E 20
6E F8
0E 00
6E F7
0E 00
6E F6
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
00 00
MOVLW 20h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 00h
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2.
Write 2 bytes and post-increment address by 2.
Write 2 bytes and post-increment address by 2.
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
2010 Microchip Technology Inc. DS39622L-page 23
PIC18F2XXX/4XXX FAMILY
3.5 Boot Block Programming
The code sequence detailed in Table 3-5 should be
used, except t hat the a ddress u sed in “Step 2” w ill be in
the range of 000000h to 0007FFh.
3.6 Configuration Bit s Programming
Unlike code memory, the Configuration bits are
programmed a byte at a time. The Table Write, Begin
Programming 4-bit command (‘1111’) is us ed, bu t on ly
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses and
the MSB will be written to odd addresses. The code
sequence to program two consecutive configuration
locations is show n in Table 3-9.
TABLE 3-9: SET ADDRESS POINTER TO CONFIGURATION LOCATION
FIGURE 3-8: CONFIGURATION PROGRAMMING FLOW
Note: The address must be explicitly written for
each byte programmed. The addresses
can not be increm en ted in this mode .
4-Bit
Command Data Payload Core Instruction
Step 1: Enable writes and direct access to configuration memo ry.
0000
0000 8E A6
8C A6 BSF EECON1, EEPGD
BSF EECON1, CFGS
Step 2: Set Table Pointer for configuration byte to be written. Write even/odd addresses.(1)
0000
0000
0000
0000
0000
0000
1111
0000
0000
0000
1111
0000
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<MSB ignored><LSB>
00 00
0E 01
6E F6
<MSB><LSB ignored>
00 00
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
MOVLW 01h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
Note 1: Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of the
Configuration bits. Always write all the Configuration bits before enabling the write protection for Configuration bits.
Load Even
Configuration
Start
Program Program
MSB
Delay P9 and P10
Time for Write
LSB
Load Odd
Configuration
Address Address
Done
Start
Delay P9 and P10
Time for Write
Done
PIC18F2XXX/4XXX FAMILY
DS39622L-page 24 2010 Microchip Technology Inc.
4.0 READING THE DEVICE
4.1 Read Code Memory, ID Locations
and Configurati on Bits
Code memory is accessed, one byte at a time, via the
4-bit command, ‘1001’ (Table Read, post-increment).
The co ntents of memory poin ted to by the Table Poin ter
(TBLPTRU:TB LPTRH:TBLPTRL) are serially output on
PGD.
The 4-bit command is shifted in, LSb first. The read is
executed during the next 8 clocks, then shifted out on
PGD during the last 8 clocks, LSb to MSb. A delay of
P6 must be introduced after the falling edge of the 8th
PGC of the op erand to allow PGD to t rans iti on fr om an
input to an output. During this time, PGC must be held
low (see Figure 4-1). This operation also increments
the Table Pointer by one, pointing to the next byte in
code memory for the next read.
This technique will work to read any memory in the
000000h to 3FFFFFh address s p a ce, s o i t also appl ie s
to the reading of the ID and Configuration registers.
TABLE 4-1: READ CODE MEMORY SEQUENCE
FIGURE 4-1: TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)
4-Bit
Command Data Payload Core Instruction
Step 1: Set Table Pointer .
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 2: Read memory and then shift out on PGD, LSb to MSb.
1001 00 00 TBLRD *+
1234
PGC
P5
PGD
PGD = Input
Shift Data Out
P6
PGD = Output
5678 1234
P5A
910 11 13 15 161412
Fetch Next 4-Bit Command
1001
PGD = Input
LSb MSb
123456
1234
nnnn
P14
2010 Microchip Technology Inc. DS39622L-page 25
PIC18F2XXX/4XXX FAMILY
4.2 Verify Code Memory and ID
Locations
The veri fy step in volves read ing back the code memo ry
space and comparing it against the copy held in the
programmer’s buffer. Memory reads occur a single byte
at a time, so two bytes must be read to compare
against the word in the programmer’s buffer. Refer to
Section 4.1 “Read Code Memory, ID Locations and
Configuration Bits” for implementation details of
reading co de mem ory.
The Table Pointer must be manually set to 200000h
(base address of the ID locations) once the code
memory has been verified. The post-increment feature
of the Table Read 4-bit command may not be used to
increment the Table Pointer beyond the code memory
space. In a 64-Kbyte device, for example, a
post-increment read of address, FFFFh, will wrap the
Table Pointe r bac k to 00 000 0h, rather than poin t to th e
unimplemented address, 010000h.
FIGURE 4-2: VERIFY CODE MEMORY FLOW
Read Low Byte
Read High Byte
Does
Word = Expect
Data? Failure,
Report
Error
All
code memory
verified?
No
Yes
No
Set TBLPTR = 0
Start
Set TBLPTR = 200000h
Yes
Read Low Byte
Read High Byte
Does
Word = Expect
Data? Failure,
Report
Error
All
ID locations
verified?
No
Yes
Done
Yes
No
with Post-Increment
with Post-Increment Increment
Pointer
with Post-Increment
with Post-Increment
PIC18F2XXX/4XXX FAMILY
DS39622L-page 26 2010 Microchip Technology Inc.
4.3 Verify Configuration Bits
A configuration address may be read and output on
PGD via th e 4-bit co mmand, ‘1001’. Config uration dat a
is read and written in a byte-wise fashion, so it is not
necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
compared to the appropriate configuration data in the
programmer’s memory for verification. Refer to
Section 4.1 “Read Code Memory, ID Locations and
Configuration Bits” for implementation details of
reading co nfiguration data.
4.4 Read Data EEPROM Memory
Data EEPROM is accessed, one byte at a time, via an
Address Pointer (register pair: EEADRH:EEADR) and
a data latch (EEDA TA). Data EEPROM is read by loa d-
ing EEADRH:EEADR with the desired memory location
and initi ating a m emory read by approp riat ely con figur-
ing the EECON1 register. The data will be loaded into
EEDATA, where it may be serially output on PGD via
the 4-bit command, ‘0010’ (Shift Out Data Holding
register). A delay of P6 must be introduced after the
falling edge of the 8th PGC of the operand to allow
PGD to transition from an input to an output. During this
time, PGC must be held low (see Figure 4-4).
The command sequence to read a single byte of data
is shown in Table 4-2.
FIGURE 4-3: READ DATA EEPROM
FLOW
TABLE 4-2: READ DATA EEPROM MEMORY
Start
Set
Address
Read
Byte
Done
No
Yes
Done?
Move to T A BLAT
Shif t Ou t Da ta
4-Bit
Command Data Payload Core Instruction
Step 1: Direct access to data EEPROM .
0000
0000 9E A6
9C A6 BCF EECON1, EEPGD
BCF EECON1, CFGS
Step 2: Set the data EEPROM Address Pointer.
0000
0000
0000
0000
0E <Addr>
6E A9
OE <AddrH>
6E AA
MOVLW <Addr>
MOVWF EEADR
MOVLW <AddrH>
MOVWF EEADRH
Step 3: Initiate a memory read.
0000 80 A6 BSF EECON1, RD
Step 4: Load data into the Serial Data Holding register.
0000
0000
0000
0010
50 A8
6E F5
00 00
<MSB><LSB>
MOVF EEDATA, W, 0
MOVWF TABLAT
NOP
Shift Out Data(1)
Note 1: The <LSB> is undefined. The <MSB> is the data.
2010 Microchip Technology Inc. DS39622L-page 27
PIC18F2XXX/4XXX FAMILY
FIGURE 4-4: SHIFT OUT DATA HOLDING REGISTER TIMING (0010)
4.5 Verify Data EEPROM
A data EEPROM add res s may b e re ad vi a a sequ enc e
of core instructions (4-bit command, ‘0000’) and then
output on PGD via the 4-bit command, ‘0010’ (TABLAT
register). The result may then be immediately
compared to the appropriate data in the programmer’s
memory for verification. Refer to Secti on 4.4 “Read
Dat a EEPROM Memory ” for i mp lem en t ati on de tails of
reading data EEPROM.
4.6 Blank Check
The term “Blank C heck” me ans to ve rify that the device
has no p ro gra mm ed m em ory ce lls . Al l me mo rie s must
be verified: code memory, data EEPROM, ID locations
and Configuration bits. The Device ID registers
(3FFFFEh:3FFFFFh) should be ignored.
A “blank” or “erased” mem ory cell will re ad as ‘1’. There-
fore, Blank Checking a device merely means to verify
that all bytes read as FFh, except the Configuration bits.
Unused (reserved) Configuration bits will read ‘0’ (pro-
grammed). Refer to Figure 4-5 for blank configuration
e x p e c t d a ta f o r t h e v a r i o u s PIC18F2 XXX/4XXX family
devices.
Given that Blank Checking is merely code and data
EEPROM verification with FFh expect data, refer to
Section 4.4 “Read Data EEPROM Memory” and
Section 4.2 “Verify Code Memory and ID Locations”
for implement atio n det ails.
FIGURE 4-5: BLANK CHECK FLOW
1234
PGC
P5
PGD
PGD = Input
Shift Data Out
P6
PGD = Output
5678 1234
P5A
91011 13 15161412
Fetch Next 4-Bi t Command
0100
PGD = Input
LSb MSb
123456
1234
nnnn
P14
Yes
No
Start
Blank Check Device
Is
device
blank? Continue
Abort
PIC18F2XXX/4XXX FAMILY
DS39622L-page 28 2010 Microchip Technology Inc.
5.0 CONFIGURATION WORD
The PIC18F2XXX/4XXX family devices have several
Configuration W ords. These bits can b e set or cleared to
select various device configurations. All other memory
areas should be programmed and verified prior to setting
the Configuration Words. These bits may be read out
normally, even after read or code protection. See
Table 5-1 for a list of Configuration bits and Device IDs,
and Table 5-3 for the Configuration bit descriptions.
5.1 ID Locations
A user may sto re ide ntif ic atio n inf orm atio n (ID ) in eig ht
ID loc ations, mappe d in 200 000h:200 007h. It is recom -
mended that the most significant nibble of each ID be
Fh. In doing so, if the user code inadvertently tries to
execute from the ID space, the ID data will execute as
a NOP.
5.2 Device ID W ord
The Device ID Word for the PIC18F2XXX/4XXX family
devices is located at 3FFFFEh:3FFFFFh. These bits
may be used by the programmer to identify what device
type is b ein g p r ogr am med a nd read out norm all y, even
after code or read protection.
In some cases, devices may share the same DEVID
values. In such cases, the Most Significant bit of the
device revision, REV4 (DEVID1<4>), will need to be
examined to completely determine the device being
accessed.
See Table 5-2 for a complete list of Device ID values.
FIGURE 5-1: READ DEVICE ID WORD FLOW
Start
Set TBLP TR = 3FF FFE
Done
Read Low Byte
Read High Byte
with Post-Increment
with Post-Increment
2010 Microchip Technology Inc. DS39622L-page 29
PIC18F2XXX/4XXX FAMILY
TABLE 5-1: CONFIGURATION BITS AND DEVICE IDS
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/
Unprogrammed
Value
300000h(1,8) CONFIG1L —— USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0 --00 0000
300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111
00-- 0101(1,8)
300002h CONFIG2L — — —BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111
VREGEN(1,8) --01 1111(1,8)
300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300005h CONFIG3H MCLRE — — — — LPT1OSC PBADEN CCP2MX(7) 1--- -011(7)
—1--- -01-
300006h CONFIG4L DEBUG XINST
ICPRT(1) — —
LVP —STVREN
100- -1-1(1)
BBSIZ1 BBSIZ0 —1000 -1-1
— BBSIZ(3) —10-0 -1-1(3)
ICPRT(8) — BBSIZ(8) 100- 01-1(8)
BBSIZ1(2) BBSIZ2(2) —1000 -1-1(2)
300008h CONFIG5L ——CP5
(10) CP4(9) CP3(4) CP2(4) CP1 CP0 --11 1111
300009h CONFIG5H CPD CPB — — — — — — 11-- ----
30000Ah CONFIG6L ——WRT5
(10) WRT4(9) WRT3(4) WRT2(4) WRT1 WRT0 --11 1111
30000Bh CONFIG6H WRTD WRTB WRTC(5) — — — — — 111- ----
30000Ch CONFIG7L —— EBTR5(10) EBTR4(9) EBTR3(4) EBTR2(4) EBTR1 EBTR0 --11 1111
30000Dh CONFIG7H — EBTRB — — — — — — -1-- ----
3FFFFEh DEVID1(6) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 See Table 5-2
3FFFFFh DEVID2(6) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Se e Table 5-2
Legend: - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Implem ent ed only on P I C 18F2455/255 0/4 45 5/4 550 and PIC1 8F 245 8/2553/44 58 /45 53 devi ce s.
2: Implemented on PIC18F2585/2680/4585/4680, PIC18F2682/2685 and PIC18F4682/4685 devices only.
3: Implem ent ed on PIC18F24 80 /258 0/4480/4 580 devices onl y.
4: These bits are only implemented on specific devices based on available memory. Refer to Section 2.3 “Memory Maps”.
5: In PIC18F2480/2580/4480/4580 devices, this bit is read-only in Normal Execution mode; it can be written only in Program mode.
6: DEVID registers are read-only and cannot be programmed by the user.
7: Implemented on all devices with the exception of the PIC18FXX8X and PIC18F2450/4450 devices.
8: Implem ent ed on PIC18F24 50 /445 0 devi ce s only.
9: Implem ent ed on P I C18F 26 82 /268 5 and PIC18F4 682 /46 85 devices only.
10: Impl em ent ed on P I C18F 26 85 /468 5 device s onl y.
PIC18F2XXX/4XXX FAMILY
DS39622L-page 30 2010 Microchip Technology Inc.
TABLE 5-2: DEVICE ID VALUES
Device Device ID Value
DEVID2 DEVID1
PIC18F2221 21h 011x xxxx
PIC18F2321 21h 001x xxxx
PIC18F2410 11h 011x xxxx
PIC18F2420 11h 010x xxxx(1)
PIC18F2423 11h 010x xxxx(2)
PIC18F2450 24h 001x xxxx
PIC18F2455 12h 011x xxxx
PIC18F2458 2Ah 011x xxxx
PIC18F2480 1Ah 111x xxxx
PIC18F2510 11h 001x xxxx
PIC18F2515 0Ch 111x xxxx
PIC18F2520 11h 000x xxxx(1)
PIC18F2523 11h 000x xxxx(2)
PIC18F2525 0Ch 110x xxxx
PIC18F2550 12h 010x xxxx
PIC18F2553 2Ah 010x xxxx
PIC18F2580 1Ah 110x xxxx
PIC18F2585 0Eh 111x xxxx
PIC18F2610 0Ch 101x xxxx
PIC18F2620 0Ch 100x xxxx
PIC18F2680 0Eh 110x xxxx
PIC18F2682 27h 000x xxxx
PIC18F2685 27h 001x xxxx
PIC18F4221 21h 010x xxxx
PIC18F4321 21h 000x xxxx
PIC18F4410 10h 111x xxxx
PIC18F4420 10h 110x xxxx(1)
PIC18F4423 10h 110x xxxx(2)
PIC18F4450 24h 000x xxxx
PIC18F4455 12h 001x xxxx
PIC18F4458 2Ah 001x xxxx
PIC18F4480 1Ah 101x xxxx
PIC18F4510 10h 101x xxxx
PIC18F4515 0Ch 011x xxxx
PIC18F4520 10h 100x xxxx(1)
PIC18F4523 10h 100x xxxx(2)
PIC18F4525 0Ch 010x xxxx
PIC18F4550 12h 000x xxxx
PIC18F4553 2Ah 000x xxxx
PIC18F4580 1Ah 100x xxxx
PIC18F4585 0Eh 101x xxxx
PIC18F4610 0Ch 001x xxxx
Legend: The ‘x’s in DEVID1 con tain th e device rev isio n code.
Note 1: DEVID1 bit 4 is used to dete rmine the device t ype (REV4 = 0).
2: DEVID1 bit 4 is used to dete rmine the device t ype (REV4 = 1).
2010 Microchip Technology Inc. DS39622L-page 31
PIC18F2XXX/4XXX FAMILY
PIC18F4620 0Ch 000x xxxx
PIC18F4680 0Eh 100x xxxx
PIC18F4682 27h 010x xxxx
PIC18F4685 27h 011x xxxx
TABLE 5-3: PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS
Bit Name Configuration
Words Description
IESO CONFIG1H Internal External Switchover bit
1 = Internal External Switchover mode is enabled
0 = Internal External Switch over mode is disabl ed
FCMEN CONFIG1H Fail- Safe Cloc k Mo nito r Enabl e bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
FOSC<3:0> CONFIG1H Oscillator Selection bits
11xx = External RC oscillator, CLKO function on RA6
101x = External RC oscillator, CLKO function on RA6
1001 = Internal RC oscillator, CLKO function on RA6, port function on RA7
1000 = Internal RC oscillator, port function on RA6, port function on RA7
0111 = External RC oscillator, port function on RA6
0110 = HS oscillator, PLL is enabled (Clock Frequency = 4 x FOSC1)
0101 = EC oscillator, port function on RA6
0100 = EC oscillator, CLKO function on RA6
0011 = External RC oscillator, CLKO function on RA6
0010 = HS oscillator
0001 = XT oscillator
0000 = LP oscillator
FOSC<3:0> CONFIG1H Oscillator Selection bits
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
111x = HS oscillator, PLL is enabled, HS is used by USB
110x = HS oscillator, HS is used by USB
1011 = Internal oscillator, HS is used by USB
1010 = Internal oscillator, XT is used by USB
1001 = Internal oscillator, CLKO function on RA6, EC is used by USB
1000 = Internal oscillator, port function on RA6, EC is used by USB
0111 = EC oscillator , PLL is enabled, CLKO function on RA6, EC is used by USB
0110 = EC oscillator, PLL i s ena bled, port fu nctio n on R A6, EC is used by USB
0101 = EC oscillator, CLKO function on RA6, EC is used by USB
0100 = EC oscillator, port function on RA6, EC is used by USB
001x = XT oscillator, PLL is enabled, XT is used by USB
000x = XT oscillator, XT is used by USB
Note 1: Th e BBS IZ bi ts, BBSI Z< 1: 0> and B BSI Z< 2: 1> bi ts, cannot be ch ang ed once an y of the fo ll owin g
code-pr ot ec t bits are en abl ed: CPB o r CP0, WRTB or WRT0, EB TRB or EB TR0.
2: Not available in PIC18FXX8X and PIC18F2450/4450 devices.
TABLE 5-2: DEVICE ID VALUES (CONTINUED)
Device Device ID Value
DEVID2 DEVID1
Legend: The ‘x’s in DEVID1 con tain th e device rev isio n code.
Note 1: DEVID1 bit 4 is used to dete rmi ne the dev ic e type (REV4 = 0).
2: DEVID1 bit 4 is used to dete rmi ne the dev ic e type (REV4 = 1).
PIC18F2XXX/4XXX FAMILY
DS39622L-page 32 2010 Microchip Technology Inc.
USBDIV CONFIG1L USB Clock Selection bit
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
Selects the clock source for fu ll-speed USB operation :
1 = USB clock source comes from the 96 MHz PLL divided by 2
0 = USB clock source comes dir ectl y from the OSC1/OSC 2 oscillator block;
no divide
CPUDIV<1:0> CONFIG1L CPU System Clock Selection bits
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
11 = CPU system clock divided by 4
10 = CPU system clock divided by 3
01 = CPU system clock divided by 2
00 = No CPU sy stem cl ock div ide
PLLDIV<2:0> CONFIG1L Oscillator Selection bits
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
Divider must be selected to provide a 4 MHz input into the 96 MHz PLL:
111 = Oscillator divided by 12 (48 MHz input)
110 = Oscillator divided by 10 (40 MHz input)
101 = Oscillator divided by 6 (24 MHz input)
100 = Oscillator divided by 5 (20 MHz input)
011 = Oscillator divided by 4 (16 MHz input)
010 = Oscillator divided by 3 (12 MHz input)
001 = Oscillator divided by 2 (8 MHz input)
000 = No divide – oscillator used directly (4 MHz input)
VREGEN CONFIG2L USB Voltage Regulator Enable bit
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
1 = USB voltage regulator is enabled
0 = USB voltage regulator is disabled
BORV<1:0> CONFIG2L Brown-out Reset Voltage bits
11 =V
BOR is set to 2.0V
10 =V
BOR is set to 2.7V
01 =V
BOR is set to 4.2V
00 =V
BOR is set to 4.5V
BOREN<1 :0> CONFIG2L Brown-out Reset Enable bits
11 = Brown-out Reset is enabled in hardware only (SBOREN is disabled)
10 = Brown-out Reset is enabled in ha rdwar e only an d disab led in Slee p mode
SBOREN is disabled)
01 = Brown-out Reset is enabled and controlled by software (SBOREN is
enabled)
00 = Brown-out Reset is disabled in hardware and software
PWRTEN CONFIG2L Power-up Ti mer Enable bit
1 = PWRT is disabled
0 = PWRT is enabled
TABLE 5-3: PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
Note 1: Th e BBS IZ bits, BBS IZ< 1: 0> and BBS IZ< 2: 1> bi ts, cannot be ch ang ed once an y of the fo ll ow in g
code-pr ot ect bits ar e en abl ed: CPB or CP0, WRTB or WRT0, EB TRB or EBTR 0.
2: Not available in PIC18FXX8X and PIC18F2450/4450 devices.
2010 Microchip Technology Inc. DS39622L-page 33
PIC18F2XXX/4XXX FAMILY
WDPS<3:0> CONFIG2H Watchdog Timer Postscaler Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
WDTEN CONFIG2H Watchdog Timer Enable bit
1 = WDT is enabled
0 = WDT is disabled (control is placed on the SWDTEN bit)
MCLRE CONFIG3H MCLR Pin Enable bit
1 =MCLR pin is enabled, RE3 input pin is disabled
0 = RE3 input pin is enabled, MCLR pin is disabled
LPT1 OSC CONFIG3H Low-Po wer Timer1 Oscillator Enable bit
1 = Timer1 is configured for low-power operation
0 = Timer1 is configured for high-power operation
PBADEN CONFIG3H PORTB A/D Enable bit
1 = PORTB A/D<4:0> pins are configured as analog input channels on Reset
0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset
PBADEN CONFIG3H PORTB A/D Enable bit (PIC18FXX8X devices only)
1 = PORTB A/D<4:0> and PORTB A/D<1:0> pins are configured as analog input
channels on Reset
0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset
CCP2MX CONFIG3H CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1(2)
0 = CCP2 input/output is multiplexed with RB3
DEBUG CONFIG4L Background Debugger Enable bit
1 = Background de bugger i s disab led, RB6 a nd RB7 are con figured as general
purpose I/O pins
0 = Background deb ugger is ena bled, RB6 and RB7 are dedicate d to In-Ci rcuit
Debug
XINST CONFIG4L Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode are enabled
0 = Instruction set extension and Indexed Addressing mode are disabled
(Legacy mode)
TABLE 5-3: PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
Note 1: Th e BBS IZ bi ts, BBSI Z< 1: 0> and B BSI Z< 2: 1> bi ts, cannot be ch ang ed once an y of the fo ll owin g
code-pr ot ec t bits are en abl ed: CPB o r CP0, WRTB or WRT0, EB TRB or EB TR0.
2: Not available in PIC18FXX8X and PIC18F2450/4450 devices.
PIC18F2XXX/4XXX FAMILY
DS39622L-page 34 2010 Microchip Technology Inc.
ICPRT CONFIG4L Dedicated In-Circuit (ICD/ICSP™) Port Enable bit
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
1 = ICPORT is enabled
0 = ICPORT is disabled
BBSIZ<1:0>(1) CONFIG4L Boot Block Size Select bits (PIC18F2585/2680/4585/4680 devices only)
11 = 4K words (8 Kbytes) Boot Block
10 = 4K words (8 Kbytes) Boot Block
01 = 2K words (4 Kbytes) Boot Block
00 = 1K word (2 Kbytes) Boot Block
BBSIZ<2:1>(1) CONFIG4L Boot Block Size Select bits (PIC18F2682/2685/4582/4685 devices only)
11 = 4K words (8 Kbytes) Boot Block
10 = 4K words (8 Kbytes) Boot Block
01 = 2K words (4 Kbytes) Boot Block
00 = 1K word (2 Kbytes) Boot Block
BBSIZ<1:0>(1) CONFIG4L Boot Block Size Select bits (PIC18F2321/4321 devices only)
11 = 1K word (2 Kbytes) Boot Block
10 = 1K word (2 Kbytes) Boot Block
01 = 512 words (1 Kbyte) Boot Block
00 = 256 words (512 bytes) Boot Block
Boot Block Size Select bits (PIC18F2221/4221 devices only)
11 = 512 words (1 Kbyte) Boot Block
10 = 512 words (1 Kbyte) Boot Block
01 = 512 words (1 Kbyte) Boot Block
00 = 256 words (512 bytes) Boot Block
BBSIZ(1) CONFIG4L Boot Block Size Select bits
(PIC18F2480/2580/4480/4580 and PIC18F2450/4450 devices only)
1 = 2K words (4 Kbytes) Boot Block
0 = 1K word (2 Kbytes) Boot Block
LVP CONFIG4L Low-Volta ge Programming Enabl e bit
1 = Low-Voltage Programming is enabled, RB5 is the PGM pin
0 = Low-Voltage Programming is disabled, RB5 is an I/O pin
STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow is enabled
0 = Reset on stack overflow/underflow is disabled
CP5 CONFIG5L Code Protection bit (Block 5 code memory area)
(PIC18F2685 and PIC18F4685 devices only)
1 = Block 5 is not code-protected
0 = Block 5 is code-pr otected
CP4 CONFIG5L Code Protection bit (Block 4 code memory area)
(PIC18F2682/2685 and PIC18F4682/4685 devices only)
1 = Block 4 is not code-protected
0 = Block 4 is code-pr otected
CP3 CONFIG5L Code Protection bit (Block 3 code memory area)
1 = Block 3 is not code-protected
0 = Block 3 is code-pr otected
TABLE 5-3: PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
Note 1: Th e BBS IZ bits, BBS IZ< 1: 0> and BBS IZ< 2: 1> bi ts, cannot be ch ang ed once an y of the fo ll ow in g
code-pr ot ect bits ar e en abl ed: CPB or CP0, WRTB or WRT0, EB TRB or EBTR 0.
2: Not available in PIC18FXX8X and PIC18F2450/4450 devices.
2010 Microchip Technology Inc. DS39622L-page 35
PIC18F2XXX/4XXX FAMILY
CP2 CONFIG5L Code Protection bit (Block 2 code memory area)
1 = Block 2 is not code-protected
0 = Block 2 is code-pr otected
CP1 CONFIG5L Code Protection bit (Block 1 code memory area)
1 = Block 1 is not code-protected
0 = Block 1 is code-pr otected
CP0 CONFIG5L Code Protection bit (Block 0 code memory area)
1 = Block 0 is not code-protected
0 = Block 0 is code-pr otected
CPD CONF IG5H Code Protection bit (Data EEPROM)
1 = Data EEPROM is not code-protected
0 = Data EEPROM is code-protected
CPB CONFIG5H Code Protection bit (Boot Block memory area)
1 = Boot Block is not code-protected
0 = Boot Block is code-protected
WRT5 CONFIG6L Write Protection bit (Block 5 code memory area)
(PIC18F2685 and PIC18F4685 devices only)
1 = Block 5 is not write-protected
0 = Block 5 is write-p rotected
WRT4 CONFIG6L Write Protection bit (Block 4 code memory area)
(PIC18F2682/2685 and PIC18F4682/4685 devices only)
1 = Block 4 is not write-protected
0 = Block 4 is write-p rotected
WRT3 CONFIG6L Write Protection bit (Block 3 code memory area)
1 = Block 3 is not write-protected
0 = Block 3 is write-p rotected
WRT2 CONFIG6L Write Protection bit (Block 2 code memory area)
1 = Block 2 is not write-protected
0 = Block 2 is write-p rotected
WRT1 CONFIG6L Write Protection bit (Block 1 code memory area)
1 = Block 1 is not write-protected
0 = Block 1 is write-p rotected
WRT0 CONFIG6L Write Protection bit (Block 0 code memory area)
1 = Block 0 is not write-protected
0 = Block 0 i s write-p rotected
WRTD CONFIG6H Write Protection bit (Data EEPROM)
1 = Data EEPROM is not write-protected
0 = Data EEPROM is write-protected
WRTB CONFIG6H Write Protection bit (Boot Block memory area)
1 = Boot Bloc k is not w rite -pro tected
0 = Boot Block is write-protected
WRTC CONFIG6H Write Protection bit (Configuration registers)
1 = Configuration registers are not write-protected
0 = Configuration registers are write-protected
TABLE 5-3: PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
Note 1: Th e BBS IZ bi ts, BBSI Z< 1: 0> and B BSI Z< 2: 1> bi ts, cannot be ch ang ed once an y of the fo ll owin g
code-pr ot ec t bits are en abl ed: CPB o r CP0, WRTB or WRT0, EB TRB or EB TR0.
2: Not available in PIC18FXX8X and PIC18F2450/4450 devices.
PIC18F2XXX/4XXX FAMILY
DS39622L-page 36 2010 Microchip Technology Inc.
EBTR5 CONFIG7L Table Read Protection bit (Block 5 code memory area)
(PIC18F2685 and PIC18F4685 devices only)
1 = Block 5 is not protected from Table Reads executed in other blocks
0 = Block 5 is protected from Table Reads executed in other blocks
EBTR4 CONFIG7L Table Read Protection bit (Block 4 code memory area)
(PIC18F2682/2685 and PIC18F4682/4685 devices only)
1 = Block 4 is not protected from Table Reads executed in other blocks
0 = Block 4 is protected from Table Reads executed in other blocks
EBTR3 CONFIG7L Table Read Protection bit (Block 3 code memory area)
1 = Block 3 is not protected from Table Reads executed in other blocks
0 = Block 3 is protected from Table Reads executed in other blocks
EBTR2 CONFIG7L Table Read Protection bit (Block 2 code memory area)
1 = Block 2 is not protected from Table Reads executed in other blocks
0 = Block 2 is protected from Table Reads executed in other blocks
EBTR1 CONFIG7L Table Read Protection bit (Block 1 code memory area)
1 = Block 1 is not protected from Table Reads executed in other blocks
0 = Block 1 is protected from Table Reads executed in other blocks
EBTR0 CONFIG7L Table Read Protection bit (Block 0 code memory area)
1 = Block 0 is not protected from Table Reads executed in other blocks
0 = Block 0 is protected from Table Reads executed in other blocks
EBTRB CONFIG7H Table Read Protection bit (Boot Block memory area)
1 = Boot Block is not protected from Table Reads executed in other blocks
0 = Boot Block is protected from Table Reads executed in other blocks
DEV<10:3> DEVID2 Device ID bits
These bits are used with the DEV<2:0> bits in the DEVID1 register to identify
part number.
DEV<2:0> DEVID1 Device ID bits
These bits are used with the DEV<10:3> bits in the DEVID2 register to identify
part number.
REV<4:0> DEVID1 Revision ID bits
These bits are used to indicate the revision of the device. The REV4 bit is
sometimes used to fully specify the device type.
TABLE 5-3: PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Bit Name Configuration
Words Description
Note 1: Th e BBS IZ bits, BBS IZ< 1: 0> and BBS IZ< 2: 1> bi ts, cannot be ch ang ed once an y of the fo ll ow in g
code-pr ot ect bits ar e en abl ed: CPB or CP0, WRTB or WRT0, EB TRB or EBTR 0.
2: Not available in PIC18FXX8X and PIC18F2450/4450 devices.
2010 Microchip Technology Inc. DS39622L-page 37
PIC18F2XXX/4XXX FAMILY
5.3 Single-Supply ICSP Programming
The LVP bit in Configuration register, CONFIG4L,
enables Single-Supply (Low-Voltage) ICSP Program-
ming. The LVP bit defaults to a ‘1’ (enabled) from the
factory.
If Single-Supply Programming mode is not used, the
LVP bit can be programmed to a ‘0’ and RB5/PGM
becomes a digital I/O pi n. However , the LVP bit may only
be programmed by entering the High-Voltage ICSP
mode, where MCLR/VPP/RE3 is raised to VIHH. Once
the L VP bit is programmed to a ‘0’, only the High-V oltage
ICSP mode is available and on ly the High-Voltage ICSP
mode can be used to program the de vice.
5.4 Embedding Configuration Word
Info rmatio n in th e H EX Fi le
To allow portability of code, a PIC18F2XXX/4XXX
fam il y programmer is required to read the Configura-
tion Word locations from the hex file. If Configuration
Word information is not present in the hex file, then a
simple warning message should be issued. Similarly,
while saving a hex file, a ll C on fig ura tion Word informa-
tion must be included. An option to not include the
Configuration Word information may be provided.
When embedding Configuration Word information in
the hex file, it should start at address, 300000h.
Microchip Technology Inc. feels strongly that this
featur e is imp orta nt for th e bene fit of t he end cu stome r.
5.5 Embedding Data EEPROM
Info rmatio n In th e H EX Fi le
To allow portability of code, a PIC18F2XXX/4XXX
family programmer is required to read the data
EEPROM information from the hex file. If data
EEPROM information is not present, a simple warning
message should be issued. Similarly, when saving a
hex file, all data EEPROM information must be
included. An option to not include the data EEPROM
information may be provided. When embedding data
EEPROM information in the hex file, it should start at
address, F00000h.
Microchip Technology Inc. believes that this feature is
important for the benefit of the end customer.
5.6 Checksum Comput ation
The check s um is cal cu lat ed by sum mi ng the foll owing:
• The contents of all code memo ry locations
• The Configu rati on Words, approp riat ely m asked
• ID locations (if any block is code-protected)
The Least Significant 16 bits of this sum is the checksum.
The cont ent s of the dat a EEPROM are no t used.
5.6.1 PROGRAM MEMORY
When program memory contents are summed, each
16-bit word is added to the checksum. The contents of
program memory, from 000000h to the end of the last
program memory block, are used for this calculation.
Overflows from bit 15 may be ignored.
5.6.2 CONFIGURATION WORDS
For checksum calculations, unimplemented bits in
Configuration Words should be ignored as such bits
always read back as ‘1’s. Each 8-bit Configuration
Word is ANDed with a corresponding mask to prevent
unused bits from affecting checksum calculations.
The mask contain s a ‘0’ in uni mplemented bit positions ,
or a ‘1’ where a choice can be made. When ANDed
with the value read out of a Configuration Word, only
implemented bits remain. A list of suitable masks is
provided in Table 5-5.
5.6.3 ID LOCATIONS
Normally, the contents of these locations are defined by
the user, but MPLAB® IDE provides the option of writing
the device’s unprotected 16-bit checksum in the 16 Most
Significant bits of the ID locations (see MPLAB IDE Con-
figure/ID Memory” menu). The l ower 16 bits are not used
and remain clear . This is the sum of all program memory
contents and Configuration Words (appropriately
masked) before any code protec tion is enab led.
If the user elects to define the contents of the ID
locations, nothing about protected blocks can be
known. If the user uses the preprotected checksum,
provided by MPLAB IDE, an indirect characteristic of
the programmed code is provided.
5.6.4 CODE PROTECTION
Blocks that are code-p rotected read back as all ‘0’s and
have no effect on checksum calculations. If any block
is cod e-protecte d, then the c on ten t s of the ID location s
are included in the checksum calculation.
All Configuration Words and the ID locations can
always be read out normally, even when the device is
fully c ode-prot ect ed. Chec king t he code prot ection se t-
tings in Confi gurati on W ords c an dire ct wh ich, if any, of
the program memory blocks can be read, and if the ID
locations should be used for checksum calculations.
Note1: The High-Voltage ICSP mode is
always available, regardless of the
state of the LVP bit, by applying V IHH to
the MCLR/VPP/RE3 pin.
2: While in Low-Voltage ICSP mode, the
RB5 pin can no longer be used as a
general purpose I/O.
PIC18F2XXX/4XXX FAMILY
DS39622L-page 38 2010 Microchip Technology Inc.
TABLE 5-4: DEVICE BLOCK LOCATIONS AND SIZES
Device Memory
Size
(Bytes) Pins
Ending Address Size (Bytes)
Boot
Block Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Boot
Block Block 0 Remaining
Blocks Device
Total
PIC18F2221 4K 28 0001FF 0007FF 000FFF — — — — 512 1536 2048 4096
0003FF 1024 1024
PIC18F2321 8K 28 0001FF 000FFF 001FFF — — — — 512 3584 4096 81920003FF 1024 3072
0007FF 2048 2048
PIC18F2410 16K 28 0007FF 001FFF 003FFF — — — — 2048 6144 8192 16384
PIC18F2420 16K 28 0007FF 001FFF 003FFF — — — — 2048 6144 8192 16384
PIC18F2423 16K 28 0007FF 001FFF 003FFF — — — — 2048 6144 8192 16384
PIC18F2450 16K 28 0007FF 001FFF 003FFF — — — — 2048 6144 8192 16384
000FFF 4096 4096
PIC18F2455 24K 28 0007FF 001FFF 003FFF 005FFF — — — 2048 6144 16384 24576
PIC18F2458 24K 28 0007FF 001FFF 003FFF 005FFF — — — 2048 6144 16384 24576
PIC18F2480 16K 28 0007FF 001FFF 003FFF — — — — 2048 6144 8192 16384
000FFF 4096 4096
PIC18F2510 32K 28 0007FF 001FFF 003FFF 005FFF 007FFF — — 2048 6144 24576 32768
PIC18F2515 48K 28 0007FF 003FFF 007FFF 00BFFF — — — 2048 14336 32768 49152
PIC18F2520 32K 28 0007FF 001FFF 003FFF 005FFF 007FFF — — 2048 14336 16384 32768
PIC18F2523 32K 28 0007FF 001FFF 003FFF 005FFF 007FFF — — 2048 14336 16384 32768
PIC18F2525 48K 28 0007FF 003FFF 007FFF 00BFFF — — — 2048 14336 32768 49152
PIC18F2550 32K 28 0007FF 001FFF 003FFF 005FFF 007FFF — — 2048 6144 24576 32768
PIC18F2553 32K 28 0007FF 001FFF 003FFF 005FFF 007FFF — — 2048 6144 24576 32768
PIC18F2580 32K 28 0007FF 001FFF 003FFF 005FFF 007FFF — — 2048 6144 24576 32768
000FFF 4096 4096
PIC18F2585 48K 28 0007FF 003FFF 007FFF 00BFFF — — — 2048 14336 32768 49152000FFF 4096 12288
001FFF 8192 8192
PIC18F2610 64K 28 0007FF 003FFF 007FFF 00BFFF 00FFFF — — 2048 14336 49152 65536
PIC18F2620 64K 28 0007FF 003FFF 007FFF 00BFFF 00FFFF — — 2048 14336 49152 65536
PIC18F2680 64K 28 0007FF 003FFF 007FFF 00BFFF 00FFFF — — 2048 14336 49152 65536000FFF 4096 12288
001FFF 8192 8192
PIC18F2682 80K 28 0007FF 003FFF 007FFF 00BFFF 00FFFF 013FFF —2048 14336 65536 81920000FFF 4096 12288
001FFF 8192 8192
PIC18F2685 96K 28 0007FF 003FFF 007FFF 00BFFF 00FFFF 013FFF 017FFF 2048 14336 81920 98304000FFF 4096 12288
001FFF 8192 8192
PIC18F4221 4K 40 0001FF 0007FF 000FFF — — — — 512 1536 2048 4096
0003FF 1024 1024
PIC18F4321 8K 40 0001FF 000FFF 001FFF — — — — 512 3584 4096 81920003FF 1024 3072
0007FF 2048 2048
PIC18F4410 16K 40 0007FF 001FFF 003FFF — — — — 2048 6144 8192 16384
PIC18F4420 16K 40 0007FF 001FFF 003FFF — — — — 2048 6144 8192 16384
PIC18F4423 16K 40 0007FF 001FFF 003FFF — — — — 2048 6144 8192 16384
PIC18F4450 16K 40 0007FF 001FFF 003FFF — — — — 2048 6144 8192 16384
000FFF 4096 4096
Legend: — = unimplemented.
2010 Microchip Technology Inc. DS39622L-page 39
PIC18F2XXX/4XXX FAMILY
PIC18F4455 24K 40 0007FF 001FFF 003FFF 005FFF — — — 2048 6144 16384 24576
PIC18F4458 24K 40 0007FF 001FFF 003FFF 005FFF — — — 2048 6144 16384 24576
PIC18F4480 16K 40 0007FF 001FFF 003FFF — — — — 2048 6144 8192 16384
000FFF 4096 4096
PIC18F4510 32K 40 0007FF 001FFF 003FFF 005FFF 007FFF — — 2048 6144 24576 32768
PIC18F4515 48K 40 0007FF 003FFF 007FFF 00BFFF — — — 2048 14336 32768 49152
PIC18F4520 32K 40 0007FF 001FFF 003FFF 005FFF 007FFF — — 2048 14336 16384 32768
PIC18F4523 32K 40 0007FF 001FFF 003FFF 005FFF 007FFF — — 2048 14336 16384 32768
PIC18F4525 48K 40 0007FF 003FFF 007FFF 00BFFF — — — 2048 14336 32768 49152
PIC18F4550 32K 40 0007FF 001FFF 003FFF 005FFF 007FFF — — 2048 6144 24576 32768
PIC18F4553 32K 40 0007FF 001FFF 003FFF 005FFF 007FFF — — 2048 6144 24576 32768
PIC18F4580 32K 40 0007FF 001FFF 003FFF 005FFF 007FFF — — 2048 6144 24576 32768
000FFF 4096 4096
PIC18F4585 48K 40 0007FF 003FFF 007FFF 00BFFF — — — 2048 14336 32768 49152000FFF 4096 12288
001FFF 8192 8192
PIC18F4610 64K 40 0007FF 003FFF 007FFF 00BFFF 00FFFF — — 2048 14336 49152 65536
PIC18F4620 64K 40 0007FF 003FFF 007FFF 00BFFF 00FFFF — — 2048 14336 49152 65536
PIC18F4680 64K 40 0007FF 003FFF 007FFF 00BFFF 00FFFF — — 2048 14336 49152 65536000FFF 4096 12288
001FFF 8192 8192
PIC18F4682 80K 40 0007FF 003FFF 007FFF 00BFFF 00FFFF 013FFF —2048 14336 65536 81920000FFF 4096 12288
001FFF 8192 8192
PIC18F4685 96K 44 0007FF 003FFF 007FFF 00BFFF 00FFFF 013FFF 017FFF 2048 14336 81920 98304000FFF 4096 12288
001FFF 8192 8192
TABLE 5-4: DEVICE BLOCK LOCATIONS AND SIZES (CONTINUED)
Device Memory
Size
(Bytes) Pins
Ending Address Size (Bytes)
Boot
Block Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Boot
Block Block 0 Remaining
Blocks Device
Total
Legend: — = unimplemented.
PIC18F2XXX/4XXX FAMILY
DS39622L-page 40 2010 Microchip Technology Inc.
TABLE 5-5: CONFIGURATION WORD MASKS FOR COMPU TIN G CHECKSUM S
Device
Configuration Word (CONFIGxx)
1L 1H 2L 2H 3L 3H 4L 4H 5L 5H 6L 6H 7L 7H
Address (30000xh)
0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh
PIC18F2221 00 CF 1F 1F 00 87 F5 00 03 C0 03 E0 03 40
PIC18F2321 00 CF 1F 1F 00 87 F5 00 03 C0 03 E0 03 40
PIC18F2410 00 CF 1F 1F 00 87 C5 00 03 C0 03 E0 03 40
PIC18F2420 00 CF 1F 1F 00 87 C5 00 03 C0 03 E0 03 40
PIC18F2423 00 CF 1F 1F 00 87 C5 00 03 C0 03 E0 03 40
PIC18F2450 3F CF 3F 1F 00 86 ED 00 03 40 03 60 03 40
PIC18F2455 3F CF 3F 1F 00 87 E5 00 07 C0 07 E0 07 40
PIC18F2458 3F CF 3F 1F 00 87 E5 00 07 C0 07 E0 07 40
PIC18F2480 00 CF 1F 1F 00 86 D5 00 03 C0 03 E0 03 40
PIC18F2510 00 1F 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
PIC18F2515 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
PIC18F2520 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
PIC18F2523 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
PIC18F2525 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
PIC18F2550 3F CF 3F 1F 00 87 E5 00 0F C0 0F E0 0F 40
PIC18F2553 3F CF 3F 1F 00 87 E5 00 0F C0 0F E0 0F 40
PIC18F2580 00 CF 1F 1F 00 86 E5 00 0F C0 0F E0 0F 40
PIC18F2585 00 CF 1F 1F 00 86 C5 00 0F C0 0F E0 0F 40
PIC18F2610 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
PIC18F2620 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
PIC18F2680 00 CF 1F 1F 00 86 C5 00 0F C0 0F E0 0F 40
PIC18F2682 00 CF 1F 1F 00 86 C5 00 3F C0 3F E0 3F 40
PIC18F2685 00 CF 1F 1F 00 86 C5 00 3F C0 3F E0 3F 40
PIC18F4221 00 CF 1F 1F 00 87 F5 00 03 C0 03 E0 03 40
PIC18F4321 00 CF 1F 1F 00 87 F5 00 03 C0 03 E0 03 40
PIC18F4410 00 CF 1F 1F 00 87 C5 00 03 C0 03 E0 03 40
PIC18F4420 00 CF 1F 1F 00 87 C5 00 03 C0 03 E0 03 40
PIC18F4423 00 CF 1F 1F 00 87 C5 00 03 C0 03 E0 03 40
PIC18F4450 3F CF 3F 1F 00 86 ED 00 03 40 03 60 03 40
PIC18F4455 3F CF 3F 1F 00 87 E5 00 07 C0 07 E0 07 40
PIC18F4458 3F CF 3F 1F 00 87 E5 00 07 C0 07 E0 07 40
PIC18F4480 00 CF 1F 1F 00 86 D5 00 03 C0 03 E0 03 40
PIC18F4510 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
PIC18F4515 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
PIC18F4520 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
PIC18F4523 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
PIC18F4525 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
PIC18F4550 3F CF 3F 1F 00 87 E5 00 0F C0 0F E0 0F 40
PIC18F4553 3F CF 3F 1F 00 87 E5 00 0F C0 0F E0 0F 40
PIC18F4580 00 CF 1F 1F 00 86 E5 00 0F C0 0F E0 0F 40
PIC18F4585 00 CF 1F 1F 00 86 C5 00 0F C0 0F E0 0F 40
PIC18F4610 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
Legend: Shaded cells are unimplemented.
2010 Microchip Technology Inc. DS39622L-page 41
PIC18F2XXX/4XXX FAMILY
PIC18F4620 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40
PIC18F4680 00 CF 1F 1F 00 86 C5 00 0F C0 0F E0 0F 40
PIC18F4682 00 CF 1F 1F 00 86 C5 00 3F C0 3F E0 3F 40
PIC18F4685 00 CF 1F 1F 00 86 C5 00 3F C0 3F E0 3F 40
TABLE 5-5: CONFIGURATION WORD MASKS FOR COMPUTI NG CHECKSUM S (CONTINUED)
Device
Configuration Word (CONFIGxx)
1L 1H 2L 2H 3L 3H 4L 4H 5L 5H 6L 6H 7L 7H
Address (30000xh)
0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh
Legend: Shaded cells are unimplemented.
PIC18F2XXX/4XXX FAMILY
DS39622L-page 42 2010 Microchip Technology Inc.
6.0 AC/DC CHAR ACTERISTICS TIMING REQUIREMENTS
FOR PROGRAM/VERIFY TEST MODE
Standard Ope ra ting Condition s
Oper ati ng Tem pe ra tu re : 25C i s re commended
Param
No. Sym Characteristic Min Max Units Conditions
D110 VIHH High-Voltage Programming Voltage on
MCLR/VPP/RE3 VDD + 4.0 12 .5 V (Note 2)
D110A VIHL Low- Voltage Progra m ming Vo l tage on
MCLR/VPP/RE3 2.00 5.50 V (Not e 2)
D111 VDD Supply Voltage During Programming 2.00 5.50 V Externally timed,
Row Erases and all writes
3.0 5.50 V Self-timed,
Bulk Erases only (Note 3)
D112 IPP Prog ra m m in g Cur r ent on M C L R /VPP/RE3 — 300 A(N ot e 2)
D113 IDDP Supply Current During Programming — 10 mA
D031 VIL Input Low Volt a ge VSS 0.2 VDD V
D041 VIH Input High Voltage 0.8 VDD VDD V
D080 VOL Output Low Voltag e — 0.6 V I OL = 8.5 mA @ 4. 5V
D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA @ 4.5V
D012 CIO Capacitive Loading on I/O pin (PGD) — 50 pF To meet AC s pec ifications
P1 TRMCLR/VPP/RE3 Rise Time to Enter
Program/ Verify mode —1.0s(Notes 1, 2)
P2 TPGC Serial Clo ck (PGC ) P eriod 100 — ns V DD = 5. 0V
1—sVDD = 2.0V
P2A TPGCL Serial C loc k (P GC ) L ow Time 40 — ns V DD = 5. 0V
400 — ns VDD = 2.0V
P2B TPGCH Serial C loc k (P GC ) H igh Time 40 — ns VDD = 5. 0V
400 — ns VDD = 2.0V
P3 TSET1 Input Data Setup Time to Serial Clock 15 — ns
P4 THLD1 Input Data Hold Time from PGC 15 — ns
P5 TDLY1 Delay Between 4-Bit C om m an d and Comm a nd
Operand 40 — ns
P5A TDLY1ADelay Bet w e en 4-Bit Comm and Ope ra nd an d
Next 4-Bit Command 40 — ns
P6 TDLY2 Delay Between Last PGC of Command Byte to
First PGC of Read of Data Word 20 — ns
P9 TDLY5 PGC High Time (minimum programming time) 1 — ms Externally timed
P10 TDLY6 PGC Low T ime After Programming
(high-vo l tag e discha rge ti m e) 100 — s
P11 TDLY7 Delay to Allow Self-Timed Data Write or
Bulk Erase to Occur 5—ms
Note 1: Do not allow excess time when tr ans i tioning MCLR between VIL and VIHH. This can cause spurious program
executions to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS , HS /P LL and XT modes only) +
2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only)
where TCY is the instruction cycle time, TPWRT i s the P ower-up Timer period a nd TOSC is the oscillator period. For
speci fic val ues, refer to th e El ect r ical C har ac t eristics sec tio n of the device data she et for th e parti cular device .
2: When IC PRT = 1, this specification also applies to ICVPP.
3: At 0°C-50°C.
2010 Microchip Technology Inc. DS39622L-page 43
PIC18F2XXX/4XXX FAMILY
P11A TDRWT Data Write Polling Time 4 — ms
P12 THLD2 Input Da ta Hold Time from MCLR/VPP/RE3 2—s
P13 TSET2VDD Setup Time to MCLR /VPP/RE 3 100 — ns (Note 2)
P14 TVALID Data Out Valid from PGC 10 — ns
P15 TSET3PGM Setup Time to MCLR/VPP/RE3 2—s(Note 2)
P16 TDLY8 Delay Between Last PG C and MCLR/VPP/RE3 0—s
P17 THLD3MCLR/VPP/RE3 to VDD —100ns
P18 THLD4MCLR/VPP/RE3 to PGM 0—s
6.0 AC/DC CHA RACTERISTICS TIMING REQUIREMENTS
FOR PROGRAM/VERIFY TEST MODE (CONTINUED)
Standard Ope ra ting Condition s
Oper ati ng Tem pe ra tu re : 25C i s re commended
Param
No. Sym Characteristic Min Max Units Conditions
Note 1: Do not allow excess time when tr ans i tioning MCLR between VIL and VIHH. This can cause spurious program
executions to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS , HS /P LL and XT modes only) +
2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only)
where TCY is the instruction cycle time, TPWRT i s the P ower-up Timer period a nd TOSC is the oscillator period. For
speci fic val ues, refer to th e El ect r ical C har ac t er is tics section of the device data she et for th e particul ar device .
2: When IC PRT = 1, this specification also applies to ICVPP.
3: At 0°C-50°C.
PIC18F2XXX/4XXX FAMILY
DS39622L-page 44 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39622L-page 45
Information contained in this publication regarding device
applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce
and may be supers eded by updates . I t is you r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPL AB, PIC , PI Cmi cro, PI CSTART,
PIC32 logo, rfPIC and UNI/O are registered trademark s of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Em bedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In - Circuit Serial
Programming, ICSP, Mindi, MiWi, MPAS M, MPLAB Cert ified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Inc orporated, Pr inted in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-578-7
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market t oday, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® co de hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39622L-page 46 2010 Microchip Technology Inc.
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