Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI(R) MCU ADuC702x Series Preliminary Technical Data FEATURES 4 X General Purpose Timers Wake-up and Watchdog Timers Power Supply Monitor Three-phase 16-bit PWM generator* PLA - Programmable Logic (Array) Power Specified for 3V operation Active Mode: 3mA (@1MHz) 50mA (@45MHz) Packages and Temperature Range From 40 lead 6x6mm LFCSP to 80 pin LQFP* Fully specified for -40C to 125C operation Tools Low-Cost QuickStart Development System Full Third-Party Support Analog I/O Multi-Channel, 12-bit, 1MSPS ADC - Up to 16 ADC channels * Fully differential and single-ended modes 0 to VREF Analog Input Range 12-bit Voltage Output DACs - Up to 4 DAC outputs available* On-Chip 20ppm/C Voltage Reference On-Chip Temperature Sensor (3C) Uncommitted Voltage Comparator Microcontroller ARM7TDMI Core, 16/32-bit RISC architecture JTAG Port supports code download and debug Clocking options: - Trimmed On-Chip Oscillator ( 3%) - External Watch crystal - External clock source 45MHz PLL with Programmable Divider Memory 62k Bytes Flash/EE Memory, 8k Bytes SRAM In-Circuit Download, JTAG based Debug Software triggered in-circuit re-programmability On-Chip Peripherals UART, 2 X I2C and SPI Serial I/O Up to 40-Pin GPIO Port* * Package, PWM, GPIO availability and number of Analog I/O depend on part model. See page 9. APPLICATIONS Industrial Control and Automation Systems Smart Sensors, Precision Instrumentation Base Station Systems, Optical Networking (See general description on page 11) FUNCTIONAL BLOCK DIAGRAM ADC0 ... ... MUX 12-BIT DAC DAC0 12-BIT DAC DAC1 12-BIT DAC DAC2 12-BIT DAC DAC3 ADuC7026* 1MSPS 12-BIT ADC ADC11 CMP0 + CMP1 CMPOUT - TEMP SENSOR BANDGAP REF PWM0H VREF PWM0L XCLKI XCLKO OSC & PLL PSM RST POR ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS PLA 2kX32 SRAM 31kX16 FLASH/EEPROM 4 GEN. PURPOSE TIMERS SERIAL I/O UART, SPI, I2C Threephase PWM PWM1H PWM1L PWM2H GPIO JTAG PWM2L EXT. MEMORY INTERFACE Figure 1 Rev. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. ADuC702x Series Preliminary Technical Data TABLE OF CONTENTS ADuC702x--Specifications ............................................................ 3 Reset and Remap ........................................................................ 36 Terminology ...................................................................................... 6 Other analog peripherals............................................................... 37 Absolute Maximum Ratings............................................................ 7 DAC.............................................................................................. 37 Ordering Guide............................................................................. 9 Power Supply Monitor ............................................................... 39 Pin function descriptions .............................................................. 10 Comparator ................................................................................. 39 General Description ....................................................................... 19 Oscillator and PLL - Power control ......................................... 40 Overview of the ARM7TDMI core.......................................... 19 Digital peripherals.......................................................................... 42 Memory organisation................................................................. 21 Three-phase PWM..................................................................... 42 ADC circuit information ............................................................... 26 General Purpose I/O.................................................................. 49 General Overview....................................................................... 26 Serial Port Mux........................................................................... 52 ADC Transfer Function............................................................. 26 Programmable Logic Array (PLA)........................................... 62 Typical Operation....................................................................... 27 Processor reference peripherals.................................................... 65 Converter operation................................................................... 29 Interrupt System ......................................................................... 65 Driving the analog inputs.......................................................... 30 Timers .......................................................................................... 67 ADC Calibration ........................................................................ 30 ADuC702x Hardware Design considerations ............................ 75 Temperature Sensor ................................................................... 30 Power supplies ............................................................................ 75 Bandgap Reference ..................................................................... 30 Grounding and Board Layout Recommendations................. 75 Nonvolatile Flash/EE Memory ..................................................... 32 Clock Oscillator .......................................................................... 76 Flash/EE memory overview ...................................................... 32 Power-on reset operation .......................................................... 76 Flash/EE Memory and the ADuC702x.................................... 32 Typical sysem configuration ..................................................... 77 Flash/EE memory security ........................................................ 32 Development Tools ........................................................................ 78 Flash/EE Control Interface........................................................ 33 In-Circuit Serial Downloader................................................... 78 Execution time from SRAM and FLASH/EE ......................... 34 Outline Dimensions ....................................................................... 79 Rev. PrB | Page 2 of 80 Preliminary Technical Data ADuC702x Series ADUC702X--SPECIFICATIONS 1 Table 1. (AVDD = IOVDD = 2.7 V to 3.6 V, VREF = 2.5 V Internal Reference, fCORE = 45MHz, All specifications TA = TMAX to TMIN, unless otherwise noted.) Parameter ADC CHANNEL SPECIFICATIONS ADC Powerup Time DC Accuracy 2, 3 Resolution Integral Nonlinearity Integral Nonlinearity 4 Differential Nonlinearity Differential Nonlinearity 4 DC Code Distribution CALIBRATED ENDPOINT ERRORS 5 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 6 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk 7 ANALOG INPUT Input Voltage Ranges Differential mode Single-ended mode Leakage Current Input Capacitance ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT9 Input Voltage Range Input Impedance DAC CHANNEL SPECIFICATIONS DC ACCURACY Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Gain Error Mismatch ADuC702x Unit 500 uS Test Conditions/Comments fSAMPLE = 1MSPS 12 1.5 0.5 2.0 +1/-0.9 0.5 +1/-0.9 1 Bits LSB max LSB typ LSB max LSB max LSB typ LSB max LSB typ 5 1 5 1 LSB max LSB typ LSB max LSB typ 71 -78 -78 -80 dB typ dB typ dB typ dB typ VCM8VREF/2 0 to VREF 5 20 Volts Volts A max pF typ 2.5 10 10 80 10 1 V mV max ppm/C typ dB typ typ ms typ 0.625 AVDD TBD V min V max K typ 2.5V internal reference 2.5V internal reference 1.0V external reference 2.5V internal reference 2.5V internal reference 1.0V external reference ADC input is a dc voltage Fin = 10kHz Sine Wave, fSAMPLE = 1MSPS During ADC Acquisition 0.47F from VREF to AGND Measured at TA = 25C RL = 5k, CL = 100pF 12 2 1 2 5 0.5 TBD Bits LSB typ LSB max mV max mV max % max % typ Rev. PrB | Page 3 of 80 Guaranteed Monotonic DAC output unbuffered DAC output buffered % of fullscale on DAC0 ADuC702x Series Parameter ANALOG OUTPUTS Output Voltage Range_0 Ouput Voltage Range_1 Output Voltage Range_2 Output Impedance DAC AC CHARACTERISTICS Voltage Output Settling Time Voltage Output Settling Time Digital to Analog Glitch Energy COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance Hysteresis Response Time TEMPERATURE SENSOR Voltage Output at 25C Voltage TC Accuracy POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Power Supply Trip Point Accuracy Watchdog Timer (WDT)4 Timeout Period Flash/EE MEMORY Endurance10 Data Retention11 Digital Inputs Input Leakage Current Input Capacitance Logic Inputs4 VINL, Input Low Voltage VINH, Input High Voltage Logic Outputs VOH, Output High Voltage VOL, Output Low Voltage12 MCU CLOCK RATE STARTUP TIME At Power-On From Idle Mode From Power-Down Mode Programmable Logic Array (PLA) Propagation Delay Preliminary Technical Data ADuC702x Unit Test Conditions/Comments 0 to DACREF 0 to 2.5V 0 to DACVDD V typ V typ DACREF range: DACGND to DACVDD 10 typ 10 15 TBD s typ s typ nV-sec typ DAC Output buffered DAC Output unbuffered I LSB change at major carry 10 5 AGND to AVDD-1.2 7 5 10 1 10 mV nA typ Vmin/Vmax pF typ mV min mv max s min s max Hysteresis can be turned on or off via the CMPHYST bit in the CMPCON register Response time may be modified via the CMPRES bits in the CMPCON register TBD -1.5 3 mV typ mV/C typ C typ 2.79 3.07 2.5 V V % max 0 TBD ms min ms max 10,000 30 Cycles min Years min 10 1 10 A max A typ pF typ 0.4 2.0 V max V min IOVDD - 400mV 0.4 355.5 45.5 V min V max kHz min MHz max V typ Two selectable Trip Points Of the selected nominal Trip Point Voltage TJ = 55C All digital inputs including XTAL1 and XTAL2 All Logic inputs including XTAL1 and XTAL2 ISOURCE = 1.6mA ISINK = 1.6mA 8 programmable core clock selections within this range Core Clock = TBD MHz TBD TBD TBD TBD ns typ Rev. PrB | Page 4 of 80 From input pin to output pin Preliminary Technical Data Parameter POWER REQUIREMENTS 13, 14 Power Supply Voltage Range AVDD - AGND and IOVDD - IOGND ADuC702x Series ADuC702x Unit 2.7 3.6 V min V max Power Supply Current Normal Mode 3mA 5 50 60 mA typ mA max mA typ mA max Power Supply Current Idle Mode 1 mA max Power Supply Current Power Down Mode 30 100 A typ A max 1 Test Conditions/Comments 1MHz clock 1MHz clock 45MHz clock 45MHz clock External Crystal or Internal Osc ON External Crystal or Internal Osc ON Temperature Range -40 to +85C All ADC Channel Specifications are guaranteed during normal MicroConverter core operation. These specification apply to all ADC input channels. 4 These numbers are not production tested but are supported by design and/or characterization data on production release. 5 Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint and achieve these specifications.. 6 SNR calculation includes distortion and noise components. 7 Channel-to-channel crosstalk is measured on adjacent channels. 8 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 9 When using an external reference input pin, the internal reference must be disabled by setting the lsb in the REFCON Memeory Mapped Register to 0. 10 Endurance is qualified to 50,000 cycles as per JEDEC Std. 22 method A117 and measured at -40C, +25C and +85C. Typical endurance at 25C is 70,000 cycles. 11 Retention lifetime equivalent at junction temperature (Tj) = 55C as per JEDEC Std. 22 method A117. Retention lifetime will derate with junction temperature. 12 Test carried out with a maximum of 20 I/O set to a low output level. 13 Power supply current consumption is measured in normal, idle and power-down modes under the following conditions: Normal Mode: TBD Idle Mode: TBD Power-Down: TBD 14 DVDD power supply current increases typically by TBD mA during a Flash/EE memory program or erase cycle. 2 3 Rev. PrB | Page 5 of 80 ADuC702x Series Preliminary Technical Data TERMINOLOGY ADC Specifications Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition and full scale, a point 1/2 LSB above the last code transition. fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitisation process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Differential Nonlinearity Thus for a 12-bit converter, this is 74 dB. This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Total Harmonic Distortion Offset Error Total Harmonic Distortion is the ratio of the rms sum of the harmonics to the fundamental. This is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., +1/2 LSB. DAC SPECIFICATIONS Gain Error Relative Accuracy This is the deviation of the last code transition from the ideal AIN voltage (Full Scale - 1.5 LSB) after the offset error has been adjusted out. Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Signal to (Noise + Distortion) Ratio Voltage Output Settling Time This is the measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the This is the amount of time it takes for the output to settle to within a 1 LSB level for a full-scale input change.. Rev. PrB | Page 6 of 80 Preliminary Technical Data ADuC702x Series ABSOLUTE MAXIMUM RATINGS Table 2. Absolute Maximum Ratings (TA = 25C unless otherwise noted) DVDD = IOVDD , AGND = REFGND = DACGND = GNDREF Parameter AVDD to DVDD AGND to DGND DVDD to DGND, AVDD to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND VREF to AGND Analog Inputs to AGND Operating Temperature Range Industrial ADuC702x Storage Temperature Range Junction Temperature JA Thermal Impedance (CSP) JA Thermal Impedance (LQFP) Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3V to +0.3V -0.3V to +0.3V -0.3V to +7V -0.3V to +5.5V -0.3V to +5.5V -0.3V to AVDD+0.3V -0.3V to AVDD+0.3V -40C to +125C TBD 125C TBD TBD TBD TBD Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD Caution ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrB | Page 7 of 80 ADuC702x Series Preliminary Technical Data PIN CONFIGURATION 40-Lead CSP 40 31 PIN 1 IDENTIFIER 1 64-Lead LQFP 30 64 ADuC7020/21/22 TOP VIEW (Not to Scale) 1 49 ADuC7024/ADuC7025 64-LEAD LQFP 21 10 48 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) 11 20 64-Lead CSP 64 16 49 PIN 1 IDENTIFIER 1 33 32 17 48 80-Lead LQFP ADuC7024/ADuC7025 TOP VIEW (Not to Scale) 80 1 16 61 60 PIN 1 IDENTIFIER 33 17 32 ADuC7026/ADuC7027 80-LEAD LQFP TOP VIEW (Not to Scale) 20 41 21 Rev. PrB | Page 8 of 80 40 Preliminary Technical Data ADuC702x Series ORDERING GUIDE Model ADC Channels DAC Channels FLASH / RAM PWM ADuC7020BCP62 5 4 62kB/8kB ADuC7021BCP62 8 2 ADuC7021BCP32 8 ADuC7021ACP32 ADuC7022BCP62 8 (10 Bit NMC) 10 ADuC7022BCP32 ADuC7022ACP32 GPIO Temp Range Package Description Package Option Single 14 Single 13 2 32kB/4kB Single 13 2 32kB/4kB Single 13 62kB/8kB Single 13 10 32kB/4kB Single 13 62kB/8kB Single 13 ADuC7024BCP62 10 (10 Bit NMC) 10 2 62kB/8kB 30 ADuC7024BST62 10 2 62kB/8kB Three Phase Three Phase ADuC7025BCP62 12 62kB/8kB 30 ADuC7025BCP32 12 32kB/4kB ADuC7026BST62 12 Three Phase Three Phase Three Phase ADuC7027BST62 16 62kB/8kB ADuC7027AST62 16 (10 Bit NMC) 62kB/8kB 40-Lead Chip Scale Package 40-Lead Chip Scale Package 40-Lead Chip Scale Package 40-Lead Chip Scale Package 40-Lead Chip Scale Package 40-Lead Chip Scale Package 40-Lead Chip Scale Package 64-Lead Chip Scale Package 64 Lead Plastic Quad Flatpack 64-Lead Chip Scale Package 64-Lead Chip Scale Package 80 Lead Plastic Quad Flatpack 80 Lead Plastic Quad Flatpack 80 Lead Plastic Quad Flatpack Development System Development System Development System CP-40 62kB/8kB -40C to + 85C -40C to + 85C -40C to + 85C -40C to + 85C -40C to + 85C -40C to + 85C -40C to + 85C -40C to + 85C -40C to + 125C 4 62kB/8kB Ext Memory 30 30 -40C to + 85C -40C to + 85C -40C to + 125C Yes 40 Three Phase Yes 40 -40C to + 125C Three Phase Yes 40 -40C to + 125C EVAL-ADuC7020QS EVAL-ADuC7024QS EVAL-ADuC7026QS Contact the factory for chip availability. Rev. PrB | Page 9 of 80 CP-40 CP-40 CP-40 CP-40 CP-40 CP-40 CP-64-1 ST-64 CP-64-1 CP-64-1 ST-80 ST-80 ST-80 ADuC702x Series Preliminary Technical Data PIN FUNCTION DESCRIPTIONS - ADUC7020/ADUC7021/ADUC7022 Table 3. Pin Function Descriptions Pin# ADuC702X Mnemonic Type* ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 I I I I I I I I I I 6 GNDREF S 6 7 8 9 7 8 DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 TMS TDI I/O I/O I/O I/O I I 10 10 9 BM/P0.0/CMPOUT/P LAI[7] I/O 11 11 10 P0.6/T1/MRST/PLA O[3] O 12 13 14 15 12 13 14 15 11 12 13 14 TCK TDO IOGND IOVDD I O S S 16 16 15 LVDD S 17 17 16 DGND S 18 18 17 P0.3/TRST/ADCBUSY I 19 19 18 RST I 20 20 19 IRQ0/P0.4/CONVST ART/PLAO[1] I/O 21 21 20 IRQ1/P0.5/ADCBUSY /PLAO[2] I/O 22 22 21 P2.0/SPM9/PLAO[ 5]/CONVSTART I/O 23 23 22 P0.7/ECLK/SPM8/ PLAO[4]/XCLK I/O 7020 38 39 40 1 2 - 7021 37 38 39 40 1 2 3 4 - 7022 36 37 38 39 40 1 2 3 4 5 3 5 4 5 6 7 8 9 Function Single-ended or differential Analog input 0 Single-ended or differential Analog input 1 Single-ended or differential Analog input 2 / Comparator Positive Input Single-ended or differential Analog input 3 / Comparator Negative Input Single-ended or differential Analog input 4 Single-ended or differential Analog input 5 Single-ended or differential Analog input 6 Single-ended or differential Analog input 7 Single-ended or differential Analog input 8 Single-ended or differential Analog input 9 Ground voltage reference for the ADC. For optimal performance the analog power supply should be separated from IOGND and DGND DAC0 Voltage Output / Single-ended or differential Analog input 12 DAC1 Voltage Output / Single-ended or differential Analog input 13 DAC2 Voltage Output / Single-ended or differential Analog input 14 DAC3 Voltage Output / Single-ended or differential Analog input 15 JTAG Test Port Input - Test Mode Select. Debug and download access JTAG Test Port Input - Test Data In. Debug and download access Multifunction I/O pin: Boot Mode. The ADuC702X will enter serial download mode if BM is low at reset and will execute code if BM is pulled high at reset through a 1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage Comparator Output/ Programmable Logic Array Input Element 7 Multifunction pin: driven low after reset General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output / Programmable Logic Array Output Element 3 JTAG Test Port Input - Test Clock. Debug and download access JTAG Test Port Output - Test Data Out. Debug and download access Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. 2.5V. Output of the on-chip voltage regulator. Must be connected to a 0.47F capacitor to DGND Ground for core logic. General Purpose Input-Output Port 0.3 / JTAG Test Port Input - Test Reset. Debug and download access / ADCBUSY signal output Reset Input. (active low) Multifunction I/O pin: External Interrupt Request 0, active high / General Purpose Input-Output Port 0.4 / Start conversion input signal for ADC / Programmable Logic Array Output Element 1 Multifunction I/O pin: External Interrupt Request 1, active high / General Purpose Input-Output Port 0.5 / ADCBUSY signal / Programmable Logic Array Output Element 2 Serial Port Multiplexed: General Purpose Input-Output Port 2.0 / UART / Programmable Logic Array Output Element 5/ Start conversion input signal for ADC Serial Port Multiplexed: General Purpose Input-Output Port 0.7 / Output for External Clock signal / UART / Programmable Logic Array Output Element 4/ Input to the Rev. PrB | Page 10 of 80 Preliminary Technical Data Pin# ADuC702X Mnemonic ADuC702x Series Type* 7020 7021 7022 24 24 23 XCLKO O 25 25 24 XCLKI I 26 26 25 P1.7/SPM7/PLAO[ 0] I/O 27 27 26 P1.6/SPM6/PLAI[6] I/O 28 28 27 P1.5/SPM5/PLAI[5] /IRQ3 I/O 29 29 28 P1.4/SPM4/PLAI[4] /IRQ2 I/O 30 30 29 P1.3/SPM3/PLAI[3] I/O 31 31 30 P1.2/SPM2/PLAI[2] I/O 32 32 31 P1.1/SPM1/PLAI[1] I/O 33 33 32 P1.0/T1/SPM0/PLA I[0] I/O 34 - - P4.2/PLAO[10] I/O 35 34 33 VREF I/O 36 37 35 36 34 35 AGND AVDD S S Function internal clock generator circuits Output from the crystal oscillator inverter Input to the crystal oscillator inverter and input to the internal clock generator circuits Serial Port Multiplexed: General Purpose Input-Output Port 1.7 / UART / SPI / Programmable Logic Array Output Element 0 Serial Port Multiplexed: General Purpose Input-Output Port 1.6 / UART / SPI / Programmable Logic Array Input Element 6 Serial Port Multiplexed: General Purpose Input-Output Port 1.5 / UART / SPI / Programmable Logic Array Input Element 5/ External Interrupt Request 3, active high Serial Port Multiplexed: General Purpose Input-Output Port 1.4 / UART / SPI / Programmable Logic Array Input Element 4/ External Interrupt Request 2, active high Serial Port Multiplexed: General Purpose Input-Output Port 1.3/ UART / I2C1 /Programmable Logic Array Input Element 3 Serial Port Multiplexed: General Purpose Input-Output Port 1.2 / UART / I2C1 /Programmable Logic Array Input Element 2 Serial Port Multiplexed: General Purpose Input-Output Port 1.1 / UART / I2C0 / Programmable Logic Array Input Element 1 Serial Port Multiplexed: General Purpose Input-Output Port 1.0/ Timer 1 Input / UART / I2C0 / Programmable Logic Array Input Element 0 General Purpose Input-Output Port 4.2 / Programmable Logic Array Output Element 10 2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor when using the internal reference. Analog Ground. Ground reference point for the analog circuitry 3.3V Analog Power * I = Input, O = Output, S = Supply. - No pin assigned. Rev. PrB | Page 11 of 80 ADuC702x Series Preliminary Technical Data PIN FUNCTION DESCRIPTIONS - ADUC7024/ADUC7025 Table 4. Pin Function Descriptions Pin# Mnemonic Type* 1 2 3 4 5 6 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 I I I I I I 7 GNDREF S 8 ADCNEG I 9 10 11 12 DAC0**/ADC12 DAC1**/ADC13 TMS TDI I/O I/O I I 13 P4.6/PLAO[14] I/O 14 P4.7/PLAO[15] I/O 15 BM/P0.0/CMPOUT/PLAI[7] I/O 16 P0.6/T1/MRST/PLAO[3] O 17 18 19 20 TCK TDO IOGND IOVDD I O S S 21 LVDD S 22 DGND S 23 P3.0/PWM0H/PLAI[8] I/O 24 P3.1/PWM0L/PLAI[9] I/O 25 P3.2/PWM1H/PLAI[10] I/O 26 P3.3/PWM1L/PLAI[11] I/O 27 P0.3/TRST/ADCBUSY I/O 28 RST 29 P3.4/PWM2H/PLAI[12] I/O 30 P3.5/PWM2L/PLAI[13] I/O I Function Single-ended or differential Analog input 4 Single-ended or differential Analog input 5 Single-ended or differential Analog input 6 Single-ended or differential Analog input 7 Single-ended or differential Analog input 8 Single-ended or differential Analog input 9 Ground voltage reference for the ADC. For optimal performance the analog power supply should be separated from IOGND and DGND Bias point or Negative Analog Input of the ADC in pseudo differential mode. Must be connected to the ground of the signal to convert. This bias point must be between 0V and 1V DAC0 Voltage Output / Single-ended or differential Analog input 12 DAC1 Voltage Output / Single-ended or differential Analog input 13 JTAG Test Port Input - Test Mode Select. Debug and download access JTAG Test Port Input - Test Data In. Debug and download access General Purpose Input-Output Port 4.6/ Programmable Logic Array Output Element 14 General Purpose Input-Output Port 4.7/ Programmable Logic Array Output Element 15 Multifunction I/O pin: Boot Mode. The ADuC7024/ADuC7025 will enter download mode if BM is low at reset and will execute code if BM is pulled high at reset through a 1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage Comparator Output/ Programmable Logic Array Input Element 7 Multifunction pin: driven low after reset General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output / Programmable Logic Array Output Element 3 JTAG Test Port Input - Test Clock. Debug and download access JTAG Test Port Output - Test Data Out. Debug and download access Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. 2.5V. Output of the on-chip voltage regulator. Must be connected to a 0.47F capacitor to DGND Ground for core logic. General Purpose Input-Output Port 3.0/ PWM phase 0 high side output / Programmable Logic Array Input Element 8 General Purpose Input-Output Port 3.1/ PWM phase 0 low side output / Programmable Logic Array Input Element 9 General Purpose Input-Output Port 3.2/ PWM phase 1 high side output / Programmable Logic Array Input Element 10 General Purpose Input-Output Port 3.3/ PWM phase 1 low side output / Programmable Logic Array Input Element 11 General Purpose Input-Output Port 0.3 / JTAG Test Port Input - Test Reset. Debug and download access / ADCBUSY signal output Reset Input. (active low) General Purpose Input-Output Port 3.4 / PWM phase 2 high side output / Programmable Logic Array Input 12 General Purpose Input-Output Port 3.5 / PWM phase 2 low side output / Programmable Logic Array Input Element 13 Rev. PrB | Page 12 of 80 Preliminary Technical Data Pin# Mnemonic ADuC702x Series Type* 31 IRQ0/P0.4/CONVSTART/PLAO[1] I/O 32 IRQ1/P0.5/ADCBUSY/PLAO[2] I/O 33 P2.0/PWMTRIP/SPM9/PLAO[5]/CONVSTART I/O 34 P0.7/ECLK/SPM8/PLAO[4]/XCLK I/O 35 XCLKO O 36 XCLKI I 37 P3.6/PWMTRIP/PLAI[14] I/O 38 P3.7/PWMSYNC/PLAI[15] I/O 39 P1.7/SPM7/PLAO[0] I/O 40 P1.6/SPM6/PLAI[6] I/O 41 42 IOGND IOVDD 43 P4.0/PLAO[8] I/O 44 P4.1/PLAO[9] I/O 45 P1.5/SPM5/PLAI[5]/IRQ3 I/O 46 P1.4/SPM4/PLAI[4]/IRQ2 I/O 47 P1.3/SPM3/PLAI[3] I/O 48 P1.2/SPM2/PLAI[2] I/O 49 P1.1/SPM1/PLAI[1] I/O 50 P1.0/T1/SPM0/PLAI[0] I/O 51 P4.2/PLAO[10] I/O S S Function Multifunction I/O pin: External Interrupt Request 0, active high / General Purpose Input-Output Port 0.4 / Start conversion input signal for ADC / Programmable Logic Array Output Element 1 Multifunction I/O pin: External Interrupt Request 1, active high / General Purpose Input-Output Port 0.5 / ADCBUSY signal / Programmable Logic Array Output Element 2 Serial Port Multiplexed: General Purpose Input-Output Port 2.0 / PWM safety cut off / UART / Programmable Logic Array Output Element 5/ Start conversion input signal for ADC Serial Port Multiplexed: General Purpose Input-Output Port 0.7 / Output for External Clock signal / UART / Programmable Logic Array Output Element 4/ Input to the internal clock generator circuits Output from the crystal oscillator inverter Input to the crystal oscillator inverter and input to the internal clock generator circuits General Purpose Input-Output Port 3.6/ PWM safety cut off / Programmable Logic Array Input Element 14 General Purpose Input-Output Port 3.7/ PWM synchronisation input output /Programmable Logic Array Input Element 15 Serial Port Multiplexed: General Purpose Input-Output Port 1.7 / UART / SPI / Programmable Logic Array Output Element 0 Serial Port Multiplexed: General Purpose Input-Output Port 1.6 / UART / SPI / Programmable Logic Array Input Element 6 Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. General Purpose Input-Output Port 4.0 / Programmable Logic Array Output Element 8 General Purpose Input-Output Port 4.1 / Programmable Logic Array Output Element 9 Serial Port Multiplexed: General Purpose Input-Output Port 1.5 / UART / SPI / Programmable Logic Array Input Element 5/ External Interrupt Request 3, active high Serial Port Multiplexed: General Purpose Input-Output Port 1.4 / UART / SPI / Programmable Logic Array Input Element 4/ External Interrupt Request 2, active high Serial Port Multiplexed: General Purpose Input-Output Port 1.3/ UART / I2C1 /Programmable Logic Array Input Element 3 Serial Port Multiplexed: General Purpose Input-Output Port 1.2 / UART / I2C1 /Programmable Logic Array Input Element 2 Serial Port Multiplexed: General Purpose Input-Output Port 1.1 / UART / I2C0 / Programmable Logic Array Input Element 1 Serial Port Multiplexed: General Purpose Input-Output Port 1.0/ Timer 1 Input / UART / I2C0 / Programmable Logic Array Input Element 0 General Purpose Input-Output Port 4.2 / Programmable Logic Array Output Element 10 Rev. PrB | Page 13 of 80 ADuC702x Series Pin# Mnemonic Preliminary Technical Data Type* 52 P4.3/PLAO[11] I/O 53 P4.4/PLAO[12] I/O 54 P4.5/PLAO[13] I/O 55 VREF I/O 56 57 58 59 60 61 62 63 64 DACREF DACGND AGND AVDD DACVDD ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 I S S S S I I I I Function General Purpose Input-Output Port 4.3 / Programmable Logic Array Output Element 11 General Purpose Input-Output Port 4.4 / Programmable Logic Array Output Element 12 General Purpose Input-Output Port 4.5 / Programmable Logic Array Output Element 13 2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor when using the internal reference. External Voltage Reference for the DACs. Range: DACGND to DACVDD Ground for the DAC. Typically connected to AGND Analog Ground. Ground reference point for the analog circuitry 3.3V Analog Power 3.3V Power Supply for the DACs. Typically connected to AVDD Single-ended or differential Analog input 0 Single-ended or differential Analog input 1 Single-ended or differential Analog input 2/ Comparator positive input Single-ended or differential Analog input 3/ Comparator negative input * I = Input, O = Output, S = Supply. ** DAC outputs not present on ADuC7025 Rev. PrB | Page 14 of 80 Preliminary Technical Data ADuC702x Series PIN FUNCTION DESCRIPTIONS - ADUC7026/ADUC7027 Table 5. Pin Function Descriptions Pin# Mnemonic Type* 1 2 3 4 5 6 7 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 I I I I I I I 8 GNDREF S 9 ADCNEG I 10 11 12 13 14 15 16 17 DAC0/ADC12 DAC1/ADC13 DAC1/ADC14 DAC1/ADC15 TMS TDI P0.1/BLE 18 P4.6/AD14/PLAO[14] I/O 19 P4.7/AD15/PLAO[15] I/O 20 BM/P0.0/CMPOUT/PLAI[7] I/O 21 P0.6/T1/MRST/PLAO[3]/AE O 22 23 24 25 26 TCK TDO P0.2/BHE IOGND IOVDD I O I/O S S 27 LVDD S 28 DGND S 29 P3.0/AD0/PWM0H/PLAI[8] I/O 30 P3.1/AD1/PWM0L/PLAI[9] I/O 31 P3.2/AD2/PWM1H/PLAI[10] I/O 32 P3.3/AD3/PWM1L/PLAI[11] I/O 33 P2.4/MS0 I/O I/O I/O I/O I/O I I I/O Function Single-ended or differential Analog input 4 Single-ended or differential Analog input 5 Single-ended or differential Analog input 6 Single-ended or differential Analog input 7 Single-ended or differential Analog input 8 Single-ended or differential Analog input 9 Single-ended or differential Analog input 10 Ground voltage reference for the ADC. For optimal performance the analog power supply should be separated from IOGND and DGND Bias point or Negative Analog Input of the ADC in pseudo differential mode. Must be connected to the ground of the signal to convert. This bias point must be between 0V and 1V DAC0 Voltage Output / Single-ended or differential Analog input 12 DAC1 Voltage Output / Single-ended or differential Analog input 13 DAC2 Voltage Output / Single-ended or differential Analog input 14 DAC3 Voltage Output / Single-ended or differential Analog input 15 JTAG Test Port Input - Test Mode Select. Debug and download access JTAG Test Port Input - Test Data In. Debug and download access General Purpose Input-Output Port 0.1/ External memory byte low enable P2.3/AE General Purpose Input-Output Port 4.6/ External Memory Interface/Programmable Logic Array Output Element 14 General Purpose Input-Output Port 4.7/ External Memory Interface / Programmable Logic Array Output Element 15 Multifunction I/O pin: Boot Mode. The ADuC7026 will enter UART download mode if BM is low at reset and will execute code if BM is pulled high at reset through a 1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage Comparator Output/ Programmable Logic Array Input Element 7 Multifunction pin: driven low after reset General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output / Programmable Logic Array Output Element 3 JTAG Test Port Input - Test Clock. Debug and download access JTAG Test Port Output - Test Data Out. Debug and download access General Purpose Input-Output Port 0.2/ External memory byte high enable Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. 2.5V. Output of the on-chip voltage regulator. Must be connected to a 0.47F capacitor to DGND Ground for core logic. General Purpose Input-Output Port 3.0 / External Memory Interface/ PWM phase 0 high side output / Programmable Logic Array Input Element 8 General Purpose Input-Output Port 3.1 / External Memory Interface / PWM phase 0 low side output / Programmable Logic Array Input Element 9 General Purpose Input-Output Port 3.2 / External Memory Interface / PWM phase 1 high side output / Programmable Logic Array Input Element 10 General Purpose Input-Output Port 3.3 / External Memory Interface / PWM phase 1 low side output / Programmable Logic Array Input Element 11 General Purpose Input-Output Port 2.4 / External Memory select 0 Rev. PrB | Page 15 of 80 ADuC702x Series Pin# Mnemonic Preliminary Technical Data Type* 34 P0.3/TRST/A16/ADCBUSY I/O 35 36 37 P2.5/MS1 P2.6/MS2 RST I/O I/O I 38 P3.4/AD4/PWM2H/PLAI[12] I/O 39 P3.5/AD5/PWM2L/PLAI[13] I/O 40 IRQ0/P0.4/CONVSTART/PLAO[1] I/O 41 IRQ1/P0.5/ADCBUSY/PLAO[2] I/O 42 P2.0/PWMTRIP/SPM9/PLAO[5]/CONVSTART I/O 43 P0.7/ECLK/SPM8/PLAO[4]/XCLK I/O 44 XCLKO O 45 XCLKI I 46 P3.6/AD6/PWMTRIP/PLAI[14] I/O 47 P3.7/AD7/ECLK/PLAI[15] I/O 48 49 50 P2.7/MS3 P2.1/WS P2.2/RS I/O I/O I/O 51 P1.7/SPM7/PLAO[0] I/O 52 P1.6/SPM6/PLAI[6] I/O 53 54 IOGND IOVDD 55 P4.0/AD8/PLAO[8] I/O 56 P4.1/AD9/PLAO[9] I/O 57 P1.5/SPM5/PLAI[5]/IRQ3 I/O 58 P1.4/SPM4/PLAI[4]/IRQ2 I/O 59 P1.3/SPM3/PLAI[3] I/O S S Function General Purpose Input-Output Port 0.3 / JTAG Test Port Input - Test Reset. Debug and download access / ADCBUSY signal output General Purpose Input-Output Port 2.5 / External Memory select 1 General Purpose Input-Output Port 2.6 / External Memory select 2 Reset Input. (active low) General Purpose Input-Output Port 3.4 / External Memory Interface / PWM phase 2 high side output / Programmable Logic Array Input 12 General Purpose Input-Output Port 3.5 / External Memory Interface /PWM phase 2 low side output / Programmable Logic Array Input Element 13 Multifunction I/O pin: External Interrupt Request 0, active high / General Purpose Input-Output Port 0.4 / Start conversion input signal for ADC / Programmable Logic Array Output Element 1 Multifunction I/O pin: External Interrupt Request 1, active high / General Purpose Input-Output Port 0.5 / ADCBUSY signal / Programmable Logic Array Output Element 2 Serial Port Multiplexed: General Purpose Input-Output Port 2.0 / PWM safety cut off / UART / Programmable Logic Array Output Element 5/ Start conversion input signal for ADC Serial Port Multiplexed: General Purpose Input-Output Port 0.7 / Output for External Clock signal / UART / Programmable Logic Array Output Element 4/ Input to the internal clock generator circuits. Output from the crystal oscillator inverter Input to the crystal oscillator inverter and input to the internal clock generator circuits General Purpose Input-Output Port 3.6 / External Memory Interface / PWM safety cut off / Programmable Logic Array Input Element 14 General Purpose Input-Output Port 3.7/ / External Memory Interface / Output for External Clock signal /Programmable Logic Array Input Element 15 General Purpose Input-Output Port 2.7 / External Memory select 3 General Purpose Input-Output Port 2.1 / External Memory Write Strobe General Purpose Input-Output Port 2.2 / External Memory Read Strobe Serial Port Multiplexed: General Purpose Input-Output Port 1.7 / UART / SPI / Programmable Logic Array Output Element 0 Serial Port Multiplexed: General Purpose Input-Output Port 1.6 / UART / SPI / Programmable Logic Array Input Element 6 Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. General Purpose Input-Output Port 4.0 / External Memory Interface / Programmable Logic Array Output Element 8 General Purpose Input-Output Port 4.1 / External Memory Interface /Programmable Logic Array Output Element 9 Serial Port Multiplexed: General Purpose Input-Output Port 1.5 / UART / SPI / Programmable Logic Array Input Element 5/ External Interrupt Request 3, active high Serial Port Multiplexed: General Purpose Input-Output Port 1.4 / UART / SPI / Programmable Logic Array Input Element 4 / External Interrupt Request 2, active high Serial Port Multiplexed: Rev. PrB | Page 16 of 80 Preliminary Technical Data Pin# * Mnemonic ADuC702x Series Type* 60 P1.2/SPM2/PLAI[2] I/O 61 P1.1/SPM1/PLAI[1] I/O 62 P1.0/T1/SPM0/PLAI[0] I/O 63 P4.2/AD10/PLAO[10] I/O 64 P4.3/AD11/PLAO[11] I/O 65 P4.4/AD12/PLAO[12] I/O 66 P4.5/AD13/PLAO[13] I/O 67 REFGND 68 VREF 69 70 71 72 73 74 75 76 77 78 79 80 DACREF DACGND AGND AGND AVDD AVDD DACVDD ADC11 ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 S I/O I S S S S S S I I I I I Function General Purpose Input-Output Port 1.3/ UART / I2C1 /Programmable Logic Array Input Element 3 Serial Port Multiplexed: General Purpose Input-Output Port 1.2 / UART / I2C1 /Programmable Logic Array Input Element 2 Serial Port Multiplexed: General Purpose Input-Output Port 1.1 / UART / I2C0 / Programmable Logic Array Input Element 1 Serial Port Multiplexed: General Purpose Input-Output Port 1.0/ Timer 1 Input / UART / I2C0 / Programmable Logic Array Input Element 0 General Purpose Input-Output Port 4.2 / External Memory Interface / Programmable Logic Array Output Element 10 General Purpose Input-Output Port 4.3 / External Memory Interface /Programmable Logic Array Output Element 11 General Purpose Input-Output Port 4.4 / External Memory Interface /Programmable Logic Array Output Element 12 General Purpose Input-Output Port 4.5 / External Memory Interface /Programmable Logic Array Output Element 13 Ground for the reference. Typically connected to AGND 2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor when using the internal reference. External Voltage Reference for the DACs. Range: DACGND to DACVDD Ground for the DAC. Typically connected to AGND Analog Ground. Ground reference point for the analog circuitry Analog Ground. Ground reference point for the analog circuitry 3.3V Analog Power 3.3V Analog Power 3.3V Power Supply for the DACs. Typically connected to AVDD Single-ended or differential Analog input 11 Single-ended or differential Analog input 0 Single-ended or differential Analog input 1 Single-ended or differential Analog input 2/ Comparator positive input Single-ended or differential Analog input 3/ Comparator negative input I = Input, O = Output, S = Supply. Rev. PrB | Page 17 of 80 ADC0 ADC1 ADuC7026* ADC2/CMP0 ADC3/CMP1 DAC CONTROL ADC4 ADC CONTROL 12-BIT SAR ADC 1MSPS ADC5 ADC6 MUX DACREF DACGND DACVDD RESET LVDD DGND IOVDD IOVDD IOGND IOGND AVDD AVDD Preliminary Technical Data REFGND AGND AGND GND REF ADuC702x Series 12-BIT VOLTAGE OUTPUT DAC BUF DAC0*/ADC12 12-BIT VOLTAGE OUTPUT DAC BUF DAC1*/ADC13 12-BIT VOLTAGE OUTPUT DAC BUF DAC2*/ADC14 12-BIT VOLTAGE OUTPUT DAC BUF DAC3*/ADC15 ADC7 ADC8 ADC9 ADC10 ADC11 TEMP SENSOR ADCNEG P3.0/PWM0H/PLAI/AD0 P3.1/PWM0L/PLAI/AD1 CMPOUT/IRQ BM/P0.0/CMPOUT/PLAI VREF DAC WAKEUP/ RTC TIMER MCU CORE P3.6/PWMTRIP/PLAI/AD6 POWER SUPPLY MONITOR OSC DOWNLOADER BAND GAP REFERENCE PROG. LOGIC ARRAY P4.7/PLAO/AD15 XCLKO PROG. CLOCK DIVIDER SPI/I2 C SERIAL INTERFACE PLL JTAG EMULATOR P4.6/PLAO/AD14 P3.4/PWM2H/PLAI/AD4 P3.5/PWM2L/PLAI/AD5 8192 BYTES USER RAM (2k X 32 bits) MUX VREF P3.3/PWM1L/PLAI/AD3 ARM7TDMI MUX DAC P3.2/PWM1H/PLAI/AD2 Threephase PWM 62 KBYTES FLASH/EE (31k X 16 bits) UART SERIAL PORT XCLKI P3.7/ECLK/PLAI/AD7 IRQ0/P0.4/CONVSTART/PLAO INTERRUPT CONTROLLER POR IRQ1/P0.5/ADCBUSY /PLAO P0.0 Figure 2: Detailed Block Diagram Rev. PrB | Page 18 of 80 P0.1/BLE P0.2/BHE P2.7/MS3 P2.6/MS2 P2.5/MS1 P2.3/AE P2.4/MS0 P2.2/RS P2.1/WS P0.6/MRST/PLAO/AE/T1 TCK/XCLK P0.3/TRST/A16/ADCBUSY TDI TDO TMS P0.7/ECLK/SPM8/PLAO P2.0/PWMTRIP/SPM9/PLAO/CONVSTART P1.7/SPM7/PLAI P1.5/SPM5/PLAI P1.6/SPM6/PLAI P1.4/SPM4/PLAI P1.3/SPM3/PLAI P1.1/SPM1/PLAI P1.2/SPM2/PLAI P1.0/SPM0/PLAI/T1 P4.5/PLAO/AD13 P4.4/PLAO/AD12 P4.3/PLAO/AD11 P4.2/PLAO/AD10 P4.1/PLAO/AD9 P4.0/PLAO/AD8 SERIAL PORT MULTIPLEXER * See selection table for feature availability on different models. Preliminary Technical Data ADuC702x Series GENERAL DESCRIPTION The ADuC702x is fully integrated, 1MSPS, 12-bit data acquisition system incorporating a high performance multichannel ADC, a 16/32-bit MCU and Flash/EE Memory on a single chip. The ADC consists of up to 12 single-ended inputs. An additional 4 inputs are available but are multiplexed with the 4 DAC output pins. The 4 DAC outputs are only available on certain models of the ADuC702x, though in many cases where the DAC is not present this pin can still be used as an additional ADC input, giving a maximum of 16 ADC input channels. The ADC can operate in single-ended or differential input modes. The ADC input voltage is 0 to VREF. Low drift bandgap reference, temperature sensor and voltage comparator complete the ADC peripheral set. The ADuC702x also integrates 4 buffered voltage output DACs on-chip. The DAC output range is programmable to one of three voltage ranges. The device operates from an on-chip oscillator and PLL generating an internal high-frequency clock of 45 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI, 16/32-bit RISC machine, offering up to 45 MIPS peak performance. 62k Bytes of non-volatile Flash/EE are provided on-chip as well as 8k Bytes of SRAM. The ARM7TDMI core views all memory and registers as a single linear array. On-chip factory firmware supports in-circuit serial download via the UART and JTAG serial interface ports while nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low-cost QuickStart Development System supporting this MicroConverter family. The parts operate from 2.7V to 3.6V and are specified over an industrial temperature range of -40C to 125C. When operating at 45MHz the power dissipation is 150mW. The ADuC702x is available in a variety of memory models and packages. These are detailed on page 9. OVERVIEW OF THE ARM7TDMI CORE The ARM7 core is a 32-bit Reduced Instruction Set Computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be 8, 16 or 32 bits and the length of the instruction word is 32 bits. The ARM7TDMI is an ARM7 core with 4 additional features: - T support for the Thumb (16 bit) instruction set. - D support for debug - M support for long multiplies - I include the EmbeddedICE module to support embedded system debugging. Thumb mode (T) An ARM instruction is 32-bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16-bits, the Thumb instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the Thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications. However the Thumb mode has two limitations: - Thumb code usually uses more instructions for the same job, so ARM code is usually best for maximising the performance of the time-critical code. - The Thumb instruction set does not include some instructions that are needed for exception handling, so the core will automatically switch to ARM code for exception handling. See ARM7TDMI User Guide for details on the core architecture, the programming model and both the ARM and ARM Thumb instruction sets. Long Multiply (M) The ARM7TDMI instruction set includes four extra instructions which perform 32-bit by 32-bit multiplication with 64-bit result and 32-bit by 32-bit multiplication-accumulation (MAC) with 64-bit result. This result is achieved in a reduced number of cycles than required on a standard ARM7 core. EmbeddedICE (I) EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers which allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug state, the processor registers may be inspected as well as the Flash/EE, the SRAM and the Memory Mapped Registers. Exceptions ARM supports five types of exceptions, and a privileged processing mode for each type. The five type of exceptions are: - Normal interrupt or IRQ. It is provided to service generalpurpose interrupt handling of internal and external events - Fast interrupt or FIQ. It is provided to service data transfer or communication channel with low latency. FIQ has priority over IRQ Rev. PrB | Page 19 of 80 ADuC702x Series Preliminary Technical Data - Memory abort - Attempted execution of an undefined instruction - Software interrupt (SWI) instruction which can be used to make a call to an operating system. Typically the programmer will define interrupts as IRQ but for higher priority interrupt, i.e. faster response time, the programmer can define interrupt as FIQ. ARM Registers ARM7TDMI has a total of 37 registers, of which 31 are general purpose registers and six are status registers. Each operating mode has dedicated banked registers. When writing user-level programs, 15 general purpose 32-bit registers (r0 to r14), the program counter (r15) and the current program status register (CPSR) are usable. The remaining registers are used only for system-level programming and for exception handling. When an exception occurs, some of the standard register are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (r13) and the link register (r14) as represented in Figure 3. The fast interrupt mode has more registers (8 to 12) for fast interrupt processing, so that the interrupt processing can begin without the need to save or restore these registers and thus save critical time in the interrupt handling process. r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (PC) CPSR user mode Interrupt latency The worst case latency for an FIQ consists of the longest time the request can take to pass through the synchronizer, plus the time for the longest instruction to complete (the longest instruction is an LDM) which loads all the registers including the PC, plus the time for the data abort entry, plus the time for FIQ entry. At the end of this time, the ARM7TDMI will be executing the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just over 1.1S in a system using a continuous 45 MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used, some compilers have an option to compile without using this command. Another option is to run the part in THUMB mode where this is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is five cycles in total which consists of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. Note that the ARM7TDMI will always be run in ARM (32-bit) mode when in privileged modes, i.e. when executing interrupt service routines. usable in user mode system modes only r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_abt r13_fiq r13_svc r14_abt r14_svc r14_fiq SPSR_fiq fiq mode SPSR_svc svc mode SPSR_abt r13_und r13_irq r14_und r14_irq SPSR_irq abort mode SPSR_und irq undefined mode mode Figure 3: register organisation More information relative to the programmer's model and the ARM7TDMI core architecture can be found in the following documents from ARM: - DDI0029G, ARM7TDMI Technical Reference Manual. - DDI0100E, ARM Architecture Reference Manual. Rev. PrB | Page 20 of 80 Preliminary Technical Data ADuC702x Series MEMORY ORGANISATION The part incorporates two separate blocks of memory, 8kByte of SRAM and 64kByte of On-Chip Flash/EE memory. 62kByte of On-Chip Flash/EE memory are available to the user, and the remaining 2kBytes are reserved for the factory configured boot page. These two blocks are mapped as shown in Figure 4. Note that by default, after a reset, the Flash/EE memory is mirrored at address 0x00000000. It is possible to remap the SRAM at address 0x00000000 by clearing bit 0 of the REMAP MMR. This remap function is described in more details in the Flash/EE memory chapter. FFFFFFFFh MMRs FFFF0000h Reserved 0008FFFFh Flash/EE Memory The total 64kBytes of Flash/EE are organised as 32k X 16 bits. 31k X 16 bits are user space and 1k X 16 bits is reserved for the on chip kernel. The page size of this Flash/EE memory is 512Bytes. 62kBytes of Flash/EE are available to the user as code and nonvolatile data memory. There is no distinction between data and program as ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, which means that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. It is therefore recommended to use Thumb mode when executing from Flash/EE memory for optimum access speed. The maximum access speed for the Flash/EE memory is 45MHz in Thumb mode and 22.5MHz in full ARM mode. More details on Flash/EE access time are outlined later in `Execution from SRAM and Flash/EE' section of this datasheet. Flash/EE SRAM 00080000h Reserved 8kBytes of SRAM are available to the user, organized as 2k X 32 bits, i.e. 2kWords. ARM code can run directly from SRAM at 45MHz , given that the SRAM array is configured as a 32-bit wide memory array. More details on SRAM access time are outlined later in `Execution from SRAM and Flash/EE' section of this datasheet. 00011FFFh SRAM 00010000h 0000FFFFh Re-mappable Memory Space (Flash/EE or SRAM) 00000000h Figure 4: Physical memory map Memory Mapped Registers Memory Access The ARM7 core sees memory as a linear array of 232 byte location where the different blocks of memory are mapped as outlined in Figure 4. The ADuC702x memory organisation is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address. bit31 Byte3 Byte2 Byte1 The Memory Mapped Register (MMR) space is mapped into the upper 2 pages of the memory array and accessed by indirect addressing through the ARM7 banked registers. The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the core registers reside in the MMR area. All shaded locations shown in Figure 6 are unoccupied or reserved locations and should not be accessed by user software. Table 6 shows a full MMR memory map. bit0 Byte0 ... ... ... ... 0xFFFFFFFFh B 7 3 A 6 2 9 5 1 8 4 0 0x00000004h 0x00000000h 32 bits Figure 5: little endian format Rev. PrB | Page 21 of 80 ADuC702x Series Preliminary Technical Data 0xFFFFFFFF 0xFFFFFC3C PWM 0xFFFFFC00 0xFFFFF820 0xFFFFF800 Flash Control Interface 0xFFFFF46C GPIO 0xFFFFF400 0xFFFF0B54 PLA 0xFFFF0B00 0xFFFF0A14 SPI 0xFFFF0A00 0xFFFF0948 I2C1 0xFFFF0900 0xFFFF0848 I2C0 0xFFFF0800 0xFFFF0730 UART 0xFFFF0700 0xFFFF0620 DAC 0xFFFF0600 0xFFFF0538 ADC 0xFFFF0500 0xFFFF0490 0xFFFF048C 0xFFFF0448 0xFFFF0440 0xFFFF0420 0xFFFF0404 0xFFFF0370 0xFFFF0360 0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 Bandgap Reference Power Supply Monitor PLL & Oscillator Control Watchdog Timer Wake Up Timer General Purpose Timer 0xFFFF0310 Timer 0 0xFFFF0300 0xFFFF0238 0xFFFF0220 0xFFFF0110 0xFFFF0000 Remap & System Control Interrupt Controller Figure 6: Memory Mapped Rev. PrB | Page 22 of 80 Preliminary Technical Data ADuC702x Series Table 6. Complete MMRs list Address Name Byte Access Type Page Address Name Byte Cycle IRQ address base = 0xFFFF0000 Access Page Type Cycle 0x0414 PLLCON 2 RW 2 41 PLLKEY2 2 W 2 41 0x0000 IRQSTA 4 R 1 65 0x0418 0x0004 IRQSIG 4 R 1 65 PSM address base = 0xFFFF0440 0x0008 IRQEN 4 RW 1 65 0x0440 PSMCON 2 RW 2 39 0x000C IRQCLR 4 W 1 65 0x0444 CMPCON 2 RW 2 39 0x0010 SWICFG 4 W 1 66 Reference address base = 0xFFFF0480 0x0100 FIQSTA 4 R 1 65 0x048C RW 2 31 0x0104 FIQSIG 4 R 1 65 ADC address base = 0xFFFF0500 0x0108 FIQEN 4 RW 1 65 0x0500 ADCCON 1 RW 2 27 0x010C FIQCLR 4 W 1 65 0x0504 ADCCP 1 RW 2 28 0x0508 ADCCN 1 RW 2 28 System Control address base = 0xFFFF0200 REFCON 1 0x0220 REMAP 1 RW 1 36 0x050C ADCSTA 1 RW 2 27 0x0230 RSTSTA 1 R 1 36 0x0510 ADCDAT 4 R 2 27 0x0234 RSTCLR 1 W 1 36 0x0514 ADCRST 1 RW 2 27 0x0530 ADCGN 2 RW 2 30 ADCOF 2 RW 2 30 Timer address base = 0xFFFF0300 0x0300 T0LD 2 RW 2 67 0x0534 0x0304 T0VAL 2 R 2 67 DAC address base = 0xFFFF0600 0x0308 T0CON 2 RW 2 67 0x0600 DAC0CON 1 RW 2 37 0x030C T0CLRI 1 W 2 67 0x0604 DAC0DAT 4 RW 2 37 0x0320 T1LD 4 RW 2 68 0x0608 DAC1CON 1 RW 2 37 0x0324 T1VAL 4 R 2 68 0x060C DAC1DAT 4 RW 2 37 0x0328 T1CON 2 RW 2 68 UART base address = 0xFFFF0700 0x032C T1CLRI 1 W 2 68 0x0700 0x0330 T1CAP 4 RW 2 0x0340 T2LD 4 RW 0x0344 T2VAL 4 0x0348 T2CON 0x034C COMTX 1 RW 2 53 68 COMRX 1 R 2 53 2 69 COMDIV0 1 RW 2 53 R 2 69 COMIEN0 1 RW 2 54 2 RW 2 69 COMDIV1 1 R/W 2 53 T2CLRI 1 W 2 69 0x0708 COMIID0 1 R 2 54 0x0360 T3LD 2 RW 2 70 0x070C COMCON0 1 RW 2 53 0x0364 T3VAL 2 R 2 70 0x0710 COMCON1 1 RW 2 55 0x0368 T3CON 2 RW 2 70 0x0714 COMSTA0 1 R 2 54 0x036C T3CLRI 1 W 2 70 0x0718 COMSTA1 1 R 2 55 0x071C COMSCR 1 RW 2 53 PLL base address = 0xFFFF0400 0x0704 0x0404 POWKEY1 2 W 2 41 0x0720 COMIEN1 1 RW 2 56 0x0408 POWCON 2 RW 2 41 0x0724 COMIID1 1 R 2 56 0x040C POWKEY2 2 W 2 41 0x0728 COMADR 1 RW 2 53 0x0410 PLLKEY1 2 W 2 41 0X072C COMDIV2 2 RW 2 55 Rev. PrB | Page 23 of 80 ADuC702x Series Address Name Byte Preliminary Technical Data Access Type Page Address Name Byte Cycle I2C0 base address = 0xFFFF0800 Access Page Type Cycle 0x0A04 SPIRX 1 R 2 57 0x0800 I2C0MSTA 1 R 2 60 0x0A08 SPITX 1 W 2 57 0x0804 I2C0SSTA 1 R 2 60 0x0A0C SPIDIV 1 RW 2 57 0x0808 I2C0SRX 1 R 2 59 0x0A10 SPICON 2 RW 2 57 0x080C I2C0STX 1 W 2 59 PLA base address = 0xFFFF0B00 0x0810 I2C0MRX 1 R 2 59 0x0B00 PLAELM0 2 RW 2 62 0x0814 I2C0MTX 1 W 2 59 0x0B04 PLAELM1 2 RW 2 62 0x0818 I2C0CNT 1 RW 2 59 0x0B08 PLAELM2 2 RW 2 62 0x081C I2C0ADR 1 RW 2 59 0x0B0C PLAELM3 2 RW 2 62 0x0824 I2C0BYTE 1 RW 2 59 0x0B10 PLAELM4 2 RW 2 62 0x0828 I2C0ALT 1 RW 2 59 0x0B14 PLAELM5 2 RW 2 62 0x082C I2C0CFG 1 RW 2 59 0x0B18 PLAELM6 2 RW 2 62 0x0830 I2C0DIVH 1 RW 2 59 0x0B1C PLAELM7 2 RW 2 62 0x0834 I2C0DIVL 1 RW 2 59 0x0B20 PLAELM8 2 RW 2 62 0x0838 I2C0ID0 1 RW 2 59 0x0B24 PLAELM9 2 RW 2 62 0x083C I2C0ID1 1 RW 2 59 0x0B28 PLAELM10 2 RW 2 62 0x0840 I2C0ID2 1 RW 2 59 0x0B2C PLAELM11 2 RW 2 62 0x0844 I2C0ID3 1 RW 2 59 0x0B30 PLAELM12 2 RW 2 62 0x0B34 PLAELM13 2 RW 2 62 I2C1 base address = 0xFFFF0900 0x0900 I2C1MSTA 1 R 2 60 0x0B38 PLAELM14 2 RW 2 62 0x0904 I2C1SSTA 1 R 2 60 0x0B3C PLAELM15 2 RW 2 62 0x0908 I2C1SRX 1 R 2 59 0x0B40 PLACLK 1 RW 2 63 0x090C I2C1STX 1 W 2 59 0x0B44 PLAIRQ 4 RW 2 63 0x0910 I2C1MRX 1 R 2 59 0x0B48 PLAADC 4 RW 2 64 0x0914 I2C1MTX 1 W 2 59 0x0B4C PLADIN 4 R 2 64 0x0918 I2C1CNT 1 RW 2 59 0x0B50 PLADOUT 4 RW 2 64 0x091C I2C1ADR 1 RW 2 59 External Memory base address = 0xFFFFF000 0x0924 I2C1BYTE 1 RW 2 59 0xF000 XMCFG 1 RW 2 71 0x0928 I2C1ALT 1 RW 2 59 0xF010 XM0CON 1 RW 2 71 0x092C I2C1CFG 1 RW 2 59 0xF014 XM1CON 1 RW 2 71 0x0930 I2C1DIVH 1 RW 2 59 0xF018 XM2CON 1 RW 2 71 0x0934 I2C1DIVL 1 RW 2 59 0xF01C XM3CON 1 RW 2 71 0x0938 I2C1ID0 1 RW 2 59 0xF020 XM0PAR 2 RW 2 71 0x093C I2C1ID1 1 RW 2 59 0xF024 XM1PAR 2 RW 2 71 0x0940 I2C1ID2 1 RW 2 59 0xF028 XM2PAR 2 RW 2 71 0x0944 I2C1ID3 1 RW 2 59 0xF02C XM3PAR 2 RW 2 71 SPI base address = 0xFFFF0A00 0x0A00 SPISTA 1 GPIO base address = 0xFFFFF400 R 2 57 0xF400 GP0CON 4 RW 1 49 0xF404 GP1CON 4 RW 1 49 Rev. PrB | Page 24 of 80 Preliminary Technical Data Address Name Byte Access ADuC702x Series Page Type Cycle 0xF408 GP2CON 4 RW 1 49 0xF40C GP3CON 4 RW 1 49 0xF410 GP4CON 4 RW 1 49 0xF420 GP0DAT 4 RW 1 51 0xF424 GP0SET 1 W 1 51 0xF428 GP0CLR 1 W 1 51 0xF430 GP1DAT 4 RW 1 51 0xF434 GP1SET 1 W 1 51 0xF438 GP1CLR 1 W 1 51 0xF440 GP2DAT 4 RW 1 51 0xF444 GP2SET 1 W 1 51 0xF448 GP2CLR 1 W 1 51 0xF450 GP3DAT 4 RW 1 51 0xF454 GP3SET 1 W 1 51 0xF458 GP3CLR 1 W 1 51 0xF460 GP4DAT 4 RW 1 51 0xF464 GP4SET 1 W 1 51 0xF468 GP4CLR 1 W 1 51 The `Access' column corresponds to the access time reading or writing a MMR. It depends on the AMBA (Advanced Microcontroller Bus Architecture) bus used to access the peripheral. The processor has two AMBA busses, AHB (Advanced High-performance Bus) used for system modules and APB (Advanced Peripheral Bus) used for lower performance peripheral. Flash/EE base address = 0xFFFFF800 0xF800 FEESTA 1 R 1 33 0xF804 FEEMOD 1 RW 1 33 0xF808 FEECON 1 RW 1 33 0xF80C FEEDAT 2 RW 1 33 0xF810 FEEADR 2 RW 1 33 0xF818 FEESIGN 3 R 1 33 0xF81C FEEPRO 4 RW 1 34 0xF820 FEEHIDE 4 RW 1 34 PWM base address= 0xFFFFFC00 0xFC00 PWMCON 2 RW 1 47 0xFC04 PWMSTA 2 RW 1 47 0xFC08 PWMDAT0 2 RW 1 47 0xFC0C PWMDAT1 2 RW 1 47 0xFC10 PWMCFG 2 RW 1 47 0xFC14 PWMCH0 2 RW 1 47 0xFC18 PWMCH1 2 RW 1 47 0xFC1C PWMCH2 2 RW 1 47 0xFC20 PWMEN 2 RW 1 48 0xFC24 PWMDAT2 2 RW 1 48 Rev. PrB | Page 25 of 80 ADuC702x Series Preliminary Technical Data ADC CIRCUIT INFORMATION ADC TRANSFER FUNCTION GENERAL OVERVIEW The Analog Digital Converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 2.7V to 3.6V supplies and is capable of providing a throughput of up to 1MSPS when the clock source is 45MHz. This block provides the user with multi-channel multiplexer, differential track-and-hold, on-chip reference and ADC. The ADC consists of a 12-bit successive-approximation converter based around two capacitor DACs. It can operate in one of three different modes, depending on the input signal configuration : * fully differential mode, for small and balanced signals * single-ended mode, for any single-ended signals * pseudo-differential mode, for any single-ended signals, taking advantage of the common mode rejection offered by the pseudo differential input. The converter accepts an analog input range of 0 to VREF when operating in single-ended mode or pseudo-differential mode. In fully differential mode, the input signal must be balanced around a common mode voltage VCM, in the range 0V to AVDD and with a maximum amplitude of 2 VREF (see Figure 7). Pseudo-differential and single-ended modes In pseudo-differential or single-ended mode, the input range is 0 V to VREF. The output coding is straight binary in pseudo differential and single-ended modes with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV or 610 V when VREF = 2.5 V. The ideal code transitions occur midway between successive integer LSB values (i.e. 1/2 LSB, 3/2 LSBs, 5/2 LSBs, . . ., FS -3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 8. OUTPUT CODE 1111 1111 1111 1111 1111 1110 1111 1111 1101 1111 1111 1100 1LSB = FS 4096 0000 0000 0011 0000 0000 0010 0000 0000 0001 0000 0000 0000 0V 1LSB VOLTAGE INPUT +FS - 1LSB Figure 8: ADC transfer function in pseudo differential mode or single-ended mode AVDD VCM VCM 2VREF Fully differential mode 2VREF VCM 2VREF 0 Figure 7: examples of balanced signals for fully differential mode A high precision, low drift, and factory calibrated 2.5 V reference is provided on-chip. An external reference can also be connected as described later. Single or continuous conversion modes can be initiated in software. An external CONVSTART pin, an output generated from the on-chip PLA or a Timer1 or a Timer2 overflow can also be used to generate a repetitive trigger for ADC conversions. A voltage output from an on-chip bandgap reference proportional to absolute temperature can also be routed through the front end ADC multiplexer (effectively an additional ADC channel input) facilitating an internal temperature sensor channel, measuring die temperature to an accuracy of 3C. The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN- pins (i.e., VIN+ - VIN-). The maximum amplitude of the differential signal is therefore -VREF to +VREF p-p (i.e. 2 X VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals, i.e. (VIN+ + VIN-)/2 and is therefore the voltage that the two inputs are centred on. This results in the span of each input being CM VREF/2. This voltage has to be set up externally and its range varies with VREF, (see driving the ADC). The output coding is two's complement in fully differential mode with 1 LSB = 2VREF/4096 or 2x2.5 V/4096 = 1.22 mV when VREF = 2.5 V. The designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs, . . ., FS -3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 9. Rev. PrB | Page 26 of 80 Preliminary Technical Data OUTPUT CODE 0111 1111 1111 0111 1111 1110 1LSB = ADuC702x Series ADC MMRS interface 2xV REF The ADC is controlled and configured via a number of MMRs that are listed below and described in detail in the following pages: 4096 0111 1111 1101 0000 0000 0001 0000 0000 0000 1111 1111 1111 1000 0000 0010 1000 0000 0001 1000 0000 0000 -V REF + 1LSB 0LSB +V REF - 1LSB VOLTAGE INPUT (Vin+ - Vin-) Figure 9: ADC transfer function in differential mode TYPICAL OPERATION Once configured via the ADC control and channel selection registers, the ADC will convert the analog input and provide a 12-bit result in the ADC data register. The top 4 bits are the sign bits and the 12-bit result is placed from bit 16 to 27 as shown in Figure 10. Again, it should be noted that in fully differential mode, the result is represented in two's complement format, and in pseudo differential and singleended mode, the result is represented in straight binary format. 31 27 16 15 SIGN BITS 12-bit ADC RESULT Figure 10: ADC Result Format - ADCCON: ADC Control Register allows the programmer to enable the ADC peripheral, to select the mode of operation of the ADC, either Single-ended, pseudo-differential or fully differential mode and the conversion type. This MMR is described Table 7. - ADCCP: ADC positive Channel selection Register - ADCCN: ADC negative Channel selection Register ADCSTA: ADC Status Register, indicates when an ADC conversion result is ready. The ADCSTA register contains only one bit, bit (bit 0), representing the status of the ADC. This bit is set at the end of an ADC conversion generating an ADC interrupt, it is cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be read externally via the ADCBusy pin. This pin is high during a conversion. When the conversion is finished, ADCBusy goes back low. This information can be available on P0.3 (see chapter on GPIO) if enabled in ADCCON register. ADCDAT: ADC Data Result Register, hold the 12-bit ADC result as shown Figure 10 ADCRST: ADC Reset Register. Resets all the ADC registers 0 to their default value. - ADCOF: Offset calibration register. 10-bit register - ADCGN: Gain calibration register. 10-bit register The same format is used in DACxDAT, simplifying the software. Table 7: ADCCON MMR Bit Designations Bit Description 7 Enable Conversion Set by the user to enable conversion mode Cleared by the user to disable conversion mode 6 Enable ADCBUSY Set by the user to enable the ADCBUSY pin Cleared by the user to disable the ADCBUSY pin 5 ADC power control: Set by the user to place the ADC in normal mode, the ADC must be powered up for at least 500uS before it will convert correctly. Cleared by the user to place the ADC in power-down mode 4-3 2-0 Conversion Mode: 00 Single Ended Mode 01 Differential Mode 10 Pseudo-Differential Mode 11 Reserved Conversion Type: Rev. PrB | Page 27 of 80 ADuC702x Series Preliminary Technical Data 000 Enable CONVSTART pin as a conversion input 001 Enable timer 1 as a conversion input 010 Enable timer 0 as a conversion input 011 Single software conversion, will be set to 000 after conversion. 100 Continuous software conversion 101 PLA conversion Other Reserved Table 9: ADCCN* MMR bit designation Table 8: ADCCP* MMR bit designation Bit Description Bit Description 7-5 Reserved 7-5 Reserved 4-0 Positive Channel Selection Bits 4-0 Negative Channel Selection Bits 00000 ADC0 00000 ADC0 00001 ADC1 00001 ADC1 00010 ADC2 00010 ADC2 00011 ADC3 00011 ADC3 00100 ADC4 00100 ADC4 00101 ADC5 00101 ADC5 00110 ADC6 00110 ADC6 00111 ADC7 00111 ADC7 01000 ADC8 01000 ADC8 01001 ADC9 01001 ADC9 01010 ADC10 01010 ADC10 01011 ADC11 01011 ADC11 01100 DAC0/ADC12 01100 DAC0/ADC12 01101 DAC1/ADC13 01101 DAC1/ADC13 01110 DAC2/ADC14 01110 DAC2/ADC14 01111 DAC3/ADC15 01111 DAC3/ADC15 10000 Temperature sensor 10000 Reference 10001 AGND Others Reserved 10010 Reference 10011 AVDD/2 Others Reserved * ADC and DAC channel availability depends on part model. See page 9 for details. Rev. PrB | Page 28 of 80 Preliminary Technical Data ADuC702x Series CONVERTER OPERATION The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. This architecture is described below for the three different modes of operation. of the ADuC702x and SW2 switches between A (Channel-) and B (VREF). VIN- pin must be connected to Ground or a low voltage. The input signal on VIN+ can then vary from VIN- to VREF + VIN-. Note VIN- must be chosen so that VREF + VIN- does not exceed AVDD. CAPACITIVE DAC AIN0 The ADuC702x contains a successive approximation ADC based on two capacitive DACs. Figure 11 and Figure 12 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC is comprised of control logic, a SAR, and two capacitive DACs. In Figure 11 (the acquisition phase), SW3 is closed and SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. CAPACITIVE DAC AIN0 MUX Channel- AIN11 Cs B A SW1 A SW2 B VREF COMPARATOR SW3 MUX Channel+ Cs B A SW1 A SW2 B AIN11 VREF COMPARATOR SW3 CONTROL LOGIC Cs CAPACITIVE DAC VINChannel- Figure 13: ADC in pseudo-differential mode Single-ended mode In Single-ended mode, SW2 is always connected internally to ground. The VIN- pin can be floating. The input signal range on VIN+ is 0V to VREF. CONTROL LOGIC CAPACITIVE DAC AIN0 Cs CAPACITIVE DAC Figure 11: ADC acquisition phase ... ... Channel+ ... Differential mode MUX Channel+ B Cs A SW1 COMPARATOR SW3 CONTROL LOGIC ChannelAIN11 When the ADC starts a conversion (Figure 12), SW3 will open and SW1 and SW2 will move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC's output code. The output impedances of the sources driving the VIN+ and VIN- pins must be matched; otherwise, the two inputs will have different settling times, resulting in errors. CAPACITIVE DAC Cs CAPACITIVE DAC VIN- Figure 14: ADC in single-ended mode Analog Input Structure Figure 15 shows the equivalent circuit of the analog input structure of the ADC. The four diodes provides ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This would cause these diodes to become forward biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. AIN0 ... Channel+ Cs B A SW1 A SW2 MUX Channel- B VREF COMPARATOR SW3 CONTROL LOGIC Cs AIN11 CAPACITIVE DAC Figure 12: ADC conversion phase Pseudo-differential mode In pseudo-differential mode, Channel- is linked to the VIN- pin The capacitors C1 in Figure 15 are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the ON resistance of the switches. The value of these resistors is typically about 100 . The capacitors, C2, are the ADC's sampling capacitors and have a capacitance of 16 pF typically. For AC applications, removing high-frequency components from the analog input signal is recommended by the use of an RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise Rev. PrB | Page 29 of 80 ADuC702x Series Preliminary Technical Data ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the AC performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application. AVDD D R1 C2 For offset error correction, either an external pin must be tied to AGND (system calibration) or the internal AGND channel must be selected (device calibration). A software loop must be implemented to tweak the value in ADCOF register each time until the transition of ADCDAT reads code 0 to 1. Offset error correction is done digitally and has a resolution of 0.25 lsb and a range of +/- 3.125% of VREF. D C1 For gain error correction, either an external pin must be tied to VREF (system calibration) or the internal reference channel must be selected (device calibration). A software loop must be implemented to tweak the value in ADCGN register each time until the transition of ADCDAT reads code 4094 to 4095. Similar to the offset calibration, the gain calibration resolution is 0.25 lsb with a range of +/- 3% of VREF. AVDD D R1 C2 D C1 TEMPERATURE SENSOR Figure 15: Equivalent Analog Input Circuit Conversion Phase: Switches Open Track Phase: Switches Closed When no amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 k . The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The THD will increase as the source impedance increases and the performance will degrade. DRIVING THE ANALOG INPUTS Internal or external reference can be used for the ADC. In differential mode of operation, there are restrictions on common mode input signal (VCM) that are dependant on reference value and supply voltage used to ensure that the signal remains within the supply rails. Table 10 gives some calculated VCM min VCM max for some conditions. Table 10: VCM ranges AVDD VREF VCM min VCM max Signal Peak-Peak 3.3V 2.5V 1.25V 2.05V 2.5V 2.048V 1.024V 2.276V 2.048V 1.25 0.75V 2.55V 1.25 2.5V 1.25V 1.75V 2.5V 2.048V 1.024V 1.976V 2.048V 1.25 0.75V 2.25V 1.25 3.0V ADCOF and ADCGN. The ADuC702x provides a voltage output from an on-chip bandgap reference proportional to absolute temperature. It can also be routed through the front end ADC multiplexer (effectively an additional ADC channel input) facilitating an internal temperature sensor channel, measuring die temperature to an accuracy of 3C. BANDGAP REFERENCE The ADuC702x provides an on-chip bandgap reference of 2.5V, which can be used for the ADC and for the DAC. This internal reference also appears on the VREF pin. When using the internal reference, a capacitor of 0.47F must be connected from the external VREF pin to AGND, to ensure stability and fast response during ADC conversions. This reference can also be connected to an external pin (VREF) and used as a reference for other circuits in the system. An external buffer would be required because of the low drive capability of the VREF output. A programmable option also allows an external reference input on the VREF pin. The bandgap reference interface consists on a 8-bit MMR, REFCON described in ADC CALIBRATION Table 11. System calibration or device calibration are performed in software. Two 10-bit registers are available for calibration, Rev. PrB | Page 30 of 80 Preliminary Technical Data ADuC702x Series Table 11: REFCON MMR bit designations Bit Description 7-2 Reserved 1 Internal reference powerdown enable Set by user to place the internal reference in power-down mode and use an external reference Cleared by user to place the internal reference in normal mode and use it for ADC conversions Internal reference output enable Set by user to connect the internal 2.5V reference to the VREF pin. The reference can be used for external component but will need to be buffered. Cleared by user to disconnect the reference from the VREF pin. 0 Rev. PrB | Page 31 of 80 ADuC702x Series Preliminary Technical Data NONVOLATILE FLASH/EE MEMORY (3) JTAG access FLASH/EE MEMORY OVERVIEW The JTAG protocol uses the on-chip JTAG interface to facilitate code download and debug. The ADuC702x incorporates Flash/EE memory technology onchip to provide the user with non-volatile, in-circuit reprogrammable memory space. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased; the erase being performed in page blocks. Thus, Flash memory is often and more correctly referred to as Flash/EE memory. Overall, Flash/EE memory represents a step closer to the ideal memory device that includes non-volatility, in-circuit programmability, high density, and low cost. Incorporated in the ADuC702x, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one time programmable (OTP) devices at remote operating nodes. FLASH/EE MEMORY AND THE ADUC702X The ADuC702x contains a 64 kByte array of Flash/EE Memory. The lower 62 Kbytes is available to the user and the upper 2 kBytes of this Flash/EE program memory array contain permanently embedded firmware, allowing in circuit serial download. These 2 Kbytes of embedded firmware also contain a power-on configuration routine that downloads factory calibrated coefficients to the various calibrated peripherals (ADC, temperature sensor, bandgap references and so on). This 2 kByte embedded firmware is hidden from user code. The 62kBytes of Flash/EE memory can be programmed incircuit, using the serial download mode or the JTAG mode provided or via parallel programming. (1) Serial Downloading (In-Circuit Programming) The ADuC702x facilitates code download via the standard UART serial port or via the I2C port. The ADuC702x will enter serial download mode after a reset or power cycle if the BM pin is pulled low through an external 1kOhm resistor. Once in serial download mode, the user can download code to the full 62kBytes of Flash/EE memory while the device is in circuit in its target application hardware. A PC serial download executable is provided as part of the development system for serial downloading via the UART. An application note is available at www.analog.com/microconverter describing the protocol for serial downloading via the UART and I2C. (2) Parallel Programming FLASH/EE MEMORY SECURITY The 62kByte of Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEEPRO/FEEHIDE MMR protects the 62kBytes from being read through JTAG and also in parallel programming mode. The other 31 bits of this register protect writing to the flash memory, each bit protects 4 pages, i.e. 2kBytes. Write protection is activated for all type of access. There are two levels of protection: - Protection can be set and removed by writing directly into FEEHIDE MMR. - FEEPRO can be protected by a key to avoid direct access to FEEPRO. The key is saved once and must be entered again to modify FEEPRO. A mass erase will set the key back to 0xFFFF but will also erase all the user code. Sequence to write the key: 1. Enter an address in FEEADR. 2. Do a single READ command, wait for the read to be successful by monitoring FEESTA. 3. Run a verify command. 4. Write the bit in FEEPRO corresponding to the page to be protected. 5. Enable key protection by setting bits 7 to 4 of FEEMOD. 6. Write a 32 bit key in FEEADR, FEEDAT 7. Run the write key command 0x0C in FEECON, wait for the read to be successful by monitoring FEESTA. To remove or modify the protection the same sequence can be used with a modified value of FEEPRO. The sequence above is illustrated in the following example, this protects writing pages 4 to 7 of the FLASH: FEEADR = 0x800; FEECON=0x01; while (!(FEESTA & 0x01)){} FEECON=0x04; FEEPRO=0xFFFFFFFD; FEEMOD=(FEEMOD & 0xF0); FEEADR=0xAA55; FEEDAT=0xAA55; FEECON= 0x0C; while (!(FEESTA & 0x01)){} The parallel programming protocol allows the on-chip Flash/EE memory be programmed by industry standard third party programmers. Rev. PrB | Page 32 of 80 //Any address, //Read command //Wait for read //Verify Command //Protect pages 4 to 7 //Write key enable //16 bit key value //16 bit key value // Write key command //Wait for command Preliminary Technical Data ADuC702x Series FLASH/EE CONTROL INTERFACE Serial, parallel and JTAG programming use the Flash/EE Control Interface, which includes seven MMRs: - FEESTA: read only register, reflects the status of the Flash Control Interface - FEEMOD: sets the operating mode of the Flash Control Interface - FEEDAT: 16-bit data register. FEEADR: 16-bit address register. FEESIGN: 24-bit code signature FEEPRO: protection following subsequent reset MMR. Requires software key. See description Table 15 - FEEHIDE: Immediate Protection MMR. Does not require any software keys. See description Table 15 - FEECON: 8-bit command register. The commands are described Table 14 Table 12: FEESTA MMR bit designations Bit Description 15-6 Reserved 5 Burst command enable Set when the command is a burst command: 0x07, 0x08 or 0x09 Cleared when other command Reserved 4 3 2 1 0 Flash interrupt status bit Set automatically when an interrupt occurs, i.e. when a command is complete and the Flash/EE interrupt enable bit in the FEEMOD register is set Cleared when reading FEESTA register Flash/EE controller busy Set automatically when the controller is busy Cleared automatically when the controller is not busy Command fail Set automatically when a command completes unsuccessfully Cleared automatically when reading FEESTA register Command complete Set by MicroConverter when a command is complete Cleared automatically when reading FEESTA register Table 13: FEEMOD MMR bit designations Bit Description 7-5 Reserved 4 Flash/EE interrupt enable: Set by user to enable the Flash/EE interrupt. The interrupt will occur when a command is complete. Cleared by user to disable the Flash/EE interrupt Reserved 3-0 Table 14: command codes in FEECON Code 0x00* 0x01* 0x02* 0x03* command Null Single Read Single Write Erase-Write 0x04* Single Verify 0x05* Single Erase Description Idle state Load FEEDAT with the 16-bit data indexed by FEEADR Write FEEDAT at the address pointed by FEEADR. This operation takes 20s. Erase the page indexed by FEEADR and write FEEDAT at the location pointed by FEEADR. This operation takes 20ms Compare the contents of the location pointed by FEEADR to the data in FEEDAT. The result of the comparison is returned in FEESTA bit 1 Erase the page indexed by FEEADR Rev. PrB | Page 33 of 80 ADuC702x Series 0x06* Mass erase 0x07 0x08 0x0B Burst read Burst readwrite Erase Burst read-write Burst termination Signature 0x0C Protect 0x0D 0x0E 0x0F Reserved Reserved Ping 0x09 0x0A * Preliminary Technical Data Erase 62kByte of user space. The 2kByte of kernel are protected. This operation takes 2.48s To prevent accidental execution a command sequence is required to execute this instruction, this is described below. Default command. No write is allowed. This operation takes 2 cycles Write can handle a maximum of 8 data of 16 bits and takes a maximum of 8 x 20 s Will automatically erase the page indexed by the write, allow to write pages without running an erase command. This command takes 20 ms to erase the page + 20 s per data to write Stops the running burst to allow execution from Flash/EE immediately Give a signature of the 64kBytes of Flash/EE in the 24-bit FEESIGN MMR. This operation takes 32778 clock cycles. This command can be run only once. The value of FEEPRO is saved and can be removed only with a mass erase (0x06) or with the key Reserved Reserved No operation, interrupt generated The FEECON will always read 0x07 immediately after execution of any of these commands. Command Sequence for executing a Mass Erase FEEADR = 0x800; FEECON=0x01; while (!(FEESTA & 0x01)){} FEECON=0x04; FEEDAT=0x06; FEECON=0x06; //Any address //Read command //Wait for read //Verify Command //Mass erase enable //Mass erase command Table 15: FEEPRO and FEEHIDE MMR bit designations Bit Description 31 Read protection Cleared by user to protect all code Set by user to allow reading the code Write protection for pages 123 to 120, for pages 119 to 116... and for pages 0 to 3 Cleared by user to protect the pages in writing Set by user to allow writing the pages 30-0 EXECUTION TIME FROM SRAM AND FLASH/EE Execution from Flash/EE This chapter describes SRAM and Flash/EE access times during execution for applications where execution time is critical. Execution from SRAM Fetching instructions from SRAM takes one clock cycle as the access time of the SRAM is 2ns and a clock cycle is 22ns minimum. However, if the instruction involve reading or writing data to memory, one extra cycle must be added if the data is in SRAM, or three cycle if the data is in Flash/EE, one cycle to execute the instruction and two cycles to get the 32-bit data from Flash/EE. A control flow instruction, for example a branch instruction will take one cycle to fetch but also two cycle to fill the pipeline with the new instructions. Because the Flash/EE width is 16-bit and access time for 16-bit words is 22ns, execution from Flash/EE cannot be done in one cycle as from SRAM when CD bit =0. Also some dead times are needed before accessing data for any value of CD bits. In ARM mode, where instructions are 32 bits, two cycles are needed to fetch any instruction when CD = 0 and in Thumb mode, where instructions are 16 bits, one cycle is needed to fetch any instruction. Timing is identical in both mode when executing instructions that involve using the Flash/EE for data memory. If the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter and then four cycles are needed to fill the pipe-line. A data processing instruction involving only core register doesn't require any extra clock cycle but if it involves data in Flash/EE, an extra clock cycle is needed to decode the address of the data and two cycles to get the 32-bit data from Flash/EE. An extra Rev. PrB | Page 34 of 80 Preliminary Technical Data ADuC702x Series cycle must also be added before fetching another instruction. Data transfer instruction are more complex and are summarised Table 16. Table 16: execution cycles in ARM/Thumb mode Instructions Fetch cycles Dead time Data access LD 2/1 1 2 1 LDH 2/1 1 1 1 Dead time LDM/PUSH 2/1 N 2xn N STR 2/1 1 2 x 20s 1 STRH 2/1 1 20s 1 STRM/POP 2/1 N 2 x N x 20s N With 1