REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD5533B
*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
32-Channel Precision
Infinite Sample-and-Hold
FEATURES
Infinite Sample-and-Hold Capability to ⴞ0.018% Accuracy
Infinite Sample-and-Hold Total Unadjusted Error ⴞ2.5 m V
High Integration:
32-Channel DAC in 12 mm ⴛ 12 mm CSPBGA
Per Channel Acquisition Time of 16 ␮s Max
Adjustable Voltage Output Range
Output Impedance 0.5 ⍀
Output Voltage Span 10 V
Readback Capability
DSP/Microcontroller Compatible Serial Interface
Parallel Interface
Temperature Range –40ⴗC to +85ⴗC
APPLICATIONS
Optical Networks
Automatic Test Equipment
Level Setting
Instrumentation
Industrial Control Systems
Data Acquisition
Low Cost I/O
FUNCTIONAL BLOCK DIAGRAM
SYNC/CS
WR
CAL
A4–A0SCLK
OFFSET SEL
AD5533B
DV
CC
VIN
DIN DOUT
ADDRESS INPUT REGISTER
AV
CC
REF IN REF OUT OFFS IN
INTERFACE
CONTROL
LOGIC
OFFS OUT
VOUT 31
VOUT 0
TRACK /RESET
BUSY
DAC GND
AGND
DGND
SER / PAR
V
DD V
SS
DAC
DAC
DAC
ADC
GENERAL DESCRIPTION
The AD5533B combines a 32-channel voltage translation function
with an infinite output hold capability. An analog input voltage on
the common input pin, V
IN
, is sampled and its digital represen-
tation transferred to a chosen DAC register. V
OUT
for this DAC
is then updated to reflect the new contents of the DAC register.
Channel selection is accomplished via the parallel address inputs
A0–A4 or via the serial input port. The output voltage range is
determined by the offset voltage at the OFFS_IN pin and the gain
of the output amplifier. It is restricted to a range from V
SS
+ 2 V
to V
DD
– 2 V because of the headroom of the output amplifier.
The device is operated with AV
CC
= +5 V ± 5%, DV
CC
= +2.7 V
to +5.25 V, V
SS
= –4.75 V to –16.5 V, and V
DD
= +8 V to
+16.5 V and requires a stable 3 V reference on REF_IN as well
as an offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
1. Precision infinite droopless sample-and-hold capability.
2. The AD5533B is available in a 74-lead CSPBGA with a
body size of 12 mm ⫻ 12 mm.
3. In infinite sample-and-hold mode, a total unadjusted error of
±2.5 mV is achieved by laser-trimming on-chip resistors.
*Protected by U.S. Patent No. 5,969,657; other patents pending.
REV. A
–2–
AD5533B–SPECIFICATIONS
(VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V;
DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFFS_IN = 0 V;
Output Range from VSS + 2 V to VDD – 2 V. All outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
1
B Version
2
Unit Conditions/Comments
ANALOG CHANNEL
V
IN
to V
OUT
Nonlinearity ±0.006 % typ Input Range 100 mV to 2.96 V
±0.018 % max After Gain and Offset Adjustment
Total Unadjusted Error (TUE) ±2.5 mV typ See TPC 6.
±12 mV
max
Gain 3.51/3.52/3.53 min/typ/max
Offset Error
±1
mV typ
See TPC 2.
±10 mV
max
ANALOG INPUT (V
IN
)
Input Voltage Range 0 to 3 V Nominal Input Range
Input Lower Dead Band 70 mV max 50 mV typ. Referred to V
IN
.
See Figure 5.
Input Upper Dead Band 40 mV max 12 mV typ. Referred to V
IN
.
See Figure 5.
Input Current 1 µA max 100 nA typ. V
IN
acquired on
one channel.
Input Capacitance
3
20 pF typ
ANALOG INPUT (OFFS_IN)
Input Voltage Range 0/4 V min/max Output Range Restricted from
V
SS
+ 2 V to V
DD
– 2 V
Input Current 1 µA max 100 nA typ
VOLTAGE REFERENCE
REF_IN
Nominal Input Voltage 3.0 V
Input Voltage Range
3
2.85/3.15 V min/max
Input Current 1 µA max <1 nA typ
REF_OUT
Output Voltage 3 V typ
Output Impedance
3
280
kΩ
typ
Reference Temperature Coefficient
3
60 ppm/°C typ
ANALOG OUTPUTS (V
OUT
0–31)
Output Temperature Coefficient
3,
4
10 ppm/°C typ
DC Output Impedance 0.5
Ω
typ
Output Range V
SS
+ 2/V
DD
– 2 V min/max 100 µA Output Load
Resistive Load
3,
5
5
kΩ
min
Capacitive Load
3, 5
100 pF max
Short-Circuit Current
3
7mA typ
DC Power Supply Rejection Ratio
3
–70 dB typ V
DD
=+15 V ± 5%
–70 dB typ V
SS
=–15 V ± 5%
DC Crosstalk
3
250 µV max Outputs Loaded
ANALOG OUTPUT (OFFS_OUT)
Output Temperature Coefficient
3, 4
10 ppm/°C typ
DC Output Impedance
3
1.3
kΩ
typ
Output Range 50 to REF_IN – 12 mV typ
Output Current 10 µA max Source Current
Capacitive Load 100 pF max
DIGITAL INPUTS
3
Input Current ±10 µA max 5 µA typ
Input Low Voltage 0.8 V max DV
CC
= 5 V ± 5%
0.4 V max DV
CC
= 3 V ± 10%
Input High Voltage 2.4 V min DV
CC
= 5 V ± 5%
2.0 V min DV
CC
= 3 V ± 10%
Input Hysteresis (SCLK and CS Only) 200 mV typ
Input Capacitance 10 pF max
REV. A –3–
AD5533B
Parameter
1
B Version
2
Unit Conditions/Comments
DIGITAL OUTPUTS (BUSY, D
OUT
)
3
Output Low Voltage 0.4 V max DV
CC
= 5 V. Sinking 200 µA.
Output High Voltage 4.0 V min DV
CC
= 5 V. Sourcing 200 µA.
Output Low Voltage 0.4 V max DV
CC
= 3 V. Sinking 200 µA.
Output High Voltage 2.4 V min DV
CC
= 3 V. Sourcing 200 µA.
High Impedance Leakage Current ±1µA max D
OUT
Only
High Impedance Output Capacitance 15 pF typ D
OUT
Only
POWER REQUIREMENTS
Power Supply Voltages
V
DD
8/16.5 V min/max
V
SS
–4.75/–16.5 V min/max
AV
CC
4.75/5.25 V min/max
DV
CC
2.7/5.25 V min/max
Power Supply Currents
6
I
DD
15 mA max 10 mA typ. All channels full-scale.
I
SS
15 mA max 10 mA typ. All channels full-scale.
AI
CC
33 mA max 26 mA typ
DI
CC
1.5 mA max 1 mA typ
Power Dissipation
6
280 mW typ V
DD
= +10 V, V
SS
= –5 V
NOTES
1
See Terminology section.
2
B Version: Industrial temperature range –40°C to +85°C; typical at +25°C.
3
Guaranteed by design and characterization, not production tested.
4
AD780 as reference for the AD5533B.
5
Ensure that you do not exceed T
J
(max). See Absolute Maximum Ratings.
6
Outputs unloaded.
Specifications subject to change without notice.
AC CHARACTERISTICS
(VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V; DVCC = +2.7 V to +5.25 V;
AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFFS_IN = 0 V; Output Range from VSS + 2 V to VDD – 2 V.
All outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted.)
Parameter B Version
1
Unit Conditions/Comments
Output Settling Time
2
3µs max
Acquisition Time 16 µs max
OFFS_IN Settling Time
2
10 µs max 500 pF, 5 k
Ω
Load; 0 V–3 V Step
Digital Feedthrough
2
0.2 nV-s typ
Output Noise Spectral Density @ 1 kHz
2
400 nV/√Hz typ
AC Crosstalk
2
5nV-s typ
NOTES
1
B version: Industrial temperature range –40°C to +85°C; typical at 25°C.
2
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
REV. A
–4–
AD5533B
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Limit at T
MIN
, T
MAX
Parameter
1, 2
(B Version) Unit Conditions/Comments
t
1
0ns min CS to WR Setup Time
t
2
0ns min CS to WR Hold Time
t
3
50 ns min CS Pulsewidth Low
t
4
50 ns min WR Pulsewidth Low
t
5
20 ns min A4–A0, CAL, OFFS_SEL to WR Setup Time
t
6
7ns min A4–A0, CAL, OFFS_SEL to WR Hold Time
NOTES
1
See Parallel Interface Timing Diagram.
2
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACE
Limit at T
MIN
, T
MAX
Parameter
1, 2
(B Version) Unit Conditions/Comments
f
CLKIN
20 MHz max SCLK Frequency
t
1
20 ns min SCLK High Pulsewidth
t
2
20 ns min SCLK Low Pulsewidth
t
3
15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time
t
4
50 ns min SYNC Low Time
t
5
10 ns min D
IN
Setup Time
t
6
5ns min D
IN
Hold Time
t
7
5ns min SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback
t
83
20 ns max SCLK Rising Edge to D
OUT
Valid
t
93
60 ns max SCLK Falling Edge to D
OUT
High Impedance
t
10
400 ns min10th SCLK Falling Edge to SYNC Falling Edge for Readback
t
114
7ns min SCLK Falling Edge to SYNC Falling Edge Setup Time for
Readback
NOTES
1
See Serial Interface Timing Diagrams.
2
Guaranteed by design and characterization, not production tested.
3
These numbers are measured with the load circuit of Figure 2.
4
SYNC should be taken low while SCLK is low for readback.
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAM
CS
WR
A4 –A 0 , CAL,
OFFS SEL
Figure 1. Parallel Write (ISHA Mode Only)
IOL
200␮A
IOH
200␮A
CL
50pF
TO
OUTPUT
PIN
1.6V
Figure 2. Load Circuit for D
OUT
Timing Specifications
REV. A –5–
AD5533B
SERIAL INTERFACE TIMING DIAGRAMS
12345678 910
t
1
t
2
t
3
t
4
t
5
t
6
MSB LSB
SCLK
SYNC
D
IN
Figure 3. 10-Bit Write (ISHA Mode and Both Readback Modes)
2134567
8
9
10
11
12 13 14
MSB
LSB
SCLK
S
YNC
D
OUT
10
t11
t10
t1
t2
t4t8t9
t7
Figure 4. 14-Bit Read (Both Readback Modes)
REV. A
–6–
AD5533B
ORDERING GUIDE
Output Output
Impedance Voltage Span Package Package
Description Function (Typ) (V) Description Option
AD5533BBC-1 32-Channel Precision ISHA Only 0.5 Ω10 74-Lead CSPBGA BC-74
AD5533ABC-1
*
32-Channel ISHA Only 0.5 Ω10 74-Lead CSPBGA BC-74
AD5532ABC-1
*
32 DACs, 32-Channel ISHA 0.5 Ω10 74-Lead CSPBGA BC-74
AD5532ABC-2
*
32 DACs, 32-Channel ISHA 0.5 Ω20 74-Lead CSPBGA BC-74
AD5532ABC-3
*
32 DACs, 32-Channel ISHA 500 Ω10 74-Lead CSPBGA BC-74
AD5532ABC-5
*
32 DACs, 32-Channel ISHA 1 kΩ10 74-Lead CSPBGA BC-74
AD5532BBC-1
*
32 DACs, 32-Channel Precision ISHA 0.5 Ω10 74-Lead CSPBGA BC-74
EVAL-AD5533EB AD5532/AD5533 Evaluation Board
*Separate Data Sheet
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C, unless otherwise noted.)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AV
CC
to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V
DV
CC
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DV
CC
+ 0.3 V
Digital Outputs to DGND . . . . . . . . . –0.3 V to DV
CC
+ 0.3 V
REF_IN to AGND, DAC_GND . . . . –0.3 V to AV
CC
+ 0.3 V
V
IN
to AGND, DAC_GND . . . . . . . . –0.3 V to AV
CC
+ 0.3 V
V
OUT
0–31 to AGND . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
OFFS_IN to AGND . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
OFFS_OUT to AGND . . . . AGND – 0.3 V to AV
CC
+ 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
J
max) . . . . . . . . . . . . . . . . . . 150°C
74-Lead CSPBGA Package, θ
JA
Thermal Impedance . . 41°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
Max Power Dissipation . . . . . . . . . . . . (150°C – T
A
)/θ
JA
mW
3
Max Continuous Load Current at T
J
= 70°C,
per Channel Group . . . . . . . . . . . . . . . . . . . . . . . 15.5 mA
4
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
3
This limit includes load power.
4
This maximum allowed continuous load current is spread over eight channels,
with channels grouped as follows:
Group 1: Channels 3, 4, 5, 6, 7, 8, 9, 10
Group 2: Channels 14, 16, 18, 20, 21, 24, 25, 26
Group 3: Channels 15, 17, 19, 22, 23, 27, 28, 29
Group 4: Channels 0, 1, 2, 11, 12, 13, 30, 31
For higher junction temperatures, derate as follows:
Max Continuous
Load Current
T
J
(°C) per Group (mA)
70 15.5
90 9.025
100 6.925
110 5.175
125 3.425
135 2.55
150 1.5
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5533B features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
AD5533B
–7–
PIN CONFIGURATION
1234567891011
A
B
C
D
E
F
G
H
J
K
L
12345 67891011
A
B
C
D
E
F
G
H
J
K
L
74-Lead CSPBGA Ball Configuration
CSPBGA Ball CSPBGA Ball CSPBGA Ball
Number Name Number Name Number Name
A1 NC*C10 AVCC1 J10 VO9
A2 A4 C11 REF_OUT J11 VO11
A3 A2 D1 VO20 K1 VO17
A4 A0 D2 DAC_GND2 K2 VO15
A5 CS/SYNC D10 AVCC2 K3 VO27
A6 DVCC D11 OFFS_OUT K4 VSS3
A7 SCLK E1 VO26 K5 VSS1
A8 OFFSET_SEL E2 VO14 K6 VSS4
A9 BUSY E10 AGND1 K7 VDD2
A10 TRACK/RESET E11 OFFS_IN K8 VO2
A11 NC*F1 VO25 K9 VO10
B1 VO16 F2 VO21 K10 VO13
B2 NC*F10 AGND2 K11 VO12
B3 A3 F11 VO6 L1 NC*
B4 A1 G1 VO24 L2 VO28
B5 WR G2 VO8 L3 VO29
B6 DGND G10 VO5 L4 VO30
B7 DIN G11 VO3 L5 VDD3
B8 CAL H1 VO23 L6 VDD1
B9 SER/PAR H2 VIN L7 VDD4
B10 DOUT H10 VO4 L8 VO31
B11 REF_IN H11 VO7 L9 VO0
C1 VO18 J1 VO22 L10 VO1
C2 DAC_GND1 J2 VO19 L11 NC*
C6 NC*J6 VSS2
*NC = Not Connected
REV. A
–8–
AD5533B
PIN FUNCTION DESCRIPTIONS
Pin Function
AGND (1–2) Analog GND Pins
AV
CC
(1–2) Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
V
DD
(1–4) V
DD
Supply Pins. Voltage range from 8 V to 16.5 V.
V
SS
(1–4) V
SS
Supply Pins. Voltage range from –4.75 V to –16.5 V.
DGND Digital GND Pins
DV
CC
Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.
DAC_GND (1–2) Reference GND Supply for all the DACs
REF_IN Reference Voltage for Channels 0–31
REF_OUT Reference Output Voltage
V
OUT
(0–31) Analog Output Voltages from the 32 Channels
V
IN
Analog Input Voltage
A4–A1
1
, A0
2
Parallel Interface. 5-address pins for 32 channels. A4 = MSB of channel address. A0 = LSB.
CAL
1
Parallel Interface. Control input that allows all 32 channels to acquire V
IN
simultaneously.
CS/SYNC This pin is both the active low chip select pin for the parallel interface and the frame synchronization pin for
the serial interface.
WR
1
Parallel Interface. Write pin. Active low. This is used in conjunction with the CS pin to address the device
using the parallel interface.
OFFSET_SEL
1
Parallel Interface. Offset select pin. Active high. This is used to select the offset channel.
SCLK
2
Serial Clock Input for Serial Interface. This operates at clock speeds up to 20 MHz.
D
IN2
Data Input for Serial Interface. Data must be valid on the falling edge of SCLK.
D
OUT
Output from the DAC Registers for Readback. Data is clocked out on the rising edge of SCLK and is valid
on the falling edge of SCLK.
SER/PAR
1
This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low,
the parallel interface will be used. If it is tied high, the serial interface will be used.
OFFS_IN Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to
this pin if the user wants to drive this pin with the offset channel.
OFFS_OUT Offset Output. This is the acquired/programmed offset voltage that can be tied to the OFFS_IN pin to
offset the span.
BUSY This output tells the user when the input voltage is being acquired. It goes low during acquisition and
returns high when the acquisition operation is complete.
TRACK/RESET
2
If this input is held high, V
IN
is acquired once the channel is addressed. While it is held low, the input to the
gain/offset stage is switched directly to V
IN
. The addressed channel begins to acquire V
IN
on the rising edge
of TRACK. See TRACK Input section for further information. This input can also be used as a means of
resetting the complete device to its power-on-reset conditions. This is achieved by applying a low going
pulse of between 90 ns and 200 ns to this pin. See section on RESET Function for further details.
NOTES
1
Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.
2
Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
REV. A
AD5533B
–9–
TERMINOLOGY
V
IN
to V
OUT
Nonlinearity
This is a measure of the maximum deviation from a straight line
passing through the endpoints of the V
IN
versus V
OUT
transfer
function. It is expressed as a percentage of the full-scale span.
Total Unadjusted Error (TUE)
This is a comprehensive specification that includes relative accu-
racy, gain, and offset errors. It is measured by sampling a range
of voltages on V
IN
and comparing the measured voltages on
V
OUT
to the ideal value. It is expressed in mV.
Offset Error
This is a measure of the output error when V
IN
= 70 mV. Ideally,
with V
IN
= 70 mV:
VGain Gain V mV
OUT OFFS IN
=×− −×()(())
_
70 1
Offset error is a measure of the difference between V
OUT
(actual)
and V
OUT
(ideal). It is expressed in mV and can be positive or
negative. See Figure 5.
Gain Error
This is a measure of the span error of the analog channel. It is
the deviation in slope of the transfer function. See Figure 5. It is
calculated as:
Gain Error Actual Full Scale Output
Ideal Full Scale Output Offset Error
=−
−
-
-
where
Ideal Full Scale Output Gain Gain V
OFFS IN
-=×− −×(.)(() )
_
296 1
Ideal Gain = 3.52
Output Temperature Coefficient
This is a measure of the change in analog output with changes in
temperature. It is expressed in ppm/°C.
DC Power Supply Rejection Ratio
DC Power Supply Rejection Ratio (PSRR) is a measure of
the change in analog output for a change in supply voltage
(V
DD
and V
SS
). It is expressed in dBs. V
DD
and V
SS
are varied ±5%.
DC Crosstalk
This is the dc change in the output level of one channel in response
to a full-scale change in the output of all other channels. It is
expressed in µV.
Output Settling Time
This is the time taken from when BUSY goes high to when the
output has settled to ±0.018%.
Acquisition Time
This is the time taken for the V
IN
input to be acquired. It is the
length of time that BUSY stays low.
OFFS_IN Settling Time
This is the time taken from a 0 V–3 V step change in input
voltage on OFFS_IN until the output has settled to within ±0.39%.
Digital Feedthrough
This is a measure of the impulse injected into the analog outputs
from the digital control inputs when the part is not being written
to, i.e., CS/SYNC is high. It is specified in nV-secs and is measured
with a worst-case change on the digital input pins, e.g., from all
0s to all 1s and vice versa.
Output Noise Spectral Density
This is a measure of internally generated random noise. Random
noise is characterized as a spectral density (voltage per root Hertz).
It is measured by acquiring 1.5 V on all channels and measuring
noise at the output. It is measured in nV/√Hz
typ.
AC Crosstalk
This is the area of the glitch that occurs on the output of one chan-
nel while another channel is acquiring. It is expressed in nV-secs.
2.96 3V70mV
0V
V
OUT
IDEAL
TRANSFER
FUNCTION
ACTUAL
TRANSFER
FUNCTION
OFFSET
ERROR
GAIN ERROR +
OFFSET ERROR
V
IN
UPPER
DEAD BAND
LOWER
DEAD BAND
Figure 5. ISHA Transfer Function
REV. A
–10–
AD5533B–Typical Performance Characteristics
V
IN
– V
0.0024
0.0000
–0.0024
0.1 2.96
V
OUT
ERROR – V
0.0020
0.0004
–0.0004
–0.0012
0.0012
0.0008
–0.0008
0.0016
–0.0020
–0.0016
T
A
= 25 C
V
REFIN
= 3V
V
OFFS_IN
= 0V
TPC 1. V
IN
to V
OUT
Accuracy After Offset and
Gain Adjustment
TEMPERATURE – C
4
3
0
–40 1200
OFFSET ERROR – mV
40 80
2
1
OFFSET ERROR
GAIN
3.530
3.525
3.500
GAIN
3.520
3.515
TPC 2. Offset Error and Gain vs. Temperature
SINK/SOURCE CURRENT – mA
3.530
3.525
3.515
6–64
VOUT – V
20–2–4
3.520
TA = 25ⴗC
VREFIN = 3V
VIN = 1V
TPC 3. V
OUT
Source and Sink Capability
100
90
10
0%
BUSY
T
A
= 25ⴗC
V
REFIN
= 3V
V
IN
= 0V TO 1.5V
V
OUT
5V
1V 2
␮
s
TPC 4. Acquisition Time and Output Settling Time
VOUT – V
70k
60k
05.2670 5.26825.2676
FREQUENCY
40k
30k
20k
10k
50k
63791
200 1545
TA = 25 C
VREFIN = 3V
VIN = 1.5V
VOFFS_IN = 0V
TPC 5. ISHA Mode Repeatability (64 K Acquisitions)
TOTA L UNADJUSTED ERROR – mV
40
20
0
–4 8–3
FREQUENCY
–2 –1 0 1 2 3 4 5 6 7
TPC 6. TUE Distribution at 25
°
C (ISHA Mode)
REV. A
AD5533B
–11–
TRACK
VIN
DAC ACQUISITION
CIRCUIT
V
OUT1
BUSY
OUTPUT
STAGE
CONTROLLER
THRESHOLD
VOLTAGE
PIN
DRIVER
DEVICE
UNDER
TEST
ONLY ONE CHANNEL SHOWN FOR SIMPLICITY
AD5533B
CONTROLLER
OUTPUT
STAGE
ACQUISITION
CIRCUIT
Figure 7. Typical ATE Circuit Using
TRACK
Input
FUNCTIONAL DESCRIPTION
The AD5533B can be thought of as consisting of an ADC and
32 DACs in a single package. The input voltage V
IN
is sampled
and converted into a digital word. The digital result is loaded into
one of the DAC registers and is converted (with gain and offset)
into an analog output voltage (V
OUT
0–V
OUT
31). Since the chan-
nel output voltage is effectively the output of a DAC there is no
droop associated with it. As long as power to the device is main-
tained, the output voltage will remain constant until this channel
is addressed again.
To update a single channel’s output voltage, the required new
voltage level is set up on the common input pin, V
IN
. The desired
channel is then addressed via the parallel port or the serial port.
When the channel address has been loaded, provided TRACK is
high, the circuit begins to acquire the correct code to load to the
DAC so that the DAC output matches the voltage on V
IN
. The
BUSY pin goes low and remains so until the acquisition is com-
plete. The noninverting input to the output buffer is tied to V
IN
during the acquisition period to avoid spurious outputs while the
DAC acquires the correct code. The acquisition is completed in
16 µs max. The BUSY pin goes high and the updated DAC output
assumes control of the output voltage. The output voltage of the
DAC is connected to the noninverting input of the output buffer.
Since the internal DACs are offset by 70 mV (max) from GND,
the minimum V
IN
in ISHA mode is 70 mV. The maximum V
IN
is
2.96 V due to the upper dead band of 40 mV (max).
On power-on, all the DACs, including the offset channel, are loaded
with zeros. Each of the 33 DACs is offset internally by 50 mV (typ)
from GND so the outputs V
OUT
0 to V
OUT
31 are 50 mV (typ) on
power-on if the OFFS_IN pin is driven directly by the on-board
offset channel (OFFS_OUT), i.e., if OFFS_IN = OFFS_OUT =
50 mV = > V
OUT
= (Gain ⫻ V
DAC
)
– (Gain – 1) ⫻ V
OFFS_IN
= 50 mV.
Analog Input
The equivalent analog input circuit is shown in Figure 6. The
capacitor C1 is typically 20 pF and can be attributed to pin capaci-
tance and 32 off-channels. When a channel is selected, an extra
7.5 pF (typ) is switched in. This capacitor C2 is charged to the
previously acquired voltage on that particular channel so it must
charge/discharge to the new level. It is essential that the external
source can charge/discharge this additional capacitance within
1µs–2 µs of channel selection so that V
IN
can be acquired accu-
rately. For this reason, a low impedance source is recommended.
C1
20pF
VIN C2
7.5pF
ADDRESSED CHANNEL
Figure 6. Analog Input Circuit
Large source impedances will significantly affect the performance
of the ADC. This may necessitate the use of an input buffer
amplifier.
Output Buffer Stage—Gain and Offset
The function of the output buffer stage is to translate the
50 mV–3 V typical output of the DAC to a wider range. This
is done by gaining up the DAC output by 3.52 and offsetting
the voltage by the voltage on OFFS_IN pin.
V 3.52 V 2.52 V
OUT DAC OFFS_IN
=× −×
V
DAC
is the output of the DAC.
V
OFFS_IN
is the voltage at the OFFS_IN pin.
Table I shows how the output range on V
OUT
relates to the
offset voltage supplied by the user.
Table I. Sample Output Voltage Ranges
V
OFFS_IN
(V) V
DAC
(V) V
OUT
(V)
00.05 to 3 0.176 to 10.56
10.05 to 3 –2.34 to +8.04
2.130 0.05 to 3 –5.192 to +5.192
V
OUT
is limited only by the headroom of the output amplifiers.
V
OUT
must be within maximum ratings.
Offset Voltage Channel
The offset voltage can be externally supplied by the user at
OFFS_IN or it can be supplied by an additional offset voltage
channel on the device itself. The required offset voltage is set up
on V
IN
and acquired by the offset DAC. This offset channel’s DAC
output is directly connected to OFFS_OUT. By connecting
OFFS_OUT to OFFS_IN, this offset voltage can be used as the
offset voltage for the 32 output amplifiers. It is important to
choose the offset so that V
OUT
is within maximum ratings.
REV. A
–12–
AD5533B
Reset Function
The reset function on the AD5533B can be used to reset all
nodes on this device to their power-on-reset condition. This is
implemented by applying a low-going pulse of between 90 ns and
200 ns to the TRACK/RESET pin on the device. If the applied
pulse is less than 90 ns, it is assumed to be a glitch and no opera-
tion takes place. If the applied pulse is wider than 200 ns, this pin
adopts its track function on the selected channel, V
IN
is switched to
the output buffer, and an acquisition on the channel will not occur
until a rising edge of TRACK.
TRACK Function
Normally in ISHA mode of operation, TRACK is held high and
the channel begins to acquire when it is addressed. However, if
TRACK is low when the channel is addressed, V
IN
is switched
to the output buffer and an acquisition on the channel will not
occur until a rising edge of TRACK. At this stage the BUSY pin
will go low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and
V
IN
is free to change again without affecting this output value.
This is useful in an application where the user wants to ramp up
V
IN
until V
OUT
reaches a particular level (Figure 7). V
IN
does
not need to be acquired continuously while it is ramping up.
TRACK can be kept low and only when V
OUT
has reached its
desired voltage is TRACK brought high. At this stage, the
acquisition of V
IN
begins.
In the example shown, a desired voltage is required on the output
of the pin driver. This voltage is represented by one input to a
comparator. The microcontroller/microprocessor ramps up the
input voltage on V
IN
through a DAC. TRACK is kept low while
the voltage on V
IN
ramps up so that V
IN
is not continually
acquired. When the desired voltage is reached on the output of the
pin driver, the comparator output switches. The µC/µP then
knows what code is required to be input in order to obtain the
desired voltage at the DUT. The TRACK input is now brought
high and the part begins to acquire V
IN
. BUSY goes low until V
IN
has been acquired. When BUSY goes high, the output buffer
is switched from V
IN
to the output of the DAC.
MODES OF OPERATION
The AD5533B can be used in three different modes. These modes
are set by two mode bits, the first two bits in the serial word.
The 01 option (DAC Mode) is not available for the AD5533B.
For information on this mode, refer to the AD5532B data sheet.
If you attempt to set up DAC Mode, the AD5533B will enter a
test mode and a 24-clock write will be necessary to clear this.
Table II. Modes of Operation
Mode Bit 1 Mode Bit 2 Operating Mode
00 ISHA Mode
01 DAC Mode (Not Available)
10 Acquire and Readback
11 Readback
1. ISHA Mode
In this standard mode, a channel is addressed and that channel
acquires the voltage on V
IN
. This mode requires a 10-bit
write (see Figure 3) to address the relevant channel
(V
OUT
0–V
OUT
31, offset channel, or all channels). MSB is
written first.
2. Acquire and Readback Mode
This mode allows the user to acquire V
IN
and read back the
data in a particular DAC register. The relevant channel is
addressed (10-bit write, MSB first) and V
IN
is acquired in 16 µs
(max). Following the acquisition, after the next falling edge
of
SYNC, the data in the relevant DAC register is clocked out
onto the D
OUT
line in a 14-bit serial format (see Figure 4).
During readback, D
IN
is ignored. The full acquisition time
must elapse before the DAC register data can be clocked out.
3. Readback Mode
Again, this is a readback mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of SYNC, the data in the relevant DAC
register is clocked out onto the D
OUT
line in a
14-bit serial format
(see Figure 4). The user must allow 400 ns
(min) between the
last SCLK falling edge in the 10-bit write and the falling edge
of SYNC in the 14-bit readback. The serial write and read words
can be seen in Figure 8.
This feature allows the user to read back the DAC register
code of any of the channels. Readback is useful if the system
has been calibrated and the user wants to know what code in
the DAC corresponds to a desired voltage on V
OUT
.
INTERFACES
Serial Interface
The SER/PAR pin is tied high to enable the serial interface and
to disable the parallel interface. The serial interface is controlled
by four pins as follows:
SYNC, D
IN
, SCLK
Standard 3-wire interface pins. The SYNC pin is shared
with the CS function of the parallel interface.
D
OUT
Data out pin for reading back the contents of the DAC registers.
The data is clocked out on the rising edge of SCLK and is
valid on the falling edge of SCLK.
Mode Bits
There are four different modes of operation as described above.
Cal Bit
When this is high, all 32 channels acquire V
IN
simultaneously. The
acquisition time is then 45 µs (typ) and accuracy may be reduced.
This bit is set low for normal operation.
Offset_Sel Bit
If this bit is set high, the offset channel is selected and bits
A4–A0 are ignored.
Test Bit
This must be set low for correct operation of the part.
A4–A0 Bit
Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).
REV. A
AD5533B
–13–
DB13–DB0 Bit
These are used in both readback modes to read a 14-bit word
from the addressed DAC register.
The serial interface is designed to allow easy interfacing to most
microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI™,
SPI™, DSP56000, TMS320, and ADSP-21xx, without the
need for any glue logic. When interfacing to the 8051, the
SCLK must be inverted. The Microprocessor/Microcontroller
Interface section explains how to interface to some popular
DSPs and microcontrollers.
Figures 3 and 4 show the timing diagram for a serial read and
write to the AD5533B. The serial interface works with both a
continuous and a noncontinuous serial clock. The first falling
edge of SYNC resets a counter that counts the number of serial
clocks to ensure the correct number of bits are shifted in and out
of the serial shift registers. Any further edges on SYNC are ignored
until the correct number of bits are shifted in or out. Once the
correct number of bits have been shifted in or out, the SCLK is
ignored. In order for another serial transfer to take place, the
counter must be reset by the falling edge of SYNC. In readback,
the first rising SCLK edge after the falling edge of SYNC causes
D
OUT
to leave its high impedance state and data is clocked out
onto the D
OUT
line and also on subsequent SCLK rising edges.
The D
OUT
pin goes back into a high impedance state on the falling
edge of the 14th SCLK. Data on the D
IN
line is latched in on the
first SCLK falling edge after the falling edge of the SYNC signal
and on subsequent SCLK falling edges. The serial interface will
not shift data in or out until it receives the falling edge of the
SYNC signal.
*SPI and QSPI are trademarks of Motorola, Inc.
OFFSET SEL A4–A0
CAL00
MSB LSB
MODE BIT 1 MODE BIT 2
MODE BITS
0
TEST BIT
a. 10-Bit Input Serial Write Word (ISHA Mode)
OFFSET SEL A4–A0
CAL01
MSB LSB
MODE BITS
DB13–DB0
0
TEST BIT
10-BIT
SERIAL WORD
WRITTEN TO PART
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
MSBLSB
b. Input Serial Interface (Acquire and Readback Mode)
OFFSET SEL A4–A0
011
MSB LSB
MODE BITS
DB13–DB0
0
TEST BIT
10-BIT
SERIAL WORD
WRITTEN TO PART
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
MSBLSB
c. Input Serial Interface (Readback Mode)
Figure 8. Serial Interface Formats
Parallel Interface
The SER/PAR bit is tied low to enable the parallel interface and
disable the serial interface. The parallel interface is controlled
by nine pins as follows:
CS
Active low package select pin. This pin is shared with the
SYNC function for the serial interface.
WR
Active low write pin. The values on the address pins are
latched on a rising edge of WR.
A4–A0
Five address pins (A4 = MSB of address, A0 = LSB). These
are used to address the relevant channel (out of a possible 32).
Offset_Sel
Offset select pin. This has the same function as the Offset_Sel
bit in the serial interface. When it is high, the offset channel
is addressed and the address on A4–A0 is ignored.
Cal
Same functionality as the Cal bit in the serial interface. When
this pin is high, all 32 channels acquire V
IN
simultaneously.
MICROPROCESSOR INTERFACING
AD5533B to ADSP-21xx Interface
The ADSP-21xx family of DSPs is easily interfaced to the
AD5533B without the need for extra logic.
A data transfer is initiated by writing a word to the TX register
after the SPORT has been enabled. In a write sequence, data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5533B on the falling edge of its SCLK. In
REV. A
–14–
AD5533B
readback, 16 bits of data are clocked out of the AD5533B on
each rising edge of SCLK and clocked into the DSP on the rising
edge of SCLK. D
IN
is ignored. The valid 14 bits of data will be
centered in the 16-bit RX register when using this configuration.
The SPORT control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right-Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0, External Framing Signal
ITFS = 1, Internal Framing Signal
SLEN = 1001, 10-Bit Data-Words (ISHA Mode Write)
SLEN = 1111, 16-Bit Data-Words (Readback Mode)
Figure 9 shows the connection diagram.
SCLK
AD5533B
*
DOUT
SYNC
DIN
DR
TFS
RFS
DT
SCLK
ADSP-2101/
ADSP-2103
*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. AD5533B to ADSP-2101/ADSP-2103 Interface
AD5533B to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is config-
ured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0
and the clock phase bit (CPHA) = 1. The SPI is configured by
writing to the SPI control register (SPCR)— see 68HC11 User
Manual. SCK of the 68HC11 drives the SCLK of the AD5533B,
the MOSI output drives the serial data line (D
IN
) of the AD5533B,
and the MISO input is driven from D
OUT
. The SYNC signal is
derived from a port line (PC7). When data is being transmitted to
the AD5533B, the SYNC line is taken low (PC7). Data appear-
ing on the MOSI output is valid on the falling edge of SCK.
Serial data from the 68HC11 is transmitted in 8-bit bytes with
only eight falling clock edges occurring in the transmit cycle.
Data is transmitted MSB first. In order to transmit 10 data bits
in ISHA mode it is important to left-justify the data in the SPDR
register. PC7 must be pulled low to start a transfer. It is taken
high and pulled low again before any further read/write cycles
can take place. A connection diagram is shown in Figure 10.
SCLK
AD5533B
*
DOUT
SYNC
DIN
MISO
PC7
SCK
MC68HC11
*
*ADDITIONAL PINS OMITTED FOR CLARITY
MOSI
Figure 10. AD5533B to MC68HC11 Interface
AD5533B to PIC16C6x/7x
The PIC16C6x synchronous serial port (SSP) is configured as an
SPI Master with the clock polarity bit = 0. This is done by writing
to the Synchronous Serial Port Control Register (SSPCON). See
PIC16/17 Microcontroller User Manual. In this example I/O port
RA1 is being used to pulse SYNC and enable the serial port
of the AD5533B. This microcontroller transfers only eight bits of
data during each serial transfer operation; therefore, two consecu-
tive read/write operations are needed for a 10-bit write and a 14-bit
readback. Figure 11 shows the connection diagram.
SCLK
PIC16C6x/7x
*
DOUT
SYNC
DIN
SCK/RC3
AD5533B
*
*ADDITIONAL PINS OMITTED FOR CLARITY
SDO/RC5
SDI/RC4
RA1
Figure 11. AD5533B to PIC16C6x/7x Interface
AD5533B to 8051
The AD5533B requires a clock synchronized to the serial
data. The 8051 serial interface must therefore be operated in
Mode 0. In this mode, serial data enters and exits through RxD
and a shift clock is output on TxD. Figure 12 shows how the 8051
is connected to the AD5533B. Because the AD5533B shifts data
out on the rising edge of the shift clock and latches data in on
the falling edge, the shift clock must be inverted. The AD5533B
requires its data with the MSB first. Since the 8051 outputs
the LSB first, the transmit routine must take this into account.
8051
*
SCLK
D
OUT
SYNC
D
IN
TXD
AD5533B
*
*ADDITIONAL PINS OMITTED FOR CLARITY
RXD
P1.1
Figure 12. AD5533B to 8051 Interface
APPLICATION CIRCUITS
AD5533B in a Typical ATE System
The AD5533B infinite sample-and-hold is ideally suited for use
in automatic test equipment. Several ISHAs are required to
control pin drivers, comparators, active loads, and signal timing.
Traditionally, sample-and-hold devices with droop were used in
these applications. These required refreshing to prevent the voltage
from drifting.
The AD5533B has several advantages: no refreshing is required,
there is no droop, pedestal error is eliminated, and there is no
need for extra filtering to remove glitches. Overall, a higher level
of integration is achieved in a smaller area. See Figure 13.
REV. A
AD5533B
–15–
ISHAs
ACTIVE
LOAD
DRIVER
COMPARATOR
FORMATTER
COMPARE
REGISTER
STORED
DATA
AND INHIBIT
PATTERN
PERIOD
GENERATION
AND
DELAY
TIMING
SYSTEM BUS
ISHA
PARAMETRIC
MEASUREMENT
UNIT
SYSTEM BUS
DUT
ISHA
ISHA
ISHA
ISHA
ISHA
ISHA
Figure 13. AD5533B in an ATE System
Typical Application Circuit
The AD5533B can be used to set up voltage levels on 32 channels as
shown in the circuit below. An AD780 provides the 3 V reference
for the AD5533B, and for the AD5541 16-bit DAC. A simple 3-wire
serial interface is used to write to the AD5541. Because the AD5541
has an output resistance of 6.25 kΩ (typ), the time taken to charge/
discharge the capacitance at the V
IN
pin is significant. Thus an
AD820 is used to buffer the DAC output. Note that it is important
to minimize noise on V
IN
and REFIN when laying out this circuit.
AD5533B*
OFFS_IN
OFFS_OUT
REFIN
V
IN
SCLK DIN
SYNC
AV
CC
DV
CC
V
SS
V
DD
V
OUT
0–31
AD820
CS
DIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
AD780*
V
OUT
AD5541*
REF
AV
CC
Figure 14. Typical Application Circuit
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5533B is mounted should be designed so that the analog
and digital sections are separated and confined to certain areas
of the board. If the AD5533B is in a system where multiple
devices require an AGND-to-DGND connection, the connection
should be made at one point only. The star ground point should
be established as close as possible to the device. For supplies with
multiple pins (V
SS
, V
DD
, AV
CC
) it is recommended to tie those
pins together. The AD5533B should have ample supply bypass-
ing of 10 µF in parallel with 0.1 µF on each supply located as
close to the package as possible, ideally right up against the device.
The 10 µF capacitors are the tantalum bead type. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), like the common ceramic types
that provide a low impedance path to ground at high frequencies,
to handle transient currents due to internal logic switching.
The power supply lines of the AD5533B should use as large a trace
as possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals such
as clocks should be shielded with digital ground to avoid radiating
noise to other parts of the board, and should never be run near
the reference inputs. A ground line routed between the D
IN
and
SCLK lines will help reduce crosstalk between them (not required
on a multilayer board as there will be a separate ground plane,
but separating the lines will help). It is essential to minimize
noise on V
IN
and REFIN lines.
Note it is essential to minimize noise on V
IN
and REFIN lines.
Particularly for optimum ISHA performance, the V
IN
line must
be kept noise-free. Depending on the noise performance of the
board, a noise filtering capacitor may be required on the V
IN
line.
If this capacitor is necessary, then for optimum throughput it may
be necessary to buffer the source that is driving V
IN
. Avoid cross-
over of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other. This reduces the
effects of feedthrough through the board. A microstrip technique is
by far the best, but not always possible with a double-sided board.
In this technique, the component side of the board is dedicated
to ground plane while signal traces are placed on the solder side.
As is the case for all thin packages, care must be taken to avoid
flexing the CSPBGA package and to avoid a point load on the
surface of this package during the assembly process.
–16–
C02715–0–9/02(A)
PRINTED IN U.S.A.
AD5533B
REV. A
OUTLINE DIMENSIONS
74-Lead Chip Scale Ball Grid Array [CSPBGA]
(BC-74)
Dimensions shown in millimeters
A
B
C
D
E
F
G
H
J
K
L
11 10 9 8 7 6 5 4 3 2 1
1.00
BSC
1.00 BSC
BOT TOM
VIEW
A1
TOP VIEW
DETAIL A
1.70
MAX
12.00 BSC
SQ
10.00 BSC
SQ
A1 CORNER
INDEX AREA
SEATING
PLANE
DETAIL A
BALL DIAMETER
0.30 MIN
0.70
0.60
0.50
0.20 MAX
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-192ABD-1
Revision History
Location Page
9/02—Data Sheet changed from REV. 0 to REV. A.
Term LFBGA updated to CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global
Replaced FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Additions to SERIAL INTERFACE Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Replaced Figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Additions to POWER SUPPLY DECOUPLING section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Updated BC-74 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16