September 2014 Rev. 1.4a www.microsemi.com 1
© 2014 Microsemi Corporation
Regulating Pulse Width Modulator
Block Diagram
+VIN
GROUND
SYNC
RT
CT
DISCHARGE
COMPENSATION
INV. INPUT
N.I. INPUT
SOFT-SART
SHUTDOWN 5k
5k
ERROR
AMP
VIN
VREF
50µA
LATCH
S
P.W.M.
F/F
OSCILLATOR
OSC OUTPUT
TO
INTERNAL CIRCUITRY
REFERENCE
REGULATOR U.V.
LOCKOUT
VREF
R
Q
Q
+
+
VC
OUTPUT A
OUTPUT B
OUTPUT A
OUTPUT B
SG1527A OUTPUT STAGE
SG1525A OUTPUT STAGE
VC
Figure 1 · Block Diagram
Features
8V to 35V Operation
5.1V Reference Trimmed to 1%
100Hz to 500kHz Oscillator Range
Separate Oscillator Sync Terminal
Adjustable Deadtime Control
Internal Soft-start
Input Undervoltage Lockout
Latching P.W.M. to Prevent Multiple Pulses
Dual Source/Sink Output Drivers
High Reliability Features
Following are the high reliability features of SG1525A
and SG1527A:
Available to MIL-STD-883, ¶ 1.2.1
MIL-M38510/12602BEA - JAN1525AJ
MIL-M38510/12604BEA - JAN1527AJ
MSC-AMS level “S” Processing Available
Description
The SG1525A/1527A series of pulse width modulator integrated
circuits are designed to offer improved performance and lower
external parts count when used to implement all types of switching
power supplies. The on-chip +5.1 V reference is trimmed to ±1%
initial accuracy and the input common-mode range of the error
amplifier includes the reference voltage, eliminating external
potentiometers and divider resistors. A Sync input to the oscillator
allows multiple units to be slaved together, or a single unit to be
synchronized to an external system clock. A single resistor between
the CT pin and the Discharge pin provides a wide range of deadtime
adjustment. These devices also feature built-in soft-start circuitry
with only a timing capacitor required externally. A Shutdown pin
controls both the soft-start circuitry and the output stages, providing
instantaneous turn-off with soft-start recycle for slow turn-on. These
functions are also controlled by an undervoltage lockout which
keeps the outputs off and the soft-start capacitor discharged for
input voltages less than that required for normal operation. Another
unique feature of these PWM circuits is a latch following the
comparator. Once a PWM pulse has been terminated for any
reason, the outputs remain off for the duration of the period. The
latch is reset with each clock pulse. The output stages are totem-
pole designs capable of sourcing or sinking in excess of 200mA.
The SG1525A output stage features NOR logic, giving a LOW
output for an OFF state. The SG1527A utilizes OR logic, which
results in a HIGH output level when OFF.
SG1525A/SG2525A/SG3525A
SG1527A/SG2527A/SG3527A
Regulating Pulse Width Modulator
2
Connection Diagrams and Ordering Information
Ambient
Temperature
Type
Package
Packaging
Type
Connection Diagram
-55°C to
125°C
J
16-PIN
ceramic DIP
CERDIP
5
4
3
2
1
INV. Input
Soft-start
C
SYNC
N.I. Input
6
15
14
13
12
11
16
7
8 9
10
Discharge
ROutput A
Ground
V
C
V
Output B
+V
T
T
REF
IN
Shutdown
Compensation
OSC. Output
N Package: RoHS Compliant / Pb-free
Transition DC: 0503
N Package: RoHS / Pb-free 100%
Matte Tin Lead Finish
-25°C to 85°C
-0°C to 70°C
-25°C to 85°C
N
16-PIN
plastic DIP
PDIP
-0°C to 70°C
-25°C to 85°C
DW
16-pin wide
body
plastic
SOIC
SOIC
5
4
3
2
1
INV. Input
Shutdown
Compensation
Soft-start
SYNC
N.I. Input
6
15
14
13
12
11
16
7
8 9
10
C
T
R
T
Ground
VC
Output B
V
REF
+V
IN
Output A
OSC. Output
Discharge
DW Package: RoHS Compliant / Pb-
free Transition DC: 0516
DW Package: RoHS / Pb-free 100%
Matte Tin Lead Finish
-0°C to 70°C
-55°C to
125°C
L
20-pin
ceramic
leadless
chip carrier
(LCC)
CLCC
5
4
3 2 1
13. Shutdown
10. Soft-start
7. C
5. OSC. Output
4. SYNC
3. N.I. Input
6
15
14
13
12
11
16
17
18
1920
7
8
9 10
15. Ground
17. V
C
18. Output B
20. V
REF
19. +V
IN
14. Output A
2. INV. Input
1. N.C.
16. N.C.
11. N.C.
12. Comp
6. N.C.
9. Discharge
T
8. R
T
Notes:
1. Contact factory for JAN and DESC product availability.
2. All packages are viewed from the top.
3. Hermetic Packages J & L use Sn63Pb37 hot solder dip lead finish, contact factory for availability of RoHS compliant
versions.
Absolute Maximum Ratings1
3
Absolute Maximum Ratings1
Parameter
Value
Units
Supply Voltage (+VIN)
40
V
Collector Supply Voltage (VC)
40
V
Logic Inputs
-0.3 to 5.5
V
Analog Inputs
-0.3 to VIN
V
Output Current, Source or Sink
500
mA
Reference Load Current
50
mA
Oscillator Charging Current
5
mA
Operating Junction Temperature
Hermetic (J, L Packages)
150
°C
Plastic (N, DW Packages)
150
°C
Storage Temperature Range
-65 to 150
°C
Lead Temperature (Soldering, 10 seconds)
300
°C
RoHS Peak Package Solder Reflow Temp. (40 s max. exp.)
260 (+0, -5)
°C
Note: Values beyond which damage may occur
Thermal Data
Parameter
Value
Units
J Package
Thermal Resistance-Junction to Case, θJC
30
°C/W
Thermal Resistance-Junction to Ambient, θJA
80
°C/W
N Package
Thermal Resistance-Junction to Case, θJC
40
°C/W
Thermal Resistance-Junction to Ambient, θJA
65
°C/W
DW Package
Thermal Resistance-Junction to Case, θJC
40
°C/W
Thermal Resistance-Junction to Ambient, θJA
95
°C/W
L Package
Thermal Resistance-Junction to Case, θJC
35
°C/W
Thermal Resistance-Junction to Ambient, θJA
120
°C/W
Notes:
1. Junction Temperature Calculation: TJ = TA + (PD × θJA).
2. The above numbers for θJC are maximums for the limiting thermal resistance of the package in a standard mounting
configuration. The θJA numbers are meant to be guidelines for the thermal performance of the device/pc-board system. All of
the above assume no ambient airflow.
Regulating Pulse Width Modulator
4
Recommended Operating Conditions1
Parameter
Value
Units
Input Voltage (+VIN)
8 to 35
V
Collector Voltage (VC)
4.5 to 35
V
Sink/Source Load Current (steady state)
0 to 100
mA
Sink/Source Load Current (peak)
0 to 400
mA
Reference Load Current
0 to 20
mA
Oscillator Frequency Range
0.1 to 350
kHz
Oscillator Timing Resistor (RT)
2 to 150
kΩ
Deadtime Resistor Range (RD)
0 to 500
Ω
Maximum Shutdown Source Impedance
5
kΩ
Oscillator Timing Capacitor (CT)
0.001 to 0.1
µF
Operating Ambient Temperature Range1
SG1525A/SG1527A
-55 to 125
°C
SG2525A/SG2527A
-25 to 85
°C
SG3525A/SG3527A
0 to 70
°C
Note: Range over which the device is functional.
Electrical Characteristics
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for
SG1525A/SG1527A with -55°C ≤ TA ≤ 125°C, SG2525A/SG2527A with -25°C ≤ TA ≤ 85°C,
SG3525A/SG3527A with 0°C ≤ TA ≤ 70°C, and +VIN = 20V. Low duty cycle pulse testing techniques are
used that maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Test Conditions
SG1525A/2525A
SG1527A/2527A
SG3525A
SG3527A
Units
Min
Typ
Max
Min
Typ
Max
Reference
Section
1
Output Voltage
TJ = 25C
5.05
5.10
5.15
5.00
5.10
5.20
V
Line Regulation
VIN = 8V to 35V
10
30
10
30
mV
Load Regulation
IL = 0 to 20mA
20
50
20
50
mV
Temperature Stability1
Over Operating
Temperature Range
20
50
20
50
mV
Total Output Voltage
Range1
Over Line, Load and
Temperature
5.00
5.20
4.95
5.25
V
Short Circuit Current
VREF = 0V, TJ = 25C
80
100
80
100
mA
Output Noise Voltage1
10Hz ≤ f ≤ 10kHz,
TJ = 25°C
40
200
40
200
Vrms
Long Term Stability1
TJ = 125C
20
50
20
50
mV/khr
Notes:
1. These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
2. FOSC = 40 kHz (RT = 3.6k Ω, CT = 0.01µF, RD = 0Ω.).
3. Applies to SG1525A/2525A/3525A only, due to polarity of output pulses.
Electrical Characteristics (continued)
5
Electrical Characteristics (continued)
Parameter
Test Conditions
SG1525A/2525A
SG1527A/2527A
SG3525A/SG3527A
Units
Min
Typ
Max
Min
Typ
Max
Oscillator Section2
Initial Accuracy
TJ = 25C
37.6
40
42.4
37.6
40
42.4
kHz
Voltage Stability
VIN = 8V to 35V
±0.3
±1
±1
±2
%
Temperature Stability1
MIN ≤ TJ ≤ MAX
±3
±6
±3
±6
%
Minimum Frequency1
RT = 150kΩ, CT = 0.1μF
150
150
Hz
Maximum Frequency1
RT = 2 kΩ, CT = 1nF
350
350
kHz
Current Mirror
IRT = 2mA
1.7
2.0
2.2
1.7
2.0
2.2
mA
Clock Amplitude
3.0
3.5
3.0
3.5
V
Clock Width
TJ = 25C
0.3
0.5
1.0
0.3
0.5
1.0
µs
Sync Threshold
1.2
2.0
2.8
1.2
2.0
2.8
V
Sync Input Current
Sync Voltage = 3.5V
1.0
2.5
1.0
2.5
mA
Error Amplifier Section (VCM = 5.1V)
Input Offset Voltage
0.5
5
2
10
mV
Input Bias Current
1
10
1
10
µA
Input Offset Current
1
1
µA
DC Open Loop Gain
RL ≥ 10MΩ, TJ = 25C
60
75
60
75
dB
Output Low Level
0.2
0.5
0.2
0.5
V
Output High Level
3.8
5.6
3.8
5.6
V
Common Mode Rejection
VCM = 1.5V to 5.2 V
60
75
60
75
dB
Supply Voltage Rejection
VIN = 8V to 35V
50
60
50
60
dB
PWM Comparator Section2
Minimum Duty Cycle
VCOMP = 0.6V
0
0
%
Maximum Duty Cycle
VCOMP = 3.6V
45
49
45
49
%
Input Threshold2
Zero Duty Cycle
0.6
0.9
0.6
0.9
V
Maximum Duty Cycle
3.3
3.6
3.3
3.6
V
Input Bias Current
0.05
2.0
0.05
2.0
µA
Soft-Start Section
Soft Start Current
VSHUTDOWN = 0V
25
50
80
25
50
80
µA
Soft Start Voltage
VSHUTDOWN = 2V
0.4
0.6
0.4
0.6
V
Shutdown Input Current
VSHUTDOWN = 2.5V
0.4
1.0
0.4
1.0
mA
Regulating Pulse Width Modulator
6
Parameter
Test Conditions
SG1525A/2525A
SG1527A/2527A
SG3525A/SG3527A
Units
Min
Typ
Max
Min
Typ
Max
Output Drivers Section (each transistor, VC = 20V)
Output High Level
ISOURCE = 20mA
18
19
18
19
V
ISOURCE = 100mA
17
18
17
18
V
Output Low Level
ISINK = 20mA
0.2
0.4
0.2
0.4
V
ISINK = 100mA
1.0
2.2
1.0
2.2
V
Undervoltage Lockout
VCOMP and VSS = High
6
7
8
6
7
8
V
Collector Leakage3
VC = 35V
200
200
µA
Rise Time
CL = 1nF, TJ = 25°C
100
600
100
600
ns
Fall Time
CL = 1nF, TJ = 25°C
50
300
50
300
ns
Shutdown Delay1
VSD = 3V, CS = 0,
TJ = 25°C
0.2
0.5
0.2
0.5
µs
Total Standby Current
Standby Current
VIN = 35V
14
20
14
20
mA
Notes:
1. These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
2. FOSC = 40 kHz (RT = 3.6k Ω, CT = 0.01µF, RD = 0Ω).
3. Applies to SG1525A/2525A/3525A only, due to polarity of output pulses.
Oscillator Section
7
Oscillator Section
VREF
GND
SYNC
RT
CT
DISCHARGE 400µA
Q1
Q3
Q5Q8
Q6Q9
Q10 Q11
Q12 Q13
Q2Q4
Q7
16
6
5
3
7
12
7.4k
14k
2k
25k Q14
3k 250
4
CLOCK
BLANKING
TO OUTPUT
RAMP
TO PWM
1k
23k
1k
5 pF
2k
Figure 2 · Oscillator Schematic
CT = 1nF
CT = 2nF
CT = 5nF
CT = .01µF
CT = .02µF
CT = .05µF
CT = 0.1µF
RD = 0
200
100
50
20
10
5
2
0
1
2
5
10
20
50
100
200
500
1000
2000
5000
RD
CT
657
RT
CHARGE TIME - µs
TIMING RESISTOR (RT) - kΩ
Figure 3 · Oscillator Charge Time versus RT And CT
CT = 1nF
CT = 2nF
CT = 5nF
CT = .01µF
CT = .02µF
CT = .05µF
CT = 0.1µF
500
400
300
200
100
0
0.2
0.5
1
10
20
50
100
200
2
5
DISCHARGE TIME - ms
DEADTIME RESISTOR (RD) - Ω
Figure 4 · Oscillator Discharge Time versus RD And CT
Oscillator charge time versus RT
and CT
Regulating Pulse Width Modulator
8
Error Amplifier Section
5.8 V
INV.
INPUT
Q2
Q3
+VIN
Q4
Q1
1
2
15
9
To PWM
COMPARATOR
100 µA
200 µA 30 Ω
N.I.
INPUT
COMP
Figure 5 · Error Amplifier
RZ
CP
1
2
80
60
40
20
0
10
RZ = 0
RZ = 20k
CP = 0
CP = 1nF
1
10
100
1k
10k
100k
1M
10M
+
-
FREQUENCY - Hz
VOLTAGE GAIN - DB
Figure 6 · Error Amplifier Open-Loop Frequency
Response
Output Section
Q1 Q2 Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q11
Q6 OMITTED
in SG1527A
5k 10k 10k
+VREF
+VIN +VC
5k
2k
13
CLOCK PWMF/F
11
14 OUTPUT
Q10
Figure 7 · Output Circuit (½ circuit shown)
4
3
1
2
0
.01
.02
.03
.05
.10
.20
.30
.50
1A
VIN = 20 V
TA = 25°C
SOURCE SAT. VC - VOH
SINK SAT. VOL
Figure 8 · Output Saturation Characteristics
Application Information
9
Application Information
+VSUPPLY
+VC
GND
13
11
14
12
B
A
R2
R1
Q1 TO OUTPUT FILTER
RETURN
SG1525A
For single-ended supplies, the driver outputs are
grounded. The VC terminal is switched to ground by
the totem-pole source transistors on alternate
oscillator cycles.
+VSUPPLY
R1
C1
R2
C2
R3
Q1
Q2
T1
A
B
GND
SG1525A
+VC
13
12
14
11
RETURN
In conventional push-pull bipolar designs, forward base
drive is controlled by R1 - R3 .Rapid turn-off times for the
power devices are achieved with speed-up capacitors
C1 and C2.
A
B
GND
SG1525A
+VC
13
12
14
11
R1
Q1
Q2
RETURN
+VSUPPLY
T1
The low source impedance of the output drivers
provides rapid charging of power FET input
capacitance while minimizing external components.
13
12
14
11
RETURN
+VSUPPLY
Q1
Q2
R1
R2
T1
A
B
GND
SG1525A
+VCT2
C1
C2
R1
Low power transformers can be driven directly by the
SG1525A. Automatic reset occurs during deadtime, when
both ends of the primary winding are switched to ground.
Regulating Pulse Width Modulator
10
Shutdown Options
1. Use an external transistor or open-collector comparator to pull down on the Comp terminal. This sets the
PWM latch turning off both outputs. If the shutdown signal is momentary, pulse-by-pulse protection can be
accomplished as the PWM latch resets with each clock pulse.
2. The same results can be accomplished by pulling down on the Soft-Start terminal with the difference that on
this pin, shutdown does not affect the amplifier compensation network but must discharge any Soft-Start
capacitor.
3. Apply a positive-going signal to the Shutdown terminal. This provides most rapid shutdown of the outputs
but will not immediately set the PWM latch if there is a Soft-Start capacitor. This capacitor discharges but
with a current of approximately twice the charging current.
4. The shutdown terminal can be used to set the PWM latch on a pulse-by-pulse basis if there is no external
capacitance on Soft-Start terminal. Slow turn-on may still be accomplished by applying an external
capacitor, blocking diode, and charging resistor to the comp terminal. (See SG1524 Application Note).
VREF
CLOCK
SYNC
3 kΩ
10 kΩ
1.5
kΩ
PWM
ADJ
0.009µF
0.1µF
RAMP
0.001µF
DEADTIME
3.6 kΩ
100 Ω
10 kΩ
0.01µF
COMP
+
_
E/A
O
S
C
I
L
L
A
T
O
R
FLIP/
FLOP
REFERENCE
REGULATOR
0.1µF
RT
CT
1 = VOS
2 = I(+)
3 = I(-)
1
3
2 2
3
1
2 2
33
V/I METER
_
+
D.U.T
50 µA
5k 5 k
A
B
11
OUT A
OUT B
GND
SOFTSTART
5µF
SHUTDOWN
2k 2k VREF
+
1k, 1W
(2)
0.1µF
VC
0.1µF
+VIN
PWM
16
4
3
6
7
5
9
1
2
8
12
14
11
13
15
10
Figure 9 · SG1525A/1527A Lab Test Fixture
Package Outline Dimensions
11
Package Outline Dimensions
Controlling dimensions are in metric, inches equivalents are shown for general information.
H
e
A 2
A 1
c
BL
E
D
18
9
16
SEATING PLANE
A
Dim
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
A
2.06
2.65
0.081
0.104
A1
0.10
0.30
0.004
0.012
A2
2.03
2.55
0.080
0.100
B
0.33
0.51
0.013
0.020
c
0.23
0.32
0.009
0.013
D
10.08
10.50
0.397
0.413
E
7.40
7.60
0.291
0.299
e
1.27 BSC
0.05 BSC
H
10.00
10.65
0.394
0.419
L
0.40
1.27
0.016
0.050
θ
0°
8°
0°
8°
*LC
-
0.10
-
0.004
*Lead co planarity
Note:
Dimensions do not include protrusions; these shall
not exceed 0.155mm (.006”) on any side. Lead
dimension shall not include solder coverage.
Dimensions are in mm, inches are for reference only.
Figure 10 · DW 16-Pin SOWB Package Dimensions
A
E1
D
eb
L
E
c
θ
b1
SEATING PLANE
1
A2
A1
Figure 11 ·
Dim
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
A
-
5.33
-
0.210
A1
0.38
-
0.015
-
A2
3.30 Typ.
0.130 Typ.
b
0.36
0.56
0.014
0.022
b1
1.14
1.78
0.045
0.070
c
0.20
0.36
0.008
0.014
D
18.67
19.69
0.735
0.775
e
2.54 BSC
0.100 BSC
E
7.62
8.26
0.300
0.325
E1
6.10
7.11
0.240
0.280
L
2.92
0.381
0.115
0.150
θ
-
15°
-
15°
Note:
Dimensions do not include protrusions; these shall
not exceed 0.155mm (.006”) on any side. Lead
dimension shall not include solder coverage.
Dimensions are in mm, inches are for reference only.
Figure 11 · N 16-Pin Plastic Dual Inline Package Dimensions
Regulating Pulse Width Modulator
12
Package Outline Dimensions (continued)
Controlling dimensions are in inches, metric equivalents are shown for general information.
θ
D
e
9
16
18
eA
b
H
b2
c
Seating Plane
E
A
Q
L
Dim
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
A
-
5.08
-
0.200
b
0.38
0.51
0.015
0.020
b2
1.04
1.65
0.045
0.065
c
0.20
0.38
0.008
0.015
D
19.30
19.94
0.760
0.785
E
5.59
7.11
0.220
0.280
e
2.54 BSC
0.100 BSC
eA
7.37
7.87
0.290
0.310
H
0.63
1.78
0.025
0.070
L
3.18
5.08
0.125
0.200
α
-
15°
-
15°
Q
0.51
1.02
0.020
0.040
Note:
Dimensions do not include protrusions; these shall
not exceed 0.155mm (.006”) on any side. Lead
dimension shall not include solder coverage.
Figure 12 · J 16-Pin Ceramic Dual Inline Package Dimensions
D
E3
L
L2
B1 eB3
A2
A1
A
1
3
8
13
18
h
E
Dim
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
D/E
8.64
9.14
0.340
0.360
E3
-
8.128
-
0.320
e
1.270 BSC
0.050 BSC
B1
0.635 TYP
0.025 TYP
L
1.02
1.52
0.040
0.060
A
1.626
2.286
0.064
0.090
h
1.016 TYP
0.040 TYP
A1
1.372
1.68
0.054
0.066
A2
-
1.168
-
0.046
L2
1.91
2.41
0.075
0.95
B3
0.203R
0.008R
Note:
All exposed metalized area shall be gold plated
60 micro-inch minimum thickness over nickel
plated unless otherwise specified in purchase
order.
Figure 13 · L 20-Pin Ceramic LCC Package Outline Dimensions
SG1525A/SG1527A.1/09.14
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