HM514800C Series HM51S4800C Series 524,288-word x 8-bit Dynamic Random Access Memory Description The Hitachi HM51(S)4800C are CMOS dynamic RAM organized as 524,288-word x 8-bit. HM51(S)4800C have realized higher density, higher performance and various functions by employing 0.8 m CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4800C offer Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM51(S)4800C to be packaged in standard 400-mil 28-pin plastic SOJ and standard 400-mil 28-pin plastic TSOPII. Internal refresh timer enables HM51S4800C self refresh operation. Features * Single 5 V ( 10%) * High speed Access time: 60 ns/70 ns/80 ns (max) * Low power dissipation Active mode: 605 mW/550 mW/495 mW (max) Standby mode: 11 mW (max) 1.1 mW (max) (L-version) * Fast page mode capability * 1,024 refresh cycles: 16 ms 128 ms (L-version) * 2 variations of refresh RAS-only refresh CAS-before-RAS refresh * Battery backup operation (L-version) * Self refresh operation (HM51S4800C) HM514800C, HM51S4800C Series Ordering Information Type No. Access Time Package HM514800CJ-6 HM514800CJ-7 HM514800CJ-8 60 ns 70 ns 80 ns 400-mil 28-pin plastic SOJ (CP-28D) HM514800CLJ-6 HM514800CLJ-7 HM514800CLJ-8 60 ns 70 ns 80 ns HM51S4800CJ-6 HM51S4800CJ-7 HM51S4800CJ-8 60 ns 70 ns 80 ns HM51S4800CLJ-6 HM51S4800CLJ-7 HM51S4800CLJ-8 60 ns 70 ns 80 ns HM514800CTT-6 HM514800CTT-7 HM514800CTT-8 60 ns 70 ns 80 ns HM514800CLTT-6 HM514800CLTT-7 HM514800CLTT-8 60 ns 70 ns 80 ns HM51S4800CTT-6 HM51S4800CTT-7 HM51S4800CTT-8 60 ns 70 ns 80 ns HM51S4800CLTT-6 HM51S4800CLTT-7 HM51S4800CLTT-8 60 ns 70 ns 80 ns 2 400-mil 28-pin plastic TSOP II (TTP-28D) HM514800C, HM51S4800C Series Pin Arrangement HM514800CJ/CLJ Series HM51S4800CJ/CLJ Series HM514800CTT/CLTT Series HM51S4800CTT/CLTT Series VCC 1 28 VSS VCC 1 28 VSS I/O0 2 27 I/O7 I/O0 2 27 I/O7 I/O1 3 26 I/O6 I/O1 3 26 I/O6 I/O2 4 25 I/O5 I/O2 4 25 I/O5 I/O3 5 24 I/O4 I/O3 5 24 I/O4 NC 6 23 CAS NC 6 23 CAS WE 7 22 OE WE 7 22 OE 21 NC RAS 8 21 NC RAS 8 A9 9 20 A8 A9 9 20 A8 A0 10 19 A7 A0 10 19 A7 A1 11 18 A6 A1 11 18 A6 A2 12 17 A5 A2 12 17 A5 A3 13 16 A4 A3 13 16 A4 VCC 14 15 VSS VCC 14 15 VSS (Top view) (Top view) Pin Description Pin Name Function A0 - A9 Address input - Row address - Column address - Refresh address A0 - A9 A0 - A8 A0 - A9 I/O0 - I/O7 Data-in/data-out RAS Row address strobe CAS Column address strobe WE Read/write enable OE Output enable VCC Power (+5 V) VSS Ground 3 4 Row Driver Row Driver Row Driver OE Control Circuit I/O5 Row Driver Row Driver Row Driver Row Address Buffer Address A0-A9 I/O6 Row Driver Row Driver Row Driver Row Driver Column Address Buffer 256 k Memory Array Mat WE Control Circuit I/O Bus & Column Decoder CAS Control Circuit 256 k Memory Array Mat OE 256 k Memory Array Mat WE 256 k Memory Array Mat CAS I/O Bus & Column Decoder Row Driver 256 k Memory Array Mat I/O1 Buff. I/O2 Buff. I/O3 Buff. I/O4 Buff. I/O Bus & Column Decoder 256 k Memory Array Mat I/O4 256 k Memory Array Mat 256 k Memory Array Mat I/O3 I/O Bus & Column Decoder Row Driver 256 k Memory Array Mat Row Driver 256 k Memory Array Mat I/O2 I/O Bus & Column Decoder RAS I/O Bus & Column Decoder 256 k Memory Array Mat Row Driver 256 k Memory Array Mat I/O1 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat RAS Control Circuit 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat HM514800C, HM51S4800C Series Block Diagram I/O7 Row Decoder & Peripheral Circuit Row Driver I/O8 I/O5 Buff. I/O6 Buff. I/O7 Buff. I/O8 Buff. Row Driver HM514800C, HM51S4800C Series Operation Mode The HM51(S)4800C series has the following 11 operation modes. 1. Read cycle 2. Early write cycle 3. Delayed write cycle 4. Read-modify-write cycle 5. RAS-only refresh cycle 6. CAS-before-RAS refresh cycle 7. Self refresh cycle (HM51S4800C) 8. Fast page mode read cycle 9. Fast page mode early write cycle 10. Fast page mode delayed write cycle 11. Fast page mode read-modify-write cycle Inputs RAS CAS WE OE Output Operation H H D D Open Standby H L H L Valid Standby L L H L L L Valid Read cycle *2 D Open Early write cycle *2 L L L L H Undefined Delayed write cycle L L H to L L to H Valid Read-modify-write cycle L H D D Open RAS-only refresh cycle H to L L D D Open CAS-before-RAS refresh cycle Self refresh cycle (HM51S4800C) L L H to L H to L H L Valid Fast page mode read cycle *2 D Open Fast page mode early write cycle *2 L L H to L L H Undefined Fast page mode delayed write cycle L H to L H to L L to H Valid Fast page mode read-modify-write cycle L L H H Open Read cycle (Output disabled) Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 5 HM514800C, HM51S4800C Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT -1.0 to +7.0 V Supply voltage relative to VSS VCC -1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Recommended DC Operating Conditions (Ta = 0 to +70C) *2 Parameter Symbol Min Typ Max Unit Notes Supply voltage VSS 0 0 0 V 2 VCC 4.5 5.0 5.5 V 1, 2 VIH 2.4 -- 6.5 V 1 (I/O pin) VIL -1.0 -- 0.8 V 1 (Others) VIL -2.0 -- 0.8 V 1 Input high voltage Input low voltage Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) *5 HM514800C, HM51S4800C -6 Parameter -7 -8 Symbol Min Max Min Max Min Max Unit Test Conditions Operating current I CC1 -- 120 -- 110 -- 100 mA RAS, CAS cycling t RC = min Standby current I CC2 -- 2 -- 2 -- 2 mA TTL interface RAS, CAS = VIH Dout = High-Z -- 1 -- 1 -- 1 mA CMOS interface RAS, CAS V CC -0.2 V Dout = High-Z *1, 2 Standby current (L-version) I CC2 -- 200 -- 200 -- 200 A CMOS interface RAS, CAS V CC -0.2 V Dout = High-Z RAS-only refresh current*2 I CC3 -- 120 -- 110 -- 100 mA t RC = min 6 HM514800C, HM51S4800C Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) *5 (cont) HM514800C, HM51S4800C -6 Parameter -7 -8 Symbol Min Max Min Max Min Max Unit Test Conditions I CC5 -- 5 -- 5 -- 5 mA RAS = VIH CAS = VIL Dout = enable CAS-before-RAS refresh current*4 I CC6 -- 120 -- 110 -- 100 mA t RC = min Fast page mode current *1, 3 I CC7 -- 120 -- 110 -- 100 mA t PC = min Battery backup current (Standby with CBR refresh) (L-version) I CC10 -- 300 -- 300 -- 300 A Standby: CMOS interface Dout = High-Z CBR refresh: tRC = 125 s t RAS 1 s, CAS = VIL WE = VIH Self refresh mode current (HM51S4800C) I CC11 -- 1 -- 1 -- 1 mA CMOS interface RAS, CAS 0.2 V Dout = High-Z Self refresh mode current (HM51S4800CL) I CC11 -- 200 -- 200 -- 200 A CMOS interface RAS, CAS 0.2 V Dout = High-Z Input leakage current I LI -10 10 -10 10 -10 10 A 0 V Vin 6.5 V Output leakage current I LO -10 10 -10 10 -10 10 A 0 V Vout 6.5 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = -5 mA Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 4.2 mA Standby current *1 *4 Notes: 1. I CC depends on output load condition when the device is selected ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page cycle. 4. VIH V CC -0.2 V, VIL 0.2 V; Address can be changed once or less while CAS = VIL. 5. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 7 HM514800C, HM51S4800C Series Capacitance (Ta = 25C, VCC = 5 V 10%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 -- 5 pF 1 Input capacitance (Clocks) CI2 -- 7 pF 1 Output capacitance (Data-in, Data-out) CI/O -- 10 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. AC Characteristics (Ta = 0 to 70C, VCC = 5 V 10%, VSS = 0 V) *1, *14, *15 Test conditions * * * * Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.4 V Input levels: 0 V, 3 V Output load: 2 TTL gate + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) HM514800C, HM51S4800C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Random read or write cycle time t RC 110 -- 130 -- 150 -- ns RAS precharge time t RP 40 -- 50 -- 60 -- ns RAS pulse width t RAS 60 10000 70 10000 80 10000 ns CAS pulse width t CAS 15 10000 20 10000 20 10000 ns Row address setup time t ASR 0 -- 0 -- 0 -- ns Row address hold time t RAH 10 -- 10 -- 10 -- ns Column address setup time t ASC 0 -- 0 -- 0 -- ns Column address hold time t CAH 15 -- 15 -- 15 -- ns RAS to CAS delay time t RCD 20 45 20 50 20 60 ns 8 RAS to column address delay time t RAD 15 30 15 35 15 40 ns 9 RAS hold time t RSH 20 -- 20 -- 20 -- ns CAS hold time t CSH 60 -- 70 -- 80 -- ns CAS to RAS precharge time t CRP 10 -- 10 -- 10 -- ns 8 Notes HM514800C, HM51S4800C Series Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) (cont) HM514800C, HM51S4800C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit OE to Din delay time t ODD 15 -- 20 -- 20 -- ns OE delay time from Din t DZO 0 -- 0 -- 0 -- ns CAS setup time from Din t DZC 0 -- 0 -- 0 -- ns Transition time (rise and fall) tT 3 50 3 50 3 50 ns Refresh period t REF -- 16 -- 16 -- 16 ms Refresh period (L-version) t REF -- 128 -- 128 -- 128 ms Notes 7 Read Cycle HM514800C, HM51S4800C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC -- 60 -- 70 -- 80 ns 2, 3 Access time from CAS t CAC -- 15 -- 20 -- 20 ns 3, 4, 13 Access time from address t AA -- 30 -- 35 -- 40 ns 3, 5, 13 Access time from OE t OAC -- 15 -- 20 -- 20 ns Read command setup time t RCS 0 -- 0 -- 0 -- ns Read command hold time to CAS t RCH 0 -- 0 -- 0 -- ns Read command hold time to RAS t RRH 0 -- 0 -- 0 -- ns Column address to RAS lead time t RAL 30 -- 35 -- 40 -- ns Output buffer turn-off time t OFF1 0 15 0 15 0 15 ns 6 Output buffer turn-off to OE t OFF2 0 15 0 15 0 15 ns 6 CAS to Din delay time t CDD 15 -- 15 -- 15 -- ns 9 HM514800C, HM51S4800C Series Write Cycle HM514800C, HM51S4800C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 -- 0 -- 0 -- ns 10 Write command hold time t WCH 15 -- 15 -- 15 -- ns Write command pulse width t WP 10 -- 10 -- 10 -- ns Write command to RAS lead time t RWL 15 -- 20 -- 20 -- ns Write command to CAS lead time t CWL 15 -- 20 -- 20 -- ns Data-in setup time t DS 0 -- 0 -- 0 -- ns 11 Data-in hold time t DH 15 -- 15 -- 15 -- ns 11 CAS to OE delay time t COD -- 0 -- 0 -- 0 ns 18 Notes Read-Modify-Write Cycle HM514800C, HM51S4800C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Read-modify-write cycle time t RWC 150 -- 180 -- 200 -- ns RAS to WE delay time t RWD 80 -- 95 -- 105 -- ns 10 CAS to WE delay time t CWD 35 -- 45 -- 45 -- ns 10 Column address to WE delay time t AWD 50 -- 60 -- 65 -- ns 10, 13 OE hold time from WE t OEH 15 -- 20 -- 20 -- ns Refresh Cycle HM514800C, HM51S4800C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit CAS setup time (CAS-before-RAS refresh cycle) t CSR 10 -- 10 -- 10 -- ns CAS hold time (CAS-before-RAS refresh cycle) t CHR 10 -- 10 -- 10 -- ns RAS precharge to CAS hold time t RPC 10 -- 10 -- 10 -- ns CAS precharge time in normal mode t CPN 10 -- 10 -- 10 -- ns 10 Notes HM514800C, HM51S4800C Series Fast Page Mode Cycle HM514800C, HM51S4800C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode cycle time t PC 40 -- 45 -- 50 -- ns Fast page mode CAS precharge time t CP 10 -- 10 -- 10 -- ns Fast page mode RAS pulse width t RASC -- 100000 -- 100000 -- 100000 ns 12 Access time from CAS precharge t ACP -- 35 -- 40 -- 45 ns 3, 13 RAS hold time from CAS precharge t RHCP 35 -- 40 -- 45 -- ns Fast page mode read-modify-write cycle CAS precharge to WE delay time t CPW 55 -- 65 -- 70 -- ns Fast page mode read-modify-write cycle time t PCM 80 -- 95 -- 100 -- ns Self-refresh Mode HM514800C, HM51S4800C -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit RAS pulse width (self-refresh) t RASS 100 -- 100 -- 100 -- s RAS precharge time (self-refresh) t RPS 110 -- 130 -- 150 -- ns CAS hold time (self-refresh) t CHS -50 -- -50 -- -50 -- ns Notes 19, 20, 21, 22 11 HM514800C, HM51S4800C Series Notes: 1. AC measurements assume t T = 5 ns. 2. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 5. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 6. t OFF (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD t CWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. t RASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longest among tAA, t CAC and t ACP. 14. An initial pause of 100 s is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either t RCH or tRRH must be satisfied for a read cycle. 17. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 18. Do not enable Dout buffer when using delayed write timing. 19. Please do not use t RASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS 100 s, then RAS precharge time should use t RPS instead of tRP. 20. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBRrefresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 21. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles of distributed CBR refresh with 15.6 s interval should be executed within 16 ms immediately after exiting from and before entering into the self refresh mode. 22. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 23. XXX: H or L (H: VIH (min) V IN V IH (max), L: VIL (min) V IN V IL (max)) ///////: Invalid Dout 12 HM514800C, HM51S4800C Series When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL. 13 HM514800C, HM51S4800C Series Timing Waveforms*23 Read Cycle t RC t RAS RAS tT t RP t RSH t CRP t CAS t RCD t CSH CAS t ASR t RAD t RAL t CAH t RAH t ASC Address Column Row t RCH t RCS t RRH WE t CAC t OFF1 t AA High-Z Dout Dout t RAC t OAC t DZC Din t OFF2 t CDD High-Z t ODD t DZO OE 14 HM514800C, HM51S4800C Series Early Write Cycle t RC t RAS t RP RAS tT t RSH t RCD t CAS t CRP t CSH CAS t ASR t RAH Address t ASC Row t CAH Column t WCH t WCS WE t DS Din Dout t DH Din High-Z * OE : V IH or V IL 15 HM514800C, HM51S4800C Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT CAS t ASR Address t CWL t RWL t ASC t RAH t CAH Row Column tRCS t WP WE t DS t DH High-Z Din Din t DZC t ODD t DZO t OEH Dout t COD Invalid Dout* t OFF2 OE * * Do not enable Dout during delayed write cycle. 16 HM514800C, HM51S4800C Series Read-Modify-Write Cycle t RWC t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR t RAH Address tCAH t ASC Column Row t CWL t CWD t RCS t RWL t AWD t WP WE t RWD t AA t CAC t DS t RAC t DH t DZC High-Z Din Dout Din Dout t OAC t OFF2 t DZO t OEH t ODD OE 17 HM514800C, HM51S4800C Series RAS-Only Refresh Cycle t RC t RP t RAS RAS tT t CRP t CRP t RPC CAS t RAH t ASR Address Dout 18 Row High-Z HM514800C, HM51S4800C Series CAS-Before-RAS Refresh Cycle t RC t RP t RC t RAS * t RP t RAS * t RP RAS tT , , t RPC t CPN t RPC t CHR t CPN t CRP t CSR t CHR )" t CSR CAS Address t OFF1 Dout High-Z > tRAS (max). * Do not extend tRAS _ Untested self refresh mode may be activated and loss of data may be resulted (HM514800C). 19 HM514800C, HM51S4800C Series Fast Page Mode Read Cycle t RASC t RHCP t RP RAS tT t CSH t RCD t PC t CAS t CP t RSH t CAS t CP t CAS t CRP CAS t RAL t ASR t RAD t RAH Address tASC Row t CAH t ASC tCAH Column Column Column t RCS t RCS t CAH t ASC t RCS t RRH t RCH t RCH t RCH WE t DZC Din t RAC t DZC t DZC t CDD t CDD t CDD High-Z High-Z t ODD t CAC tCAC t CAC t AA t ACP t AA t AA High-Z Dout t OAC t DZO OE 20 t OFF2 t OFF1 t ACP t OFF1 Dout t OFF1 t DZO Dout Dout t OAC t DZO t ODD t ODD t OFF2 t OAC t OFF2 HM514800C, HM51S4800C Series Fast Page Mode Early Write Cycle t RASC t RP RAS t CSH tT t CAS t RCD t RSH t PC t CP t CAS t CP t CAS t CRP CAS t ASR Address t RAH Row t ASC t CAH Column t WCS t WCH t ASC t CAH t ASC Column Column t WCS t CAH t WCH t WCS t WCH WE t DS Din Dout Din t DS t DS t DH t DH t DH Din Din High-Z 21 HM514800C, HM51S4800C Series Fast Page Mode Delayed Write Cycle t RASC t RP RAS t CSH t RSH t PC tT t CAS t RCD t CP t CP t CAS t CAS t CRP CAS t ASC t ASR t RAH Address Row t CAH t CAH Column t ASC t CWL t ASC Column t CAH Column t CWL t CWL t RCS t WP t RWL t WP t WP WE t DH t DS Din t DH t RCS t DS Din Din t RCS t DH t DS Din t OEH High-Z Dout t ODD OE 22 HM514800C, HM51S4800C Series Fast Page Mode Read-Modify-Write Cycle t RP t RASC RAS t RCD tT t PCM t CAS CAS t CAS t RAD t RAH Address t CAS t ACP t CAH t ASR t CRP t CP t CP t ASC t ASC Row t ASC Column Column t RCS t CAH t CAH t AWD t CWD t CWL t RWD t WP Column t AWD t CWL t CWD t RCS t CPW t WP t RCS t CPW tCWL t AWD t RWL t CWD t WP WE t CAC t DZC t DZC t CAC t DH High-Z Din High-Z Din tAA Din t DS t DH t DZC High-Z Din t CAC t DZO tOAC t OEH Dout t DZO t DH t AA t RAC Dout t ACP t DS t DS t OAC tOEH Dout t OFF2 t OAC t OEH Dout t OFF2 t DZO t OFF2 OE t ODD t ODD t ODD 23 HM514800C, HM51S4800C Series Self Refresh Cycle*19, 20, 21, 22 t RASS t RP t RPS RAS tT t CRP , t RPC t CPN t CSR t CHS )" CAS Address t OFF1 Dout 24 High-Z HM514800C, HM51S4800C Series Package Dimensions HM51(S)4800CJ/CLJ Series (CP-28D) Unit: mm 18.17 18.54 Max 10.16 0.13 1 1.27 +0.25 -0.17 0.80 3.50 0.26 1.30 Max 0.21 2.40 +- 0.24 14 0.74 0.43 0.10 11.18 0.13 15 28 9.40 0.25 0.10 25 HM514800C, HM51S4800C Series HM51(S)4800CTT/CLTT Series (TTP-28D) Unit: mm 18.41 18.81 Max 15 10.16 28 0.40 0.10 1.27 0.21 14 M 11.76 0.20 26 0.10 0.17 0.05 1.20 Max 1.15 Max 0.13 0.05 1 0 - 5 0.80 0.50 0.10