LTC4257-1
1
42571fb
The LTC
®
4257-1 provides complete signature and power
interface functions for a device operating in an IEEE
802.3af Power over Ethernet (PoE) system. The LTC4257-1
simplifies Powered Device (PD) design by incorporating
the 25k signature resistor, classification current source,
input current limit, undervoltage lockout, thermal over-
load protection, signature disable and power good signal-
ling, all in a single 8-pin package. The LTC4257-1 includes
a precision, dual level current limit circuit. This allows it to
charge large load capacitors and interface with legacy
Power over Ethernet systems while maintaining compat-
ibility with the current IEEE 802.3af specification. By
incorporating a high voltage power MOSFET onboard, the
LTC4257-1 provides the system designer with reduced
cost while also saving board space.
The LTC4257-1 can interface directly with a variety of Lin-
ear Technology DC/DC converter products to provide a cost
effective power solution for IP phones, wireless access
points and other PDs. Linear Technology also provides
network power controllers for Power Sourcing Equipment
(PSE) applications.
The LTC4257-1 is available in the 8-pin SO and low profile
(3mm × 3mm) DFN packages.
■
IP Phone Power Management
■
Wireless Access Points
■
Telecom Power Control
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Complete Power Interface Port for IEEE 802
®
.3af
Powered Devices (PDs)
■
Onboard 100V, 400mA Power MOSFET
■
Precision Dual Level Current Limit
■
Onboard 25k Signature Resistor with Disable
■
Programmable Classification Current (Class 0-4)
■
Undervoltage Lockout
■
Thermal Overload Protection
■
Power Good Signal
■
Available in 8-Pin SO and Low Profile (3mm × 3mm)
DFN Packages
IEEE 802.3af PD
Power over Ethernet Interface
Controller with Dual Current Limit
GND
RCLASS
RCLASS
SMAJ58A
0.1µFSIGDISA
PWRGD
LTC4257-1 VIN
SHDN
100k
5µF
MIN
3.3V
TO LOGIC
RTN
SWITCHING
POWER SUPPLY
VIN VOUT
–48V FROM
POWER SOURCING
EQUIPMENT
(PSE)
42571 TA01
+
–
+
DF01SA
~
~
+
–
Powered Device (PD)
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
All other trademarks are the property of their respective owners.
LTC4257-1
2
42571fb
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Supply Voltage Voltage with Respect to GND Pin (Notes 4, 5, 6)
Maximum Operating Voltage ●–57 V
Signature Range ●–1.5 –9.5 V
Classification Range ●– 12.5 – 21 V
UVLO Turn-On Voltage ●–34.8 –36.0 –37.2 V
UVLO Turn-Off Voltage ●–29.3 –30.5 –31.5 V
I
IN_ON
IC Supply Current when ON V
IN
= –48V, Pins 5, 6, 7 Floating ●3mA
I
IN_CLASS
IC Supply Current During Classification V
IN
= –17.5V, Pins 2, 7 Floating, V
OUT
Tied to GND ●0.35 0.50 0.65 mA
(Note 7)
∆I
CLASS
Current Accuracy During Classification 10mA < I
CLASS
< 40mA, –12.5V ≤ V
IN
≤ –21V, ●±3.5 %
(Notes 8, 9)
R
SIGNATURE
Signature Resistance –1.5V ≤ V
IN
≤ –9.5V, V
OUT
Tied to GND, ●23.25 26.00 kΩ
IEEE 802.3af 2-Point Measurement (Notes 4, 5)
R
INVALID
Invalid Signature Resistance – 1.5V ≤ V
IN
≤ –9.5V, SIGDISA and V
OUT
●9 11.8 kΩ
Tied to GND, IEEE 802.3af 2-Point Measurement
(Notes 4, 5)
(Notes 1, 2)
V
IN
Voltage ............................................. 0.3V to – 100V
V
OUT
, SIGDISA,
PWRGD Voltage ...................... V
IN
+ 100V to V
IN
– 0.3V
R
CLASS
Voltage ............................ V
IN
+ 7V to V
IN
– 0.3V
PWRGD Current .................................................. 10mA
R
CLASS
Current .................................................. 100mA
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
ABSOLUTE AXI U RATI GS
WWWU
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grades are identified by a label on the shipping container.
PACKAGE/ORDER I FOR ATIO
UU
W
Operating Ambient Temperature Range
LTC4257C-1 ............................................ 0°C to 70°C
LTC4257I-1 ......................................... –40°C to 85°C
Storage Temperature Range
S8 Package....................................... – 65°C to 150°C
DD Package ...................................... – 65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART NUMBER
1
2
3
4
8
7
6
5
TOP VIEW
GND
SIGDISA
PWRGD
V
OUT
NC
R
CLASS
NC
V
IN
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 150°C, θ
JA
= 150°C/W
TOP VIEW
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
5
6
7
8
4
3
2
1NC
RCLASS
NC
VIN
GND
SIGDISA
PWRGD
VOUT
T
JMAX
= 125°C, θ
JA
= 43°C/W
EXPOSED PAD TO BE SOLDERED TO ELECTRICALLY ISOLATED PCB HEATSINK
S8 PART MARKING
42571
4257I1
LTC4257CS8-1
LTC4257IS8-1
ORDER PART NUMBER DD PART MARKING*
LBFZLTC4257CDD-1
LTC4257IDD-1
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF
Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/
LTC4257-1
3
42571fb
V
IH
Signature Disable With Respect to V
IN
,
High Level Input Voltage High Level Invalidates Signature (Note 10) ●357V
V
IL
Signature Disable With Respect to V
IN
,
Low Level Input Voltage Low Level Enables Signature ●0.45 V
R
INPUT
Signature Disable With Respect to V
IN
Input Resistance ●100 kΩ
V
PG_OUT
Power Good Output Low Voltage I = 1mA, V
IN
= –48V, PWRGD Referenced to V
IN
●0.5 V
Power Good Trip Point V
IN
= –48V, Voltage Between V
IN
and V
OUT
(Note 9)
V
PG_THRES_FALL
V
OUT
Falling ●1.3 1.5 1.7 V
V
PG_THRES_RISE
V
OUT
Rising ●2.7 3.0 3.3 V
I
PG_LEAK
Power Good Leakage V
IN
= 0V, PWRGD FET Off, V
PWRGD
= 57V ●1µA
R
ON
On-Resistance I = 350mA, V
IN
= – 48V, Measured from V
IN
to V
OUT
1.0 1.6 Ω
(Note 9) ●2.0 Ω
I
OUT_LEAK
V
OUT
Leakage V
IN
= 0V, Power MOSFET Off, V
OUT
= 57V (Note 11) ●150 µA
I
LIMIT_HIGH
Input Current Limit, High Level V
IN
= – 48V, V
OUT
= –43V (Notes 12, 13)
0°C ≤ T
A
≤ 70°C●350 375 400 mA
–40°C ≤ T
A
≤ 85°C●340 375 400 mA
I
LIMIT_LOW
Input Current Limit, Low Level V
IN
= – 48V, V
OUT
= –43V (Notes 12, 13) ●100 140 180 mA
T
SHUTDOWN
Thermal Shutdown Trip Temperature (Notes 12, 14) 140 °C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to GND pin unless otherwise noted.
Note 3: The LTC4257-1 operates with a negative supply voltage in the
range of –1.5V to –57V. To avoid confusion, voltages in this data sheet are
always referred to in terms of absolute magnitude. Terms such as
“maximum negative voltage” refer to the largest negative voltage and a
“rising negative voltage” refers to a voltage that is becoming more
negative.
Note 4: The LTC4257-1 is designed to work with two polarity protection
diode drops between the PSE and PD. Parameter ranges specified in the
Electrical Characteristics are with respect to LTC4257-1 pins and are
designed to meet IEEE 802.3af specifications when these diode drops are
included. See Applications Information.
Note 5: Signature resistance is measured via the 2-point ∆V/∆I method as
defined by IEEE 802.3af. The LTC4257-1 signature resistance is offset
from 25k to account for diode resistance. With two series diodes, the total
PD resistance will be between 23.75kΩ and 26.25kΩ and meet IEEE
802.3af specifications. The minimum probe voltages measured at the
LTC4257-1 pins are –1.5V and –2.5V. The maximum probe voltages are
–8.5V and –9.5V.
Note 6: The LTC4257-1 includes hysteresis in the UVLO voltages to
preclude any start-up oscillation. Per IEEE 802.3af requirements, the
LTC4257-1 will power up from a voltage source with 20Ω series
resistance on the first trial.
Note 7: I
IN_CLASS
does not include classification current programmed at
Pin 2. Total supply current in classification mode will be I
IN_CLASS
+ I
CLASS
(see Note 8).
Note 8: I
CLASS
is the measured current flowing through R
CLASS
.
∆I
CLASS
accuracy is with respect to the ideal current defined as
I
CLASS
= 1.237/R
CLASS
. The current accuracy specification does not
include variations in R
CLASS
resistance. The total classification current for
a PD also includes the IC quiescent current (I
IN_CLASS
). See Applications
Information.
Note 9: For the DD package, this parameter is assured by design and
wafer level testing.
Note 10: To disable the 25k signature, tie SIGDISA to GND (±0.1V) or hold
SIGDISA high with respect to V
IN
. See Applications Information.
Note 11: I
OUT_LEAK
includes current drawn at the V
OUT
pin by the power
good status circuit. This current is compensated for in the 25kΩ signature
resistance and does not affect PD operation.
Note 12: The LTC4257-1 includes thermal protection. In the event of an
overtemperature condition, the LTC4257-1 will turn off the power MOSFET
until the part cools below the overtemperature limit. The LTC4257-1 is
also protected against thermal damage from incorrect classification
probing by the PSE. If the LTC4257-1 exceeds the overtemperature trip
point, the classification load current is disabled.
Note 13: The LTC4257-1 includes dual level input current limit. At turn-on,
before C1 is charged, the LTC4257-1 current level is set to the low level.
After C1 is charged and the V
OUT
– V
IN
voltage difference is below the
power good threshold, the LTC4257-1 switches to high level current limit.
The LTC4257-1 stays in high level current limit until the input voltage
drops below the UVLO turn-off threshold.
Note 14: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
ELECTRICAL CHARACTERISTICS
LTC4257-1
4
42571fb
Signature Resistance
vs Input Voltage
Normalized UVLO Threshold
vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VOUT Leakage Current Current Limit vs Input Voltage
Input Current vs Input Voltage
Input Current vs Input Voltage
25k Detection Range Input Current vs Input Voltage
INPUT VOLTAGE (V)
0
0
INPUT CURRENT (mA)
0.1
0.2
0.3
0.4
0.5
–2 –4 –6 –8
4357 G01
–10
TA = 25°C
INPUT VOLTAGE (V)
0
0
INPUT CURRENT (mA)
10
20
30
40
50
–10 –20 –30 –40
42571 G02
–50 –60
CLASS 4
CLASS 3
CLASS 2
CLASS 1
CLASS 0
TA = 25°C
INPUT VOLTAGE (V)
–12
9.0
INPUT CURRENT (mA)
9.5
10.5
11.0
11.5
–14 –16
42571 G03
10.0
–18 –20 –22
12.0
85°C
–40°C
CLASS 1 OPERATION
Input Current vs Input Voltage
INPUT VOLTAGE (V)
0
INPUT CURRENT (mA)
1
2
3
–45 –55
42571 G04
–60–40 –50
EXCLUDES ANY LOAD CURRENT
T
A
= 25°C
INPUT VOLTAGE (V)
–1
22
V1:
V2:
SIGNATURE RESISTANCE (kΩ)
23
25
26
27
–3 –5
42571 G05
24
–7 –9
–6 –10
–2 –4 –8
28
RESISTANCE =
DIODES: S1B
T
A
= 25°C
=
∆V
∆I
V2 – V1
I
2
– I
1
IEEE UPPER LIMIT
IEEE LOWER LIMIT
LTC4257-1 + 2 DIODES
LTC4257-1 ONLY
TEMPERATURE (°C)
–40
–2
NORMALIZED UVLO THRESHOLD (%)
–1
0
1
2
–20 0 20 40
42571 G06
60 80
APPLICABLE TO TURN-ON
AND TURN-0FF THRESHOLDS
Power Good Output Low Voltage
vs Current
CURRENT (mA)
0
V
PG_OUT
(V)
2
3
8
42571 G07
1
024610
4T
A
= 25°C
V
OUT
PIN VOLTAGE (V)
0
0
V
OUT
CURRENT (µA)
30
60
120
90
20 40
42571 G08
60
V
IN
= 0V
T
A
= 25°C
INPUT VOLTAGE (V)
–40
CURRENT LIMIT (mA)
200
–60
42571 G09
100 –45 –50 –55
400
300
85°C
85°C
–40°C
–40°C
HIGH CURRENT MODE
LOW CURRENT MODE
LTC4257-1
5
42571fb
NC (Pin 1): No Internal Connection.
R
CLASS
(Pin 2): Class Select Input. Used to set the current
value the LTC4257-1 maintains during classification. Con-
nect a resistor between R
CLASS
and V
IN
(see Table 2).
NC (Pin 3): No Internal Connection.
V
IN
(Pin 4): Power Input. Tie to system –48V through the
input diode bridge.
V
OUT
(Pin 5): Power Output. Supplies –48V to the PD load
through an internal power MOSFET that limits input cur-
rent. V
OUT
is high impedance until the input voltage rises
above the turn-on UVLO threshold. The output is then
current limited. See Applications Information.
PWRGD (Pin 6): Power Good Output, Open-Drain. Signals
to the PD load that the LTC4257-1 MOSFET is on and that
the PD’s DC/DC converter can start operation. Low imped-
ance indicates power is good. PWRGD is high impedance
during detection, classification and in the event of a
thermal overload. PWRGD is referenced to V
IN
.
SIGDISA (Pin 7): Signature Disable Input. Allows the PD
to command the LTC4257-1 to present an invalid signa-
ture resistance and to remain inactive. Connecting SIGDISA
to GND lowers the signature resistance to an invalid value
and disables all functions of the LTC4257-1. If left floating,
SIGDISA is internally pulled to V
IN
. If unused, tie SIGDISA
to V
IN
.
GND (Pin 8): Ground. Tied to system ground and power
return through the input diode bridge.
UU
U
PI FU CTIO S
BLOCK DIAGRA
W
42571 BD
V
IN
BOLD LINE INDICATES HIGH CURRENT PATH
V
OUT
–
+
8
54
NC 3
R
CLASS
2
NC
PWRGD
SIGDISA
GND
1
7
6
CONTROL
CIRCUITS
INPUT
CURRENT
LIMIT
POWER GOOD
CLASSIFICATION
CURRENT LOAD
1.237V
EN
375mA
140mA
SIGNATURE DISABLE
9k
16k
0.3Ω
–
+
EN 25k SIGNATURE
RESISTOR
LTC4257-1
6
42571fb
The LTC4257-1 is intended for use as the front end of a
Powered Device (PD) adhering to the IEEE 802.3af standard.
The LTC4257-1 includes a trimmed 25k signature resistor,
classification current source, and an input current limit cir-
cuit. With these functions integrated into the LTC4257-1,
the signature and power interface for a PD that meets all
the requirements of the IEEE 802.3af specification can be
built with a minimum of external components.
The LTC4257-1 has been specifically designed to interface
with legacy PoE PSEs which do not meet the inrush
current requirement of the IEEE 802.3af specification. By
setting the initial inrush current limit to a low level, a PD
using the LTC4257-1 minimizes the current drawn from
the PSE during start-up. After powering up, the LTC4257-1
switches to the high level current limit, thereby allowing
the PD to consume up to 12.95 watts if an 802.3af PSE is
present. This low level current limit also allows the
LTC4257-1 to charge arbitrarily large load capacitors
without exceeding the inrush limits of the IEEE 802.3af
specification. This dual level current limit provides the
system designer with flexibility to design PDs which are
compatible with legacy PSEs while also being able to take
advantage of the higher power allocation available in an
IEEE 802.3af system.
Using an LTC4257-1 for the power and signature inter-
face functions of a PD provides several advantages. The
LTC4257-1 current limit circuit includes an onboard,
100V, 400mA power MOSFET with low leakage. This
onboard low leakage MOSFET avoids the possibility of
corrupting the 25k signature resistor while also saving
board space and cost. In addition, the inrush current limit
requirement of the IEEE 802.3af standard causes large
transient power dissipation in the PD. The LTC4257-1 is
designed to allow multiple turn-on sequences without
overheating the miniature 8-lead package. In the event of
excessive power cycling, the LTC4257-1 provides ther-
mal overload protection to keep the onboard power
MOSFET within its safe operating area.
Operation
The LTC4257-1 has several modes of operation depend-
ing on the applied input voltage as shown in Figure 1 and
DETECTION V1
CLASSIFICATION
UVLO
TURN-ON
UVLO
OFF
POWER
BAD
UVLO
OFF
UVLO
ON
UVLO
TURN-OFF
τ = R
LOAD
C1
PWRGD TRACKS
V
IN
DETECTION V2
10
TIME
20
30
V
IN
(V)
40
50
10
TIME
20
30
V
OUT
(V)
40
50
10
TIME
20
30
PWRGD (V)
40
50
I
CLASS
PD CURRENT
I
LIMIT
dV
dt
I
LIMIT
C1
=
POWER
BAD
POWER
GOOD
DETECTION I
1
CLASSIFICATION
I
CLASS
DETECTION I
2
LOAD, I
LOAD
CURRENT
LIMIT, I
LIMIT
42571 F01
I
CLASS
DEPENDENT ON R
CLASS
SELECTION
I
LIMIT
= 140mA (NOMINAL)
I
1
= V1 – 2 DIODE DROPS
25kΩ
I
LOAD
= V
IN
R
LOAD
I
2
= V2 – 2 DIODE DROPS
25kΩ
GND
2
PSE
I
IN
LTC4257-1
8
6
5
R9 R
LOAD
R
CLASS
V
OUT
C1
GND
4
R
CLASS
PWRGD
V
OUT
V
IN
V
IN
Figure 1. Output Voltage, PWRGD and PD Current
as a Function of Input Voltage
APPLICATIO S I FOR ATIO
WUUU
LTC4257-1
7
42571fb
summarized in Table 1. These various modes satisfy the
requirements defined in the IEEE 802.3af specification.
The input voltage is applied to the V
IN
pin and is with
reference to the GND pin. This input voltage is always
negative. To avoid confusion, voltages in this data sheet
are always referred to in terms of absolute magnitude.
Terms such as
maximum negative voltage
refer to the
largest negative voltage and a
rising negative voltage
refers to a voltage that is becoming more negative. Refer-
ences to electrical parameters in this applications section
use the nominal value. Refer to the Electrical Characteris-
tics section for the range of values a particular parameter
will have.
Table 1. LTC4257-1 Operational Mode
as a Function of Input Voltage
INPUT VOLTAGE
(V
IN
with RESPECT to GND) LTC4257-1 MODE OF OPERATION
0V to –1.4V Inactive
–1.5V to – 10V 25k Signature Resistor Detection
–11V to – 12.4V Classification Load Current Ramps up from
0% to 100%
–12.5V to UVLO* Classification Load Current Active
UVLO* to –57V Power Applied to PD Load
*UVLO includes hysteresis.
Rising input threshold ≅ –36.0V
Falling input threshold ≅ –30.5V
Figure 2. PD Front End Using Diode Bridges On Main and Spare Inputs
Series Diodes
The IEEE 802.3af defined operating modes for a PD
reference the input voltage at the RJ45 connector on the
PD. However, PD circuitry must include diode bridges
between the RJ45 connector and the LTC4257-1 (Figure
2). The LTC4257-1 takes this into account by compensat-
ing for these diode drops in the threshold points for each
range of operation. Since the voltage ranges specified in
the LTC4257-1 electrical specifications are with respect to
the IC pins, for both the signature and classification
ranges, the LTC4257-1 lower end extends two diode drops
below the IEEE 802.3af specification. A similar adjustment
is made for the UVLO voltages.
Detection
During detection, the PSE will apply a voltage in the range
of –2.8V to –10V on the cable and look for a 25k signature
resistor. This identifies the device at the end of the cable
as a PD. With the terminal voltage in this range, the
LTC4257-1 connects an internal 25k resistor between GND
and the V
IN
pins. This precision, temperature compensated
resistor presents the proper characteristics to alert the
Power Sourcing Equipment (PSE) at the other end of the
cable that a PD is present and desires power to be applied.
APPLICATIO S I FOR ATIO
WUUU
RX
–
6
RX
+
3
TX
–
2
TX
+
RJ45 T1
POWERED DEVICE (PD)
INTERFACE
AS DEFINED
BY IEEE 802.3af
42571 F02
1
7
8
5
4
SPARE
–
SPARE
+
TO PHY
BR2
BR1
GND 8
4
D3
LTC4257-1
V
IN
LTC4257-1
8
42571fb
Classification
Once the PSE has detected a PD, the PSE may optionally
classify the PD. Classification provides a method for more
efficient allocation of power by allowing the PSE to identify
lower-power PDs and allocate less power for these de-
vices. The IEEE 802.3af specification defines five classes
(Table 2) with varying power levels. The designer selects
the appropriate classification based on the power con-
sumption of the PD. For each class, there is an associated
load current that the PD asserts onto the line during
classification probing. The PSE measures the PD load
current to determine the proper classification and PD
power requirements.
Table 2. Summary of IEEE 802.3af Power Classifications and
LTC4257-1 RCLASS Resistor Selection
MAXIMUM NOMINAL LTC4257-1
POWER LEVELS CLASSIFICATION R
CLASS
AT INPUT OF PD LOAD CURRENT RESISTOR
CLASS USAGE (W) (mA) (Ω, 1%)
0 Default 0.44 to 12.95 <5 Open
1 Optional 0.44 to 3.84 10.5 124
2 Optional 3.84 to 6.49 18.5 68.1
3 Optional 6.49 to 12.95 28 45.3
4 Reserved Reserved* 40 30.9
*Class 4 is currently reserved and should not be used.
Early revisions of the IEEE 802.3af draft specification
defined two methods that a PSE could use in order to
perform PD classification. These methods are known as
Measured Current and Measured Voltage. The IEEE has
since removed the Measured Voltage method from the
The power applied to a PD is allowed to use either of two
polarities and the PD must be able to accept this power so
it is common to install a diode bridge on the input. The
LTC4257-1 is designed to compensate for the voltage and
resistance effects of these two series diodes. The signa-
ture range extends below the IEEE range to accommodate
the voltage drop of the diodes. The IEEE specification
requires the PSE to use a ∆V/∆I measurement technique
to keep the DC offset of these diodes from affecting the
signature resistance measurement. However, the diode
resistance appears in series with the signature resistor
and must be included in the overall signature resistance
of the PD. The LTC4257-1 compensates for the two series
diodes in the signature path by offsetting the resistance
so that a PD built using the LTC4257-1 will meet the IEEE
specification.
In some applications it is necessary to control whether or
not the PD is detected. In this case, the 25k signature can
be enabled and disabled with the use of the SIGDISA pin
(Figure 3). Disabling the signature via the SIGDISA pin will
change the signature resistor to 9k which is an invalid sig-
nature per the IEEE 802.3af specification. This invalid
signature is present for PD input voltages from –2.8V to
–10V. If the input rises above –10V, the signature resis-
tor reverts to 25k to minimize power dissipation in the
LTC4257-1. To disable the signature, tie SIGDISA to GND.
Alternately, the SIGDISA pin can be driven high with re-
spect to V
IN
. When SIGDISA is high, all functions of the
LTC4257-1 are disabled.
Figure 3. 25k Signature Resistor with Disable
APPLICATIO S I FOR ATIO
WUUU
GND
V
IN
8
7
4
LTC4257-1
42571 F03
25k SIGNATURE
RESISTOR
SIGNATURE DISABLE
SIGDISA
9k
16k
TO
PSE
LTC4257-1
9
42571fb
specification. The LTC4257-1 is compatible with the IEEE
802.3af standard and also works with the obsolete Mea-
sured Voltage method.
In the Measured Current method (Figure 4), the PSE
presents a fixed voltage between –15.5V and –20.5V to the
PD. With the input voltage in this range, the LTC4257-1
asserts a load current from the GND pin through the
R
CLASS
resistor. The magnitude of the load current is set
with the selection of the R
CLASS
resistor. The resistor value
associated with each class is shown in Table 2.
In the Measured Voltage method (Figure 5), the PSE drives
a current into the PD and monitors the voltage across the
PD terminals. The PSE current steps between classifica-
tion load current values in order to classify the PD under
test. For PSE probe currents below the PD load current, the
LTC4257-1 will keep the PD terminal voltage below the
classification voltage range. For PSE probe currents above
the PD load current, the LTC4257-1 will force the PD
terminal voltage above the classification voltage range.
During classification, a moderate amount of power is
dissipated in the LTC4257-1. The IEEE 802.3af specifica-
tion limits the classification time to 75ms. The LTC4257-1
is designed to handle the power dissipation for this time
period. If the PSE probing exceeds 75ms, the LTC4257-1
may overheat. In this situation, the thermal protection
circuit will engage and disable the classification current
source in order to protect the part. The LTC4257-1 stays
in classification mode until the input voltage rises above
the UVLO turn-on voltage.
APPLICATIO S I FOR ATIO
WUUU
Figure 5. IEEE 802.af Measured-Voltage Method
of Classification Probing
GND
R
CLASS
V
IN
82
4
LTC4257-1
CONSTANT
LOAD
CURRENT
INTERNAL
TO LTC4257-1
42571 F05
R
CLASS
CURRENT PATH
V
PDPSE
PSE
VOLTAGE
MONITOR
PSE
PROBING
CURRENT
SOURCE
IF PSE PROBING CURRENT < LTC4257-1 LOAD CURRENT, PD TERMINAL VOLTAGE IS < 15V
IF PSE PROBING CURRENT > LTC4257-1 LOAD CURRENT, PD TERMINAL VOLTAGE IS > 20V
GND
R
CLASS
V
IN
82
4
LTC4257-1
CONSTANT
LOAD
CURRENT
INTERNAL
TO LTC4257-1
42571 F04
R
CLASS
CURRENT PATH
V
PD
PSE
PSE CURRENT MONITOR
PSE
PROBING
VOLTAGE
SOURCE
–15.5V TO –20.5V
Figure 4. IEEE 802.3af Measured-Current Method
of Classification Probing
LTC4257-1
10
42571fb
Undervoltage Lockout
The IEEE specification dictates a maximum turn-on volt-
age of 42V and a minimum turn-off voltage of 30V for the
PD. In addition, the PD must maintain large on-off hyster-
esis to prevent resistive losses in the wiring between the
PSE and the PD from causing start-up oscillation. The
LTC4257-1 incorporates an undervoltage lockout (UVLO)
circuit that monitors line voltage to determine when to
apply power to the PD load (Figure 6). Before power is
applied to the load, the V
OUT
pin is high impedance and
sitting at ground potential since there is no charge on
capacitor C1. When the input voltage rises above the UVLO
turn-on threshold, the LTC4257-1 removes the classifica-
tion load current and turns on the internal power MOSFET.
C1 charges up under LTC4257-1 current limit control and
the V
OUT
pin transitions from 0V to V
IN
. This sequence is
shown in Figure 1. The LTC4257-1 includes a hysteretic
UVLO circuit that keeps power applied to the load until the
input voltage falls below the UVLO turn-off threshold.
Once the input voltage drops below –30V, the internal
power MOSFET is turned off and the classification load
current is re-enabled. C1 will discharge through the PD
circuitry and the V
OUT
pin will go to a high impedance state.
Input Current Limit
IEEE 802.3af specifies a maximum inrush current and also
specifies a minimum load capacitor between the GND and
V
OUT
pins. To control turn-on surge current in the system,
the LTC4257-1 integrates a dual level current limit circuit
with an onboard power MOSFET and sense resistor to
provide a complete inrush control circuit without additional
external components. At turn on, the LTC4257-1 will limit
input current to the low level, allowing the load capacitor
to ramp up to the line voltage in a controlled manner.
The LTC4257-1 has been specifically designed to interface
with legacy PSEs which do not meet the inrush current
requirement of the IEEE 802.3af specification. This is
APPLICATIO S I FOR ATIO
WUUU
GND C1
5µF
MIN
V
IN
8
4V
OUT
5
LTC4257-1
42571 F06
TO
PSE UNDERVOLTAGE
LOCKOUT
CIRCUIT
PD
LOAD
CURRENT-LIMITED
TURN ON
+
INPUT LTC4257-1
VOLTAGE POWER MOSFET
0V TO UVLO* OFF
>UVLO* ON
*UVLO INCLUDES HYSTERESIS
RISING INPUT THRESHOLD ≅ –36V
FALLING INPUT THRESHOLD ≅ –30.5V
Figure 6. LTC4257-1 Undervoltage Lockout
LTC4257-1
11
42571fb
accomplished by a dual level current limit. At turn on
before C1 is charged, the LTC4257-1 current limit is set to
the low level. After C1 is charged up and the V
OUT
– V
IN
voltage difference is below the power good threshold, the
LTC4257-1 switches to the high level current limit. The
dual level current limit allows legacy PSEs with limited
current sourcing capability to power up the PD while also
allowing the PD to draw full power from an IEEE 802.3af
PSE.
The dual level current limit also allows use of arbitrarily
large load capacitors. The IEEE 802.3af specification man-
dates that at turn on the PD not exceed the inrush current
limit for more than 50ms. The LTC4257-1 is not restricted
by the 50ms time limit because the load capacitor is
charged with a current below the IEEE inrush current limit
specification. Therefore, it is possible to use larger load
capacitors with the LTC4257-1.
As the LTC4257-1 switches from the low to the high level
current limit, a momenatry increase in current can be
observed. This current spike is a result of the LTC4257-1
charging the last 1.5V at the high level current limit. When
charging a 10µF capacitor, the current spike is typically
100µs wide and 125% of the nominal low level current
limit.
The LTC4257-1 stays in the high level current limit mode
until the input voltage drops below the UVLO turn-off
threshold. This dual level current limit provides the sys-
tem designer with the flexibility to design PDs which are
compatible with legacy PSEs while also being able to take
advantage of the higher power allocation available in an
IEEE 802.3af system.
During the current limited turn on, a large amount of power
is dissipated in the power MOSFET. The LTC4257-1 is
designed to accept this thermal load and is thermally
protected to avoid damage to the onboard power MOSFET.
Note that in order to adhere to the IEEE 802.3af standard,
it is necessary for the PD designer to ensure the PD steady-
state power consumption falls within the limits shown in
Table 2.
Power Good
The LTC4257-1 includes a power good circuit (Figure 7)
that is used to indicate to the PD circuitry that load
capacitor C1 is fully charged and that the PD can start
DC/DC converter operation. The power good circuit moni-
tors the voltage across the internal power MOSFET and
PWRGD is asserted when the voltage drops below 1.5V.
The power good circuit includes a large amount of hyster-
esis to allow the LTC4257-1 to operate near the current
limit point without inadvertently disabling PWRGD. The
MOSFET voltage must increase to 3V before PWRGD is
disabled.
APPLICATIO S I FOR ATIO
WUUU
Figure 7. LTC4257-1 Power Good
PWRGD
C1
5µF
MIN
V
IN
6
4V
OUT
1.125V
300k 300k
R9
100k
5
LTC4257-1
THERMAL SHUTDOWN
UVLO
42571 F07
TO
PSE
PD
LOAD
SHDN
+
–+
+
–
LTC4257-1
12
42571fb
If a sudden increase in voltage appears on the input line,
this voltage step will be transferred through capacitor C1
and appear across the power MOSFET. The response of
the LTC4257-1 will depend on the magnitude of the
voltage step, the rise time of the step, the value of capacitor
C1 and the DC load. For fast rising inputs, the LTC4257-1
will attempt to quickly charge capacitor C1 using an
internal secondary current limit circuit. In this scenario,
the PSE current limit should provide the overall limit for
the circuit. For slower rising inputs, the 375mA current
limit in the LTC4257-1 will set the charge rate of capacitor
C1. In either case, the PWRGD signal may go inactive
briefly while the capacitor is charged up to the new line
voltage. In the design of a PD, it is necessary to determine
if a step in the input voltage will cause the PWRGD signal
to go inactive and how to respond to this event. In some
designs, the charge on C1 is sufficient to power the PD
through this event. In this case, it may be desirable to filter
the PWRGD signal so that intermittent power bad condi-
tions are ignored. Figure 10 demonstrates methods to
insert a lowpass filter on the power good interface.
For PD designs that use a large load capacitor and also
consume a lot of power, it is important to delay activation
of the PD circuitry with the PWRGD signal. If the PD cir-
cuitry is not disabled during the current-limited turn-on se-
quence, the PD circuitry will rob current intended for charg-
ing up the load capacitor and create a slow rising input,
possibly causing the LTC4257-1 to go into thermal shut-
down.
The PWRGD pin connects to an internal open-drain, 100V
transistor capable of sinking 1mA. Low impedance indi-
cates power is good. PWRGD is high impedance during
signature and classification probing and in the event of a
thermal overload.
During turn-off, PWRGD is deactivated when the input
voltage drops below 30V. In addition, PWRGD may go
active briefly at turn-on for fast rising input waveforms.
PWRGD is referenced to the V
IN
pin and when active will
be near the V
IN
potential. The PD DC/DC converter will
typically be referenced to V
OUT
and care must be taken to
ensure that the difference in potential of the PWRGD signal
does not cause any detrimental effects. Use of diode clamp
D6, as shown in Figure 10, will alleviate any problems.
Thermal Protection
The LTC4257-1 includes thermal overload protection in
order to provide full device functionality in a miniature
package while maintaining safe operating temperatures.
Several factors create the possibility for tremendous
power dissi
pation within the LTC4257-1. At turn on,
before the load capacitor has charged up, the instanta-
neous power dissipated by the LTC4257-1 can be 10W. As
the load capacitor charges up, the power dissipation in the
LTC4257-1 will decrease until it reaches a steady-state
value dependent on the DC load current. The size of the
load capacitor determines how fast the power dissipation
in the LTC4257-1 will subside. At room temperature, the
LTC4257-1 can handle load capacitors as large as 800µF
without going into thermal shutdown. With a large load
capacitor like this, the LTC4257-1 die temperature will
increase by about 50°C during a single turn-on sequence.
If for some reason power were removed from the part and
then quickly reapplied so that the LTC4257-1 has to
charge up the load capacitor again, the temperature
rise would be excessive if safety precautions were not
implemented.
The LTC4257-1 protects itself from thermal damage by
monitoring the die temperature. If the die temperature
exceeds the overtemperature trip point, the current is
reduced to zero and very little power is dissipated in the
part until it cools below the overtemperature set point.
Once the LTC4257-1 has charged up the load capacitor
and the PD is powered and running, there will be some
residual heating due to the DC load current of the PD
flowing through the internal MOSFET. In some applica-
tions, the LTC4257-1 power dissipation may be signifi-
cant and if dissipated in the S8 package, excessive pack-
age heating could occur. This problem can be solved with
the use of the DD package which has superior thermal
performance. The DD package includes an exposed pad
which should be soldered to an isolated heatsink on the
printed circuit board.
During classification, excessive heating of the LTC4257-1
can occur if the PSE violates the 75ms probing time limit.
To protect the LTC4257-1, thermal protection circuitry will
disable classification current if the die temperature exceeds
APPLICATIO S I FOR ATIO
WUUU
LTC4257-1
13
42571fb
APPLICATIO S I FOR ATIO
WUUU
the overtemperature trip point. When the die cools down
below the trip point, classification current is enabled again.
If the PD is designed to operate at a high ambient tempera-
ture and with the maximum allowable supply (57V), there
will be a limit to the size load capacitor that can be charged
up before the LTC4257-1 reaches the overtemperature trip
point. Hitting the overtemperature trip point intermittently
does not harm the LTC4257-1, but it will delay completion
of capacitor charging. Capacitors up to 200µF can be
charged without a problem.
EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer (Figure 8). For
powered devices, the isolation transformer must include
a center tap on the media (cable) side. Proper termination
is required around the transformer to provide correct
impedance matching and to avoid radiated and conducted
emissions. Transformer vendors such as Pulse, Bel Fuse,
Tyco and others (Table 3) can provide assistance with
selection of an appropriate isolation transformer and
proper termination methods. These vendors have trans-
formers specifically designed for use in PD applications.
Table 3. Power over Ethernet Transformer Vendors
VENDOR CONTACT INFORMATION
Pulse Engineering 12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
FAX: 858-674-8262
http://www.pulseeng.com/
Bel Fuse Inc. 206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
FAX: 201-432-9542
http://www.belfuse.com/
Tyco Electronics 308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
FAX: 650-361-2508
http://www.circuitprotection.com/
Diode Bridges
IEEE 802.3af allows power wiring in either of two configu-
rations on the TX/RX wires, plus power can be applied to
the PD via the spare wire pair in the RJ45 connector. The
PD is required to accept power in either polarity on both
the main and spare inputs; therefore, it is common to
install diode bridges on both inputs in order to accommo-
date the different wiring configurations. Figure 8 demon-
strates an implementation of these diode bridges. The
specification also mandates that the leakage back through
the unused bridge be less than 28µA when the PD is
powered with 57V.
Figure 8. PD Front End with Isolation Transformer, Diode Bridges and Capacitor
16
14
15
1
3
2
RX–
6
RX+
3
TX–
2
TX+
RJ45
T1
PULSE H2019
42571 F08
1
7
8
5
4
11
9
10
6
8
7
D3
SMAJ58A
TVS
BR1
DF01SA
BR2
DF01SA
TO PHY
GND 8
54
LTC4257-1 C1
VIN VOUT VOUT
SPARE–
SPARE+
C14
0.1µF
100V
LTC4257-1
14
42571fb
APPLICATIO S I FOR ATIO
WUUU
The IEEE standard includes an AC impedance requirement
in order to implement the AC disconnect function. Capaci-
tor C14 in Figure 8 is used to meet this AC impedance
requirement. A 0.1µF capacitor is recommended for this
application.
The LTC4257-1 has several different modes of operation
based on the voltage present between the V
IN
and GND pins.
The forward voltage drop of the input diodes in a PD design
subtracts from the input voltage and will affect the transi-
tion point between modes. When using the LTC4257-1, it
is necessary to pay close attention to this forward voltage
drop. Selection of oversized diodes will help keep the PD
thresholds from exceeding IEEE specifications.
The input diode bridge of a PD can consume over 4% of the
available power in some applications. It may be desirable
to use Schottky diodes in order to reduce this power loss.
However, if the standard diode bridge is replaced with a
Schottky bridge, the transition points between modes will
be affected. The application circuit (Figure 11) shows a tech-
nique for using Schottky diodes while maintaining proper
threshold points to meet IEEE 802.3af compliance.
Auxiliary Power Source
In some applications, it may be desirable to power the PD
from an auxiliary power source such as a wall transformer.
The auxiliary power can be injected into the PD at several
locations and various trade-offs exist. Power can be
injected at the 3.3V or 5V output of the isolated power
supply with the use of a diode ORing circuit. This method
accesses the internal circuits of the PD after the isolation
barrier and therefore meets the 802.3af isolation safety
requirements for the wall transformer jack on the PD.
Power can also be injected into the PD interface portion of
the LT4257-1. In this case, it is necessary to ensure the
user cannot access the terminals of the wall transformer
jack on the PD since this would compromise the 802.3af
isolation safety requirements. Figure 9 demonstrates three
methods of diode ORing external power into a PD. Option
1 inserts power before the LTC4257-1 while options 2 and
3 apply power after the LTC4257-1.
If power is inserted before the LTC4257-1 (option 1), it is
necessary for the wall transformer to exceed the LTC4257-1
UVLO turn-on requirement and limit the maximum voltage
to 57V. This option provides input current limit for the
transformer, provides a valid power good signal and
simplifies power priority issues. As long as the wall
transformer applies power to the PD before the PSE, it will
take priority and the PSE will not power up the PD because
the wall power will corrupt the 25k signature. If the PSE is
already powering the PD, the wall transformer power will
be in parallel with the PSE. In this case, priority will be
given to the higher supply voltage. If the wall transformer
voltage is higher, the PSE should remove line voltage since
no current will be drawn from the PSE. On the other hand,
if the wall transformer voltage is lower, the PSE will
continue to supply power to the PD and the wall trans-
former power will not be used. Proper operation should
occur in either scenario.
If auxiliary power is applied after the LTC4257-1 (option 2),
a different set of tradeoffs arise. In this configuration, the
wall transformer does not need to exceed the LTC4257-1
turn-on UVLO requirement; however, it is necessary to
include diode D9 to prevent the transformer from applying
power to the LTC4257-1. The transformer voltage require-
ments will be governed by the needs of the PD switcher and
may exceed 57V. However, power priority issues require
more intervention. If the wall transformer voltage is below
the PSE voltage, then priority will be given to the PSE power.
The PD will draw power from the PSE while the transformer
will sit unused. This configuration is not a problem in a PoE
system. On the other hand, if the wall transformer voltage
is higher than the PSE voltage, the PD will draw power from
the transformer. In this situation, it is necessary to address
the issue of power cycling that may occur if a PSE is present.
The PSE will detect the PD and apply power. If the PD is being
powered by the wall transformer, then the PD will not meet
the minimum load requirement and the PSE will subse-
quently remove power. The PSE will again detect the PD and
power cycling will start. With a transformer voltage above
the PSE voltage, it is necessary to either disable the signa-
ture, as shown in option 2, or install a minimum load on the
output of the LTC4257-1 to prevent power cycling.
The third option also applies power after the LTC4257-1,
while omitting diode D9. With the diode omitted, the
transformer voltage is applied to the LTC4257-1 in addi-
tion to the load. For this reason, it is necessary to ensure
LTC4257-1
15
42571fb
APPLICATIO S I FOR ATIO
WUUU
Figure 9. Auxiliary Power Source for PD
RX–
6
RX+
3
TX–
2
TX+
RJ45 T1
1
7
8
5
4
SPARE–
+
–
SPARE+
ISOLATED
WALL
TRANSFORMER
TO PHY
GND 8
45
OPTION 1: AUXILARY POWER INSERTED BEFORE LTC4257-1
OPTION 2: AUXILARY POWER INSERTED AFTER LTC4257-1 WITH SIGNATURE DISABLED
VIN VOUT
38V TO 57V
D8
S1B
D3
SMAJ58A
TVS
C1 PD
LOAD
C14
0.1µF
100V
RX–
6
RX+
3
TX–
2
TX+
RJ45 T1
1
7
8
5
4
SPARE–
+
–
SPARE+
ISOLATED
WALL
TRANSFORMER
TO PHY
GND
SIGDISA
LTC4257-1
LTC4257-1
BR2
DF01SA
~
~
+
–
BR1
DF01SA
~
~
+
–
BR1
DF01SA
~
~
+
–
8
7
45
VIN VOUT
42571 F09
D10
S1B
D3
SMAJ58A
TVS
C1
100k
PD
LOAD
D9
S1B
OPTION 3: AUXILARY POWER APPLIED TO LTC4257-1 AND PD LOAD
RX–
6
RX+
3
TX–
2
TX+
RJ45 T1
1
7
8
5
4
SPARE–
+
–
SPARE+
ISOLATED
WALL
TRANSFORMER
TO PHY
38V TO 57V
GND
LTC4257-1
8
45
VIN VOUT
D10
S1B
D3
SMAJ58A
TVS
C1 PD
LOAD
C14
0.1µF
100V
C14
0.1µF
100V
BR2
DF01SA
~
~
+
–
BR1
DF01SA
~
~
+
–
BR2
DF01SA
~
~
+
–
100k
BSS63
LTC4257-1
16
42571fb
APPLICATIO S I FOR ATIO
WUUU
that the transformer maintain the voltage between 38V and
57V to keep the LTC4257-1 in its normal operating range.
The third option has the advantage of automatically dis-
abling the 25k signature when the external voltage ex-
ceeds the PSE voltage.
Classification Resistor Selection (R
CLASS
)
The IEEE specification allows classifying PDs into four
distinct classes with class 4 being reserved for future use
(Table 2). An external resistor connected from R
CLASS
to
V
IN
(Figure 4) sets the value of the load current. The
designer should determine which power category the PD
falls into and then select the appropriate value of R
CLASS
from Table 2. If a unique load current is required, the value
of R
CLASS
can be calculated as:
R
CLASS
= 1.237V/(I
DESIRED
– I
IN_CLASS
)
where I
IN_CLASS
is the LTC4257-1 IC supply current
during classification and is given in the electrical speci-
fications. The R
CLASS
resistor must be 1% or better to
avoid degrading the overall accuracy of the classification
circuit. Resistor power dissipation will be 50mW maxi-
Figure 10. Power Good Interface Examples
mum and is transient so heating is typically not a con-
cern. In order to maintain loop stability, the layout should
minimize capacitance at the R
CLASS
node. The classifica-
tion circuit can be disabled by floating the R
CLASS
pin. The
R
CLASS
pin should not be shorted to V
IN
as this would
force the LTC4257-1 classification circuit to attempt to
source very large currents. In this case, the LTC4257-1
will quickly go into thermal shutdown.
Power Good Interface
The PWRGD signal is controlled by a high voltage, open-
drain transistor. Examples of active-high and active-low
interface circuits for controlling the PD load are shown in
Figure 10.
In some applications it is desirable to ignore intermittent
power bad conditions. This can be accomplished by
including capacitor C15 in Figure 10 to form a lowpass
filter. With the components shown, power bad conditions
less than about 200µs will be ignored. Conversely, in other
applications it may be desirable to delay assertion of
PWRGD to the PD load. The PWRGD signal can be delayed
with the addition of capacitor C17 in Figure 10.
GND
C1
5µF
100V
V
IN
8
4
–48V V
OUT
5
*C15 OPTIONAL TO FILTER PWRGD.
SEE APPLICATIONS INFORMATION
LTC4257-1
PD
LOAD
SHDN
PWRGD 6
D6
5.1V
MMBZ5231B
C15*
0.047µF
10V
R9
100k
R9
100k
R18
10k
R18
10k
+
GND
C1
5µF
100V
Q1
FMMT2222
D6
MMBD4148
V
IN
8
4
–48V V
OUT
5
LTC4257-1
42571 F10
PD
LOAD
RUN
C17*
PWRGD 6
INTERNAL
PULLUP
+
ACTIVE-LOW ENABLE, 5.1V SWING
ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULLUP
TO
PSE
TO
PSE
C15*
0.047µF
10V
*C15 AND C17 OPTIONAL TO FILTER PWRGD.
SEE APPLICATIONS INFORMATION
LTC4257-1
17
42571fb
APPLICATIO S I FOR ATIO
WUUU
Signature Disable Interface
To disable the 25k signature, connect the SIGDISA pin to the
GND pin. Alternately, SIGDISA can be driven high with
respect to V
IN
. An example of a signature disable interface
circuit is shown in Figure 9, option 2. Note that the SIGDISA
input resistance is relatively large and the threshold voltage
is fairly low. Because of high voltages present on the printed
circuit board, leakage currents from the GND pin could
inadvertently pull SIGDISA high. To insure trouble-free
operation, use high-voltage layout techniques in the vicinity
of SIGDISA. If unused, connect SIGDISA to V
IN
.
Load Capacitor
The IEEE 802.3af specification requires that the PD main-
tain a minimum load capacitance of 5µF. It is permissible
to have a much larger load capacitor and the LTC4257-1
can charge very large load capacitors before thermal
issues become a problem. However, the load capacitor
must not be too large or the PD design may violate IEEE
802.3af requirements.
If the load capacitor is too large there can be a problem with
inadvertent power shutdown by the PSE. Consider the fol-
lowing scenario. If the PSE is running at –57V (maximum
allowed) and the PD has been detected and powered up,
the load capacitor will be charged to nearly –57V. If for
some reason the PSE voltage suddenly is reduced to – 44V
(minimum allowed), the input bridge will reverse bias and
PD power will be supplied solely by the load capacitor.
Depending on the size of the load capacitor and the DC load
of the PD, the PD will not draw any power from the PSE
for a period of time. If this period of time exceeds the IEEE
802.3af 300ms disconnect delay, the PSE may remove
power from the PD. For this reason, it is necessary to
evaluate the load capacitance and load current to ensure
that inadvertent shutdown cannot occur.
Very small output capacitors (≤10µF) will charge very
quickly in current limit. The rapidly changing voltage at
the output may reduce the current limit temporarily,
causing the capacitor to charge at a somewhat reduced
rate. Conversely, charging very large capacitors may
cause the current limit to increase slightly. In either case,
once the output voltage reaches its final value, the input
current limit will be restored to its nominal value.
Maintain Power Signature
In an IEEE 802.3af system, the PSE uses the
maintain
power signature
(MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25kΩ in parallel with 0.05µF. The PD application
circuits shown in this data sheet meet the requirements
necessary to maintain power. If either the DC current is
less than 10mA or the AC impedance is above 26.25kΩ,
the PSE might disconnect power. The DC current must be
less than 5mA and the AC impedance must be above 2MΩ
to guarantee power will be removed.
Layout
The LTC4257-1 is relativity immune to layout problems.
Excessive parasitic capacitance on the R
CLASS
pin should
be avoided. If using the DD package, include an electrically
isolated heat sink to which the exposed pad on the bottom
of the package can be soldered. For optimum thermal
performance, make the heatsink as large as possible.
Voltages in a PD can be as large as –57V, so high voltage
layout techniques should be employed.
The load capacitor connected between Pins 5 and 8 of the
LTC4257-1 can store significant energy when fully charged.
The design of a PD must ensure that this energy is not
inadvertently dissipated in the LTC4257-1. The polarity-
protection diode(s) prevent an accidental short on the
cable from causing damage. However, if the V
IN
pin is
shorted to the GND pin inside the PD while the load
capacitor is charged, current will flow through the para-
sitic body diode of the internal MOSFET and may cause
permanent damage to the LTC4257-1.
Electro Static Discharge and Surge Suppression
The LTC4257-1 is specified to operate with an absolute
maximum voltage of –100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily V
IN
and GND) can routinely
see peak voltages in excess of 10kV. To protect the
LTC4257-1, it is highly recommended that a transient
voltage suppressor be installed between the bridge and
the LTC4257-1 (D3 in Figure 2).
LTC4257-1
18
42571fb
APPLICATIO S I FOR ATIO
WUUU
•
1
•
•
5
4
•
1
3
2
RX
–
SPARE
–
6
RX
+
3
TX
–
2
TX
+
J2
IN
FROM
PSE
T1
RJ45
1
7
8
5
4
6
8
7
TXOUT
+
OUT
TO PHY
TXOUT
–
SPARE
+
RXOUT
+
RXOUT
–
16
14
15
11
9
10
C19
47pF
C13
470pF
V
OUT+
V
OUT–
R24
100k R28
10k
R23
3.65k
1%
R13
30.1k
1%
R17
10k
R14
100k
R11
10k
R10
62k
R25
62k
R26
10k
R27
62k C20
0.47µF
C21
0.1µF
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE 5%
2. ALL CAPACITORS ARE 25V
3. SELECT R
CLASS
FOR CLASS 1-4 OPERATION. REFER
TO DATA SHEET APPLICATIONS INFORMATION SECTION
4. CONNECT TO CHASSIS GROUND
C4 TO C6: TDK C4532X5R0J107M
C2, C23: AVX 1808GC102MAT
D1, D7: MM3Z12VT1
D3: MMBD1505
D9 TO D12, D14 TO D16: DIODES INC., B1100
L1: COILCRAFT D01608C-472
T1: PULSE H2019
T2: PULSE PB2134
T3: PULSE PA0184
OSCAP SFSTt
ON
ENDLYMINENAB
LT1737CGN
R
OCMP
V
CC
R
CMPC
UVLO GATE
SGND PGND
V
C
FB
3V
OUT
I
SENSE
C22
680pF
0603 D8
BAT54
D5
B0540W
C17
3300pF
R15
0.22Ω
1/2W
1%
R4
10k
T2
SEPARATING
LINE
FOR GROUND
PLANE
T3
8
D7
12V
1
C12
0.1µF
50V
C10
4.7µF
35V
R16
330Ω
C16
0.1µF
50V
C23
1000pF
2kV
•
9
10
3
•
5
4
C18
1nF
R18
100Ω
Q6
Si7892DP
Q7
FMMT718
Q8
MMBT3904
8
11
C14
1µF
R12
47Ω
C4 TO C6
100µF
6.3V 3.3V @ 3.3A
Q3
Si4490DY
R
CLASS
1%
NC
R
CLASS
NC
V
IN
C1B
0.82µF
100V
C1C
0.82µF
100V
L1
4.7µH
Q2
MMBT3904
Q4
MMBT2907ALT1
Q5
MMBT3904
R9
100Ω
R8
47Ω
R6
47Ω
C9
100pF
D2
BAT54
Q1
MMBTA06
D4
BAS21LT1
D1
12V
D3A D3B
R7
33Ω
1/4W
C1A
10µF
100V
R5
47K
+
Q9
2N7002
D13
MMSD4148
C11
0.1µF
100V
D6
SMAJ58A
R30
75Ω
C24
0.01µF
200V
R31
75Ω
C25
0.01µF
200V
R1
75Ω
C7
0.01µF
200V
R2
75Ω
C3
0.01µF
200V
C2
1000pF
2kV
42571 TA02
D10
B1100
D12
B1100
D9
B1100
D11
B1100
D17
B1100
D16
B1100
D15
B1100
D14
B1100
3
4
4
LTC4257CDD-1
GND
SIGDISA
PWRGD
V
OUT
Figure 11. PD Power Interface with 3.3V, 3.3A High Efficiency Isolated Power Supply
LTC4257-1
19
42571fb
U
PACKAGE DESCRIPTIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 1203
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
LTC4257-1
20
42571fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2003
LT 1205 1K REV B • PRINTED IN USA
PD Power Interface with 3.3V, 3A Nonisolated Power Supply
TYPICAL APPLICATIO
U
1
3
2
RX
–
6
RX
+
3
TX
–
2
TX
+
J1
T1
XFMR
RJ45
1
7
8
5
4
SPARE
–
SPARE
+
6
8
7
TXOUT
+
TXOUT
–
RXOUT
+
RXOUT
–
TO
PHY
R12
75Ω
R11
75Ω
75Ω
C4
0.01µF
200V
C3
0.01µF
200V
0.01µF
200V
0.01µF
200V
C8
0.001µF
2kV
16
14
15
11
9
10 C14
0.1µF
100V
LTC4257-1
LTC1871
Q3
FDC2512
C1A
4.7µF
100V
Q2
FMMT625
D3
TVS
SMAJ58A
D4
MMBZ5235B
6.8V
R
CLASS
1%
NC
R
CLASS
NC
V
IN
GND
SIGDISA
PWRGD
V
OUT
RUN
I
TH
FB
FREQ
MODE/SYNC
SENSE
V
IN
INTV
CC
GATE
GND
BR2
DF01SA
~+
~–
BR1
DF01SA
~+
~–
C1B
2.2µF
100V
R10
100k
R
T
80.6k
1%
R14
12.4k
1%
R15
21k 1%
C6
1µF 6.3V
Q1
2N7002
C
C1
1nF
R
C
12k
R17
750Ω
R13
100k
L1
1µH
R16
100Ω
Q4
FMMT2222
D6
1N4148
R9
100k
R18
10k
+
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTOR VALUES ARE 5%
2. SELECT R
CLASS
FOR CLASS 1-4 OPERATION.
REFER TO DATA SHEET APPLICATIONS INFORMATION SECTION
3. CONNECT TO CHASSIS GROUND
C1A: PANASONIC ECEV2AA4R7P
C1B: TDK C5750X7R2A225KT
C8: AVX 1808GC102MAT
C9, C10, C12, C13: TDK C4532X5ROJ107
L1: LQLB2518T1ROM
T1: PULSE H2019
R5
0.1Ω
1%
C5
4.7µF
6.3V
•
4
2
11
9
T2
CTX-02-15242
D5
UPS840
12
4257 TA03
10
••
C9
100µF
X5R
6.3V
C10
100µF
X5R
6.3V
V
OUT+
3.3V
AT 3A
V
OUT–
+
+
C12
100µF
X5R
6.3V
C13
100µF
X5R
6.3V
+
+
3
2
75Ω
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1737 High Power Isolated Flyback Controller Sense Output Voltage Directly from Primary-Side Winding
LTC1871 Wide Input Range, No R
SENSE
™ Current Mode Flyback, Adjustable Switching Frequency, Programmable Undervoltage
Boost and SEPIC Controller Lockout, Optional Burst Mode
®
Operation at Light Load
LTC3803 Current Mode Flyback DC/DC Controller in ThinSOT™ 200kHz Constant Frequency, Adjustable Slope Compensation,
Optimized for High Input Voltage Applications
LTC4257 IEEE 802.3af PD Interface Controller 100V, 400mA Internal Switch, Programmable Classification
LTC4258 Quad IEEE 802.3af Power over Ethernet Controller DC Disconnect Only, IEEE-Compliant PD Detection and Classification,
Autonomous Operation or I
2
C™ Control
LTC4259A-1 Quad IEEE 802.3af Power over Ethernet Controller AC or DC Disconnect, IEEE-Compliant PD Detection and
Classification, Autonomous Operation or I
2
C Control
LTC4267 IEEE 802.3af PD Interface Controller with Onboard 100V, 400mA Internal Switch, 16-Pin SSOP or 3mm × 5mm
Integrated Switching Regulator DFN Packages
Burst Mode is a registered trademark of Linear Technology Corporation. No R
SENSE
and ThinSOT are trademarks of Linear Technology Corporation.
