MAX6412–MAX6420
Interfacing to Other Voltages for Logic
Compatibility
The open-drain outputs of the MAX6414/MAX6417/
MAX6420 can be used to interface to µPs with other
logic levels. As shown in Figure 5, the open-drain out-
put can be connected to voltages from 0 to 5.5V. This
allows for easy logic compatibility to various micro-
processors.
Negative-Going VCC Transients
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, these supervisors
are relatively immune to short-duration negative-going
transients (glitches). The Maximum Transient Duration vs.
Reset Threshold Overdrive graph in the
Typical
Operating Characteristics
shows this relationship.
The area below the curve of the graph is the region in
which these devices typically do not generate a reset
pulse. This graph was generated using a negative-
going pulse applied to VCC, starting above the actual
reset threshold (VTH) and ending below it by the magni-
tude indicated (reset-threshold overdrive). As the mag-
nitude of the transient decreases (farther below the
reset threshold), the maximum allowable pulse width
decreases. Typically, a VCC transient that goes 100mV
below the reset threshold and lasts 50µs or less will not
cause a reset pulse to be issued.
Ensuring a Valid RESET or
RESET
Down to VCC = 0V
When VCC falls below 1V, RESET/RESET current sink-
ing (sourcing) capabilities decline drastically. In the
case of the MAX6412, MAX6415, and MAX6418, high-
impedance CMOS-logic inputs connected to RESET
can drift to undetermined voltages. This presents no
problems in most applications, since most µPs and
other circuitry do not operate with VCC below 1V.
In those applications where RESET must be valid down
to 0, adding a pulldown resistor between RESET and
ground sinks any stray leakage currents, holding
RESET low (Figure 6). The value of the pulldown resis-
tor is not critical; 100kΩis large enough not to load
RESET and small enough to pull RESET to ground. For
applications using the MAX6413, MAX6416, and
MAX6419, a 100kΩpullup resistor between RESET and
VCC will hold RESET high when VCC falls below 1V
(Figure 7). Open-drain RESET versions are not recom-
mended for applications requiring valid logic for VCC
down to 0V.
Low-Power, Single/Dual-Voltage µP Reset Circuits
with Capacitor-Adjustable Reset Timeout Delay
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