DS077-3 (v1.0) No vember 15, 2001 www.xilinx.com Module 3 of 4
Preliminary Product Specification 1-800-255-7778 1
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Definition o f Term s
In this document, some specifications may be designated as Advance or Preliminary. These terms are defined as foll ows:
Advance: Initial estima tes based on s imulation and/ or extrapolation from ot her speed grades, devices, or families. Val ues
are subject to chan ge. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are
deriv ed from measuring internal test patterns. All specifications are representativ e of worst-case supply voltage and junction
temperature conditions. The parameters included are common to popular designs and typical applications. All
specifications are subject to change witho ut notice .
Specifications are Preliminary for the XC2S50E, XC2S100E, XC2S200E, and XC2S300E, -6 speed grade. Specifications for
the XC2S150E and -7 spe ed grade (all devices) are Advance Information.
DC Specifications
Ab solu te Maxim u m Rati ng s(1)
0Spartan-IIE 1.8V FPGA Family:
DC and Switc hing Characteristics
DS077-3 (v1.0) November 15, 2001 00Preliminary Product Speci fication
Symbol Description Min Max Units
VCCINT Supply voltage relativ e to GND –0.5 2.0 V
VCCO Supply voltage relative to GND –0.5 4.0 V
VREF Input reference voltage –0.5 4.0 V
VIN Input voltage relative to GND(2,3) –0.5 4.0 V
VTS Voltage app lied to 3-state output(3) –0.5 4.0 V
TSTG Storage temperature (ambient) –65 +150 °C
TJJunction temperature - +125 °C
Notes:
1. Stresses beyond t hose listed un der Absolute Maximum Ratings may cause permanent damage to the device . These are stress
ratings only, and fu nctional operation of the de vice at these or an y oth er conditions bey ond t hose listed under Oper ating Conditions
is not imp lied. Exposure to Absolute Maximum Rating s conditions for e xtended periods o f tim e may affect de vice rel iabili ty.
2. VIN should not exceed VCCO by more than 3.6V over extended periods of time (e.g., longer than a day).
3. Maxim um DC overshoot must be limited to either VCCO + 0.5V or 10 mA, and unde rshoot mu st be l imited to –0. 5V or 10 mA,
whichever is easier to achieve . The Maximum AC conditi ons are as follows: The device pins ma y undershoot to –2.0 V or ove rshoot
to VCCO + 2.0V, provided thi s over/undershoot lasts no more t han 11 ns wit h a forcing cur rent no greater than 100 mA.
4. For soldering guidel ines , see th e Packa ging Information on the Xilinx website.
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Recommended Operating Conditions
DC Char acteristics Over Recommended Operating Conditions
Symbol Description Min Max Units
TJJunct ion temperature Commercial 0 85 °C
Industrial –40 100 °C
VCCINT Supply voltage relativ e to GND(1) Commercial 1.8 – 5% 1.8 + 5% V
Industr ial 1.8 – 5% 1.8 + 5% V
VCCO Supply voltage relative to GND(2) Commercial 1.2 3.6 V
Industrial 1.2 3.6 V
TIN Input signal transition time(3) - 250 ns
Notes:
1. Functi onal operati on is guaranteed down to a mini m um VCCINT of 1.62V (Nominal VCCINT –10%). For every 50 mV reduction in
VCCINT below 1.71V (nominal VCCINT –5%), all delay parameters increase by 3%.
2. Mi nimum and maximum values for VCCO v ary according to the I/O standard selected.
3. Input and output measurement threshold is ~50% of VCCO.
Symbol Description Min Max Units
VDRINT Data retention VCCINT voltage (below which configuration
data may be lost) 1.5 - V
VDRIO Data retention VCCO voltage (below which configuration
data may be lost) 1.2 - V
ICCINTQ Quiescent VCCINT supply
current(1) XC2S50E - 200 mA
XC2S100E - 200 mA
XC2S150E - 300 mA
XC2S200E - 300 mA
XC2S300E - 300 mA
ICCOQ Quiescent VCCO suppl y current(1) -2mA
IREF VREF curren t per VREF pin - 20 µA
ILInput or o utput leakage current –10 +10 µA
CIN Input capacitance (sampl e teste d) TQ, PQ, FG, FT
packages -8pF
IRPU Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V
(sample tested)(2) -0.25mA
IRPD Pad pull-down (when selected) @ VIN = 3.6V
(sample tested)(2) -0.25mA
Notes:
1. With no output curr ent loads, no active input pull -up res istors, all I/O pin s 3-stated and floating.
2. Internal p ull- up an d pull -down res istors guar antee v alid logi c le v e ls at unconnec ted input pins . These pul l-up and pull-do wn resistors
do not provide valid logic l evels when input pins are connected to other circuits.
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Preliminary Product Specification 1-800-255-7778 3
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Power-On Requirements
Spartan-IIE FPGAs require that a minimum suppl y current
ICCPO be provided to the VCCINT lines for a successful
power-on. If more current is available, the FPGA can con-
sume more than ICCPO min., though this cannot adversely
affe c t r e l iabi lity.
A maximum limit for ICCPO is not specified. Be careful when
using foldback/crowbar suppli es and fuses. It is possible to
control the magnitude of ICCPO by limiting the supply current
av ailable to the FPGA. A current limit below the trip lev el will
avoid inadvertently activating over-current protection cir-
cuits.
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for VOL and VOH are guaranteed output voltages
over t he recom men ded operating conditions. Only sele cted
standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards
are tested at minimum VCCO with the respective IOL and IOH
currents shown. Other standards are sample tested.
Symbol Description Min(1) Max Units
ICCPO Total VCCINT supply current required
dur ing power-on Commercial 500 - mA
Industrial 2 - A
TCCPO VCCINT(2,3) ramp t ime 2 50 ms
Notes:
1. The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCCINT ramps from 0 to 1.8V.
2. The ramp ti m e is measured from GND to 1.8V on a fully loaded boa rd.
3. VCCINT mus t not d ip i n the negative direction during power on.
4. Power -on current is measured with VCCINT and VCCO po wering up simul taneously.
5. I/Os ar e not guaran teed to be disabled until VCCINT is appli ed.
Input/Output
Standard VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
LVTTL(1) –0.5 0.8 2.0 3.6 0.4 2.4 24 –24
LVCMOS2 –0.5 0.7 1.7 2.7 0.4 1.9 12 –12
LVCMOS18 –0.5 35% VCCO 65% VCCO 1.95 0.4 VCCO – 0.4 8 –8
PCI, 3.3V –0.5 30% VCCO 50% VCCO VCCO + 0.5 10% VCCO 90% V CCO Not e (2) Note (2)
GTL –0.5 VREF – 0.05 VREF + 0.05 3.6 0 .4 - 40 -
GTL+ –0.5 VREF – 0.1 VREF + 0.1 3.6 0.6 - 36 -
HSTL I –0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 8 –8
HSTL III –0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 24 –8
HSTL IV –0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 48 –8
SSTL 3 I –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.6 VREF + 0 .6 8 –8
SSTL 3 II –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.8 VREF + 0.8 16 –16
SSTL 2 I –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.61 VREF + 0. 61 7 .6 –7.6
SSTL 2 II –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.8 VREF + 0.8 15.2 –15.2
CTT –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.4 VREF + 0 .4 8 –8
AGP –0.5 VREF – 0.2 VREF + 0.2 3.6 10% VCCO 90% V CCO Note (2) Note (2)
Notes:
1. VOL and VOH f or l o wer drive currents are sample tested.
2. Tested according to the relevant specificati ons.
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LVDS DC Specif ications
LVPECL DC Specifications
These values are valid at the output of the sourc e termina-
tion pack shown under LVPECL, with a 100Ω differential
load only. The VOH levels are 200 mV below standard
LVPECL levels and are compatible with devices tolerant of
lower common-mode ranges. The following table
summa2rizes the DC output specifications of LVPECL.
Symbol Description Conditions Min Typ Max Units
VCCO Supply volta ge 2.375 2.5 2. 625 V
VOH Output High voltage for Q and Q RT = 100Ω across Q and Q signals 1.25 1.425 1.6 V
VOL Output Low voltage for Q and Q RT = 100Ω across Q and Q signals 0.9 1.075 1.25 V
VODIFF Diff erential output voltage (Q – Q),
Q = High or (Q – Q), Q = High RT = 100Ω across Q and Q signals 250 350 450 mV
VOCM Output common-mode v oltage RT = 100Ω across Q and Q signals 1.125 1.25 1.375 V
VIDIFF Differential in put voltage (Q – Q),
Q = High or (Q – Q), Q = High Common-mode input voltage = 1.25 V 100 350 - mV
VICM In put commo n-mod e voltage Differential input voltag e = ±350 mV 0. 2 1.25 2.2 V
Notes:
1. Refer to Application Not e XAPP179 for termination schematics.
DC Pa rameter Min Max Min Max Min Max Units
VCCO 3.0 3.3 3.6 V
VOH 1.8 2.11 1.92 2.28 2.13 2.41 V
VOL 0.96 1.27 1.06 1.43 1.30 1.57 V
VIH 1.49 2.72 1.49 2.72 1.49 2.72 V
VIL 0.86 2.125 0.86 2.125 0.86 2.125 V
Differential input voltage 0.3 - 0.3 - 0.3 - V
Spartan-IIE 1.8V FPGA Fa mily: DC and Switching Characteristics
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Switching Characteristics
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer
(TRA CE in the Xilinx De v elopment System) and back -anno-
tated to the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan-IIE devices
unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)(1)
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)(1)
Symbol Description
Spee d Grad e
Units
All -7 -6
Min Max Max
TICKOFDLL LVTT L global clock inpu t to output delay us in g
output flip-flop f or L V TTL, 12 mA, f ast sle w rate,
with DLL.
--3.1ns
Notes:
1. Listed above are representative val ues where one global clock input drives one ver tical clock line in each accessible column, and
where all accessib le IOB an d CLB flip-flops are clocked by the global cloc k net.
2. Output timin g is m easured at 50% VCC thres hold wi th 35 pF e xternal capa ci tiv e load fo r LVTTL. The 3 5 pF load does not appl y to the
Min values. For other I/O st andards and differen t l oads, see the tables Constants for Calculating TIOOP and Delay M easurement
Methodology, page 11.
3. DLL output jitter is already included in t he ti m ing calcul ati on.
4. For data output with different standards , adjust del ays with the v alues show n in IOB Output Dela y Adjustmen ts f or Differ ent
Standards, page 10. For a global cl ock input with standards other t han LVTTL, adjust delays with v alues from the I/O Standard
Global Clock Input Adjustments, page 12.
Symbol Description Device
Spee d Grad e
Units
All -7 -6
Min Max Max
TICKOF LVTTL global clock input to output
delay using output flip-flop for
LVTTL, 12 mA, fast slew rate,
without DLL.
XC2S50E - - 4.6 ns
XC2S100E - - 4.6 ns
XC2S150E - - 4.7 ns
XC2S200E - - 4.7 ns
XC2S300E - - 4.7 ns
Notes:
1. Listed above are representative val ues where one global clock input drives one ver tical clock line in each accessible column, and
where all accessib le IOB an d CLB flip-flops are clocked by the global cloc k net.
2. Output tim ing is measur ed at 50% VCC thr eshold with 35 p F ex ternal c apacit iv e l oad for LVTTL. Th e 35 pF load do es n ot appl y to th e
Min values. F or other I /O standards and different loads , see the tab les Constants for Calcul ating TIOOP and Del ay Measurement
Methodology, page 11.
3. For data output with different standards , adjust del ays with the v alues show n in IOB Output Dela y Adjustmen ts f or Differ ent
Standards, page 10. For a global cl ock input with standards other t han LVTTL, adjust delays with v alues from the I/O Standard
Global Clock Input Adjustments, page 12.
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Global Clock Setup and Hold for LVTTL Standard, with D LL (Pin-to-Pin)
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)
Symbol Description
Sp eed Gr ade
Units
-7 -6
Min Min
TPSDLL / TPHDLL Input setup and hold time relative to global clock input signal
for LV TT L standa rd, no delay, IFF,(1) with DLL - 1.7 / 0 ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup tim e is measured rel ati ve to the Global Clock input s ignal with the fastest route an d the l ightest l oad. Hold time is measured
relat ive to the Global Cl ock input signal wi th the s lowe st r oute and hea viest load.
3. DLL output jitter is already included in t he ti m ing calcul ati on.
4. For data input wi th different standards, adjust the setup time del ay by the values shown in IOB Input Delay Adjustments for
Different Standar ds, page 8. For a global clock input wit h standards other than LVTTL, adju st del ays with values from the I/O
Standard Global Clock Input Adjust m ents , page 12.
Symbol Description Device
Speed Grade
Units
-7 -6
Min Min
TPSFD / TPHFD Input setup and hold time relative
to global clock input signal for
LVTTL standa rd , no delay, IFF,(1)
without DLL
XC2S 50E - 1.8 / 0 ns
XC2S 100E - 1.8 / 0 ns
XC2S 150E - 1.9 / 0 ns
XC2S 200E - 1.9 / 0 ns
XC2S 300E - 2.0 / 0 ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup tim e is measured rel ati ve to the Global Clock input s ignal with the fastest route an d the l ightest l oad. Hold time is measured
relat ive to the Global Cl ock input signal wi th the s lowe st r oute and hea viest load.
3. For data input wi th different standards, adjust the setup time del ay by the values shown in IOB Input Delay Adjustments for
Different Standar ds, page 8. For a global clock input wit h standards other than LVTTL, adju st del ays with values from the I/O
Standard Global Clock Input Adjust m ents , page 12.
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IOB Input Switching Characteristics(1)
Input delays assoc iated with the pad are specified for LVTTL levels. For other standard s, adjust the delays with the values
shown in IOB Input Delay Adjustme nts for Different Standards, page 8.
Symbol Description Device
Speed Grade
Units
-7 -6
Min Max Min Max
Propagation Delays
TIOPI Pa d to I output, no delay All - - - 0.8 ns
TIOPID Pa d to I output, with delay All - - - 1.0 ns
TIOPLI P ad to output IQ via transparent latch,
no delay All - - - 1.6 ns
TIOPLID Pad to output IQ via transparent latch,
with delay XC2S50E - - - 3.1 ns
XC2S100E - - - 3.1 ns
XC2S150E - - - 3.3 ns
XC2S200E - - - 3.3 ns
XC2S300E - - - 3.3 ns
Sequential Delays
TIOCKIQ Clock CLK to output IQ All - - - 0.7 ns
Setup/Hold Times with Respect to Clock CLK
TIOPICK / TIOICKP Pad, no delay All - - 1.5 / 0 - ns
TIOPICKD / TIOICKPD Pa d, with d elay XC2S50E - - 2.9 / 0 - ns
XC2S 100 E - - 2. 9 / 0 - ns
XC2S 150 E - - 3. 1 / 0 - ns
XC2S 200 E - - 3. 1 / 0 - ns
XC2S 300 E - - 3. 1 / 0 - ns
TIOICECK / TIOCKICE ICE input All - - 0.7 / 0.01 - ns
Set/Reset Delays
TIOSRCKI SR input (IFF, synch ronous) All - - 1. 0 - ns
TIOSRIQ S R input to IQ (asynchrono us) All - - - 1.4 ns
TGSRQ G SR to o u tp ut IQ A ll - - - 9.7 ns
Notes:
1. Input timing for LVTTL i s measured at 1. 4V. For other I/O standards, see the table Delay Measurement Methodology, page 11.
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IOB Input Delay Adjustments for Different Standards
Input delay s associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values sho wn. A
delay adjusted in this way constitut es a worst-case limit.
Symbol Description Standard
Speed Grade
Units-7 -6
Data I n put Delay Adjustme nts
TILVTTL Standard-specific data input delay
adjustments LVTTL - 0 ns
TILVCMOS2 LVCMOS2 - 0 ns
TILVCMOS18 LVCMOS18 - 0.20 ns
TILVDS LVDS - 0.15 ns
TILVPECL LVPECL - 0.15 ns
TIPCI33_3 PCI, 33 MHz, 3.3V - 0.08 ns
TIPCI66_3 PCI, 66 MHz, 3.3V - –0.11 ns
TIGTL GTL - 0.14 ns
TIGTLP GTL+ - 0.14 ns
TIHSTL HSTL - 0.04 ns
TISSTL2 SSTL2 - 0.04 ns
TISSTL3 SSTL3 - 0.04 ns
TICTT CTT - 0.10 ns
TIAGP AGP - 0.04 ns
Spartan-IIE 1.8V FPGA Fa mily: DC and Switching Characteristics
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IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate . For other standards, adjust
the delays with the values s hown in IOB Output Delay Adjustments for Different Standards, page 10.
Symbol Description
Sp eed Gra de
Units
-7 -6
Min Max Min Max
Propagation Delays
TIOOP O input to pad - - - 2.9 ns
TIOOLP O input to pad via transparent latch - - - 3.4 ns
3-state Delays
TIOTHZ T input to pad high impedance(1) ---1.9ns
TIOTON T input to valid data on pad - - - 3.1 ns
TIOTLPHZ T input to pad high mpedance via transparent latch(1) ---2.2ns
TIOTLPON T input to val id data on pad via transparent latch - - - 3.4 ns
TGTS GTS to pad high impedanc e(1) ---4.9ns
Sequential Delays
TIOCKP Clo ck CLK to pad - - - 2 .9 ns
TIOCKHZ Clock CLK to pad high imped ance (synchronou s) (1) ---2.2ns
TIOCKON Clo ck CLK to valid data on pad (synchrono us) - - - 3 .4 ns
Setup/Hold Times wi th Respec t to Clock CL K
TIOOCK / TIOCKO O input - - 1.1 / 0 ns
TIOOCECK / TIOCKOCE OCE i n pu t - - 0 .7 / 0 ns
TIOSRCKO / TIOCKOSR SR input (OFF ) - - 1.0 / 0 ns
TIOTCK / TIOCKT 3-st ate setup times, T input - - 0.7 / 0 ns
TIOTCECK / T IOCKTCE 3-st ate setup times, TCE input - - 0.8 / 0 ns
TIOSRCKT / TIOCKTSR 3-s tate setup times, SR input (TFF) - - 1.0 / 0 ns
Set/Reset Delays
TIOSRP SR input to pad (asynchronous ) - - - 3 .5 ns
TIOSRHZ S R input to pad high impeda nce (asynchronou s) (1) ---2.7ns
TIOSRON SR input to valid data on pad (asynchrono us ) - - - 3 .9 ns
TIOGSRQ G SR to pad - - - 9 .7 ns
Notes:
1. Three-state turn-off delays should not be adjusted.
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IOB Output Delay Adjustments for Different Standards(1)
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate . For other standards, adjust
the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit.
1
Symbol Description Standard Speed Grade Units-7 -6
Output D e lay Adjustments (Adj)
TOLVTTL_S2 Standard-spe cific adjustment s for
output delays ter m ina ting at pads
(based on standard capacitive
load, CSL)
LVTTL, Slow, 2 mA - 14.7 ns
TOLVTTL_S4 4 mA - 7.5 ns
TOLVTTL_S6 6 mA - 4.8 ns
TOLVTTL_S8 8 mA - 3.0 ns
TOLVTTL_S12 12 mA - 1. 9 ns
TOLVTTL_S16 16 mA - 1. 7 ns
TOLVTTL_S24 24 mA - 1. 3 ns
TOLVTTL_F2 LVTTL, Fast, 2 mA - 13.1 ns
TOLVTTL_F4 4 m A - 5.3 ns
TOLVTTL_F6 6 m A - 3.1 ns
TOLVTTL_F8 8 m A - 1.0 ns
TOLVTTL_F12 12 mA - 0 ns
TOLVTTL_F16 16 mA - –0.05 ns
TOLVTTL_F24 24 mA - –0.20 ns
TOLVCMOS2 LVCMOS2 - 0.09 ns
TOLVCMOS18 LVCMS18 - 0.7 ns
TOLVDS LVDS - –1.2 ns
TOLVPECL LVPECL - –0.41 ns
TOPCI33_3 PCI, 33 MHz, 3.3V - 2. 3 ns
TOPCI66_3 PCI, 66 MHz, 3.3V - –0.41 ns
TOGTL GTL - 0.49 ns
TOGTLP GTL+ - 0.8 ns
TOHSTL_I HSTL I - –0.51 ns
TOHSTL_III HSTL III - –0.91 ns
TOHSTL_IV HSTL IV - –1.01 ns
TOSSTL2_I SST L2 I - –0.51 ns
TOSSLT2_II SSTL2 II - –0.91 ns
TOSSTL3_I SST L3 I - –0.51 ns
TOSSTL3_II SST L3 II - –1.01 ns
TOCTT CTT - –0.61 ns
TOAGP AGP - –0.91 ns
Notes:
1. Output tim ing is measur ed at 1.4V with 35 pF external capaci tiv e load fo r LVTTL. Fo r other I/O standar ds and diff erent loads, see th e
tables Constants for Calcul ating TIOOP and Delay Measurement Methodology, page 11.
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Calculation of TIOOP as a Func tion of
Capacitance
TIOOP is the prop agation d elay from the O Input of the IOB
to the pad. The value s for T IOOP a re bas ed on the standard
capacitive load (CSL) for each I/O standard as listed in the
table C onsta nts f or Calcula ting TIOOP, b elow.
F or other capacitive l oads, use the formulas below to calcu-
late an adjusted propagation delay, TIOOP1.
TIOOP1 = TIOOP + A dj + ( C LOAD – CSL) * FL
Where:
Adj i s se lected from IOB Output Delay
Adjustments for Different Stand ards,
page 10, according to the I/O standard used
CLOAD is the capacitive load for the design
FLis the capac itanc e scaling factor
Delay Measurement Methodology
Standard VL(1) VH(1) Meas.
Point VREF
Typ(2)
LVTTL 0 3 1.4 -
LVCMOS2 0 2.5 1.125 -
PCI33_3 Per PCI Spec -
PCI66_3 Per PCI Spec -
GTL VREF – 0.2 VREF + 0. 2 V REF 0.80
GTL+ VREF – 0.2 V REF + 0.2 VREF 1.0
HSTL Class I VREF – 0.5 V REF + 0.5 VREF 0.75
HSTL Class III VREF – 0.5 V REF + 0.5 VREF 0.90
HSTL Class IV VREF – 0.5 VREF + 0. 5 V REF 0.90
SSTL3 I and II VREF – 1.0 V REF + 1.0 V REF 1.5
SSTL2 I and II VREF – 0.75 VREF + 0.75 VREF 1.25
CTT VREF – 0.2 VREF + 0.2 V REF 1.5
AGP VREF –
(0.2xVCCO)VREF +
(0.2xVCCO)VREF Per AGP
Spec
LV DS 1. 2 – 0.125 1.2 + 0.125 1.2
LV PECL 1.6 – 0.3 1.6 + 0.3 1.6
Notes:
1. Input waveform switches between VL and VH.
2. Meas urements are made at VREF Typ, Maximum, and
Minimum. Wors t- case values are r eported.
3. I/O parameter measurements are made wit h the capacitance
value s shown in the foll owing table, Constants for
Calcul ating TIOOP. Refer to Application Note XAPP179 for
appropriate te rminat ions.
4. I/O standard measurements are refl ected in the IBIS model
informati on except where the IBIS f ormat precludes i t.
Constants for Calcul ating TIOOP
Standard CSL(1)
(pF) FL
(ns/pF)
LVTTL Fast Slew Rate, 2 mA drive 35 0.41
LVTTL Fast Slew Rate, 4 mA drive 35 0.20
LVTTL Fast Slew Rate, 6 mA drive 35 0.13
LVT TL Fast Slew Rate, 8 mA dr ive 35 0.079
LVT TL Fast Slew Rate, 12 mA dr ive 35 0.044
LVT TL Fast Slew Rate, 16 mA dr ive 35 0.043
LVT TL Fast Slew Rate, 24 mA dr ive 35 0.033
LVTTL Slow Slew Rate, 2 mA driv e 35 0.41
LVTTL Slow Slew Rate, 4 mA driv e 35 0.20
LVTTL Slow Slew Rate, 6 mA drive 35 0.100
LVTTL Slow Slew Rate, 8 mA drive 35 0.086
LVTTL Slow Slew Rate, 12 mA drive 35 0.058
LVTTL Slow Slew Rate, 16 mA drive 35 0.050
LVTTL Slow Slew Rate, 24 mA drive 35 0.048
LVCMOS2 35 0.041
LVCMOS18 35 0.050
PCI 33 MHz 3.3V 10 0.050
PCI 66 MHz 3.3V 10 0.033
GTL 0 0.014
GTL+ 0 0.017
HSTL Class I 20 0.022
HSTL Class III 20 0.016
HSTL Class IV 20 0.014
SSTL2 Class I 30 0.028
SSTL2 Class II 30 0.016
SSTL3 Class I 30 0.029
SSTL3 Class II 30 0.016
CTT 20 0.035
AGP 10 0.037
Notes:
1. I/ O par ameter measuremen ts are made with the cap acitance
v alu es show n abov e . Refer to Appli cation Note XAPP179 for
appropriate t erminat ions.
2. I/O standard measurements are reflected in the IBIS model
information except wher e the IBIS for mat precludes it.
Spartan - IIE 1.8V FPGA Family: DC and Switching Characteri stics
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Clock Distribution Switching Characteristics
TGPIO is specified for LVTTL levels. F or other standards, adjust TGPIO with the values shown in I/O Standard Global Clock
Input Adjustments.
I/O Standard Global Clock Input Adjustments
Dela ys associated with a global clock input pad are specified for LVTTL level s. For other standards, adjust the delay s by the
values shown. A delay adjusted in this way cons titutes a worst-case limit.
Symbo l Description
Speed Grade
Units
-7 -6
Max Max
GCLK IOB and Buffer
TGPIO Global clock pad to output - 0. 7 ns
TGIO Global clock buffer I input to O output - 0.5 ns
Symbol Description Standard
Speed Grade
Units-7 -6
Data I n put Delay Adjustme nts
TGPLVTTL Standa rd-spe cific global clock
input dela y adjustments LVTTL - 0 ns
TGPLVCMOS2 LVCMOS2 - 0 ns
TGPLVCMOS18 LVCMOS18 - 0.2 ns
TGPLVCDS LVDS - 0.38 ns
TGPLVPECL LVCPECL - 0.38 ns
TGPPCI33_3 PC I, 33 M Hz, 3.3V - 0.08 ns
TGPPCI66_3 PC I, 66 M Hz, 3.3V - –0.11 ns
TGPGTL GTL - 0.37 ns
TGPGTLP GTL+ - 0.37 ns
TGPHSTL HSTL - 0.27 ns
TGPSSTL2 SSTL2 - 0.27 ns
TGPSSTL3 SSTL3 - 0.27 ns
TGPCTT CTT - 0.33 ns
TGPAGP AGP - 0.27 ns
Notes:
1. Input timin g for GPLVTTL is m easured at 1.4V. Fo r other I/ O standards, see the table Delay Measure me nt Methodology, page 11.
Spartan-IIE 1.8V FPGA Fa mily: DC and Switching Characteristics
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Preliminary Product Specification 1-800-255-7778 13
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DLL Timing Parameters
Switching parameters testing is modeled after testing meth-
ods specified by MIL-M-38510/605. Because of the difficulty
in directly measuring many internal timing parameters,
those parameters are derived from benchmark timing pat-
terns. The following guidelines reflect worst-case values
across the recom me nded operating conditions.
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were deter-
mined through statisti cal mea suremen t at the package pins
using a clock mirror configuration and matched drivers.
Figure 1, pag e 1 4, provides def initions for various parame-
ters in the table below.
Symbol Description FCLKIN
Spee d Grad e(1)
Units
-7(2) -6
Min Max Min Max
FCLKINHF Input clock frequency (CLKDLLHF) - 60 320 60 275 MHz
FCLKINLF Input clock f requency (CLKDLL) - 25 160 25 135 MHz
TDLLPW Input clock pulse width ≥2 5 M H z 5.0 - 5.0 - ns
≥50 MH z 3 .0 - 3.0 - ns
≥100 MHz 2.4 - 2.4 - ns
≥150 MHz 2.0 - 2.0 - ns
≥200 MHz 1.8 - 1.8 - ns
≥250 MHz 1.5 - 1.5 - ns
≥300 MHz 1.3 - NA -
Notes:
1. All spe cif ications correspond to Commercial Operating Temperatu res (0°C to +8 5 °C).
2. Advance Information
Symbol Description FCLKIN
CLKDLLHF CLKDLL UnitsMin Max Min Max
TIPTOL Input clock period tolerance - 1 .0 - 1.0 ns
TIJITCC Input clock jitter tolerance (cycle-to-cycle) - ±150 - ±300 ps
TLOCK Time required for D LL to acquire lock > 60 MHz - 20 - 20 µs
50-60 MHz - - - 25 µs
40-50 MHz - - - 50 µs
30-40 MHz - - - 90 µs
25-30 MHz - - - 120 µs
TOJITCC Output jitter (cycle-t o-cycle) f o r an y DLL cloc k output(1) - ±60 - ±60 ps
TPHIO P has e offset between CLKIN and CLKO(2) - ±100 - ±100 ps
TPHOO Phas e offset between clock outpu ts on the DLL(3) - ±140 - ±140 ps
TPHIOM Phase difference between CLKIN and CLKO(4) - ±160 - ±160 ps
TPHOOM Phase difference between clock outputs on the DLL(5) - ±200 - ±200 ps
Notes:
1. Output Jitter is cycle-to-cycle jitter measured on the DLL outp ut clock, excluding input clo ck jitter.
2. Phase Offset between CLKIN and CLK O is t he worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input cloc k jitt er.
3. Phase Offset between Cloc k Outputs on the DLL is the worst-case fi xed time dif fe rence between ri sing edges of any two DLL
outputs, excluding output jitte r and in put clock jitt er.
4. Maxim um Phase Differenc e bet ween CLKIN and CLK O i s the sum of output jit ter and p hase off set bet ween CLKIN and CLKO , or
the greatest difference bet ween CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5. Maxim um Phase Difference betwe en Clock Outputs on the DLL is the sum of output jitter and phase offset between any DLL
clock outputs, or the greatest di fference between any two DLL output rising edges due to DLL alone (excluding input cl ock jitte r).
6. All spe cif ications correspond to Commercial Operating Temperatu res (0°C to +8 5 °C).
Spartan - IIE 1.8V FPGA Family: DC and Switching Characteri stics
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14 1-800-255-7778 Preliminary Product Specification
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F igur e 1: Period Tolerance and Clock Jitter
Period Tolerance:
the allowed input clock period change in nanoseconds.
Output Jitter:
the difference between an ideal
reference clock edge and the actual design.
TCLKIN + TIPTOL
_
DS077_52_071201
Actual Period
+ Jitter
+/- Jitter
+ Maximum
Phase Difference
Phase Offset and Maximum Phase Difference
+ Phase Offset
Ideal Period
1
FCLKIN
T =
CLKIN
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Preliminary Product Specification 1-800-255-7778 15
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CLB Switching Char acteristics
Delays or iginating at F/G i nputs va ry slightly according to th e input used. The values listed be low are worst-case. Precise
values are provided by the timing analyzer.
Symbol Description
Speed Grade
Units
-7 -6
Min Max Min Max
Combinatorial Delays
TILO 4-in put functi on: F/G inputs to X/Y outputs - - - 0.4 7 ns
TIF5 5-input function: F/G inp uts to F5 output - - - 0.9 ns
TIF5X 5-in put functi on: F/G inputs to X output - - - 0.9 ns
TIF6Y 6-in put functi on: F/G inputs to Y output via F6 MUX - - - 1.0 ns
TF5INY 6-input function: F5IN inpu t to Y o utput - - - 0.22 ns
TIFNCTL Increme ntal delay routing through transparen t latch to
XQ/Y Q out puts ---0.8ns
TBYYB BY input to YB output - - - 0.51 ns
Sequential Delays
TCKO F F clock CLK to XQ/YQ out puts - - - 1.0 ns
TCKLO Latch clock CLK to XQ/YQ out puts - - - 1.0 ns
Setup/Hold Times wi th Respec t to Clock CL K
TICK / TCKI 4-in put function: F/G inp uts - - 1. 1 / 0 - ns
TIF5CK / TCKIF5 5-input function: F/G inputs - - 1.5 / 0 - ns
TF5INCK / TCKF5IN 6-input function: F5IN input - - 0. 8 / 0 - ns
TIF6CK / TCKIF6 6-input function: F/G inputs via F6 MUX - - 1.6 / 0 - ns
TDICK / TCKDI BX/BY inputs - - 0. 8 / 0 - ns
TCECK / TCKCE CE input - - 0. 7 / 0 - ns
TRCK / TCKR SR/BY inputs (synchronou s) - - 0. 6 / 0 - ns
Clock CLK
TCH Pulse width, High - - 1.4 - ns
TCL Pulse width, Low - - 1.4 - ns
Set/Reset
TRPW Pulse width, SR/BY inputs - - 2.4 - ns
TRQ Delay from SR /BY inputs to XQ/YQ out put s
(asynchronous) ---1.0ns
FTOG Toggle frequency (for export control) - - - 3 57 MHz
Spartan - IIE 1.8V FPGA Family: DC and Switching Characteri stics
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CLB Arithmetic Switching Characteristics
Setup time s not list ed explicitly can be approximated by dec reasing the co mbinat oria l del ays by th e set up t ime adj us tment
listed. Precise values are provided by the timing analyzer.
Symbol Description
Sp eed Gr ade
Units
-7 -6
Min Max Min Max
Combinatorial Delays
TOPX F operand inputs to X via XOR - - - 0.8 ns
TOPXB F operand input to XB output - - - 0.9 ns
TOPY F operand input to Y via XOR - - - 1.5 ns
TOPYB F operand input to YB output - - - 1.3 ns
TOPCYF F operand input to COUT output - - - 1.0 ns
TOPGY G operand inputs to Y via XOR - - - 0.9 ns
TOPGYB G opera nd input to YB output - - - 1.3 ns
TOPCYG G operand input to COUT output - - - 1.0 ns
TBXCY BX initialization input to COUT - - - 0.6 ns
TCINX CIN input to X output via XOR - - - 0.7 ns
TCINXB C IN i n p ut to XB - - - 0 .1 ns
TCINY CIN input to Y v ia XOR - - - 0.7 ns
TCINYB C IN i n p ut to YB - - - 0 .5 ns
TBYP CIN inpu t to COUT output - - - 0. 15 ns
Multiplier Oper ation
TFANDXB F1/2 operand inputs to XB output via AN D - - - 0.4 ns
TFANDYB F1/2 operand inputs to YB output via AND - - - 0.8 ns
TFANDCY F1/2 operand inputs to COUT output via AND - - - 0.6 ns
TGANDYB G1/2 operand inputs to YB output via AND - - - 0.7 ns
TGANDCY G1/2 operand inputs to COUT output via AND - - - 0.4 ns
Setup/Hold Times with Respect to Clock CLK
TCCKX / TCKCX CIN i n p ut to FF X - - 1. 3 / 0 - ns
TCCKY / TCKCY CIN i n p ut to FF Y - - 1. 3 / 0 - ns
Spartan-IIE 1.8V FPGA Fa mily: DC and Switching Characteristics
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Preliminary Product Specification 1-800-255-7778 17
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CLB Distributed RAM Switching Characteristics
CLB Shift Register Switching Characteristics
Block RAM Switching Characteristics
Symbol Description
Speed Grad e
Units
-7 -6
Min Max Min Max
Sequential Delays
TSHCKO16 Cloc k CLK to X/Y outputs (WE active, 16 x 1 mode) - - - 1.7 ns
TSHCKO32 Cloc k CLK to X/Y outputs (WE active, 32 x 1 mode) - - - 2.1 ns
Setup/Hold Times with Respect to Clock CLK
TAS / TAH F/G addres s inputs - - 0. 5 / 0 - ns
TDS / TDH BX/BY data inputs (DIN) - - 0. 6 / 0 - ns
TWS / TWH CE input (WS) - - 0.8 / 0 - ns
Clock CLK
TWPH Pulse width, High - - 2.4 - ns
TWPL Pulse width, Low - - 2.4 - ns
TWC Clock peri od to meet address wri te cycle time - - 4.8 - ns
Symb ol Description
Speed Grade
Units
-7 -6
Min Max Min Max
Sequential Delays
TREG Clock CLK to X/Y outputs - - - 3.2 ns
Setup/Hold Times with Respect to Clock CLK
TSHDICK B X/BY d a ta i n puts (D IN ) - - 0.6 / 0 - n s
TSHCECK CE input (WS) - - 0.8 / 0 - ns
Clock CLK
TSRPH Pulse width, High - - 2.4 - ns
TSRPL Pulse width, Low - - 2.4 - ns
Symbol Description
Speed Grade
Units
-7 -6
Min Max Min Max
Sequential Delays
TBCKO Clock CLK to DOUT output - - - 3.5 ns
Setup/Hold Times with Respect to Clock CLK
TBA CK / T BCKA ADDR inputs - - 1.1 / 0 - ns
TBDCK/ TBCKD DIN inputs - - 1.1 / 0 - ns
TBECK/ TBCKE EN inputs - - 2.5 / 0 - ns
TBRCK/ TBCKR RST input - - 2.3 / 0 - ns
TBWCK/ TBCKW WEN input - - 2.2 / 0 - ns
Clock CLK
TBPWH Pulse width, High - - 1.5 - ns
TBPWL Pulse width, Lo w - - 1.5 - ns
TBCCS CLKA -> CLKB setup time for different por t s - - 3. 0 - ns
Spartan - IIE 1.8V FPGA Family: DC and Switching Characteri stics
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TBUF Sw itching Characteristics
JTAG Test Access Port Switching Characteristics
Configuration Switching Characteristics
Symbol Description
Speed Grade
Units
-7 -6
Max Max
TIO IN i n p ut to O U T ou tpu t - 0 n s
TOFF TRI input to OUT output high impedance - 0.11 ns
TON TRI input to valid data on OUT output - 0.11 ns
Symbol Description
Speed Grade
Units
-7 -6
Min Max Min Max
Setup/Hold Times with Respect to TC K
TTAPTCK / TTCKTAP TMS and TDI setup times and hold times - - 4.0 / 2.0 - ns
Sequential Delays
TTCKTDO Output delay from clock TCK to output TDO - - - 11. 0 ns
FTCK T CK clock frequency - - - 33 MH z
Notes:
1. Before configuration can begin, VCCINT and VCCO Bank 2 must reach the recomme nded operating voltage.
F igur e 2: Co nf i gurat io n Ti m in g on Power-Up
DS077_02_110101
T
POR
T
PL
T
ICCK
Valid
CCLK Output or Input
M0, M1, M2
(Required)
PROGRAM
INIT
V
CC
(1)
.
Symbol Description All Devices UnitsMin Max
TPOR Power-on reset - 2 m s
TPL Program latency - 100 µs
TICCK CCLK output delay (Master serial
mode only) 0.5 4 µs
TPROGRAM Program pulse width 300 - ns
Spartan-IIE 1.8V FPGA Fa mily: DC and Switching Characteristics
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Preliminary Product Specification 1-800-255-7778 19
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Figure 3: Sla ve Serial Mode Timing
Figure 4: Master Serial Mo de Timing
TCCH
TCCO
TCCL
TCCD
TDCC
DIN
CCLK
DOUT
(Output)
DS001_16_032300
.
Symbol Description All Devices UnitsMin Max
TDCC /
TCCD
CCLK
DIN setup/hold 5 / 0 - ns
TCCO DOUT - 12 ns
TCCH High time 5 - ns
TCCL Low time 5 - ns
FCC Maximum frequency - 66 MHz
Serial Data In
CCLK
(Output)
Serial DOUT
(Output)
TDSCK
TCCO
TCKDS
DS001_17_110101
.
Symbol Description All De vices Units
Min Max
TDSCK /
TCKDS CCLK
DIN setup/hold 5 / 0 - ns
TCCO DOUT - 12 ns
FCC Frequency tolerance wit h respect to
nominal –30% +45% -
Spartan - IIE 1.8V FPGA Family: DC and Switching Characteri stics
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Figure 5: Slave Para llel (SelectMAP) Mode Writ e Timing
Figure 6: Slave Pa rallel (SelectMAP) Mode Write Abort Waveforms
DS001_20_061200
CCLK
No Write Write No Write Write
DATA[7:0]
CS
WRITE
TSMDCC TSMCCD
TSMCKBY
TSMCCCS
TSMWCC
TSMCCW
TSMCSCC
BUSY
Symbol Description All Devices UnitsMin Max
TSMDCC /
TSMCCD
CCLK
D0-D7 setup/hold 5 / 1 - ns
TSMCSCC /
TSMCCCS
CS setup/ho ld 7 / 1 - ns
TSMCCW /
TSMWCC
WRITE setup/hold 7 / 1 - ns
TSMCKBY BU SY propag ation delay - 1 2 ns
FCC Frequency - 66 MHz
FCCNH F requency with no handshake - 50 MHz
DS001_21_032300
CCLK
CS
WRITE
Abort
DATA[7:0]
BUSY
Spartan-IIE 1.8V FPGA Fa mily: DC and Switching Characteristics
DS077-3 (v1.0) No vember 15, 2001 www.xilinx.com Modul e 3 of 4
Preliminary Product Specification 1-800-255-7778 21
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Revision History
The Spartan-IIE Family Data Sheet
DS077-1, Spart an- I IE 1 .8V FP GA Fa mily: Introduction and Ordering Information (M odule 1)
DS077-2, Spart an- I IE 1 .8V FP GA Fa mily: Funct i on a l Des crip tio n (Mod ule 2)
DS077-3, Spartan-I IE 1.8V FPGA Family: DC and Switching Character istics (Modu le 3)
DS077-4, Spart an- I IE 1 .8V FP GA Fa mily: Pinout Tables (Mo dule 4)
Version No. Date Description
1.0 11/15/01 Initial X ilinx releas e .
