DS1682S+ - Maxim Integrated

General Description

The DS1682 is an integrated elapsed-time recorder con-

taining a factory-calibrated, temperature-compensated

RC time base that eliminates the need for an external

crystal. Using EEPROM technology to maintain data in

the absence of power, the DS1682 requires no backup

power source. The DS1682 detects and records the num-

ber of events on the EVENT pin and the total cumulative

event time since the DS1682 was last reset to 0. The

ALARM pin alerts the user when the total time accu-

mulated equals the user-programmed alarm value. The

polarity of the open-drain ALARM pin can be programmed

to either drive low or to become high impedance upon an

alarm condition. The DS1682 is ideal for applications that

monitor the total amount of time that a device has been

in operation and/or the number of uses since inception of

service, repair, or the last calibration.

Applications

●High-Temp, Rugged, Industrial Applications Where

Vibration or Shock Could Damage a Quartz Crystal

●Any System Where Time-of-Use is Important

(Warranty Tracking)

Benets and Features

●Records the Total Time That the Event Input Has

Been Active and the Number of Events That Have

Occurred

●32-Bit, Nonvolatile, Elapsed Time Counter (ETC)

Monitors Event Duration with Quarter-Second

Resolution and Provides 34 Years of Total Time

Accumulation

●Programmable Elapsed Time ALARM Output

●Nonvolatile, 17-Bit Event Counter Records the Total

Number of Times an Event has Occurred

●Calibrated, Temperature-Compensated RC Time

Base Accurate to 2% Typical

●10 Bytes of EEPROM User Memory

●Write Disable Function to Prevent the Memory from

Being Changed or Erased

●2-Wire Serial Communication

●Wide 2.5V to 5.5V Power-Supply Range

●Useful in Time-of-Use Warranty, Calibration, Repair,

and Maintenance Applications

Ordering Information appears at end of data sheet.

For related parts and recommended products to use with this part, refer

to www.maximintegrated.com/DS1682.related.

Figure 1. Block Diagram

SERIAL INTERFACE

EVENT COUNTER

CONTROL

LOGIC AND

EVENT

GLITCH

FILTER

OSCILLATOR

AND DIVIDER

SCL

SDA

VCC

ALARM

EVENT

DS1682

ELAPSED TIME

COUNTER (ETC)

USER, CONTROL, AND

CONFIGURATION

REGISTERS

ALARM REGS

AND

COMPARE LOGIC

EEPROM ARRAY

DS1682 Total-Elapsed-Time Recorder

with Alarm

19-6835; Rev 1; 11/13

Voltage Range on Any Pin Relative to Ground ......-0.3V to +6V

Operating Temperature Range ........................... -40°C to +85°C

Storage Temperature Range ............................ -55°C to +125°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) ....................................... +260°C

(TA = -40°C to +85°C, unless otherwise noted.)

(VCC = 2.5V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Power-Supply Voltage VCC 2.5 5.5 V

Input Trip Point VETP

0.3 x

VCC

0.5 x

VCC

0.7 x

VCC

Event Trip-Point Hysteresis VHYS

1% of

VCC

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Leakage ILI -1 +1 µA

ALARM Output (IOL = 10mA) VOL 0.8 V

SDA Output (IOL = 4mA) VOL 0.8 V

Active Supply Current

(Event Active) ICCA (Note 1) 120 300 µA

Standby Current

(Event Active) (Note 1) ICCS

VCC = 5.5V 6 15 µA

VCC = 3.0V 2 4

EEPROM Write Current IEE (Note 1) 150 300 µA

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Time Event Minimum tG(Note 1) 10 35 70 ms

Time Event Start tES (Note 1) 112 125 137 ms

Time Event Increment tEI (Note 1) 237.5 250 262.5 ms

Time Event Max tEM 34 Years

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Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Recommended DC Operating Conditions

DC Electrical Characteristics

Event Timing

(VCC = 2.5V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

EEPROM Endurance EE(Note 2) 50k writes

EEPROM Write Time tEW (Notes 1, 3, 4) 150 300 ms

EEPROM Transfer to RAM tER (Notes 1, 5) 1 ms

ALARM Output Active-Low Pulse

Width tSL (Note 1) 62.5 ms

ALARM Output Active-High Pulse

Width tSH (Note 1) 437.5 ms

ALARM Input Pulled Low

and Released Pulse Width tSPL (Note 1) 500 ms

SCL Clock Frequency fSCL

Fast mode 400 kHz

Standard mode 100

Bus Free Time Between a

STOP and START Condition tBUF

Fast mode 1.3 µs

Standard mode 4.7

Hold Time (Repeated)

START Condition (Note 6) tHD:STA

Fast mode 0.6 µs

Standard mode 4.0

Low Period of SCL tLOW

Fast mode 1.3 µs

Standard mode 4.7

High Period of SCL tHIGH

Fast mode 0.6 µs

Standard mode 4.0

Setup Time for a Repeated

START tSU:STA

Fast mode 0.6 µs

Standard mode 4.0

Data Hold Time (Notes 7, 8) tHD:DAT

Fast mode 0 µs

Standard mode 0

Data Setup Time (Note 9) tSU:DAT

Fast mode 100 ns

Standard mode 250

Rise Time of SDA and SCL

Signals (Note 10) tR

Fast mode 20 +

0.1CB

300

Standard mode 20 +

0.1CB

1000

Fall Time of SDA and SCL

Signals (Note 10) tF

Fast mode 20 +

0.1CB

300

Standard mode 20 +

0.1CB

300

Setup Time for STOP tSU:STO

Fast mode 0.6 µs

Standard mode 4.0

Input Capacitance CI/O (Note 1) 10 pF

Capacitive Load for Each

Bus Line CB(Note 10) 400 pF

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AC Electrical Characteristics

(VCC = 2.5V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.)

Note 1: Typical values are at TA = +25°C, VCC = 4.0V.

Note 2: The elapsed time and event counters are backed by three EEPROM arrays, which are used sequentially, allowing up to 3 x

EE. The configuration register, alarm trip-point register, and user memory use a single array, limiting them to one EE.

Note 3: A decoupling capacitor to supply high instantaneous currents during EEPROM writes is recommended. A typical value is

0.01μF. VCC must be maintained above VCC minimum, including transients, during EEPROM writes.

Note 4: VCC must be at or above 2.5V for tEW after the end of an event to ensure data transfer to the EEPROM.

Note 5: Reading data while the contents of EEPROM are transferred to RAM results in incorrect reads.

Note 6: After this period, the first clock pulse is generated.

Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal)

to bridge the undefined region of the falling edge of SCL.

Note 8: The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal.

Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must be met. This is

automatically the case if the device does not stretch the tLOW. If such a device does stretch tLOW, it must output the next

data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.

Note 10: CB—Total capacitance of one bus line in pF.

SCL

NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).

SDA

STOP START REPEATED

START

tBUF

tHD:STA

tHD:DAT tSU:DAT

tSU:STO

tHD:STA tSP

tSU:STA

tHIGH

tLOW

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Timing Diagram

PIN NAME FUNCTION

1 EVENT

Event Input. The EVENT pin is the input the DS1682 monitors to determine when an event occurs. When

the pin is pulled high, the contents of the EEPROM are transferred to the ETC and the oscillator starts.

The ETC begins to count in quarter-second increments. When the EVENT pin falls to logic 0, the event

counter increments, and the event counter, ETC, and user-memory data are stored in the EEPROM array.

When the EVENT pin changes states, the 2-wire bus is unavailable for communications for tEW (falling)

and tER (rising). The EVENT input is also deglitched (tG) to prevent short noise spikes from triggering an

event.

2, 7 N.C. No Connection. These pins are not connected internally.

3ALARM

Active-Low Alarm Output. The DS1682 monitors the values in the ETC for the programmed value in

the alarm register. When the ETC matches the alarm value, the alarm ag (AF) is set. Once set, the

alarm ag cannot be reset. See the operating descriptions for the AOS and AP bits for details about the

operation of the ALARM pin.

4 GND Ground

5 SCL 2-Wire Serial-Clock Input. The SCL pin is the serial-clock input for the 2-wire synchronous

communications channel. The SCL pin is an input that requires an external pullup resistor.

6 SDA 2-Wire Input/Output. The SDA pin is the data input/output signal for the 2-wire synchronous

communications channel. The SDA pin is an open-drain I/O, which requires an external pullup resistor.

8 VCC +2.5V to +5.5V Input Supply

EVENT +

N.C.

ALARM

5GND

VCC

N.C.

SDA

SCL

(150 mils)

TOP VIEW

DS1682

DS1682 Total-Elapsed-Time Recorder

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Pin Description

Pin Conguration

Figure 2. Total Run Time

DS1682

VCC

EVENT

TRIGGER SWITCH

LED

SCL

PUSHBUTTON

SWITCH

ALARM

SDAGND

0.01µF

Operation

The block diagram in Figure 1 shows the relationship

between the major functional blocks, the serial interface,

and the EEPROM memory section of the DS1682. Upon

power-up, the DS1682 transfers the contents of the

EEPROM into the counters and memory registers where

the data can be read and written through the serial inter-

face. The content of the counters and memory registers

are written into the EEPROM memory when the EVENT

pin transitions from a logic-high to a logic-low.

The DS1682 uses a calibrated, temperature-compensat-

ed RC time base to increment an ETC while an event

is active. When the event becomes active, the contents

of the nonvolatile EEPROM are transferred to the ETC

and event counter and the oscillator starts. As the event

continues, the ETC is incremented in quarter-second

increments. When the event becomes inactive, the event

counter is incremented and the contents of the ETC and

event counter are written to the nonvolatile EEPROM.

The ALARM output can be used to indicate when the ETC

has matched the value in the alarm register.

The DS1682 can be configured to prevent clearing the

alarm and the elapsed time and event counters.The user

memory can be separately write protected.

User-modified data is not stored in EEPROM until an

event becomes inactive.

Figure 2 shows the DS1682 measuring total run time and

operating from a battery with the alarm tied to an LED and

a pushbutton switch to trigger the alarm output.

Figure 3 shows the DS1682 in a total time-of-use applica-

tion where power may be removed at the same time as

the end of the event. The VCC slew rate at power-down is

fast with respect to tEW. A capacitor maintains VCC on the

DS1682 above 2.5V until the EEPROM write completes. A

Schottky diode blocks current from the capacitor to other

devices connected to VCC.

The VCC holding capacitor value of 30μF is calculated

using the maximum EEPROM write current and EEPROM

write time. This assumes that the VCC slew rate allows

time from EVENT trip point to VCC at 2.5V on the DS1682

is at least tEW.

Figure 4 shows the DS1682 in a total time-of-use applica-

tion with power that can be removed at the sametime as

the end of the event. In this application, the VCC slew rate

at power-down is slow with respect to tEW. The external

reset IC (DS1816) ends the event as VCC begins to drop.

VCC must remain above 2.5V until the end of tEW.

Figure 3. Total Time-of-Use Application with Fast VCC Slew Rate

DS1682

VCC

EVENT

LED

SCLALARM

SDAGND

0.01µF 30µF typ

VCC

Figure 4. Total Time-of-Use Application with Slow VCC Slew Rate

DS1682

VCC

ALARM

LED

SCLEVENT

SDAGND

0.01µF

RPU = tR/CBUS

RPU RPU

VCC

DS1816

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Table 1. Memory Map

ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION

00h 0 AF WDF WMDF AOS RE AP ECMSB Conguration

01h Low Byte

Low-Middle Byte

High-Middle Byte

High Byte

Alarm Register

02h

03h

04h

05h Low Byte

Low-Middle Byte

High-Middle Byte

High Byte

Elapsed Time

Counter (ETC)

06h

07h

08h

09h Low Byte

High Byte Event Counter

0Ah

0Bh Byte 1

User Memory

0Ch Byte 2

0Dh Byte 3

0Eh Byte 4

0Fh Byte 5

10h Byte 6

11h Byte 7

12h Byte 8

13h Byte 9

14h Byte 10

15h

Not Used (reads 00h) Not Used

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh Reset Command Reset Command

1Eh Write Disable Write Disable

1Fh Write Memory Disable Memory Disable

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Event Logging

When the DS1682 is powered up, the event time and

count values recorded in the EEPROM are transferred to

the ETC and event counter, and the device waits for an

event. When an event triggers the input by transitioning

the EVENT pin from a low to a high level, the following

occurs:

1) The RC oscillator starts.

2) The alarm, ETC, and event counter are transferred

from EEPROM to RAM.

3) Note: Reading the RAM during the transfer results in

invalid data.

4) After tES, the ETC increments. An event greater than

tG but less than tES increments the event counter, but

not the ETC (zero-length event).

5) The ETC increments every tEI. The ETC holds time in

quarter-second resolution.

6) When the EVENT pin goes low, the event counter

increments, the oscillator stops, and the ETC and

event counter are transferred to EEPROM. The 2-wire

bus is not available for tEW.

The ETC stops counting and does not roll over once

FFFFFFFFh, or approximately 34 years, is reached. See

Figure 5 for timing.

Device Setup

Once installed in a system, the DS1682 can be pro-

grammed to record events as required by the application,

and can be tested by generating events and monitoring

the results. Afterwards, it can be “locked” to prevent

alteration of the event and alarm registers and the alarm

condition.

The following is a typical sequence:

1) Write the configuration register, alarm registers, and

user memory to the desired values.

2) Write-protect the alarm, ETC, and event counter regis-

ters with the write disable command if needed.

3) Write-protect the user memory with the write-memory-

disable command, if needed.

4) Issue a reset (described in the Reset Command section).

The alarm, ETC and event counter registers, and user

memory, once locked, cannot be changed.

Upon reset, the ETC and event counter registers are

cleared. The device clears the RE bit, and the configu-

ration register becomes read-only. Additional resets are

ignored.

Figure 5. Event Input Timing

INTERNAL EVENT

CLOCK

tES

tEI

EVENT INPUT

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Alarm

The alarm register is a 32-bit register that holds time in

quarter-second resolution. When a nonzero number is

programmed into the alarm register, the ALARM func-

tion is enabled and the DS1682 monitors the values in

the ETC for the programmed value in the alarm register.

When the ETC matches the alarm value, the alarm flag

is set.

EEPROM Array

When power is applied, the contents of the EEPROM are

transferred to the configuration register, alarm register,

ETC, event counter, and user memory. When the event

pin goes low, VCC must remain above VCC minimum for

tEW to ensure the EEPROM is properly written.

The EEPROM array for the ETC and the event counter is

made up of three banks. Each bank can be written a maxi-

mum of 50k times. The device switches between banks

based upon the value in the event counter. Resetting the

event counter before the counter reaches 50,000 causes

additional writes to the first bank, which can allow writes

in excess of 50k. If the event counter is set to greater

than 50k or 100k prior to reset, the device stays on the

selected bank. This could result in writes in excess of 50k

to one bank.

The configuration and alarm registers and the user mem-

ory are held in one bank of EEPROM. Writes at the end

of an event only occur if the data has changed in one or

more of those registers.

User-modified data in any of the registers is stored in

EEPROM only if the data was written while an event was

active and is stored when the event ends.

Event Counter Register

This 17-bit event counter register set provides the total

number of data samples logged during the life of the prod-

uct up to 131,072 separate events. The event counter

consists of 2 bytes of memory in the memory map plus

the event counter MSB bit (ECMSB) in the configuration

counting stops.

Reset Command

If RE is set to a 1, a reset occurs when a reset command

is sent through the 2-wire bus. A reset command is issued

by writing 55h twice into memory location 1Dh. The writes

need not be consecutive. Cycling power on VCC prior to

the second write terminates the reset sequence.

Upon reset, the ETC and event counter registers are

cleared. The AF, RE, and ECMSB bits are cleared by the

device, and the configuration register becomes read-only.

The data are written to the EEPROM, and additional

resets are ignored.

When a reset command is issued, no additional command

should be issued during the EEPROM write time (tEW).

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Bit 6: Alarm Flag (AF). The alarm flag is set to a 1 when

the ETC value matches the alarm register. Once the AF

bit is set to a 1, it cannot be set to a 0. This bit is read-only.

Bit 5: Write Disable Flag (WDF). When the write disable

command is written to AAh twice at memory location 1Eh,

the WDF is set to a 1 and cannot be cleared or reset.

When WDF is set to a 1, the alarm, ETC, and event coun-

ter registers are read-only. This bit is read-only. The writes

need not be consecutive. Cycling power on VCC prior to

the second write terminates the reset sequence.

Bit 4: Write-Memory-Disable Flag (WMDF). When the

write-memory-disable command is written to F0h twice

at memory location 1Fh, the WMDF is set to a 1 and

cannot be reset or cleared. Once the WMDF is set to a

1, the 10-byte user memory becomes read-only. This bit

is read-only. The writes need not be consecutive. Cycling

power on VCC prior to the second write terminates the

reset sequence.

Bit 3: Alarm Output Select (AOS). If AOS is 0 and AF is

true, the DS1682 activates the ALARM output during an

event when AF becomes true. The DS1682 also activates

the ALARM output by pulling the pin low four times at

power-up, at the start and end of an event, or when the

ALARM pin is pulled low and released. This output mode

can be used to flash an LED or to communicate with

another device to indicate that an alarm has occurred. AP

has no affect on the output when AOS is 0.

If AOS is a 1 and AF is true, the ALARM output is constant

when the alarm is active. AP determines the polarity of

the output.

Bit 2: Reset Enable (RE). The reset enable bit allows the

device to be reset by enabling the reset command. The

sections of the DS1682 that are reset are then dependent

on the value in the WDF. With the WDF set to 0 and the

reset enable bit set to a 1, the reset command clears

the ETC, EEPROM, and event counter. When the reset

enable bit is set to a 0, the reset command is disabled.

Bit 1: Alarm Polarity (AP). When the alarm polarity bit

in the configuration register is set to 0, the ALARM output

is high impedance during the period that the value in the

ETC is less than the alarm register value. When the ETC

matches the alarm value, the ALARM pin is driven low.

If the AP bit is set to a 1, the ALARM output is driven

low during the period that the ETC is less than the alarm

value.

When the ETC matches the alarm value, the ALARM pin

becomes high impedance. The AP bit has no affect if AOS

is set to a 0.

Bit 0: Event Counter MSB (ECMSB). This bit is read-

only.

Configuration Register

Note: The configuration register is not stored in EEPROM until an event becomes inactive. RE does not need to be stored in

EEPROM to reset the device.

MSB LSB

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 AF WDF WMDF AOS RE AP ECMSB

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User Memory

There are 10 bytes of user-programmable, EEPROM

memory. Once the write-memory disable flag is set to

1, the memory becomes read-only. User memory is not

stored in EEPROM until an event becomes inactive.

2-Wire Serial Data Bus

The DS1682 supports a bidirectional, 2-wire bus and

data-transmission protocol. A device that sends data onto

the bus is defined as a transmitter and a device receiving

data, a receiver. The device that controls the message is

called a master, and the devices controlled by the master

are slaves. A master device that generates the serial clock

(SCL), controls the bus access, and generates the START

and STOP conditions must control the bus. The DS1682

operates as a slave on the 2-wire bus. Connections to

the bus are made through the open-drain I/O lines SDA

and SCL.

The following bus protocol has been defined (Figure 6):

●Data transfer can be initiated only when the bus is

not busy.

●During data transfer, the data line must remain stable

whenever the clock line is high. Changes in the data

line while the clock line is high are interpreted as

control signals.

Accordingly, the following bus conditions have been

defined:

Bus Not Busy: Both data and clock lines remain high.

Start Data Transfer: A change in the state of the data

line, from high to low, while the clock is high,

defines a START condition.

Stop Data Transfer: A change in the state of the data

line, from low to high, while the clock line is high, defines

the STOP condition.

Data Valid: The state of the data line represents valid

data when, after a START condition, the data line is stable

for the duration of the high period of the clock signal. The

data on the line must be changed during the low period of

the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

data bytes transferred between START and STOP condi-

tions are not limited, and are determined by the master

device. The information is transferred byte-wise and each

receiver acknowledges with a ninth bit. Within the bus

specifications a standard mode (100kHz clock rate) and a

fast mode (400kHz clock rate) are defined.

Acknowledge: Each receiving device, when addressed,

is obliged to generate an acknowledge after it receives

each byte. The master device must generate an extra

clock pulse, which is associated with this acknowledge bit.

A device that acknowledges must pull down the SDA line

during the acknowledge clock pulse in such a way that

the SDA line is stable low during the high period of the

acknowledge-related clock pulse. Of course, setup and

hold times must be considered. A master must signal an

end-of-data to the slave by not generating an acknowl-

edge bit on the last byte that has been clocked out of the

slave. In this case, the slave must leave the data line high

to enable the master to generate the STOP condition.

Figure 6. Timing Diagram: Data Transfer on 2-Wire Serial Bus

1SCL

MSB

SDA

START

CONDITION

SLAVE ADDRESS

26 7 8 83-89

ACK

R/W

DIRECTION

BIT

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

REPEATED IF MORE BYTES

ARE TRANSFERRED

STOP CONDITION

REPEATED

START CONDITION

ACK

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Depending upon the state of the R/W bit, two types of

data transfer are possible:

Data transfer from a master transmitter to a slave

receiver. The first byte transmitted by the master is the

slave address. Next follows a number of data bytes. The

slave returns an acknowledge bit after each received

byte.

Data transfer from a slave transmitter to a master

receiver. The master transmits the first byte (the slave

address). The slave then returns an acknowledge bit. Next

follows a number of data bytes transmitted by the slave to

the master. The master returns an acknowledge bit after

all received bytes other than the last byte. A “not acknowl-

edge” is returned at the end of the last received byte.

The master device generates all of the serial clock pulses

and the START and STOP conditions. A transfer is ended

with a STOP condition or with a repeated START condi-

tion. Since a repeated START condition is also the begin-

ning of the next serial transfer, the bus is not released.

Slave Receiver Mode (Write Mode): Serial data and

clock are received through SDA and SCL. After each byte

is received, the receiver transmits an acknowledge bit.

START and STOP conditions are recognized as the begin-

ning and end of a serial transfer. The slave address byte is

the first byte received after the master generates a START

condition. The address byte contains the 7-bit DS1682

address, which is 1101011 (D6h), followed by the direction

bit (R/W). The second byte from the master is the register

address. This sets the register pointer. The master then

transmits each byte of data, with the DS1682 acknowledg-

ing each byte received. The register pointer increments

after each byte is written. The master generates a STOP

condition to terminate the data write (Figure 7).

Slave Transmitter Mode (Read Mode): The first byte

is received and handled as in the slave receiver mode.

However, in this mode, the direction bit indicates that the

transfer direction is reversed. Serial data is transmitted on

SDA by the DS1682 while the serial clock is input on SCL.

The slave address byte is the first byte received after the

master generates a START condition. The address byte

contains the 7-bit DS1682 address, followed by the direc-

tion bit (R/W). After receiving a valid slave address byte

and direction bit, the DS1682 generates an acknowledge

on the SDA line. The DS1682 begins to transmit data on

each SCL pulse starting with the register address pointed

to by the register pointer. As the master reads each byte,

it must generate an acknowledge. The register pointer

increments after each byte is read. The DS1682 must

receive a “not acknowledge” on the last byte to end a

read (Figure 8).

Figure 7. Data Write—Slave Receiver Mode

Figure 8. Data Read—Slave Transmitter Mode

R/W

R/W – READ/WRITE OR DIRECTION BIT

S 1101011 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX P

DATA TRANSFERRED

(X + 1 BYTES + ACKNOWLEDGE)

SLAVE

ADDRESS

S – START

A – ACKNOWLEDGE

P – STOP

DATA (n) DATA (n + 1) DATA (n + x)

R/W

/A – NOT ACKNOWLEDGE

S 1101011 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX /A

DATA TRANSFERRED

(X + 1 BYTES + ACKNOWLEDGE)

SLAVE

ADDRESS

S – START

A – ACKNOWLEDGE

P – STOP

DATA (n + 1) DATA (n) DATA (n + 2) DATA (n + x)

R/W – READ/WRITE OR DIRECTION BIT

DS1682 Total-Elapsed-Time Recorder

with Alarm

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Note: All devices are specified over the -40°C to +85°C operating

range.

+Denotes a lead(Pb)-free/RoHS-compliant package.

T&R = Tape and reel.

PART PIN-PACKAGE TOP MARK

DS1682S+ 8 SO DS1682

DS1682S+T&R 8 SO DS1682

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

8 SO S8+5 21-0041 90-0096

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Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

Chip Information

PROCESS: CMOS

Ordering Information

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

1 11/13 Added the lead and soldering temperature information to the Absolute Maximum

Ratings section; updated the Ordering Information and Package Information tables 2, 14

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

DS1682 Total-Elapsed-Time Recorder

with Alarm

│

Revision History

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

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