E
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INTEL CONFIDENTIAL
(until publication date)
June 1997
Order Number 242323-004
n
Compatible with Large Software Base
−MS-DOS*, Windows*, OS/2*, UNIX*
n
32-Bit CPU with 64-Bit Data Bus
n
Superscalar Architecture
−Two Pipelined Integer Units Are
Capable of 2 Instructions/Clock
−Pipelined Floating Point Unit
n
Separate Code and Data Caches
−8K Code, 8K Writeback Data
−MESI Cache Protocol
n
Advanced Design Features
−Branch Prediction
−Virtual Mode Extensions
n
3.3V BiCMOS Silicon Technology
n
4M Pages for Increased TLB Hit Rate
n
IEEE 1149.1 Boundary Scan
n
Internal Error Detection Features
n
SL Enhanced Power Management
Features
−
System Management Mode
−
Clock Control
n
Fractional Bus Operation
−
75-MHz Core / 50-MHz Bus
The Pentium® processor is fully compatible with the entire installed base of applications for DOS*, Windows*,
OS/2*, and UNIX*, and all other software that runs on any earlier Intel 8086 family product. The Pentium
processor’s superscalar architecture can execute two instructions per clock cycle. Branch prediction and
separate caches also increase performance. The pipelined floating-point unit delivers workstation level
performanc e. Separate c ode and data c ac hes r educ e cac he c onflic ts w hile remaining s oftw are trans par ent. The
Pentium processor (610\75) has 3.3 million transistors, is built on Intel’s advanced 3.3V BiCMOS silicon
technology, and has full SL Enhanced power management features, including System Management Mode
(SMM) and cloc k control. The additional SL Enhanced features, 3.3V operation, and the TCP package, which
are not available in the Pentium processor (510\60, 567\66), make the Pentium processor (610\75) TCP ideal for
enabling mobile Pentium processor designs. The Pentium processor may contain design defects or errors
known as errata which may cause the produc t to deviate from published specifications. Current characterized
errata are available upon request.
PENTIUM® PROCESSOR at iCOMP® INDEX 610\75 MHz
PENTIUM® PROCESSOR (610\75) E
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CONTENTS
PAGE
1.0. INTRODUCTION................................................2
1.1. Pentium® Processor (610\75) SPGA
Specifications and Differences from the TCP
Package.............................................................2
2.0. MICROPROCESSOR ARCHITECTURE
OVERVIEW...........................................................3
2.1. Pentium® Processor Family Architecture........4
3.0. TCP PINOUT......................................................7
3.1. TCP Pinout and Pin Descriptions...................7
3.1.1. Pentium® Processor (610\75) TCP
PINOUT.........................................................7
3.1.2. PIN CROSS REFERENCE TABLE FOR
Pentium® Processor (610\75) TCP................8
3.2. Design Notes................................................10
3.3. Quick Pin Reference.....................................10
3.4. Pin Reference Tables...................................19
3.5. Pin Grouping According to Function.............22
4.0. Pentium® Processor (610\75) TCP
ELECTRICAL SPECIFICATIONS......................23
4.1. Maximum Ratings.........................................23
4.2. DC Specifications.........................................23
PAGE
4.3. AC Specifications..........................................25
4.3.1. POWER AND GROUND.......................25
4.3.2. DECOUPLING RECOMMENDATIONS25
4.3.3. CONNECTION SPECIFICATIONS ......26
4.3.4. AC TIMINGS FOR A 50-MHZ BUS.......26
4.4. I/O Buffer Models..........................................35
4.4.1. BUFFER MODEL PARAMETERS........38
4.4.2. SIGNAL QUALITY SPECIFICATIONS.39
4.4.2.1. Ringback.........................................40
4.4.2.2. Settling Time...................................40
5.0. Pentium® Processor (610\75) TCP
MECHANICAL SPECIFICATIONS.....................42
5.1. TCP Package Mechanical Diagrams............42
6.0. Pentium® Processor (610\75) TCP THERMAL
SPECIFICATIONS...............................................47
6.1. Measuring Thermal Values...........................47
6.2. Thermal Equations........................................47
6.3. TCP Thermal Characteristics........................47
6.4. PC Board Enhancements..............................47
6.4.1. STANDARD TEST BOARD
CONFIGURATION ......................................48
Information in this document is pr ovided in connection with Intel products . No license, expr ess or implied, by estoppel or otherwise, to any
intellectual property r ights is granted by this doc ument. Except as provided in Intel’s Terms and C onditions of Sale for s uch products , Intel
as s ume s no lia bilit y wha ts o ev er , and Intel disclaims any expres s or implied warranty, r elating to sale and/or us e of Intel products including
liability o r wa rr a ntie s r elat ing t o fit ne s s for a p ar tic u lar pu rp os e , me rc hantabilit y, or infr ingement of any patent, copy right or other intellectual
property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the abs ence or c haracteris tics of any featur es or instr uctions marked "reserv ed" or "undefined." Intel r eserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Pentium® processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect IL 60056-7641
or call 1-800-879-4683
or visit Intel’s website at http:\\www.intel.com
Copyright © Intel Corporation 1996, 1997.
* Third-party brands and names are the property of their respective owners.
PENTIUM® PROCESSOR (610\75)
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1.
0. INTRODUCTION
Intel is now manufacturing its latest version of the
Pentium® processor family that is designed
specifically for mobile systems, with a core
frequency of 75 MHz and a bus frequency of 50
MHz. The Pentium processor (610\75) is provided
in the TCP (Tape Carrier Package) and SPGA
packages, and has all of the advanced features of
the Pentium processor (735\90, 815\100) .
The new Pentium processor (610\75) TCP
package has several features which allow high-
performance notebooks to be designed with the
Pentium processor, including the following:
•TCP package dimensions are ideal for small
form-factor designs.
•The TCP package has superior thermal
resistance characteristics.
•3.3V VCC reduces power consumption by half
(in both the TCP and SPGA packages).
•The SL Enhanced feature set, which was
initially implemented in the Intel486™ CPU.
The architecture and internal features of the
Pentium processor (610\75) TCP and SPGA
packages are identical to those of the Pentium
processor (735\90, 815\100), although several
features have been eliminated for the Pentium
processor (610\75) TCP, as described in section
1.1.
This document should be used in conjunction with
the Pentium processor documents listed below.
List of related documents:
•Pentium® Processor Family Developer’s
Manual, Vol. 1 (Order Number: 241428)
•Pentium® Processor Family Developer’s
Manual, Vol. 3: Architecture and Programming
Manual (Order Number: 241430)
1.1.
Pentium® Processor (610\75)
SPGA Specifications and
Differences from the TCP
Package
This section provides references to the Pentium
processor (610\75) SPGA specifications and
describes the major differences between the
Pentium processor (610\75) SPGA and TCP
packages.
All Pentium processor (610\75) SPGA
specifications, with the exception of power
consumption, are identical to the Pentium
processor (735\90, 815\100) specifications
provided in the Pentium® Processor Family
Developer’s Manual, Volume 1. See Tables 8 and
11 in section 4.2 for the Pentium processor
(610\75) SPGA and TCP power specifications.
The following features have been eliminated for
the Pentium processor (610\75) TCP: the Upgrade
feature, the Dual Processing (DP) feature, and the
Master/Checker functional redundancy feature.
Table 1 lists the corresponding pins which exist on
the Pentium processor (610\75) SPGA but have
been removed on the Pentium processor (610\75)
TCP.
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Table 1. SPGA Signals Removed in TCP
Signal Function
ADSC# Additional Address Status. This signal is mainly used for large or standalone L2
cache memory subsystem support required for high-performance desktop or
server models.
BRDYC# Additional Burst Ready. This signal is mainly used for large or standalone L2
cache memory subsystem support required for high-performance desktop or
server models.
CPUTYP CPU Type. This signal is used for dual processing systems.
D/P# Dual/Primary processor identification. This signal is only used for an Upgrade
processor.
FRCMC# Functional Redundancy Checking. This signal is only used for error detection
via processor redundancy, and requires two Pentium processors
(master/checker).
PBGNT# Private Bus Grant. This signal is only used for dual processing systems.
PBREQ# Private Bus Request. This signal is used only for dual processing systems.
PHIT# Private Hit. This signal is only used for dual processing systems.
PHITM# Private Modified Hit. This signal is only used for dual processing systems.
The I/O buffer models provided in section 4.4 of this
document apply to both the Pentium processor
(610\75) TCP and SPGA packages, although the
capacitance (Cp) and inductance (Lp) parameter
values differ between the two packages. Also, the
thermal parameters, TCASE max and θCA, differ
between the TCP and SPGA packages. For
Pentium processor (610\75) SPGA values, refer to
Chapters 24 and 26 of the Pentium® Processor
Family Developer’s Manual, Volume 1 .
2.
0. MICROPROCESSOR
ARCHITECTURE OVERVIEW
The Pentium processor at iCOMP® rating 610\75
MHz extends the Intel Pentium family of
microprocessors. It is compatible with the 8086/88,
80286, Intel386™ DX CPU, Intel386 SX CPU,
Intel486™ DX CPU, Intel486 SX CPU, Intel486
DX2 CPUs, the Pentium processor at iCOMP Index
510\60 MHz and iCOMP Index 567\66 MHz, and
the Pentium processor at iCOMP Index 735\90
MHz and iCOMP Index 815\100 MHz.
The Pentium processor family consists of the new
Pentium processor at iCOMP rating 610\75 MHz,
described in this document, the original Pentium
processor (510\60, 567\66), and the Pentium
processor (735\90, 815\100). The name "Pentium
processor (610\75)" will be used in this document to
refer to the Pentium processor at iCOMP rating
610\75 MHz. "Pentium Processor" will be used in
this document to refer to the entire Pentium
processor family in general.
The Pentium processor family architecture contains
all of the features of the Intel486 CPU family, and
provides significant enhancements and additions
including the following:
•Superscalar Architecture
•Dynamic Branch Prediction
•Pipelined Floating-Point Unit
•Improved Instruction Execution Time
•Separate 8K Code and 8K Data Caches
•Writeback MESI Protocol in the Data Cache
•64-Bit Data Bus
•Bus Cycle Pipelining
•Address Parity
•Internal Parity Checking
•Execution Tracing
•Performance Monitoring
•IEEE 1149.1 Boundary Scan
•System Management Mode
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•Virtual Mode Extensions
2.1.
Pentium® Processor Family
Architecture
The application instruction set of the Pentium
processor family includes the complete Intel486
CPU family instruction set with extensions to
accommodate some of the additional functionality
of the Pentium processors. All application software
written for the Intel386 and Intel486 family
microprocessors will run on the Pentium processors
without modification. The on-chip memory
management unit (MMU) is completely compatible
with the Intel386 family and Intel486 family of
CPUs.
The Pentium processors implement several
enhancements to increase performance. The two
instruction pipelines and floating-point unit on
Pentium processors are capable of independent
operation. Each pipeline issues frequently used
instructions in a single clock. Together, the dual
pipes can issue two integer instructions in one
clock, or one floating point instruction (under certain
circumstances, two floating-point instructions) in
one clock.
Branch prediction is implemented in the Pentium
processors. To support this, Pentium processors
implement two prefetch buffers, one to prefetch
code in a linear fashion, and one that prefetches
code according to the BTB so the needed code is
almost always prefetched before it is needed for
execution.
The floating-point unit has been completely
redesigned over the Intel486 CPU. Faster
algorithms provide up to 10X speed-up for common
operations including add, multiply, and load.
Pentium processors include separate code and
data caches integrated on-chip to meet perform-
ance goals. Each cache is 8 Kbytes in size, with a
32-byte line size and is 2-way set associative. Each
cache has a dedicated Translation Lookaside Buffer
(TLB) to translate linear addresses to physical
addresses. The data cache is configurable to be
writeback or writethrough on a line-by-line basis
and follows the MESI protocol. The data cache tags
are triple ported to support two data transfers and
an inquire cycle in the same clock. The code cache
is an inherently write-protected cache. The code
cache tags are also triple ported to support
snooping and split line accesses. Individual pages
can be configured as cacheable or non-cacheable
by software or hardware. The caches can be
enabled or disabled by software or hardware.
The Pentium processors have increased the data
bus to 64 bits to improve the data transfer rate.
Burst read and burst writeback cycles are
supported by the Pentium processors. In addition,
bus cycle pipelining has been added to allow two
bus cycles to be in progress simultaneously. The
Pentium processors' Memory Management Unit
contains optional extensions to the architecture
which allow 2-Mbyte and 4-Mbyte page sizes.
The Pentium processors have added significant
data integrity and error detection capability. Data
parity checking is still supported on a byte-by-byte
basis. Address parity checking, and internal parity
checking features have been added along with a
new exception, the machine check exception.
As more and more functions are integrated on chip,
the complexity of board level testing is increased.
To address this, the Pentium processors have
increased test and debug capability. The Pentium
processors implement IEEE Boundary Scan
(Standard 1149.1). In addition, the Pentium
processors have specified 4 breakpoint pins that
correspond to each of the debug registers and
externally indicate a breakpoint match. Execution
tracing provides external indications when an
instruction has completed execution in either of the
two internal pipelines, or when a branch has been
taken.
System Management Mode (SMM) has been
implemented along with some extensions to the
SMM architecture. Enhancements to the virtual
8086 mode have been made to increase
performance by reducing the number of times it is
necessary to trap to a virtual 8086 monitor.
PENTIUM® PROCESSOR (610\75)
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Figure 1. Pentium® Processor Block Diagram
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The block diagram shows the two instruction
pipelines, the "u" pipe and the "v" pipe. The u-pipe
can execute all integer and floating point
instructions. The v-pipe can execute simple integer
instructions and the FXCH floating-point
instructions.
The separate caches are shown, the code cache
and data cache. The data cache has two ports, one
for each of the two pipes (the tags are triple ported
to allow simultaneous inquire cycles). The data
cache has a dedicated Translation Lookaside Buffer
(TLB) to translate linear addresses to the physical
addresses used by the data cache.
The code cache, branch target buffer and prefetch
buffers are responsible for getting raw instructions
into the execution units of the Pentium processor.
Instructions are fetched from the code cache or
from the external bus. Branch addresses are
remembered by the branch target buffer. The code
cache TLB translates linear addresses to physical
addresses used by the code cache.
The decode unit decodes the prefetched
instructions so the Pentium processor can execute
the instruction. The control ROM contains the
microcode which controls the sequence of
operations that must be performed to implement the
Pentium processor architecture. The control ROM
unit has direct control over both pipelines.
The Pentium processors contain a pipelined
floating-point unit that provides a significant
floating-point performance advantage over previous
generations of processors.
The architectural features introduced in this section
are more fully described in the Pentium® Processor
Family Developer’s Manual.
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3.
0. TCP PINOUT
3.1.
TCP Pinout and Pin Descriptions
3.1.1. Pentium® Processor (610\75) TCP PINOUT
Figure 2. Pentium® Processor (610\75) TCP Pinout
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3.1.2. PIN CROSS REFERENCE TABLE FOR Pentium® Processor (610\75) TCP
Table 2. TCP Pin Cross Reference by Pin Name
Address
A3 219 A9 234 A15 251 A21 200 A27 208
A4 222 A10 237 A16 254 A22 201 A28 211
A5 223 A11 238 A17 255 A23 202 A29 212
A6 227 A12 242 A18 259 A24 205 A30 213
A7 228 A13 245 A19 262 A25 206 A31 214
A8 231 A14 248 A20 265 A26 207
Data
D0 152 D13 132 D26 107 D39 87 D52 62
D1 151 D14 131 D27 106 D40 83 D53 61
D2 150 D15 128 D28 105 D41 82 D54 56
D3 149 D16 126 D29 102 D42 81 D55 55
D4 146 D17 125 D30 101 D43 78 D56 53
D5 145 D18 122 D31 100 D44 77 D57 48
D6 144 D19 121 D32 96 D45 76 D58 47
D7 143 D20 120 D33 95 D46 75 D59 46
D8 139 D21 119 D34 94 D47 72 D60 45
D9 138 D22 116 D35 93 D48 70 D61 40
D10 137 D23 115 D36 90 D49 69 D62 39
D11 134 D24 113 D37 89 D50 64 D63 38
D12 133 D25 108 D38 88 D51 63
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Table 2. TCP Pin Cross Reference by Pin Name (Contd.)
Control
A20M# 286 BREQ 312 HITM# 293 PM1/BP1 29
ADS# 296 BUSCHK# 288 HLDA 311 PRDY 318
AHOLD 14 CACHE# 21 HOLD 4PWT 299
AP 308 D/C# 298 IERR# 34 R/S# 198
APCHK# 315 DP0 140 IGNNE# 193 RESET 270
BE0# 285 DP1 127 INIT 192 SCYC 273
BE1# 284 DP2 114 INTR/LINT0 197 SMI# 196
BE2# 283 DP3 99 INV 15 SMIACT# 319
BE3# 282 DP4 84 KEN# 13 TCK 161
BE4# 279 DP5 71 LOCK# 303 TDI 163
BE5# 278 DP6 54 M/IO# 22 TDO 162
BE6# 277 DP7 37 NA# 8TMS 164
BE7# 276 EADS# 297 NMI/LINT1 199 TRST# 167
BOFF# 9EWBE# 16 PCD 300 W/R# 289
BP2 28 FERR# 31 PCHK# 316 WB/WT# 5
BP3 25 FLUSH# 287 PEN# 191
BRDY# 10 HIT# 292 PM0/BP0 30
APIC Clock Control
PICCLK 155 PICD1 158 BF 186 STPCLK# 181
PICD0 156
[APICEN]
CLK 272
[DPEN#]
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Table 2. TCP Pin Cross Reference by Pin Name (Contd.)
Vcc
1*
2
6*
11*
17*
19
23
27*
33*
35
41*
43
49*
51
57*
59
65*
67
73
79
85
91
97
103
109
111*
117
123
129
135
141
147
153*
157*
160
165*
168*
170*
172*
174*
177*
178
180*
183*
188*
190*
195*
204
210
216
217*
221
225*
226
230
232*
236
240*
241
243*
247
249*
253
257*
258
260*
264
266*
268*
275
281
291
295
301
304*
306
309*
313
317*
Vss
3
7
12
18
20
24
26
32
36
42
44
50
52
58
60
66
68
74
80
86
92
98
104
110
112
118
124
130
136
142
148
154
159
166
169
171
173
176
179
182
187
189
194
203
209
215
218
220
224
229
233
235
239
244
246
250
252
256
261
263
267
269
274
280
290
294
302
305
307
310
314
320
NC
175 184 185 271
NOTE:
*These Vcc pins are 3.3V supplies for the Pentium processor (610\75) TCP but will be lower voltage pins on future offerings of
this microprocessor family. All other Vcc pins will remain at 3.3V.
3.2.
Design Notes
For reliable operation, always connect unused
inputs to an appropriate signal level. Unused active
low inputs should be connected to Vcc. Unused
active HIGH inputs should be connected to GND
(Vss).
No Connect (NC) pins must remain unconnected.
Connection of NC pins may result in component
failure or incompatibility with processor steppings.
3.3.
Quick Pin Reference
This section gives a brief functional description of
each of the pins. For a detailed description, see the
"Hardware Interface" chapter in the Pentium®
Processor Family Developer’s Manual, Volume 1.
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Note that all input pins must meet their AC/DC
specifications to guarantee proper functional
behavior.
The # symbol at the end of a signal name indicates
that the active, or asserted state occurs when the
signal is at a low voltage. When a # symbol is not
present after the signal name, the signal is active,
or asserted at the high voltage level.
Table 3. Quick Pin Reference
Symbol Type Name and Function
A20M# IWhen the address bit 20 mask pin is asserted, the Pentium processor
(610\75) emulates the address wraparound at 1 Mbyte which occurs on the
8086. When A20M# is asserted, the Pentium processor (610\75) masks
physical address bit 20 (A20) before performing a lookup to the internal caches
or driving a memory cycle on the bus. The effect of A20M# is undefined in
protected mode. A20M# must be asserted only when the processor is in real
mode.
A31-A3 I/O As outputs, the address lines of the processor along with the byte enables
define the physical area of memory or I/O accessed. The external system
drives the inquire address to the processor on A31-A5.
ADS# OThe address status indicates that a new valid bus cycle is currently being
driven by the Pentium processor (610\75) .
AHOLD IIn response to the assertion of address hold, the Pentium processor (610\75)
will stop driving the address lines (A31-A3), and AP in the next clock. The rest
of the bus will remain active so data can be returned or driven for previously
issued bus cycles.
AP I/O Address parity is driven by the Pentium processor (610\75) with even parity
information on all Pentium processor (610\75) generated cycles in the same
clock that the address is driven. Even parity must be driven back to the
Pentium processor (610\75) during inquire cycles on this pin in the same clock
as EADS# to ensure that correct parity check status is indicated by the Pentium
processor (610\75).
APCHK# OThe address parity check status pin is asserted two clocks after EADS# is
sampled active if the Pentium processor (610\75) has detected a parity error on
the address bus during inquire cycles. APCHK# will remain active for one clock
each time a parity error is detected.
[APICEN]
PICD1 IThe Advanced Programmable Interrupt Controller Enable pin enables or
disables the on-chip APIC interrupt controller. If sampled high at the falling
edge of RESET, the APIC is enabled. APICEN shares a pin with the
Programmable Interrupt Controller Data 1 signal.
BE7#-BE5#
BE4#-BE0# O
I/O The byte enable pins are used to determine which bytes must be written to
external memory, or which bytes were requested by the CPU for the current
cycle. The byte enables are driven in the same clock as the address lines
(A31-3).
The lower four byte enables (BE3#-BE0#) are used on the Pentium processor
(610\75) as APIC ID inputs and are sampled at RESET.
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Table 3. Quick Pin Reference (Contd.)
Symbol Type Name and Function
[BF] I Bus Frequency determines the bus-to-core frequency ratio. BF is sampled at
RESET, and cannot be changed until another non-warm ( 1 ms) assertion of
RESET. Additionally, BF must not change values while RESET is active. For
proper operation of the Pentium processor (610\75) this pin should be strapped
high or low. When BF is strapped to V
cc
, the processor will operate at a 2/3
bus/core frequency ratio. When BF is strapped to V
ss
, the processor will
operate at a 1/2 bus/core frequency ratio. If BF is left floating, the Pentium
processor (610\75) defaults to a 2/3 bus ratio. Note the Pentium processor
(610\75) will not operate at a 1/2 bus/core frequency ratio.
BOFF# IThe backoff input is used to abort all outstanding bus cycles that have not yet
completed. In response to BOFF#, the Pentium processor (610\75) will float all
pins normally floated during bus hold in the next clock. The processor remains
in bus hold until BOFF# is negated, at which time the Pentium processor
(610\75) restarts the aborted bus cycle(s) in their entirety.
BP[3:2]
PM/BP[1:0]
OThe breakpoint pins (BP3-0) correspond to the debug registers, DR3-DR0.
These pins externally indicate a breakpoint match when the debug registers are
programmed to test for breakpoint matches.
BP1 and BP0 are multiplexed with the performance monitoring pins (PM1
and PM0). The PB1 and PB0 bits in the Debug Mode Control Register
determine if the pins are configured as breakpoint or performance monitoring
pins. The pins come out of RESET configured for performance monitoring.
BRDY# IThe burst ready input indicates that the external system has presented valid
data on the data pins in response to a read or that the external system has
accepted the Pentium processor (610\75) data in response to a write request.
This signal is sampled in the T2, T12 and T2P bus states.
BREQ OThe bus request output indicates to the external system that the Pentium
processor (610\75) has internally generated a bus request. This signal is
always driven whether or not the Pentium processor (610\75) is driving its bus.
BUSCHK# IThe bus check input allows the system to signal an unsuccessful completion
of a bus cycle. If this pin is sampled active, the Pentium processor (610\75) will
latch the address and control signals in the machine check registers. If, in
addition, the MCE bit in CR4 is set, the Pentium processor (610\75) will vector
to the machine check exception.
CACHE# OFor Pentium processor (610\75)-initiated cycles the cache pin indicates internal
cacheability of the cycle (if a read), and indicates a burst writeback cycle (if a
write). If this pin is driven inactive during a read cycle, the Pentium processor
(610\75) will not cache the returned data, regardless of the state of the KEN#
pin. This pin is also used to determine the cycle length (number of transfers in
the cycle).
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Table 3. Quick Pin Reference (Contd.)
Symbol Type Name and Function
CLK IThe clock input provides the fundamental timing for the Pentium processor
(610\75). Its frequency is the operating frequency of the Pentium processor
(610\75) external bus and requires TTL levels. All external timing parameters
except TDI, TDO, TMS, TRST#, and PICD0-1 are specified with respect to the
rising edge of CLK.
D/C# OThe data/code output is one of the primary bus cycle definition pins. It is driven
valid in the same clock as the ADS# signal is asserted. D/C# distinguishes
between data and code or special cycles.
D63-D0 I/O These are the 64 data lines for the processor. Lines D7-D0 define the least
significant byte of the data bus; lines D63-D56 define the most significant byte
of the data bus. When the CPU is driving the data lines, they are driven during
the T2, T12, or T2P clocks for that cycle. During reads, the CPU samples the
data bus when BRDY# is returned.
DP7-DP0 I/O These are the data parity pins for the processor. There is one for each byte of
the data bus. They are driven by the Pentium processor (610\75) with even
parity information on writes in the same clock as write data. Even parity
information must be driven back to the Pentium processor (610\75) on these
pins in the same clock as the data to ensure that the correct parity check status
is indicated by the Pentium processor (610\75). DP7 applies to D63-D56; DP0
applies to D7-D0.
[DPEN#]
PICD0
I/O Dual processing enable is an output of the Dual processor and an input of the
Primary processor. The Dual processor drives DPEN# low to the Primary
processor at RESET to indicate that the Primary processor should enable dual
processor mode. Since the dual processing feature is not supported on the
Pentium processor (610\75) TCP package, DPEN# should never be asserted
(low) at RESET. DPEN# shares a pin with PICD0.
EADS# IThis signal indicates that a valid external address has been driven onto the
Pentium processor (610\75) address pins to be used for an inquire cycle.
EWBE# IThe external write buffer empty input, when inactive (high), indicates that a
write cycle is pending in the external system. When the Pentium processor
(610\75) generates a write, and EWBE# is sampled inactive, the Pentium
processor (610\75) will hold off all subsequent writes to all E- or M-state lines in
the data cache until all write cycles have completed, as indicated by EWBE#
being active.
FERR# OThe floating point error pin is driven active when an unmasked floating point
error occurs. FERR# is similar to the ERROR# pin on the Intel387™ math
coprocessor. FERR# is included for compatibility with systems using DOS-type
floating point error reporting.
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Table 3. Quick Pin Reference (Contd.)
Symbol Type Name and Function
FLUSH# IWhen asserted, the cache flush input forces the Pentium processor (610\75)
to write back all modified lines in the data cache and invalidate its internal
caches. A Flush Acknowledge special cycle will be generated by the Pentium
processor (610\75) indicating completion of the writeback and invalidation.
If FLUSH# is sampled low when RESET transitions from high to low, tristate
test mode is entered.
HIT# OThe hit indication is driven to reflect the outcome of an inquire cycle. If an
inquire cycle hits a valid line in either the Pentium processor (610\75) data or
instruction cache, this pin is asserted two clocks after EADS# is sampled
asserted. If the inquire cycle misses the Pentium processor (610\75) cache,
this pin is negated two clocks after EADS#. This pin changes its value only as a
result of an inquire cycle and retains its value between the cycles.
HITM# OThe hit to a modified line output is driven to reflect the outcome of an inquire
cycle. It is asserted after inquire cycles which resulted in a hit to a modified line
in the data cache. It is used to inhibit another bus master from accessing the
data until the line is completely written back.
HLDA OThe bus hold acknowledge pin goes active in response to a hold request
driven to the processor on the HOLD pin. It indicates that the Pentium
processor (610\75) has floated most of the output pins and relinquished the bus
to another local bus master. When leaving bus hold, HLDA will be driven
inactive and the Pentium processor (610\75) will resume driving the bus. If the
Pentium processor (610\75) has a bus cycle pending, it will be driven in the
same clock that HLDA is de-asserted.
HOLD IIn response to the bus hold request, the Pentium processor (610\75) will float
most of its output and input/output pins and assert HLDA after completing all
outstanding bus cycles. The Pentium processor (610\75) will maintain its bus
in this state until HOLD is de-asserted. HOLD is not recognized during LOCK
cycles. The Pentium processor (610\75) will recognize HOLD during reset.
IERR# OThe internal error pin is used to indicate internal parity errors. If a parity error
occurs on a read from an internal array, the Pentium processor (610\75) will
assert the IERR# pin for one clock and then shutdown.
IGNNE# IThis is the ignore numeric error input. This pin has no effect when the NE bit
in CR0 is set to 1. When the CR0.NE bit is 0, and the IGNNE# pin is asserted,
the Pentium processor (610\75) will ignore any pending unmasked numeric
exception and continue executing floating-point instructions for the entire
duration that this pin is asserted. When the CR0.NE bit is 0, IGNNE# is not
asserted, a pending unmasked numeric exception exists (SW.ES = 1), and the
floating-point instruction is one of FINIT, FCLEX, FSTENV, FSAVE, FSTSW,
FSTCW, FENI, FDISI, or FSETPM, the Pentium processor (610\75) will
execute the instruction in spite of the pending exception. When the CR0.NE bit
is 0, IGNNE# is not asserted, a pending unmasked numeric exception exists
(SW.ES = 1), and the floating-point instruction is one other than FINIT, FCLEX,
FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM, the Pentium
processor (610\75) will stop execution and wait for an external interrupt.
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Table 3. Quick Pin Reference (Contd.)
Symbol Type Name and Function
INIT IThe Pentium processor (610\75) initialization input pin forces the Pentium
processor (610\75) to begin execution in a known state. The processor state
after INIT is the same as the state after RESET except that the internal caches,
write buffers, and floating point registers retain the values they had prior to
INIT. INIT may NOT be used in lieu of RESET after power up.
If INIT is sampled high when RESET transitions from high to low, the Pentium
processor (610\75) will perform built-in self test prior to the start of program
execution.
INTR / LINT0 IAn active maskable interrupt input indicates that an external interrupt has
been generated. If the IF bit in the EFLAGS register is set, the Pentium
processor (610\75) will generate two locked interrupt acknowledge bus cycles
and vector to an interrupt handler after the current instruction execution is
completed. INTR must remain active until the first interrupt acknowledge cycle
is generated to assure that the interrupt is recognized.
If the local APIC is enabled, this pin becomes local interrupt 0.
INV IThe invalidation input determines the final cache line state (S or I) in case of
an inquire cycle hit. It is sampled together with the address for the inquire
cycle in the clock EADS# is sampled active.
KEN# IThe cache enable pin is used to determine whether the current cycle is
cacheable or not and is consequently used to determine cycle length. When the
Pentium processor (610\75) generates a cycle that can be cached (CACHE#
asserted) and KEN# is active, the cycle will be transformed into a burst line fill
cycle.
LINT0/INTR IIf the APIC is enabled, this pin is local interrupt 0. If the APIC is disabled, this
pin is interrupt.
LINT1/NMI IIf the APIC is enabled, this pin is local interrupt 1. If the APIC is disabled, this
pin is non-maskable interrupt.
LOCK# OThe bus lock pin indicates that the current bus cycle is locked. The Pentium
processor (610\75) will not allow a bus hold when LOCK# is asserted (but
AHOLD and BOFF# are allowed). LOCK# goes active in the first clock of the
first locked bus cycle and goes inactive after the BRDY# is returned for the last
locked bus cycle. LOCK# is guaranteed to be de-asserted for at least one
clock between back-to-back locked cycles.
M/IO# OThe memory/input-output is one of the primary bus cycle definition pins. It is
driven valid in the same clock as the ADS# signal is asserted. M/IO#
distinguishes between memory and I/O cycles.
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Table 3. Quick Pin Reference (Contd.)
Symbol Type Name and Function
NA# IAn active next address input indicates that the external memory system is
ready to accept a new bus cycle although all data transfers for the current cycle
have not yet completed. The Pentium processor (610\75) will issue ADS# for a
pending cycle two clocks after NA# is asserted. The Pentium processor
(610\75) supports up to 2 outstanding bus cycles.
NMI/LINT1 IThe non-maskable interrupt request signal indicates that an external non-
maskable interrupt has been generated.
If the local APIC is enabled, this pin becomes local interrupt 1.
PCD OThe page cache disable pin reflects the state of the PCD bit in CR3, the Page
Directory Entry, or the Page Table Entry. The purpose of PCD is to provide an
external cacheability indication on a page-by-page basis.
PCHK# OThe parity check output indicates the result of a parity check on a data read. It
is driven with parity status two clocks after BRDY# is returned. PCHK#
remains low one clock for each clock in which a parity error was detected.
Parity is checked only for the bytes on which valid data is returned.
PEN# IThe parity enable input (along with CR4.MCE) determines whether a machine
check exception will be taken as a result of a data parity error on a read cycle.
If this pin is sampled active in the clock a data parity error is detected, the
Pentium processor (610\75) will latch the address and control signals of the
cycle with the parity error in the machine check registers. If, in addition, the
machine check enable bit in CR4 is set to "1", the Pentium processor (610\75)
will vector to the machine check exception before the beginning of the next
instruction.
PICCLK IThe APIC interrupt controller serial data bus clock is driven into the
programmable interrupt controller clock input of the Pentium processor
(610\75).
PICD0-1
[DPEN#]
[APICEN]
I/O Programmable interrupt controller data lines 0-1 of the Pentium processor
(610\75) comprise the data portion of the APIC 3-wire bus. They are open-
drain outputs that require external pull-up resistors. These signals share pins
with DPEN# and APICEN.
PM/BP[1:0] OThese pins function as part of the performance monitoring feature.
The breakpoint 1-0 pins are multiplexed with the performance monitoring 1 -0
pins. The PB1 and PB0 bits in the Debug Mode Control Register determine if
the pins are configured as breakpoint or performance monitoring pins. The pins
come out of RESET configured for performance monitoring.
PRDY OThe probe ready output pin indicates that the processor has stopped normal
execution in response to the R/S# pin going active, or Probe Mode being
entered.
PWT OThe page writethrough pin reflects the state of the PWT bit in CR3, the page
directory entry, or the page table entry. The PWT pin is used to provide an
external writeback indication on a page-by-page basis.
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Table 3. Quick Pin Reference (Contd.)
Symbol Type Name and Function
R/S# IThe run / stop input is an asynchronous, edge-sensitive interrupt used to stop
the normal execution of the processor and place it into an idle state. A high to
low transition on the R/S# pin will interrupt the processor and cause it to stop
execution at the next instruction boundary.
RESET IRESET forces the Pentium processor (610\75) to begin execution at a known
state. All the Pentium processor (610\75) internal caches will be invalidated
upon the RESET. Modified lines in the data cache are not written back.
FLUSH# and INIT are sampled when RESET transitions from high to low to
determine if tristate test mode will be entered, or if BIST will be run.
SCYC OThe split cycle output is asserted during misaligned LOCKed transfers to
indicate that more than two cycles will be locked together. This signal is defined
for locked cycles only. It is undefined for cycles which are not locked.
SMI# IThe system management interrupt causes a system management interrupt
request to be latched internally. When the latched SMI# is recognized on an
instruction boundary, the processor enters System Management Mode.
SMIACT# OAn active system management interrupt active output indicates that the
processor is operating in System Management Mode.
STPCLK# IAssertion of the stop clock input signifies a request to stop the internal clock of
the Pentium processor (610\75) thereby causing the core to consume less
power. When the CPU recognizes STPCLK#, the processor will stop execution
on the next instruction boundary, unless superseded by a higher priority
interrupt, and generate a Stop Grant Acknowledge cycle. When STPCLK# is
asserted, the Pentium processor (610\75) will still respond to external snoop
requests.
TCK IThe testability clock input provides the clocking function for the Pentium
processor (610\75) boundary scan in accordance with the IEEE Boundary Scan
interface (Standard 1149.1). It is used to clock state information and data into
and out of the Pentium processor (610\75) during boundary scan.
TDI IThe test data input is a serial input for the test logic. TAP instructions and
data are shifted into the Pentium processor (610\75) on the TDI pin on the
rising edge of TCK when the TAP controller is in an appropriate state.
TDO OThe test data output is a serial output of the test logic. TAP instructions and
data are shifted out of the Pentium processor (610\75) on the TDO pin on
TCK's falling edge when the TAP controller is in an appropriate state.
TMS IThe value of the test mode select input signal sampled at the rising edge of
TCK controls the sequence of TAP controller state changes.
TRST# IWhen asserted, the test reset input allows the TAP controller to be
asynchronously initialized.
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Table 3. Quick Pin Reference (Contd.)
Symbol Type Name and Function
Vcc IThe Pentium processor (610\75) has 79 3.3V power inputs.
Vss IThe Pentium processor (610\75) has 72 ground inputs.
W/R# OWrite/read is one of the primary bus cycle definition pins. It is driven valid in
the same clock as the ADS# signal is asserted. W/R# distinguishes between
write and read cycles.
WB/WT# IThe writeback/writethrough input allows a data cache line to be defined as
writeback or writethrough on a line-by-line basis. As a result, it determines
whether a cache line is initially in the S or E state in the data cache.
3.4.
Pin Reference Tables
Table 4. Output Pins
Name Active Level When Floated
ADS# Low Bus Hold, BOFF#
APCHK# Low
BE7#-BE5# Low Bus Hold, BOFF#
BREQ High
CACHE# Low Bus Hold, BOFF#
FERR# Low
HIT# Low
HITM# Low
HLDA High
IERR# Low
LOCK# Low Bus Hold, BOFF#
M/IO#, D/C#, W/R# n/a Bus Hold, BOFF#
PCHK# Low
BP3-2, PM1/BP1, PM0/BP0 High
PRDY High
PWT, PCD High Bus Hold, BOFF#
SCYC High Bus Hold, BOFF#
SMIACT# Low
TDO n/a All states except Shift-DR and Shift-IR
NOTE:
All output and input/output pins are floated during tristate test mode (except TDO).
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Table 5. Input Pins
Name
Active Level
Synchronous/
Asynchronous
Internal resistor
Qualified
A20M# Low Asynchronous
AHOLD High Synchronous
BF High Synchronous/RESET Pullup
BOFF# Low Synchronous
BRDY# Low Synchronous Bus State T2, T12, T2P
BUSCHK# Low Synchronous Pullup BRDY#
CLK n/a
EADS# Low Synchronous
EWBE# Low Synchronous BRDY#
FLUSH# Low Asynchronous
HOLD High Synchronous
IGNNE# Low Asynchronous
INIT High Asynchronous
INTR High Asynchronous
INV High Synchronous EADS#
KEN# Low Synchronous First BRDY#/NA#
NA# Low Synchronous Bus State T2,TD,T2P
NMI High Asynchronous
PEN# Low Synchronous BRDY#
PICCLK High Asynchronous Pullup
R/S# n/a Asynchronous Pullup
RESET High Asynchronous
SMI# Low Asynchronous Pullup
STPCLK# Low Asynchronous Pullup
TCK n/a Pullup
TDI n/a Synchronous/TCK Pullup TCK
TMS n/a Synchronous/TCK Pullup TCK
TRST# Low Asynchronous Pullup
WB/WT# n/a Synchronous First BRDY#/NA#
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Table 6. Input/Output Pins
Name
Active
Level
When Floated
Qualified
(when an input)
Internal
Resistor
A31-A3 n/a Address Hold, Bus Hold, BOFF# EADS#
AP n/a Address Hold, Bus Hold, BOFF# EADS#
BE4#-BE0# Low Bus Hold, BOFF# RESET Pulldown*
D63-D0 n/a Bus Hold, BOFF# BRDY#
DP7-DP0 n/a Bus Hold, BOFF# BRDY#
PICD0[DPEN#] Pullup
PICD1[APICEN] Pulldown
NOTES:
All output and input/output pins are floated during tristate test mode (except TDO).
*BE3#-BE0# have pulldowns during RESET only.
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3.5.
Pin Grouping According to Function
Table 7 organizes the pins with respect to their function.
Table 7. Pin Functional Grouping
Function Pins
Clock CLK
Initialization RESET, INIT
Address Bus A31-A3, BE7# - BE0#
Address Mask A20M#
Data Bus D63-D0
Address Parity AP, APCHK#
APIC Support PICCLK, PICD0-1
Data Parity DP7-DP0, PCHK#, PEN#
Internal Parity Error IERR#
System Error BUSCHK#
Bus Cycle Definition M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK#
Bus Control ADS#, BRDY#, NA#
Page Cacheability PCD, PWT
Cache Control KEN#, WB/WT#
Cache Snooping/Consistency AHOLD, EADS#, HIT#, HITM#, INV
Cache Flush FLUSH#
Write Ordering EWBE#
Bus Arbitration BOFF#, BREQ, HOLD, HLDA
Interrupts INTR, NMI
Floating Point Error Reporting FERR#, IGNNE#
System Management Mode SMI#, SMIACT#
TAP Port TCK, TMS, TDI, TDO, TRST#
Breakpoint/Performance Monitoring PM0/BP0, PM1/BP1, BP3-2
Clock Control STPCLK#
Probe Mode R/S#, PRDY
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4.
0. Pentium® Processor (610\75) TCP
ELECTRICAL SPECIFICATIONS
4.1.
Maximum Ratings
The following values are stress ratings only.
Functional operation at the maximum ratings is not
implied or guaranteed. Functional operating
conditions are given in the AC and DC specification
tables.
Extended exposure to the maximum ratings may
affect device reliability. Furthermore, although the
Pentium processor (610\75) contains protective
circuitry to resist damage from static electric
discharge, always take precautions to avoid high
static voltages or electric fields.
Case temperature under bias .........−65°C to 110°C
Storage temperature.......................−65°C to 150°C
3V Supply voltage
with respect to Vss...........................−0.5V to +4.6V
3V Only Buffer DC Input
Voltage....−0.5V to Vcc + 0.5; not to exceed 4.6V (2)
5V Safe Buffer
DC Input Voltage .........................−0.5V to 6.5V (1,3)
NOTES:
1. Applies to CLK and PICCLK.
2. Applies to all Pentium processor (610\75) inputs except
CLK and PICCLK.
3. See Table 9.
WARNING
Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent
damage. These are stress ratings only.
Operation beyond the "Operating Conditions"
is not recommended and extended exposure
beyond the "Operating Conditions" may
affect device reliability.
4.2.
DC Specifications
Tables 8, 9, and 10 list the DC specifications which
apply to the Pentium processor (610\75). The
Pentium processor (610\75) is a 3.3V part
internally. The CLK and PICCLK inputs may be a
3.3V or 5V inputs. Since the 3.3V (5V safe) input
levels defined in Table 9 are the same as the 5V
TTL levels, the CLK and PICCLK inputs are
compatible with existing 5V clock drivers. The
power dissipation specification in Table 11 is
provided for design of thermal solutions during
operation in a sustained maximum level. This is the
worst-case power the device would dissipate in a
system for a sustained period of time. This number
is used for design of a thermal solution for the
device.
Table 8. 3.3V DC Specifications
TCASE = 0 to 95 °C; Vcc = 3.3V ±5%
Symbol Parameter Min Max Unit Notes
VIL3 Input Low Voltage −0.3 0.8 VTTL Level (3)
VIH3 Input High Voltage 2.0 Vcc+0.3 VTTL Level (3)
VOL3 Output Low Voltage 0.4 VTTL Level (1) (3)
VOH3 Output High Voltage 2.4 VTTL Level (2) (3)
ICC3 Power Supply Current 2650 mA @75 MHz (4)
NOTES:
1. Parameter measured at 4 mA.
2. Parameter measured at 3 mA.
3. 3.3V TTL levels apply to all signals except CLK and PICCLK.
4. This value should be used for power supply design. It was determined using a worst-case instruction mix and V cc + 5%.
Power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current
changes occurring during transitions from stop clock to full active modes. For more information, refer to section 4.3.2.
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Table 9. 3.3V (5V Safe) DC Specifications
Symbol Parameter Min Max Unit Notes
VIL5Input Low Voltage −0.3 0.8 VTTL Level (1)
VIH5Input High Voltage 2.0 5.55 VTTL Level (1)
NOTES:
1.Applies to CLK and PICCLK only.
Table 10. Input and Output Characteristics
Symbol Parameter Min Max Unit Notes
CIN Input Capacitance 15 pF (4)
COOutput Capacitance 20 pF (4)
CI/O I/O Capacitance 25 pF (4)
CCLK CLK Input Capacitance 15 pF (4)
CTIN Test Input Capacitance 15 pF (4)
CTOUT Test Output Capacitance 20 pF (4)
CTCK Test Clock Capacitance 15 pF (4)
ILI Input Leakage Current ±15 µA0 < VIN < VCC3 (1)
ILO Output Leakage Current ±15 µA0 < VIN < VCC3 (1)
IIH Input Leakage Current 200 µA VIN = 2.4V (3)
IIL Input Leakage Current −400 µA VIN = 0.4V (2)
NOTES:
1. This parameter is for input without pull up or pull down.
2. This parameter is for input with pull up.
3. This parameter is for input with pull down.
4. Guaranteed by design.
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Table 11. Power Dissipation Requirements for Thermal Solution Design
Parameter Typical(1) Max(2) Unit Notes
Active Power Dissipation 3-4 8.0 Watts @ 75 MHz
Stop Grant and Auto Halt
Powerdown Power Dissipation 1.2 Watts @ 75 MHz (3)
Stop Clock Power Dissipation .02 ≤.05 Watts (4) (5)
NOTES:
1. This is the typical power dissipation in a system. This value was the average value measured in a system using a typical
device at Vcc = 3.3V running typical applications. This value is highly dependent upon the specific system configuration.
2. Systems must be designed to thermally dissipate the maximum active power dissipation. It is determined using a worst-
case instruction mix with Vcc = 3.3V. The use of nominal Vcc in this measurement takes into account the thermal time
constant of the package.
3. Stop Grant/Auto Halt Powerdown Power Dissipation is determined by asserting the STPCLK# pin or executing the HALT
instruction.
4. Stop Clock Power Dissipation is determined by asserting the STPCLK# pin and then removing the external CLK input.
5. Complete characterization of the specification was still in process at the time of print. Please contact Intel for the latest
information. The final specification may be less than 50 mW.
4.3.
AC Specifications
The AC specifications of the Pentium processor
(610\75) consist of setup times, hold times, and
valid delays at 0 pF.
WARNING
Do not exceed the Pentium processor
(610\75) internal maximum frequency of 75
MHz by either selecting the 1/2 bus fraction
or providing a clock greater than 50 MHz.
4.3.1. POWER AND GROUND
For clean on-chip power distribution, the Pentium
processor (610\75) has 79 Vcc (power) and 72 Vss
(ground) inputs. Power and ground connections
must be made to all external Vcc and Vss pins of the
Pentium processor (610\75). On the circuit board
all Vcc pins must be connected to a 3.3V Vcc plane.
All Vss pins must be connected to a V ss plane.
4.3.2. DECOUPLING RECOMMENDATIONS
Liberal decoupling capacitance should be placed
near the Pentium processor (610\75). The Pentium
processor (610\75) driving its large address and
data buses at high frequencies can cause transient
power surges, particularly when driving large
capacitive loads.
Low inductance capacitors and interconnects are
recommended for best high frequency electrical
performance. Inductance can be reduced by
shortening circuit board traces between the
Pentium processor (610\75) and decoupling
capacitors as much as possible.
These capacitors should be evenly distributed
around each component on the 3.3V plane.
Capacitor values should be chosen to ensure they
eliminate both low and high frequency noise
components.
For the Pentium processor (610\75), the power
consumption can transition from a low level of
power to a much higher level (or high to low power)
very rapidly. A typical example would be entering
or exiting the Stop Grant state. Another example
would be executing a HALT instruction, causing the
Pentium processor (610\75) to enter the Auto HALT
Powerdown state, or transitioning from HALT to the
Normal state. All of these examples may cause
abrupt changes in the power being consumed by
the Pentium processor (610\75). Note that the Auto
HALT Powerdown feature is always enabled even
when other power management features are not
implemented.
Bulk storage capacitors with a low ESR (Effective
Series Resistance) in the 10 to 100 µf range are
required to maintain a regulated supply voltage
during the interval between the time the current
load changes and the point that the regulated
power supply output can react to the change in
load. In order to reduce the ESR, it may be
necessary to place several bulk storage capacitors
in parallel.
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These capacitors should be placed near the
Pentium processor (610\75) (on the 3.3V plane) to
ensure that the supply voltage stays within
specified limits during changes in the supply current
during operation.
4.3.3. CONNECTION SPECIFICATIONS
All NC pins must remain unconnected.
For reliable operation, always connect unused
inputs to an appropriate signal level. Unused active
low inputs should be connected to Vcc. Unused
active high inputs should be connected to ground.
4.3.4. AC TIMINGS FOR A 50-MHZ BUS
The AC specifications given in Table 12 consist of
output delays, input setup requirements and input
hold requirements for a 50-MHz external bus. All
AC specifications (with the exception of those for
the TAP signals and APIC signals) are relative to
the rising edge of the CLK input.
All timings are referenced to 1.5V for both "0" and
"1" logic levels unless otherwise specified. Within
the sampling window, a synchronous input must be
stable for correct Pentium processor (610\75)
operation.
Table 12. Pentium® Processor (610\75) TCP
AC Specifications for 50-MHz Bus Operation
Vcc = 3.3V± 5%, TCASE = 0 °C to 95 °C, CL = 0 pF
Symbol Parameter Min Max Unit Figure Notes
Frequency 25.0 50.0 MHz Max Core Freq. =
75 MHz @ 2/3
t1a CLK Period 20.0 40.0 nS 3
t1b CLK Period Stability ±250 pS (1), (19)
t2CLK High Time 4.0 nS 3@2V, (1)
t3CLK Low Time 4.0 nS 3@0.8V, (1)
t4CLK Fall Time 0.15 1.5 nS 3(2.0V-0.8V), (1), (5)
t5CLK Rise Time 0.15 1.5 nS 3(0.8V-2.0V), (1), (5)
t6a ADS#, PWT, PCD, BE0-7#,
M/IO#, D/C#, CACHE#, SCYC,
W/R# Valid Delay
1.0 7.0 nS 4
t6b AP Valid Delay 1.0 8.5 nS 4
t6c A3-A31, LOCK# Valid Delay 1.1 7.0 nS 4
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Table 12. Pentium® Processor (610\75) TCP
AC Specifications for 50-MHz Bus Operation (Contd.)
Vcc = 3.3V± 5%, TCASE = 0 °C to 95 °C, CL = 0 pF
Symbol Parameter Min Max Unit Figure Notes
t7ADS#, AP, A3-A31, PWT, PCD,
BE0-7#, M/IO#, D/C#, W/R#,
CACHE#, SCYC, LOCK# Float
Delay
10.0 nS 5(1)
t8APCHK#, IERR#, FERR#,
PCHK# Valid Delay 1.0 8.3 nS 4(4)
t9a BREQ, HLDA, SMIACT# Valid
Delay 1.0 8.0 nS 4(4)
t10a HIT# Valid Delay 1.0 8.0 nS 4
t10b HITM# Valid Delay 1.1 6.0 nS 4
t11a PM0-1, BP0-3 Valid Delay 1.0 10.0 nS 4
t11b PRDY Valid Delay 1.0 8.0 nS 4
t12 D0-D63, DP0-7 Write Data Valid
Delay 1.3 8.5 nS 4
t13 D0-D63, DP0-3 Write Data Float
Delay 10.0 nS 5(1)
t14 A5-A31 Setup Time 6.5 nS 6(20)
t15 A5-A31 Hold Time 1.0 nS 6
t16a INV, AP Setup Time 5.0 nS 6
t16b EADS# Setup Time 6.0 nS 6
t17 EADS#, INV, AP Hold Time 1.0 nS 6
t18a KEN# Setup Time 5.0 nS 6
t18b NA#, WB/WT# Setup Time 4.5 nS 6
t19 KEN#, WB/WT#, NA# Hold Time 1.0 nS 6
t20 BRDY# Setup Time 5.0 nS 6
t21 BRDY# Hold Time 1.0 nS 6
t22 BOFF# Setup Time 5.5 nS 6
t22a AHOLD Setup Time 6.0 nS 6
t23 AHOLD, BOFF# Hold Time 1.0 nS 6
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Table 12. Pentium® Processor (610\75) TCP
AC Specifications for 50-MHz Bus Operation (Contd.)
Vcc = 3.3V± 5%, TCASE = 0 °C to 95 °C, CL = 0 pF
Symbol Parameter Min Max Unit Figure Notes
t24 BUSCHK#, EWBE#, HOLD,
PEN# Setup Time 5.0 nS 6
t25 BUSCHK#, EWBE#, PEN# Hold
Time 1.0 nS 6
t25a HOLD Hold Time 1.5 nS 6
t26 A20M#, INTR, STPCLK# Setup
Time 5.0 nS 6(11), (15)
t27 A20M#, INTR, STPCLK# Hold
Time 1.0 nS 6(12)
t28 INIT, FLUSH#, NMI, SMI#,
IGNNE# Setup Time 5.0 nS 6(11), (15), (16)
t29 INIT, FLUSH#, NMI, SMI#,
IGNNE# Hold Time 1.0 nS 6(12)
t30 INIT, FLUSH#, NMI, SMI#,
IGNNE# Pulse Width, Async 2.0 CLKs 6(14), (16)
t31 R/S# Setup Time 5.0 nS 6 (11), (15)
t32 R/S# Hold Time 1.0 nS 6(12)
t33 R/S# Pulse Width, Async. 2.0 CLKs 6(14), (16)
t34 D0-D63, DP0-7 Read Data Setup
Time 3.8 nS 6
t35 D0-D63, DP0-7 Read Data Hold
Time 2.0 nS 6
t36 RESET Setup Time 5.0 nS 7 (11), (15)
t37 RESET Hold Time 1.0 nS 7 (12)
t38 RESET Pulse Width, Vcc & CLK
Stable 15 CLKs 7 (16)
t39 RESET Active After Vcc & CLK
Stable 1.0 mS 7Power up
t40 Reset Configuration Signals
(INIT, FLUSH#) Setup Time 5.0 nS 7 (15), (16)
t41 Reset Configuration Signals
(INIT, FLUSH#) Hold Time 1.0 nS 7(12)
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Table 12. Pentium® Processor (610\75) TCP
AC Specifications for 50-MHz Bus Operation (Contd.)
Vcc = 3.3V± 5%, TCASE = 0 °C to 95 °C, CL = 0 pF
Symbol Parameter Min Max Unit Figure Notes
t42a Reset Configuration Signals
(INIT, FLUSH#) Setup Time,
Async.
2.0 CLKs 7To RESET falling
edge (15)
t42b Reset Configuration Signals
(INIT, FLUSH#, BRDY#,
BUSCHK#) Hold Time, Async.
2.0 CLKs 7To RESET falling
edge (211)
t42c Reset Configuration Signal
(BRDY#, BUSCHK#) Setup Time,
Async.
3.0 CLKs 7To RESET falling
edge (21)
t42d Reset Configuration Signal
BRDY# Hold Time, RESET driven
synchronously
1.0 nS To RESET falling
edge (1), (21)
t43a BF Setup Time 1.0 mS 7(18) to RESET
falling edge
t43b BF Hold Time 2.0 CLKs 7(18) to RESET
falling edge
t43c APICEN Setup Time 2.0 CLKs 7To RESET falling
edge
t43d APICEN Hold Time 2.0 CLKs 7To RESET falling
edge
t44 TCK Frequency —16.0 MHz
t45 TCK Period 62.5 nS 3
t46 TCK High Time 25.0 nS 3@2V, (1)
t47 TCK Low Time 25.0 nS 3@0.8V, (1)
t48 TCK Fall Time 5.0 nS 3(2.0V–0.8V), (1),
(8), (9)
t49 TCK Rise Time 5.0 nS 3(0.8V–2.0V), (1),
(8), (9)
t50 TRST# Pulse Width 40.0 nS 9(1), Asynchronous
t51 TDI, TMS Setup Time 5.0 nS 8(7)
t52 TDI, TMS Hold Time 13.0 nS 8(7)
t53 TDO Valid Delay 3.0 20.0 nS 8(8)
t54 TDO Float Delay 25.0 nS 8(1), (8)
t55 All Non-Test Outputs Valid Delay 3.0 20.0 nS 8(3), (8), (10)
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Table 12. Pentium® Processor (610\75) TCP
AC Specifications for 50-MHz Bus Operation (Contd.)
Vcc = 3.3V± 5%, TCASE = 0 °C to 95 °C, CL = 0 pF
Symbol Parameter Min Max Unit Figure Notes
t56 All Non-Test Outputs Float Delay 25.0 nS 8(1), (3), (8), (10)
t57 All Non-Test Inputs Setup Time 5.0 nS 8(3), (7), (10)
t58 All Non-Test Inputs Hold Time 13.0 nS 8(3), (7), (10)
APIC AC Specifications
t60a PICCLK Frequency 2.0 16.66 MHz
t60b PICCLK Period 60.0 500.0 nS 3
t60c PICCLK High Time 9.0 nS 3
t60d PICCLK Low Time 9.0 nS 3
t60e PICCLK Rise Time 1.0 5.0 nS 3
t60f PICCLK Fall Time 1.0 5.0 nS 3
t60g PICD0-1 Setup Time 3.0 nS 6to PICCLK
t60h PICD0-1 Hold Time 2.5 nS 6to PICCLK
t60i PICD0-1 Valid Delay (LtoH) 4.0 38.0 nS 4from PICCLK, (22)
t60j PICD0-1 Valid Delay (HtoL) 4.0 22.0 nS 4from PICCLK, (22)
NOTES:
Notes 2, 6, and 14 are general and apply to all standard TTL signals used with the Pentium Processor family.
1. Not 100% tested. Guaranteed by design.
2. TTL input test waveforms are assumed to be 0 to 3V transitions with 1V/nS rise and fall times.
3. Non-test outputs and inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and TMS). These
timings correspond to the response of these signals due to boundary scan operations.
4. APCHK#, FERR#, HLDA, IERR#, LOCK#, and PCHK# are glitch-free outputs. Glitch-free signals monotonically transition
without false transitions (i.e., glitches).
5. 0.8V/ns ≤ CLK input rise/fall time ≤ 8V/ns.
6. 0.3V/ns ≤ input rise/fall time ≤ 5V/ns.
7. Referenced to TCK rising edge.
8. Referenced to TCK falling edge.
9. 1 ns can be added to the maximum TCK rise and fall times for every 10 MHz of frequency below 33 MHz.
10. During probe mode operation, do not use the boundary scan timings (t55-58).
11. Setup time is required to guarantee recognition on a specific clock.
12. Hold time is required to guarantee recognition on a specific clock.
13. All TTL timings are referenced from 1.5V.
14. To guarantee proper asynchronous recognition, the signal must have been de-asserted (inactive) for a minimum of 2
clocks before being returned active and must meet the minimum pulse width.
15. This input may be driven asynchronously.
16. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, and SMI# must be de-asserted (inactive) for a
minimum of 2 clocks before being returned active.
17. The D/C#, M/IO#, W/R#, CACHE#, and A5-A31 signals are sampled only on the CLK that ADS# is active.
18. BF should be strapped to Vcc or Vss.
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19. These signals are measured on the rising edge of adjacent CLKs at 1.5V. To ensure a 1:1 relationship between the
amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power
spectrum peaking between 500 KHz and 1/3 of the CLK operating frequency. The amount of jitter present must be
accounted for as a component of CLK skew between devices.
20. Timing t14 is required for external snooping (e.g., address setup to the CLK in which EADS# is sampled active).
21. BUSCHK# is used as a reset configuration signal to select buffer size.
22. This assumes an external pullup resistor to Vcc and a lumped capacitive load. The pullup resistor must be between
150 ohms and 1K ohms, the capacitance must be between 20 pF and 240 pF, and the RC product must be between 3 ns
and 36 ns.
** Each valid delay is specified for a 0 pF load. The system designer should use I/O buffer modeling to account for signal
flight time delays.
Figure 3. Clock Waveform
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Figure 4. Valid Delay Timings
Figure 5. Float Delay Timings
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Figure 6. Setup and Hold Timings
Figure 7. Reset and Configuration Timings
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Figure 8. Test Timings
Figure 9. Test Reset Timings
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4.4.
I/O Buffer Models
This section describes the I/O buffer models of the
Pentium processor (610\75).
The first order I/O buffer model is a simplified
representation of the complex input and output
buffers used in the Pentium processor (610\75).
Figures 10 and 11 show the structure of the input
buffer model and Figure 12 shows the output buffer
model. Tables 13 and 14 show the parameters
used to specify these models.
Although simplified, these buffer models will
accurately model flight time and signal quality. For
these parameters, there is very little added
accuracy in a complete transistor model.
The following two models represent the input buffer
models. The first model, Figure 10, represents all
of the input buffers of the Pentium processor
(610\75) except for a special group of input buffers.
The second model, Figure 11, represents these
special buffers. These buffers are the inputs:
AHOLD, EADS#, KEN#, WB/WT#, INV, NA#,
EWBE#, BOFF#, CLK, and PICCLK.
Figure 10. Input Buffer Model, Except Special Group
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Figure 11. Input Buffer Model for Special Group
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Table 13. Parameters Used in the Specification of the First Order Input Buffer Model
Parameter Description
Cin Minimum and Maximum value of the capacitance of the input buffer model.
Lp Minimum and Maximum value of the package inductance.
Cp Minimum and Maximum value of the package capacitance.
Rs Diode Series Resistance
D1, D2 Ideal Diodes
Figure 12 shows the structure of the output buffer model. This model is used for all of the output buffers of
the Pentium processor (610\75).
Figure 12. First Order Output Buffer Model
Table 14. Parameters Used in the Specification of the First Order Output Buffer Model
Parameter Description
dV/dt Minimum and maximum value of the rate of change of the open circuit
voltage source used in the output buffer model.
Ro Minimum and maximum value of the output impedance of the output buffer
model.
Co Minimum and Maximum value of the capacitance of the output buffer model.
Lp Minimum and Maximum value of the package inductance.
Cp Minimum and Maximum value of the package capacitance.
In addition to the input and output buffer
parameters, input protection diode models are
provided for added accuracy. These diodes have
been optimized to provide ESD protection and
provide some level of clamping. Although the
diodes are not required for simulation, it may be
more difficult to meet specifications without them.
Note, however, some signal quality specifications
require that the diodes be removed from the input
model. The series resistors (Rs) are a part of the
diode model. Remove these when removing the
diodes from the input model.
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4.4.1. BUFFER MODEL PARAMETERS
This section gives the parameters for each Pentium
processor (610\75) input, output, and bidirectional
signal, as well as the settings for the configurable
buffers.
Some pins on the Pentium processor (610\75) have
selectable buffer sizes. These pins use the
configurable output buffer EB2. Table 15 shows the
drive level for BRDY# required at the falling edge of
RESET to select the buffer strength. The buffer
sizes selected should be the appropriate size
required; otherwise AC timings might not be met, or
too much overshoot and ringback may occur.
There are no other selection choices; all of the
configurable buffers get set to the same size at the
same time.
Table 15. Buffer Selection Chart
Environment BRDY# Buffer Selection
Typical Stand Alone Component 1EB2
Loaded Component 0EB2A
NOTES:
For correct buffer selection, the BUSCHK# signal must be held inactive (high) at the falling edge of RESET.
For the Pentium processor (610\75) SPGA version, BRDYC# is used to configure selectable buffer sizes.
Please refer to Table 16 for the groupings of the buffers.
Table 16. Signal to Buffer Type
Signals Type
Driver Buffer
Type
Receiver
Buffer Type
CLK IER0
A20M#, AHOLD, BF, BOFF#, BRDY#, BUSCHK#,
EADS#, EWBE#, FLUSH#, HOLD, IGNNE#, INIT, INTR,
INV, KEN#, NA#, NMI, PEN#, PICCLK, R/S#, RESET,
SMI#, STPCLK#, TCK, TDI, TMS, TRST#, WB/WT#
IER1
APCHK#, BE[7:5]#, BP[3:2], BREQ, FERR#, IERR#, PCD,
PCHK#, PM0/BP0, PM1/BP1, PRDY, PWT, SMIACT#,
TDO, U/O#
OED1
A[31:21], AP, BE[4:0]#, CACHE#, D/C#, D[63:0], DP[8:0],
HLDA, LOCK#, M/IO#, SCYC I/O EB1 EB1
A[20:3], ADS#, HITM#, W/R# I/O EB2A EB2
HIT# I/O EB3 EB3
PID0, PICD1 I/O EB4 EB4
The input, output and bidirectional buffer values are
listed in Table 17. This table contains listings for all
three types, do not get them confused during
simulation. When a bidirectional pin is operating as
an input, just use the Cin, Cp and Lp values; if it is
operating as a driver, use all of the data
parameters.
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Table 17. Input, Output and Bidirectional Buffer Model Parameters
Buffer
Type
Transition
dV/dt
(V/nsec)
Ro
(Ohms)
Cp
(pF)
Lp
(nH)
Co/Cin
(pF)
min max min max min max min max min max
ER0 Rising 0.3 0.4 3.9 5.0 0.8 1.2
(input) Falling 0.3 0.4 3.9 5.0 0.8 1.2
ER1 Rising 0.2 0.5 3.1 6.0 0.8 1.2
(input) Falling 0.2 0.5 3.1 6.0 0.8 1.2
ED1 Rising 3/3.0 3.7/0.9 21.6 53.1 0.3 0.6 3.7 6.6 2.0 2.6
(output) Falling 3/2.8 3.7/0.8 17.5 50.7 0.3 0.6 3.7 6.6 2.0 2.6
EB1 Rising 3/3.0 3.7/0.9 21.6 53.1 0.2 0.5 2.9 6.1 2.0 2.6
(bidir) Falling 3/2.8 3.7/0.8 17.5 50.7 0.2 0.5 2.9 6.1 2.0 2.6
EB2 Rising 3/3.0 3.7/0.9 21.6 53.1 0.2 0.5 3.1 6.4 9.1 9.7
(bidir) Falling 3/2.8 3.7/0.8 17.5 50.7 0.2 0.5 3.1 6.4 9.1 9.7
EB2A Rising 3/2.4 3.7/0.9 10.1 22.4 0.2 0.5 3.1 6.4 9.1 9.7
(bidir) Falling 3/2.4 3.7/0.9 9.0 21.2 0.2 0.5 3.1 6.4 9.1 9.7
EB3 Rising 3/3.0 3.7/0.9 21.6 53.1 0.2 0.4 3.2 4.1 3.3 3.9
(bidir) Falling 3/2.8 3.7/0.8 17.5 50.7 0.2 0.4 3.2 4.1 3.3 3.9
EB4 Rising 3/3.0 3.7/0.9 21.6 53.1 0.3 0.4 4.0 4.1 5.0 7.0
(bidir) Falling 3/2.8 3.7/0.8 17.5 50.7 0.3 0.4 4.0 4.1 5.0 7.0
Table 18. Input Buffer Model Parameters: D (Diodes)
Symbol Parameter D1 D2
IS Saturation Current 1.4e-14A 2.78e-16A
NEmission Coefficient 1.19 1.00
RS Series Resistance 6.5 ohms 6.5 ohms
TT Transit Time 3 ns 6 ns
VJ PN Potential 0.983V 0.967V
CJ0 Zero Bias PN Capacitance 0.281 pF 0.365 pF
MPN Grading Coefficient 0.385 0.376
4.4.2. SIGNAL QUALITY SPECIFICATIONS
Signals driven by the system into the Pentium
processor (610\75) must meet signal quality
specifications to guarantee that the components
read data properly and to ensure that incoming
signals do not affect the reliability of the
component. There are two signal quality
parameters: Ringback and Settling Time.
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4.4.2.1. Ringback
Excessive ringback can contribute to long-term
reliability degradation of the Pentium processor
(610\75), and can cause false signal detection.
Ringback is simulated at the input pin of a
component using the input buffer model. Ringback
can be simulated with or without the diodes that are
in the input buffer model.
Ringback is the absolute value of the maximum
voltage at the receiving pin below Vcc (or above
Vss) relative to Vcc (or Vss) level after the signal
has reached its maximum voltage level. The input
diodes are assumed present.
Maximum Ringback on Inputs = 0.8V (with
diodes)
If simulated without the input diodes, follow the
Maximum Overshoot/Undershoot specification. By
meeting the overshoot/undershoot specification, the
signal is guaranteed not to ringback excessively.
If simulated with the diodes present in the input
model, follow the maximum ringback specification.
Overshoot (Undershoot) is the absolute value of the
maximum voltage above Vcc (below Vss). The
guideline assumes the absence of diodes on the
input.
•Maximum Overshoot/Undershoot on 5V 82497
Cache Controller, and 82492 Cache SRAM
Inputs (CLK and PICCLK only) = 1.6V above
VCC5 (without diodes)
•Maximum Overshoot/Undershoot on 3.3V
Pentium processor (610\75) Inputs (not CLK and
PICCLK) = 1.4V above VCC3 (without diodes)
Figure 13. Overshoot/Undershoot and Ringback Guidelines
4.4.2.2. Settling Time
The settling time is defined as the time a signal
requires at the receiver to settle within 10 percent of
Vcc or Vss. Settling time is the maximum time
allowed for a signal to reach within 10 percent of its
final value.
Most available simulation tools are unable to
simulate settling time so that it accurately reflects
silicon measurements. On a physical board,
second-order effects and other effects serve to
dampen the signal at the receiver. Because of all
these concerns, settling time is a recommendation
or a tool for layout tuning and not a specification.
Settling time is simulated at the slow corner, to
make sure that there is no impact on the flight times
of the signals if the waveform has not settled.
Settling time
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may be simulated with the diodes included or
excluded from the input buffer model. If diodes are
included, settling time recommendation will be
easier to meet.
Although simulated settling time has not shown
good correlation with physical, measured settling
time, settling time simulations can still be used as a
tool to tune layouts.
Use the following procedure to verify board
simulation and tuning with concerns for settling
time.
1. Simulate settling time at the slow corner for a
particular signal.
2. If settling time violations occur, simulate signal
trace with D.C. diodes in place at the receiver
pin. The D.C. diode behaves almost identically
to the actual (non-linear) diode on the part as
long as excessive overshoot does not occur.
3. If settling time violations still occur, simulate
flight times for 5 consecutive cycles for that
particular signal.
4. If flight time values are consistent over the 5
simulations, settling time should not be a
concern. If however, flight times are not
consistent over the 5 simulations, tuning of the
layout is required.
5. Note that, for signals that are allocated 2 cycles
for flight time, the recommended settling time is
doubled.
A typical design method would include a settling
time that ensures a signal is within 10% of VCC or
VSS for at least 2.5 ns prior to the end of the CLK
period.
Figure 14. Settling Time
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5.
0. Pentium® Processor (610\75) TCP
MECHANICAL SPECIFICATIONS
Today's portable computers face the challenge of
meeting desktop performance in an environment
that is constrained by thermal, mechanical, and
electrical design considerations. These
considerations have driven the development and
implementation of Intel’s Tape Carrier Package
(TCP). The Intel TCP package has been designed
to offer a high pin count, low profile, reduced
footprint package with uncompromised thermal and
electrical performance. Intel continues to provide
packaging solutions that meet our rigorous criteria
for quality and performance, and this new entry into
the Intel package portfolio is no exception.
Key features of the TCP package include: surface
mount technology design, lead pitch of 0.25 mm,
polyimide body size of 24 mm and polyimide up for
pick&place handling. TCP components are shipped
with the leads flat in slide carriers, and are designed
to be excised and lead formed at the customer
manufacturing site. Recommendations for the
manufacture of this package are included in the
Pentium® Processor (610\75) Tape Carrier Package
User’s Guide.
Figure 15 shows a cross-sectional view of the TCP
package as mounted on the Printed Circuit Board.
Figures 16 and 17 show the TCP as shipped in its
slide carrier, and key dimensions of the carrier and
package. Figure 18 shows a blow up detail of the
package in cross-section. Figure 19 shows an
enlarged view of the outer lead bond area of the
package.
Tables 19 and 20 provide Pentium processor
(610\75) TCP package dimensions.
5.1.
TCP Package Mechanical Diagrams
TAB Lead
(OFC Copper)
Gold Bump
Polyimide
Support Ring Polyimide
Keeper
Bar
Thermally & Electrically
Conductive Adhesive
(Silver Filled Thermoplastic)
Note:
Sketches Not to Scale
Encapsulant
Die
Full X-Section
1/2 X-Section
Thermal vias
PCB
Ground plane
PCB
Figure 15. Cross-Sectional View of the Mounted TCP Package
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Figure 16. One TCP Site in Carrier (Bottom View of Die)
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(until publication date)
Figure 17. One TCP Site in Carrier (Top View of Die)
PENTIUM® PROCESSOR (610\75)
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Figure 18. One TCP Site (Cross-Sectional Detail)
Figure 19. Outer Lead Bond (OLB) Window Detail
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Table 19. TCP Key Dimensions
Symbol Description Dimension
Symbol Description Dimension
NLeadcount 320 leads
WTape Width 48.18 ±0.12
LSite Length (43.94) reference only
e1 Outer Lead Pitch 0.25 nominal
bOuter Lead Width 0.10 ±0.01
D1,E1 Package Body Size 24.0 ±0.1
A2 Package Height 75 MHz/90 MHz--0.615 ±0.030
120 MHz--0.605 ±0.030
DL Die Length 75 MHz/90 MHz--12.769 ±0.015
120 MHz--9.929 ±0.015
DW Die Width 75 MHz/90 MHz--11.755 ±0.015
120 MHz--9.152 ±0.015
LT Lead Thickness 75 MHz/90 MHz--0.035 mm
120 MHz--0.025 mm
EL Encap Length 75 MHz/90 MHz--(13.40 mm) reference only
120 MHz--(10.56 mm) reference only
EW Encap Width 75 MHz/90 MHz--(12.39 mm) reference only
120 MHz--(9.78 mm) reference only
NOTES:
Dimensions are in millimeters unless otherwise noted.
Dimensions in parentheses are for reference only.
Table 20. Mounted TCP Package Dimensions
Description Dimension
Package Height 0.75 max.
Terminal Dimension 29.5 nom.
Package Weight 0.5 g max.
NOTE:
Dimensions are in millimeters unless otherwise noted.
Package terminal dimension (lead tip-to-lead tip) assumes the use of a keeper bar.
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6.
0. Pentium® Processor (610\75) TCP
THERMAL SPECIFICATIONS
The Pentium processor (610\75) is specified for
proper operation when the case temperature,
TCASE, (TC) is within the specified range of 0 °C to
95 °C.
6.1.
Measuring Thermal Values
To verify that the proper TC (case temperature) is
maintained for the Pentium processor (610\75), it
should be measured at the center of the package
top surface (encapsulant). To minimize any
measurement errors, the following techniques are
recommended:
•Use 36 gauge or finer diameter K, T, or J type
thermocouples. Intel's laboratory testing was
done using a thermocouple made by Omega
(part number: 5TC-TTK-36-36).
•Attach the thermocouple bead or junction to the
center of the package top surface using highly
thermally conductive cements. Intel's laboratory
testing was done by using Omega Bond (part
number: OB-100).
•The thermocouple should be attached at a 90°
angle as shown in Figure 20.
Figure 20. Technique for Measuring Case
Temperature (TC)
6.2.
Thermal Equations
For the Pentium processor (610\75), an ambient
temperature (TA) is not specified directly. The only
requirement is that the case temperature (TC) is
met. The ambient temperature can be calculated
from the following equations:
[ ]
T T P
T T P
T T P
T T P
JCJC
AJJA
ACCA
CAJA JC
CA JA JC
=
+
×
= − ×
= − ×
= + ×−
= −
θ
θθ
θ θ
θ θ θ
( )
where,
TA and TC are ambient and case temperatures (°C)
θCA = Case-to-Ambient thermal resistance (°C/W)
θJA = Junction-to-Ambient thermal resistance (°C/W)
θJC = Junction-to-Case thermal resistance (°C/W)
P = maximum power consumption (Watts)
P (maximum power consumption) is specified in
section 4.2.
6.3.
TCP Thermal Characteristics
The primary heat transfer path from the die of the
Tape Carrier Package (TCP) is through the back
side of the die and into the PC board. There are
two thermal paths traveling from the PC board to
the ambient air. One is the spread of heat within
the board and the dissipation of heat by the board
to the ambient air. The other is the transfer of heat
through the board and to the opposite side where
thermal enhancements (e.g., heat sinks, pipes) are
attached. To prevent the possibility of damaging
the TCP component, the thermal enhancements
should be attached to the opposite side of the TCP
site — not directly mounted to the package surface.
6.4.
PC Board Enhancements
Copper planes, thermal pads, and vias are design
options that can be used to improve heat transfer
from the PC board to the ambient air. Tables 21
and 22 present thermal resistance data for copper
plane thickness and via effects. It should be noted
that although thicker copper planes will reduce the
θca of a system without any thermal
enhancements, they have less effect on the θca of
a system with thermal enhancements. However,
placing vias under the die will reduce the θca of a
system with and without thermal enhancements.
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Table 21. Thermal Resistance vs. Copper Plane
Thickness with and without Enhancements
Copper
Plane
Thickness*
θ
CA
(°C/W)
No
Enhancements
θ
CA
(°C/W)
With
Heat Pipe
1 oz. Cu 18 8
3 oz. Cu 14 8
NOTES:
*225 vias underneath the die
(1 oz = 1.3 ml)
Table 22. Thermal Resistance vs. Thermal Vias
underneath the Die
No. of Vias Under
the Die* θ
CA
(°C/W)
No Enhancements
0 15
144 13
NOTE:
*3 oz. copper planes in test boards
6.4.1. STANDARD TEST BOARD
CONFIGURATION
All Tape Carrier Package (TCP) thermal
measurements provided in the following tables were
taken with the component soldered to a 2" x 2" test
board outline. This six-layer board contains 225
vias (underneath the die) in the die attach pad
which are connected to two 3 oz. copper planes
located at layers two and five. For the Pentium
processor (610\75) TCP, the vias in the die attach
pad should be connected without thermal reliefs to
the ground plane(s). The die is attached to the die
attach pad using a thermally and electrically
conductive adhesive. This test board was designed
to optimize the heat spreading into the board and
the heat transfer through to the opposite side of the
board.
NOTE
Thermal resistance values should be used
as guidelines only, and are highly system
dependent. Final system verification should
always refer to the case temperature
specification.
Table 23. Pentium® Processor (610\75)
TCP Package Thermal Resistance
without Enhancements
θJC
(°C/W)
θCA
(°C/W)
Thermal Resistance without
Enhancements .8 13.9
Table 24. Pentium® Processor (610\75)
TCP Package Thermal Resistance
with Enhancements (without Airflow)
Thermal
Enhancements
θCA
(°C/W) Notes
Heat sink 11.7 1.2"×1.2"×.35"
Al Plate 8.7 4"×4"×.030"
Al Plate with
Heat Pipe 7.8 .3×1"×4"
Table 25. Pentium® Processor (610\75)
TCP Package Thermal Resistance
with Enhancements (with Airflow)
Thermal
Enhancements
θCA
(°C/W) Notes
Heat sink with Fan
@ 1.7 CFM 5.0 1.2"×1.2"×.35" HS
1"×1"×.4" Fan
Heat sink with
Airflow @ 400 LFM 5.1 1.2"×1.2"×.35" HS
Heat sink with
Airflow @ 600 LFM 4.3 1.2"×1.2"×.35" HS
HS = heat sink
LFM = Linear Feet/Minute
CFM = Cubic Feet/Minute
