MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
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Detailed Description
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
logic-level translators provide the level shifting neces-
sary to allow data transfer in a multivoltage system.
Externally applied voltages, VCC and VL, set the logic
levels on either side of the device. Logic signals pre-
sent on the VLside of the device appear as a higher
voltage logic signal on the VCC side of the device, and
vice-versa. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E are bidirectional level translators allowing
data translation in either direction (VL↔VCC) on
any single data line. The MAX13101E/MAX13102E/
MAX13103E/MAX13108E accept VLfrom +1.2V to VCC.
All devices have a VCC range from +1.65V to +5.5V,
making them ideal for data transfer between low-volt-
age ASICs/PLDs and higher voltage systems.
The MAX13101E/MAX13102E/MAX13103E feature an
output enable mode that reduces VCC supply current to
less than 1µA, and VLsupply current to less than 2µA
when in shutdown. The MAX13108E features a multi-
plexing input that selects one byte between the two,
thus allowing multiplexing of the signals. The
MAX13101E/MAX13102E/MAX13103E/MAX13108E
have ±15kV ESD protection on the I/O VCC side for
greater protection in applications that route signals
externally. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E operate at a guaranteed data rate of
20Mbps. The maximum data rate depends heavily
on the load capacitance (see the
Typical Operating
Characteristics
) and the output impedance of the
external driver.
Power-Supply Sequencing
For proper operation, ensure that +1.65V ≤VCC ≤+5.5V,
+1.2V ≤VL≤+5.5V, and VL≤VCC. During power-up
sequencing, VL≥VCC does not damage the device.
When VCC is disconnected and VLis powering up, up to
10mA of current can be sourced to each load on the VL
side, yet the device does not latch up. To guarantee that
no excess leakage current flows and that the device
does not interfere with the I/O on the VLside, VCC should
be connected to GND with a max 50Ωresistor when the
VCC supply is not present (Figure 5).
Input Driver Requirements
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
architecture is based on a one-shot accelerator output
stage (Figure 6). Accelerator output stages are always
in tri-state except when there is a transition on any of
the translators on the input side, either I/O VL_ or
I/O VCC_. Then a short pulse is generated, during
which the accelerator output stages become active and
charge/discharge the capacitances at the I/Os. Due to
the bidirectional nature, both input stages become
active during the one-shot pulse. This can lead to some
current feeding into the external source that is driving
the translator. However, this behavior helps to speed
up the transition on the driven side.
For proper full-speed operation, the output current of a
device that drives the inputs of the MAX13101E/
MAX13102E/MAX13103E/MAX13108E should meet the
following requirement:
i > 108x V x (C + 10pF)
where, i is the driver output current, V is the logic-supply
voltage (i.e., VLor VCC) and C is the parasitic capaci-
tance of the signal line.
Enable Output Mode (EN)
The MAX13101E/MAX13102E/MAX13103E feature an
enable input (EN) that, when driven low, places the
device into shutdown mode. During shutdown, the
MAX13101E I/O VCC_ ports are pulled down to ground
with internal 6kΩresistors and the I/O VL_ ports enter
tri-state. MAX13102E I/O VCC_ lines enter tri-state and
the I/OVL_ lines are pulled down to ground with internal
6kΩresistors. All I/O VCC_ and I/O VL_ lines on the
MAX13103E enter tri-state while the device is in shut-
down mode. During shutdown, the VCC supply current
reduces to less than 1µA, and the VLsupply current
reduces to less than 2µA. To guarantee minimum shut-
down supply current, all I/O VL_ need to be driven to
GND or VL, or pulled to GND or VLthrough 100kΩ
resistors. All I/O VCC_ need to be driven to GND or
VCC, or pulled to GND or VCC through 100kΩresistors.
Drive EN to logic-high (VLor VCC) for normal operation.