Description
The CXD2027Q/R are audio signal processors
designed for DBS applications. These LSIs perform
all digital processing from QPSK demodulation to
analog audio output on a single chip.
Features
QPSK and PCM demodulators and DAC output
are configured on a single chip.
Descrambler interface according to the COATEC
system and SkyPort system .
Functions
QPSK demodulator
• Carrier, clock and data regeneration
• ALC and VCXO adjustment-free
PCM demodulator
• Frame sync protection by correlation detection
• De-interleaving and descrambling
• BCH error correction, range bit error correction
• Audio data range control
Expansion from 10 to 14 bits in A mode
Upper bit majority correction in B mode
• Control sign integration correction, chargeable
flag integration correction by master frame
synchronization
• Interface output for external DAC
• Digital interface output
1-bit DAC output
• Quadruple oversampling filter
• Digital de-emphasis circuit
• 1-bit stereo DAC with 2nd-order ∆∑ format noise
shaper
S/N ratio : 90dB (Typ.)
Distortion: 0.011% (Typ.)
CPU interface
•I
2
C bus
Descrambler interface
• COATEC system, SkyPort system
Mute functions
• Error occurrence frequency detection mute
• Audio chargeable flag detection mute
• Control sign (B7) detection mute
Structure
Silicon gate CMOS IC
Applications
TVs, VCRs with built-in BS tuners
Absolute Maximum Ratings (Ta = 25°C, Vss = 0V)
•Supply voltage VDD Vss – 0.5 to +7.0 V
•Input voltage VIVss – 0.5 to VDD + 0.5V
•Output voltage VOVss – 0.5 to VDD + 0.5V
•Storage temperature Tstg –55 to +150 °C
Operating Conditions
•Supply voltage VDD 4.75 to 5.25 V
•Operating temperature Topr –20 to +75 °C
– 1 –
CXD2027Q/R
E94808-ST
DBS Audio Signal Processor
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXD2027Q
64 pin QFP (Plastic) CXD2027R
80 pin LQFP (Plastic)
For the availability of this product, please contact the sales office.
– 2 –
CXD2027Q/R
DATA
RECOVERY FRAME SYNC DE-SCRAMBLER BCH DECODER
(63, 56)
SHIFTER
&
RANGE BIT
BCH (7, 3)
ALC SIGNAL
GENERATOR
MASTER FRAME
SYNC DE-INTERLEAVER
4 kBIT-RAM 10 → 14 BIT
DATA EXPAND MAJORITY
ERROR
CORRECTION
MUTE SIGNAL
GENERATOR
CONTROL WORD
INTEGRAL
CORRECTION
8TH RANGE BIT
INTEGRAL
CORRECTION CLOCK GENERATOR
CARRIER
RECOVERY
SYSTEM CLOCK
GENERATOR AUDIO DATA
INTERPOLATOR
DIGITAL FILTER
DE-ENPHASIS
DAC1
DAC2
AUDIO
INTERFACE
DIGITAL
INTERFACE
I2C BUS I/F
TIMING
GENERATOR
CLOCK
RECOVERY
ADC
RT
ADIN
RB
GR
ALCO
PHAA
M23I
M23O
PHAB
MCKI
F256
BCLK
AUD
RNO
RPO
LNO
LPO
MUTE
LRCK
DATB
DATA
DATO
DSLA
NSYN
BITI
DSLB
BITO
FRAM
TX
SASL
SCLK
SDA
DTUP
CC1
CK2M
MCKO
45
678
9
11
12
13
14 15
25
28
38
35
32
43
44
45
46
47
48
50 51
54
56
57
58
67
64
65
66
71
73
76
77
Block Diagram
Note) Pin numbers are for the CXD2027R.
– 3 –
CXD2027Q/R
Pin Configuration 1
CXD2027Q
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
VDD5
M23O
M23I
PHAA
ALCO
VSS9
TST7
RT
ADIN
ADVD
ADVS
RB
GR
VSS6
VSS5
RNO
VDD2
RPO
VSS4
TST1
VSS3
LPO
VDD1
LNO
VSS2
VSS1
TST0
MRST
V
SS
0
BITO
BITI
DSLB
DSLA
DATB
DATA
V
DD
0
CK2M
FRAM
DATO
CC1
TX
TST2
TST3
TST4
TST5
V
DD
4
PHAB
MCKI
MCKO
V
SS
8
MUTE
TST8
V
SS
7
SCLK
SDA
V
DD
3
NSYN
DTUP
F256
BCLK
LRCK
AUD
TST6
SASL
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9 10111213141516171819
– 4 –
CXD2027Q/R
Pin Configuration 2
CXD2027R
68
69
70
71
72
73
74
75
76
77
78
79
80
33
32
31
30
29
28
27
26
25
24
23
22
21
RT
ADIN
ADVD
ADVS
RB
GR
VDD2
RPO
VSS4
TST1
VSS3
LPO
VDD1
N.C.
LNO
VSS2
VSS1
N.C.
N.C.
N.C.
MRST
V
SS
0
BITO
BITI
DSLB
DSLA
DATB
DATA
V
DD
0
CK2M
FRAM
DATO
CC1
TX
TST2
TST3
TST4
TST5
V
DD
4
PHAB
MCKI
MCKO
V
SS
8
MUTE
TST8
V
SS
7
SCLK
SDA
V
DD
3
NSYN
DTUP
F256
BCLK
LRCK
AUD
TST6
N.C.
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
1 2 3 4 5 6 7 8 9 10111213141516171819
N.C.
20
40
39
38
37
36
35
34
N.C.
N.C.
SASL
VSS6
VSS5
RNO
N.C.
N.C.
41
61
62
63
64
65
66
67
VDD5
M23O
M23I
PHAA
ALCO
VSS9
TST7
N.C.
N.C.
TST0
N.C.
N.C.
N.C.
N.C.
– 5 –
CXD2027Q/R
Pin Description 1
CXD2027Q (64pin QFP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
TST0
MRST
VSS Digital
BITO
BITI
DSLB
DSLA
DATB
DATA
VDD Digital
CK2M
FRAM
DATO
CC1
TX
TST2
TST3
TST4
TST5
VSS Digital
VSS D/A
LNO
VDD D/A
LPO
VSS D/A
TST1
VSS D/A
RPO
VDD D/A
RNO
VSS D/A
VSS Digital
SASL
TST6
I
I
—
O
I
I
I
I
I
—
O
O
O
O
O
I
I
I
I
—
—
O
—
O
—
I
—
O
—
O
—
—
I
I
Test pin; normally low
Master reset; H: normal operation; L: reset
Digital ground
Bit stream output after PSK demodulation
Bit stream input after PSK demodulation
External descrambler pin
External descrambler pin
Data input 2 after BCH correction (for COATEC)
Data input 1 after BCH correction (for SkyPort)
Digital +5V power supply
2.048MHz clock output
Frame start bit flag
Data output after BCH correction
Control sign first bit output
Digital format audio output
Test pin; normally low
Test pin; normally low
Test pin; normally low
Test pin; normally high
Digital ground
Analog ground
Lch D/A converter output
Analog +5V power supply
Lch D/A converter output
Analog ground
Test pin; normally low
Analog ground
Rch D/A converter output
Analog +5V power supply
Rch D/A converter output
Analog ground
Digital ground
I2C bus slave address select (L: D4, H: D6)
Test pin; normally low
Internal pull down
Internal pull up
TTL input
TTL input
TTL input
TTL input
TTL input
Internal pull down
Internal pull down
Internal pull down
Internal pull down
Internal pull down
Internal pull down
Symbol I/O Pin Description Remarks
– 6 –
CXD2027Q/R
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AUD
LRCK
BCLK
F256
DTUP
NSYN
VDD Digital
SDA
SCLK
VSS Digital
TST8
MUTE
VSS Digital
MCKO
MCKI
PHAB
VDD Digital
VDD Digital
M23O
M23I
PHAA
ALCO
VSS Digital
TST7
RT
ADIN
VDD A/D
VSS A/D
RB
GR
O
O
O
O
O
O
—
I
I
—
I
I
—
O
I
O
—
—
O
I
O
O
—
I
I
I
—
—
I
I
Audio data output for external DF/DAC
LR clock output for external DF/DAC
Bit clock output for external DF/DAC
Clock output for external DF/DAC
CCUP: control sign update flag / DED: BCH 2 error detection
Asynchronous flag (H: asynchronous; L: synchronous)
Digital +5V power supply
SDA (I2C bus)
SCL (I2C bus)
Digital ground
Test pin; normally low
External forced muting input
Digital ground
MCKI inversion output
24.576MHz clock input
Clock regeneration phase error data output
Digital +5V power supply
Digital +5V power supply
M23I inversion output
22.909088MHz clock input
Carrier regeneration phase error data output
ALC A/D control output
Digital ground
Test pin; normally low
A/D converter VRT input
Analog data input
Analog +5V power supply
Analog ground
A/D converter VRB input; connect to analog ground
A/D converter VGR input; connect to analog ground
Switched by I2C bus
I2C bus compatible
I2C bus compatible
TTL input
Pin
No. Symbol I/O Pin Description Remarks
– 7 –
CXD2027Q/R
Pin Description 2
CXD2027R (80pin LQFP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
N.C.
MRST
VSS Digital
BITO
BITI
DSLB
DSLA
DATB
DATA
VDD Digital
CK2M
FRAM
DATO
CC1
TX
TST2
TST3
TST4
TST5
N.C.
N.C.
N.C.
VSS Digital
VSS D/A
LNO
N.C.
VDD D/A
LPO
VSS D/A
TST1
VSS D/A
RPO
VDD D/A
N.C.
—
I
—
O
I
I
I
I
I
—
O
O
O
O
O
I
I
I
I
—
—
—
—
—
O
—
—
O
—
I
—
O
—
—
Non-connection
Master reset; H: normal operation; L: reset
Digital ground
Bit stream output after PSK demodulation
Bit stream input after PSK demodulation
External descrambler pin
External descrambler pin
Data input 2 after BCH correction (for COATEC)
Data input 1 after BCH correction (for SkyPort)
Digital +5V power supply
2.048MHz clock output
Frame start bit flag
Data output after BCH correction
Control sign first bit output
Digital format audio output
Test pin; normally low
Test pin; normally low
Test pin; normally low
Test pin; normally high
Non-connection
Non-connection
Non-connection
Digital ground
Analog ground
Lch DAC output
Non-connection
Analog +5V power supply
Lch DAC output
Analog ground
Test pin; normally low
Analog ground
Rch DAC output
Analog +5V power supply
Non-connection
Internal pull up
TTL input
TTL input
TTL input
TTL input
TTL input
Internal pull down
Internal pull down
Internal pull down
Internal pull down
Pin
No. Symbol I/O Pin Description Remarks
– 8 –
CXD2027Q/R
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
RNO
VSS D/A
VSS Digital
SASL
N.C.
N.C.
N.C.
TST6
AUD
LRCK
BCLK
F256
DTUP
NSYN
VDD Digital
SDA
SCLK
VSS Digital
TST8
MUTE
VSS Digital
MCKO
MCKI
PHAB
VDD Digital
N.C.
N.C.
N.C.
VDD Digital
M23O
M23I
PHAA
ALCO
VSS Digital
N.C.
TST7
O
—
—
I
—
—
—
I
O
O
O
O
O
O
—
I
I
—
I
I
—
O
I
O
—
—
—
—
—
O
I
O
O
—
—
I
Rch D/A converter output
Analog ground
Digital ground
I2C bus slave address select (L: D4, H: D6)
Non-connection
Non-connection
Non-connection
Test pin; normally low
Audio data output for external DF/DAC
LR clock output for external DF/DAC
Bit clock output for external DF/DAC
Clock output for external DF/DAC
CCUP: control sign update flag/DED: BCH 2 error detection
Asynchronous flag (H: asynchronous; L: synchronous)
Digital +5V power supply
SDA (I2C bus)
SCL (I2C bus)
Digital ground
Test pin; normally low
External forced muting input
Digital ground
MCKI inversion output
24.576MHz clock input
Clock regeneration phase error data output
Digital +5V power supply
Non-connection
Non-connection
Non-connection
Digital +5V power supply
M23I inversion output
22.909088MHz clock input
Carrier regeneration phase error data output
ALC A/D control output
Digital ground
Non-connection
Test pin; normally low
Internal pull down
Internal pull down
Switched by I2C bus
I2C bus compatible
I2C bus compatible
TTL input
Pin
No. Symbol I/O Pin Description Remarks
– 9 –
CXD2027Q/R
71
72
73
74
75
76
77
78
79
80
RT
N.C.
ADIN
VDD A/D
VSS A/D
RB
GR
TST0
N.C.
N.C.
I
—
I
—
—
I
I
I
—
—
A/D converter VRT input
Non-connection
Analog data input
Analog +5V power supply
Analog ground
A/D converter VRB input; connect to analog ground
A/D converter VGR input; connect to analog ground
A/D test pin; normally low
Non-connection
Non-connection
Internal pull down
Absolute Maximum Ratings (Ta = 25°C, Vss = 0V)
Item
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
VDD
VI
VO
Topr
Tstg
Vss – 0.5 to +7.0
Vss – 0.5 to VDD + 0.5
Vss – 0.5 to VDD + 0.5
–20 to +75
–55 to +150
V
V
V
°C
°C
Symbol Ratings Unit
I/O Pin Capacitance (VDD = VI= 0V, f = 1MHz)
Item
Input pin capacitance
Output pin capacitance
Input/output pin capacitance
CIN
COUT
CI/O
9
10
11
11
10
pF
∗1
∗2
∗3
∗4
∗5
Symbol Min. Typ. Max. Unit Corresponding pins
∗1Input pins other than ∗2and ∗3
∗2SCLK
∗3BITI, DSLB, DSLA, DATB, DATA, TST5
∗4All output pins
∗5SDA
Pin
No. Symbol I/O Description Remarks
– 10 –
CXD2027Q/R
Electrical Characteristics
[DC characteristics] (VDD = 5V ± 0.25V, Vss = 0V, Ta = –20 to +75°C)
Item
Power consumption
Input/output voltage
Input
voltage
Input rise/fall time
Output voltage
PD
VI, VO
VIH
VIL
VIH
VIL
Vt+
Vt–
Vt+
–
Vt
–
tr, tf
VOH
VOL
VOH
VOL
VOH
VOL
VOL
VOL
VDD = 4.75 to 5.25V
IOH = –2mA
IOL = 4mA
IOH = –4mA
IOL = 4mA
IOH = –4mA
IOL = 8mA
IOL = 3mA
IOL = 6mA
180
Vss
0.7VDD
2.2
0.7VDD
0
VDD – 0.8
VDD – 0.8
VDD – 0.8
0
0
280
0.5
350
VDD
0.3VDD
0.8
0.3VDD
500
0.4
0.4
0.4
0.4
0.6
mW
V
V
ns
V
∗1
∗2
∗3
∗4
∗5
∗6
∗7
∗8
∗9
Symbol Measurement
conditions Min. Typ. Max. Unit Corre-
sponding
pins
CMOS input
TTL input
High level
Low level
Hysteresis voltage
∗1All pins
∗2Input pins other than ∗3and ∗4
∗3BITI, DSLB, DSLA, DATB, DATA, MUTE
∗4SDA, SCLK
∗5All input pins
∗6Output pins other than ∗7, ∗8and ∗9
∗7LNO, LPO, RPO, RNO
∗8BITO, CK2M, FRAM, DATO, CCI, TX
∗9SDA, SCLK
– 11 –
CXD2027Q/R
Input
leak
current
Output leak current
(I2C bus)
II
IIL
IIH
II
IOZ
VIN = VSS or VDD
VIN = VSS
VIN = VDD
VIN = VSS or VDD
VIN = VSS
–10
–40
40
–40
–10
–100
100
10
–240
240
40
–10
µA
µA
µA
µA
µA
∗1
∗2
∗3
∗4
∗5
Normal input pin
With pull-up
resistor
With pull-down
resistor
Bidirectional pin
(during input state)
∗1Input pins other than ∗2, ∗3and ∗4
∗2MRST
∗3TST0, TST1, TST2, TST3, TST4, SASL, TST6
∗4BITI, DSLB, DSLA, DATB, DATA, TST5
∗5SDA, SCLK
∗6MCKI, M23I
∗7MCKI, MCKO, M23I, M23O
∗8MCKO, M23O
[Oscillation cell electrical characteristics] (VDD = 5V ± 0.25V, Ta = –20 to +75°C)
Item Symbol Measurement
conditions Min. Typ. Max. Unit Corre-
sponding
pins
LVth
VIH
VIL
RFB
VOH
VOL
Logic threshold value
Input voltage
Feedback resistance
Output voltage
VIN = VSS or VDD
IOH = –12mA
IOL = 12mA
0.7VDD
250k
VDD/2
VDD/2
1M
0.3VDD
2.5M
VDD/2
V
V
V
Ω
V
∗6
∗7
∗8
Item Symbol Measurement
conditions Min. Typ. Max. Unit Corre-
sponding
pins
– 12 –
CXD2027Q/R
[Internal A/D converter characteristics]
Absolute Maximum Ratings (Ta = 25°C)
Item
Supply voltage
Input voltage (analog)
Input voltage (digital)
Reference voltage
AVD
AIN
RB, RT
+7.0
AVDto AVS
VDD to VSS
AVDto AVS
V
V
V
V
Symbol Ratings Unit
Item
Supply voltage
Reference input
voltage
Analog input
Operating ambient
temperature
AVD, AVS
l DVS– AVSl
RB
RT
AIN
Topr
4.75 to 5.25
0 to 100
0 to
to 3.75
100 to 300
(typ. 200)
typ.1.25
–20 to +75
V
mV
V
mVp-p
V
°C
Symbol Ratings Unit
Operating Conditions
Amplitude
DC level
– 13 –
CXD2027Q/R
[AC characteristics] (VDD = 5.0V ± 0.25V, Ta = 25°C)
Item
ALC characteristics
Carrier
regeneration
PLL pull-in range
Clock
regeneration
PLL pull-in range
Deviation from standard input level 200mVp-p
Pull-in frequency∗relative to 5.7272MHz.
Includes temperature characteristics (–20 to +75°C)
and supply voltage fluctuation (± 5%) of VCXO.
Pull-in frequency∗relative to 2.048MHz.
Includes temperature characteristics (–20 to +75°C)
and supply voltage fluctuation (± 5%) of VCXO.
±50 %
Hz
Hz
Conditions Min. Typ. Max. Unit
∗Performance guaranteed only when using constants of the recommended oscillation circuit.
22.909088MHz (for carrier regeneration PLL) VCXO circuit
PHAA M23I M23O
100K
2.7µ 68
390p (CH)
HVU359
22K
4.7K
0.01µ
12p (UJ)
X'tal
VC
L
: Daishinku AG8865C
: Hitachi HVU359
: Matsushita ELJ-FC series
24.576MHz (for clock regeneration PLL) VCXO circuit
PHAB MCKI MCKO
100K
330
1800p (CH)
HVU359
22K
4.7K
0.047µ
10p (UJ)
X'tal
VC : Daishinku AG8865C
: Hitachi HVU359
Upper
Lower
Upper
Lower
+750
–450
+300
–100
– 14 –
CXD2027Q/R
(VDD = 5.0V ± 0.25V, Ta = –20 to +75°C, CL= 60pF)
Item
BITI set-up time
DATA set-up time
DATB set-up time
BITI hold time
DATA hold time
DATB hold time
tsu1
th1
Value relative to CK2M fall
Value relative to CK2M fall
32
0
ns
ns
Symbol Conditions Min. Typ. Max. Unit
(VDD = 5.0V ± 0.25V, Ta = –20 to +75°C, CL= 60pF)
Item
BITO delay time
DATO delay time
NSYN delay time
FRAM delay time
DTUP delay time
CC1 delay time
AUD delay time
LRCK delay time
td1
td2
td3
td4
td5
td6
td7
td8
Value relative to CK2M fall
Value relative to BCLK fall
17
24
37
23
38
21
28
26
ns
ns
ns
ns
ns
ns
ns
ns
Symbol Conditions Min. Typ. Max. Unit
AAAAA
AA
AA
AA
AA
tsu1 th1
td1 to td6
td7 to td8
BITI, DATA, DATB
CK2M
CK2M
BITO, DATO, NSYN,
FRAM, DTUP, CC1
BCLK
AUD, LRCK
– 15 –
CXD2027Q/R
Internal 1-bit DAC analog characteristics
(fs = 48kHz, VDD = 5.0V, Ta = 25°C, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, B mode)
Item
S/N
THD + N
Output level
90
0.011
1.95
dB
%
V(rms)
(EIAJ) ∗1
(EIAJ)
∗2
Min. Typ. Max. Unit Remarks
∗1"A" characteristic weighting filter used
∗2When master clock is 256fs
The following circuit is used for analog characteristics measurement.
DATA Lch ANALOG
Rch
TEST DISC CXD2027Q/R ANALOG
CIRCUIT ANALOG TESTER
(ADVANTEST T7342)
CXD2027Q/R
LNO (RNO)
LPO (RPO)
130k
130k
47p
47p
5.4k
5.4k
4.7k 820p
4.7k
820p
4.7k
1800p
4.7k 4.7k
820p
0.015 22
12k
100
OUTPUT
– 16 –
CXD2027Q/R
Description of Functions
• ALC
This detects the fluctuation of the input QPSK modulated signal level and absorbs the fluctuation by
controlling A/D VRT. With this function, a signal is output from ALCO after PWM modulation, and should be
fed back to the RT pin after integration.
• Carrier regeneration
A 5.727272MHz carrier is regenerated.
The input QPSK modulated signal is A/D converted at a sample rate of 22.909088MHz (5.727272MHz ×4),
and control voltage is generated using that sampling position as phase error data. The control voltage is
output from the PHAA pin after PWM modulation, and controls VCXO, which consists of an internal
oscillation cell and external crystal.
• Clock regeneration
This is a PLL circuit with 24.576MHz clock. It is 512 ×fs, for use with the DAC.
Phase comparison is carried out using the regenerated I and Q signals and VCXO divided output, and
control voltage is generated. After PWM modulation, the control voltage is output from the PHAB pin, and
controls VCXO, which consists of an internal oscillation cell and external crystal.
• Data regeneration
A 2.048MHz bit stream is regenerated from the regenerated I and Q signals.
• Frame sync and master frame sync
Correlated detection and competitive counter format is used for sync protection. The number of rear
protection is set at three times, and that of front protection is set at 3, 5, 7, or 9 times.
Also, synchronizing to the master frame can be done when the master frame signal is being sent to the
control sign 14th bit. In this case, the number of rear protection is set to 2 times, and that of front protection
is set at 7, 9 or 11 times.
• Descramble
A superimposed PN signal is removed for BS.
Also, there is a built-in interface for an external descrambler unit.
• De-interleave
The data interleaved by the built-in 4kbit SRAM is returned to the correct data array.
• (63, 56) BCH sign error correction
This performs (63, 56) BCH sign error correction. Error capability is 1 error correction, 2 errors detection.
• Range bit BCH sign error correction
This performs (7, 3) BCH sign error correction. Error capability is 1 error correction, 2 errors detection.
When there are 2 errors, the previous value is held.
– 17 –
CXD2027Q/R
• Control sign integration detection and 8th range bit integration detection
Integration detection is carried out in units of 15 frames. When a match of 12/15 or more is obtained, a
defined control sign is detected. However, updating is every 18 frames.
When a match of 12/15 or more is not obtained, the previous value is held.
Further, synchronizing to the master frame can be done when the master frame signal is being sent to the
control sign 14th bit.
After integration detection, the control sign and range bit can be read by the I2C bus.
• 10 →14 bit data expansion
During A mode, the instantaneously compressed 10 bits of audio data are expanded to 14 bits according to
the range expansion rule. The lower bits of data are fixed at a set value during expansion, and the data is
treated as 16 bits.
• Upper bit majority detection
During B mode, this carries out upper bit majority detection and protects the upper bits.
• Mute signal generation
This performs muting by the external MUTE signal and internal logic, and also generates a mute signal
according to the mute setting from the I2C bus.
• Audio data interpolation
This receives the bit error detection signal and interpolation indication signal from majority detection, and
then carries out the average value interpolation or the previous value hold.
• Clock generation for D/A converter
This generates the clock for the DAC.
• Digital filter (DF) and de-emphasis
A 2ch 1-bit DAC with 2nd-order ∆∑ format noise shaper of quadruple oversampling filter is built in.
The output format is differential.
De-emphasis function corresponding to the mode is also built in.
• Audio interface
One of the following three output formats can be selected.
1) SONY: bit clock 32 fs/ MSB first/ 16 bits (for built-in D/A converter)
2) IIS: SONY format 1 BCLK delay
3) Bit clock 64fs / MSB first / 16 bits rearward truncation
• Digital interface
Conforms to the following digital audio interface format: type II form I(for consumer digital audio equipment)
•I
2
C bus interface
Control by microcomputer is carried out by the I2C bus I/F.
The slave address can be switched by controlling SASL; for low: D4, for high: D6.
– 18 –
CXD2027Q/R
• Output channel selection
The output channels provided are analog output for built-in D/A converter Lch/Rch, one output system for
external D/A audio output and one for digital audio output. Channel selection can be done easily through
the I2C bus.
Unused channels can be suppressed using the I2C bus.
• Audio output selection
Mode selection can be carried out via the I2C bus.
• Zero cross muting
The I2C bus can be used for zero cross muting.
When a mute signal is input, muting is not carried out until zero cross conditions are satisfied for 1 frame.
If these conditions are not met for 1 frame, muting is forced at the next frame.
Zero cross mute cancel is performed in frame units.
The conditions for zero cross are a change in audio data MSB, or when audio data value is between 00ffh
and ff00h.
• Description of mute function
A signal is treated as a mute signal in the following cases:
1) when asynchronous
2) control sign 7th bit (non-broadcast flag) or 16th bit (audio suppression flag) is high
3) 8th range bit (audio chargeable flag) is high (however, only channel for high)
4) number of double error flags goes over a certain TH level (error frequency detection mute)
5) audio carrier (5.7272MHz) can not be detected
6) an I2C bus mute flag is up
7) for other than audio
1. Asynchronous flag mute
Muting is applied when an asynchronous state exists. Also, the number of front sync protection can be
changed among 3, 5, 7 or 9 times by the I2C bus, so the conditions for asynchronous flag muting can be
changed.
2. Muting by control sign 7th and 16th bits
The control sign 7th bit is a flag indicating broadcast or non-broadcast. If this bit is high, muting is
applied. Also, the I2C bus can be used so that this bit does not apply muting.
The control sign 16th bit audio suppression flag is used when broadcast channels are switched and
when transmission modes are switched. Both use the value after integration detection.
3. Chargeable flag detection mute
The 8th range bit indicates if audio data is for a chargeable broadcast or not. For a chargeable
broadcast, a flag ("H") goes up in that bit's position. When this bit is high, the broadcast is detected as
chargeable and muting is applied. Further, the I2C bus can be used for each channel so that this bit
does not apply muting. The value after every 18 frames of integration detection is used.
– 19 –
CXD2027Q/R
4. Error frequency detection mute
Muting is applied after BCH (63, 56) sign error correction is executed for every 64 data, when the
number of double error detection flags goes over a certain TH (threshold value) level during a certain
number of frames. Also, the I2C bus can be used so that muting is not applied. The setting values are
indicated below.
Number of frames: 128, 256, 512, 1024
Up to 32 double errors can be detected in one frame, so 1/16, 1/8, 1/4 and 1/2 of the maximum
detections for each frame number are set as the TH levels.
Therefore, there are 16 possible combinations, and the value is set by the I2C bus.
The TH level for muting cancel is half of the TH value when muting is applied; in other words, 1/32, 1/16,
1/8 and 1/4, respectively.
5. Carrier detection mute
When the BS broadcast audio carrier frequency of 5.7272MHz can not be detected by the PSK
demodulator unit, muting is applied. Also, the I2C bus can be used so that muting is not applied.
6. I2C bus muting
The I2C bus can apply forced muting to analog and AUD outputs. TX output is locked to analog output.
7. Muting other than audio
Muting is done for other than audio mode when the control sign 2nd and 3rd, or 4th and 5th bits are "H, H".
– 20 –
CXD2027Q/R
External descramble I/F circuit example
COATEC and SkyPort units can be connected simultaneously.
BITO
BSTMI
BITI
BSTMO
DSLB
RGND
DATO
DATI
DATB
DSDO
DATA
DATI
DSLA
DASL
DATO
CXD2027Q/R
COATEC unit SkyPort unit
Unit connection
DASLC I2C BUS
register
DSLA
0
0
1
1
DSLB
0
1
0
1
Descramble format
COATEC, SkyPort ∗
SkyPort
COATEC
Internal
∗The COATEC unit and SkyPort unit can be connected simultaneously.
However, use the I2C bus to set DASLC at high when turning off the COATEC unit power supply.
– 21 –
CXD2027Q/R
Bit stream signal interface
Data interface after BCH error correction
BITO is output at falling sync.
2048 1 2 3 4 2047 2048 1 2
CK2M
BITO
DATO is output at falling sync.
2048 1 2 3 4 2047 2048 1 2
CK2M
DATO
FRAM
1ms
1 frame
Examples of error detection countermeasures for low C/N control sign and chargeable flag integration
detection
When C/N is low, NSYN frequently goes high level (asynchronous state).
In this case, problems such as wrong display or wrong detection of control sign 7th bit "broadcast/non-
broadcast" flag may occur due to incorrect integration detection. This can be improved using the
microcomputer software shown below.
Integration detection result can be updated only when NSYN is low level. Detection results of this IC are read
by the standard trigger of the microcomputer, and if the result values match for 5 to 6 times continuously, the
detection result is taken as an update for the system. It is also possible to update the integration detection
result by the continuous matching of 7 times or more. However, standard trigger cycle of the microcomputer
must be set about 18ms.
18ms 123456
NSYN
Control sign,Chargeable flag
(IC)
Control sign,Chargeable flag
(microcomputer)
→ integration detection results
Standard trigger
(microcomputer)
– 22 –
CXD2027Q/R
Description of I2C bus
The I2C bus is a bidirectional serial bus system developed by Philips. It can transmit and receive data
between multiple devices using two lines, SCLK (Serial Clock) and SDA (Serial Data).
This LSI has a built-in I2C bus interface circuit and is compatible with slave RECEIVER and slave
TRANSMITTER operation modes.
For the transfer configuration, both RECEIVER mode and TRANSMITTER mode have sub-addresses.
RECEIVER mode
The first byte is the slave address, the second byte is the sub-address, and data is read at the third byte
and after. Continuous data reading is also possible. After transmission of the first byte, the sub-address
is made (+1) automatically.
TRANSMITTER mode
The first byte is the slave address, and data is sent at the second byte and after. Continuous data output
is also possible. After transmission of the first byte, the sub-address is made (+1) automatically.
When there is no verification answer from the master, the SDA line is released.
To read data, the sub-address for the data to be read is written in RECEIVER mode, then the data is read
in TRANSMITTER mode.
The SDA line is released for initial reset, so the bus is not occupied. Also, even if the IC supply voltage falls
to 0V, the bus is not occupied. Nonetheless, please keep within the absolute maximum ratings.
This bus is compatible not only with standard mode (maximum 100kbit/s) but with high speed mode
(maximum 400kbit/s) as well.
– 23 –
CXD2027Q/R
• Specifications
Data write (RECEIVER mode)
to
7654321
SLAm Wm SUBm As DATAm AsAsSm
0 76543210 1 76543210 11
to DATAm As DATAm As P
76543210 1 176543210
to
7654321
SLAm Wm SUBm AsAsSm
0 76543210 11
to DATAsSLAm AmAsRmSrm DATAs XAm P
765432107654321 110187654321
Data read (RECEIVER mode & TRANSMITTER mode)
Symbol
∗m
∗s
S
Sr
P
SLA
SUB
DATA
W
R
A
XA
from master to slave
from slave to master
Start Condition
Start Condition
Stop Condition
Slave Address
Sub Address
Data
0 : Write Master →Slave
1 : Read Slave →Master
Clock pulse for Acknowledgement (SDA: L)
Acknowledgement none (SDA:H)
Description
– 24 –
CXD2027Q/R
I2C bus control table
SASL
Slave address
L
D4
H
D6
R/W
WR
RD
Sub-
address
00'H
01'H
02'H
03'H
04'H
05'H
06'H
07'H
00'H
01'H
02'H
A1S1
BUSMT1
OTSTP1
DASLC
(TSB0)
RGOF1
CC1
CC9
(L)
A1S2
BUSMT2
OTSTP2
C1SL
(TSB1)
RGOF2
CC2
CC10
(L)
A1S3
AMUTE
OTSTP3
LRSL
XEOFF
RGOF3
CC3
CC11
(L)
SIG
OTSTP4
IIS
XINH
RGOF4
CC4
CC12
(L)
A2S1
DOS1
MTOF0
NF1
BLFS
C2
PI1
OTSL
CC5
CC13
RG81
A2S2
DOS2
MTOF1
NF2
FPCC
C10
PI2
MFRAM
CC6
CC14
RG82
A2S3
DOS3
MTOF2
TH1
FPCB
XPRT
NR
(TEST2)
CC7
CC15
RG83
MTOF3
TH2
(TEST1)
DOMU
(TEST3)
CC8
CC16
RG84
MSB
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Data LSB
Blanks : Data not related to internal logic.
( ) : Data for testing. Fix to the default value.
(L) : Low is output.
MSB, LSB : Data is transmitted with MSB first.
Default data (default value of internal register after master reset)
W
WR
Sub-
address
00'H
01'H
02'H
03'H
04'H
05'H
06'H
07'H
0
—
0
0
0
—
(0)
1
1
—
0
0
0
—
(0)
1
0
—
1
0
0
—
1
1
—
—
0
0
0
—
0
1
0
0
1
0
1
1
0
0
1
1
1
1
0
1
0
0
0
0
1
0
1
0
0
(0)
—
—
1
1
(0)
0
—
(0)
MSB
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Data LSB
( ) : Always fix to the default value.
– 25 –
CXD2027Q/R
• BUS setting values for audio output selection
Sub-address 00'H 00000000'B
BIT No.
bit7
bit6
bit5
bit3
bit2
bit1
A1S1
A1S2
A1S3
A2S1
A2S2
A2S3
Audio output mode selection when using built-in DF/DAC
Audio output mode selection when using external DF/DAC
Name Description
Applications
A1S1
A2S1
DOS1
0
1
X
0
0
0
1
1
1
X
X
X
0
1
X
TV
independent
main + sub
main
sub
main + sub
main
sub
main + sub
main
sub
main
main
main
TV
independent
TV
independent
A mode
A mode
stereo
2ch mono
1ch mono
B mode
B mode
A mode
B mode
A1S2
A2S2
DOS2
X
X
X
1
0
0
1
0
0
1
0
0
X
X
X
A1S3
A2S3
DOS3
X
X
X
X
0
1
X
0
1
X
0
1
X
X
X
Sub-address 01'H 00000001'B
BIT No.
bit3
bit2
bit1
DOS1
DOS2
DOS3
Output mode selection when using digital interface
Name Description
Same setting method as for A1S1, A1S2 and A1S3
– 26 –
CXD2027Q/R
• Muting-related BUS setting values
Sub-address 02'H 00000010'B
BIT No.
bit7
bit6
bit3
bit2
bit1
bit0
BUSMT1
BUSMT2
MTOF0
MTOF1
MTOF2
MTOF3
Audio data mute when using built-in DF/DAC
Audio data mute when using external DF/DAC
Carrier detection mute
Non-broadcast flag mute
Error occurrence frequency mute
External mute (EXMU)
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
Name Description H L
Sub-address 03'H 00000011'B
BIT No.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
OTSTP1
OTSTP2
OTSTP3
OTSTP4
NF1
NF2
TH1
TH2
Signal suppression for external DF/DAC (AUD, LRCK, BCLK)
Signal suppression for external descramble
(CK2M, FRAM, DATO)
Control sign output suppression (NSYN, CCUP, CC1)
Built-in DF/DAC operation / non-operation selection
Error occurrence frequency mute setting (number of frames)
Error occurrence frequency mute setting (threshold value)
Non-
operation
Non-
operation
Non-
operation
Non-
operation
Operation
Operation
Operation
Operation
Name Description H L
bit3
NF1
0
0
1
1
bit2
NF2
0
1
0
1
Number of frames
128
256
512
1024
bit1
TH1
0
0
1
1
bit0
TH2
0
1
0
1
Threshold value
MUTE∗1
1/2
1/4
1/8
1/16
Cancel∗2
1/4
1/8
1/16
1/32
∗1MUTE when over this value
∗2MUTE cancel when below this value
– 27 –
CXD2027Q/R
BIT No.
bit7
bit6
bit5
bit4
bit2
bit1
bit0
RGOF1
RGOF2
RGOF3
RGOF4
MFRAM
TEST2
TEST3
Audio 1ch mute
Audio 2ch mute
Audio 3ch mute
Audio 4ch mute
Master frame sync processing
For testing (fix to low)
For testing (fix to low)
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
Name Description H L
• BUS setting values for chargeable flag mute
Sub-address 07'H 00000111'B
BIT No.
bit4 SIG Signal polarity selection for external descramble I/F Inverted Positive
Name Description H L
• BUS setting values for external I/F, etc.
Sub-address 02'H 00000010'B
Corresponding input pins : BITI, DATA, DATB
Corresponding output pins: CK2M, DATO, FRAM
– 28 –
CXD2027Q/R
Sub-address 04'H 00000100'B
BIT No.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DASLC
C1SL
LRSL
IIS
BLFS
FPCC
FPCB
TEST1
External descramble I/F control
CC1 (control sign 1st bit) output polarity inversion
LRCK polarity inversion
Audio output format switching
Selection of the number of front protection for frame sync protection and master
frame syncprotection selection
For testing (fix to low)
Inverted
Inverted
Positive
Positive
Refer to page 20.
Name Description H L
bit4
IIS
1
1
0
0
bit3
BLFS
1
0
1
0
Format
Prohibited
2) IIS
3) 64fs
1) SONY
bit2
FPCC
1
1
0
0
bit1
FPCB
1
0
1
0
The number of frame sync
front protection
3
5
7
9
BIT No.
bit3 OTSL DTUP pin output signal switching DED CCUP
Name Description H L
Sub-address 07'H 00000111'B
BIT No.
bit3
bit2
bit1
bit0
C2
C10
XPRT
DOMU
Digital copy allowed/prohibited selection
Channel status 10th bit
Parity inversion selection for digital interface
Mute for digital interface (TX is DC low)
Allowed
General
Transmission error
ON
Prohibited
BS
Normal
OFF
Name Description H L
• Digital I/F BUS setting values
Sub-address 05'H 00000101'B
The number of master
frame sync front protection
7
9
11
11
– 29 –
CXD2027Q/R
• DF and D/A converter-related BUS setting values
Write register
Sub-address 06'H 00000110'B
BIT No.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
TSB0
TSB1
XEOFF
XINH
PI1
PI2
NR
For testing (normally set to low regardless of input data)
Digital de-emphasis selection
DC dither selection
DC dither phase control Rch
DC dither phase control Lch
Modulation NR
ON
ON
Inverted
Inverted
ON
OFF
OFF
Positive
Positive
OFF
Name Description H L
• Control sign bit reading after integration correction
Sub-address 00'H 00010000'B
BIT No.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CC1
CC2
CC3
CC4
CC5
CC6
CC7
CC8
Control sign 1st bit
Control sign 2nd bit
Control sign 3rd bit
Control sign 4th bit
Control sign 5th bit
Control sign 6th bit
Control sign 7th bit
Control sign 8th bit
Mode selection
TV audio
Additional audio
Name Description
Sub-address 01'H 00010001'B
BIT No.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CC9
CC10
CC11
CC12
CC13
CC14
CC15
CC16
Control sign 9th bit
Control sign 10th bit
Control sign 11th bit
Control sign 12th bit
Control sign 13th bit
Control sign 14th bit
Control sign 15th bit
Control sign 16th bit
Expansion bits
Video scramble existent/non-existent
—
Master frame sync flag H: asynchronous, L: synchronous
Data suppression
Audio output suppression
Name Description
Suppression backup
Broadcast identification
Expansion bit
– 30 –
CXD2027Q/R
• Range 8th bit read after integration correction
Sub-address 02'H 00010010'B
BIT No.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
—
—
—
—
RG81
RG82
RG83
RG84
Low level fixed output
Range 8th bit (chargeable flag) 1ch
Range 8th bit (chargeable flag) 2ch
Range 8th bit (chargeable flag) 3ch
Range 8th bit (chargeable flag) 4ch
Name Description
– 31 –
CXD2027Q/R
Application Circuit
CXD2027R
61
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
62 NC10
VDD5
M23O
M23I
PHAA
ALCO
VSS9
NC12
TST7
RT
NC13
ADIN
ADVD
ADVS
RB
GR
TST0
NC14
NC15
NC11
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2NC0
VSS0
BITO
DSLB
DSLA
DATB
DATA
VDD0
CK2M
FRAM
DATO
CC1
BITI
TX
TST2
TST3
TST4
TST5
NC1
MRST
40
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
39
NC7
SASL
VSS6
VSS5
RNO
NC5
VDD2
RPO
VSS4
TST1
VSS3
LPO
VDD1
NC4
LNO
VSS2
VSS1
NC3
NC6
NC2
60
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
59
NC9
PHAB
MDKI
MCKO
VSS8
MUTE
TST8
VSS7
SCLK
SDA
VDD3
NSYN
DTUP
F256
BCLK
LRCK
AUD
TST6
NC8
VDD4
100k
330
24MHz
10p: CH
4.7k 22k
0.047µ/16V
HVU359TRF
D24 + 5V
0.1µ
47µ/16V
4.7k
D24 + 5V
4.7k
220
× 2
NSYN
D23 + 5V
47µ
16V
0.1µ
23MHz
12p: CH
68
2.7µ
390p: CH
0.01µ HVU359TRF
100k
22k
4.7k
47µ
16V
0.1µ
Dad + 5V
47µ/16V
1
3
3
1
2
2
5.6k
22k 2SC2712
(hFE ≥ 200)
2SA1162
2200p
12k
12k
0.01µ
1000p
BPF
10k
D24 + 5V
SW
REST
100
D24 + 5V
5.6k
× 5
COATEC
SkyPort
8 BITO
7 BITI
6 DSLB
5 DATO
4 DATB
3 CK2M
2 FRAM
1
7 DATO
6 DATA
5 DSLA
4 CK2M
3 FRAM
2 CC1
1
100
× 6
Dad + 5V
D23 + 5V
D24 + 5V
Aout + 12V
A + 5V
A + 5V
47µ/16V
9.1k 8.2k
9.1k 8.2k
120p: CH
9.1k 8.2k
9.1k 8.2k
150p
: CH
6.8k
2200p: CH
2
31
8
4
NJM4580E
30k
30k
2200p: CH
6.8k
150p: CH
15k
0.1µ
47µ/16V
2200p: CH
6.8k
150p: CH
15k
2
31
8
4
150p:
CH
6.8k
2200p: CH
NJM4580E
30k
30k
6
57
NJM4580E
1500p: CH
680 0.027µ
680 680
0.01µ
: CH
47µ/16V
Output
R ch
6
57
NJM4580E
1500p: CH
680 0.027µ
680 680
0.01µ
: CH
47µ/16V
Output
L ch
D24 + 5V
0.01µ 47µ/16V
5.6k
100 TX
BITO
100
× 4
1F256 2BCLK 3LRCK 4AUD 5
100
× 5
D_out
1
SCL 2
SDA 3I2C
ANALOG
INPUT
Aout + 12V
1800p: CH
120p: CH
120p: CH
120p: CH
0.1µ
0.1µ
5.6k
D24 + 5V
Buffer
0.1µ
0.1µ
Note 1) Circuit connection and constants are the same for the CXD2027Q.
Note 2) This circuit example shows digital de-emphasis off.
The analog de-emphasis circuit is included in the external circuit connected to the built-in
DAC.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to the same.
– 32 –
CXD2027Q/R
Package Outline Unit: mm
CXD2027Q
CXD2027R
SONY CODE
EIAJ CODE
JEDEC CODE
23.9 ± 0.4
20.0 – 0.1
1.0 0.4 – 0.1
+ 0.15
14.0 – 0.1
119
20
32
33
51
52
64
0.15 – 0.05
+ 0.1
2.75 – 0.15
16.3
0.1 – 0.05
+ 0.2
0.8 ± 0.2
M
± 0.12
0.15
+ 0.4
17.9 ± 0.4
+ 0.4
+ 0.35
64PIN QFP(PLASTIC)
QFP–64P–L01
∗QFP064–P–1420
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER/PALLADIUM
COPPER /42 ALLOY
PACKAGE STRUCTURE
PLATING
1.5g
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY
PACKAGE STRUCTURE
14.0 ± 0.2
∗ 12.0 ± 0.1
(0.22)
60 41
40
21
20
80
61
1
0.5 ± 0.08 0.18 – 0.03
+ 0.08
A
1.5 – 0.1
+ 0.2 0.127 – 0.02
+ 0.05
0.5 ± 0.2 (13.0)
0.1 ± 0.1
0.5 ± 0.2
0° to 10°
DETAIL A
80PIN LQFP (PLASTIC)
0.5g
LQFP-80P-L01
∗QFP080-P-1212-A
0.1
NOTE: Dimension “∗” does not include mold protrusion.
