2.0 Amp Output Current IGBT
Gate Drive Optocoupler
Technical Data
HCPL-3120
HCPL-J312
HCNW3120
Features
• 2.0 A Minimum Peak Output
Current
• 15 kV/µs Minimum Common
Mode Rejection (CMR) at
VCM = 1500 V
• 0.5 V Maximum Low Level
Output Voltage (VOL)
Eliminates Need for Negative
Gate Drive
• ICC = 5 mA Maximum Supply
Current
• Under Voltage Lock-Out
Protection (UVLO) with
Hysteresis
• Wide Operating VCC Range:
15 to 30 Volts
• 500 ns Maximum Switching
Speeds
• Industrial Temperature
Range: -40°C to 100°C
• Safety Approval
UL Recognized
2500 Vrms for 1 min. for
HCPL-3120
3750 Vrms for 1 min. for
HCPL-J312
5000 Vrms for 1 min. for
HCNW3120
CSA Approval
VDE 0884 Approved
VIORM = 630 Vpeak for
HCPL-3120 (Option 060)
VIORM = 891 Vpeak for
HCPL-J312
VIORM = 1414 Vpeak for
HCNW3120
BSI Certified (HCNW3120
only) (Pending)
Applications
• IGBT/MOSFET Gate Drive
• AC/Brushless DC Motor
Drives
• Industrial Inverters
• Switch Mode Power
Supplies
A 0.1
µ
F bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component
to prevent damage and/or degradation which may be induced by ESD.
Functional Diagram
TRUTH TABLE
VCC - VEE VCC - VEE
“POSITIVE GOING” “NEGATIVE GOING”
LED (i.e., TURN-ON) (i.e., TURN-OFF) VO
OFF 0 - 30 V 0 - 30 V LOW
ON 0 - 11 V 0 - 9.5 V LOW
ON 11 - 13.5 V 9.5 - 12 V TRANSITION
ON 13.5 - 30 V 12 - 30 V HIGH
1
3
SHIELD
2
4
8
6
7
5
N/C
CATHODE
ANODE
N/C
V
CC
V
O
V
O
V
EE
1
3
SHIELD
2
4
8
6
7
5
N/C
CATHODE
ANODE
N/C
V
CC
N/C
V
O
V
EE
HCNW3120HCPL-3120/J312
2
Description
The HCPL-3120 contains a
GaAsP LED while the HCPL-J312
and the HCNW3120 contain an
AlGaAs LED. The LED is optically
coupled to an integrated circuit
with a power output stage. These
optocouplers are ideally suited
for driving power IGBTs and
MOSFETs used in motor control
inverter applications. The high
operating voltage range of the
output stage provides the drive
voltages required by gate
controlled devices. The voltage
and current supplied by these
optocouplers make them ideally
suited for directly driving IGBTs
with ratings up to 1200 V/100 A.
For IGBTs with higher ratings,
the HCPL-3120 series can be
used to drive a discrete power
stage which drives the IGBT gate.
The HCNW3120 has the highest
insulation voltage of
VIORM = 1414 Vpeak in the
VDE0884. The HCPL-J312 has an
insulation voltage of
VIORM = 891 Vpeak and the
VIORM = 630 Vpeak is also
available with the HCPL-3120
(Option 060).
Selection Guide
Part Number HCPL-3120 HCPL-J312 HCNW3120 HCPL-3150*
Output Peak Current ( IO) 2.0 A 2.0 A 2.0 A 0.5 A
VDE0884 Approval VIORM = 630 Vpeak VIORM = 891 Vpeak VIORM = 1414 Vpeak VIORM = 630 Vpeak
(Option 060) (Option 060)
*The HCPL-3150 Data sheet available. Contact Agilent sales representative or authorized distributor.
Ordering Information
Specify Part Number followed by Option Number (if desired)
Example:
HCPL-3120#XXX
060 = VDE0884, VIORM = 630 Vpeak (HCPL-3120 only)
300 = Gull Wing Surface Mount Option
500 = Tape and Reel Packaging Option
Option 500 contains 1000 units (HCPL-3120/J312), 750 units (HCNW3120) per reel.
Other options contain 50 units (HCPL-3120/J312), 42 units (HCNW312) per tube.
Option data sheets available. Contact Agilent sales representative or authorized distributor.
3
0.635 ± 0.25
(0.025 ± 0.010) 12° NOM.
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.65 ± 0.25
(0.380 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
1.016 (0.040)
1.194 (0.047)
1.194 (0.047)
1.778 (0.070)
9.398 (0.370)
9.906 (0.390)
4.826
(0.190)
TYP.
0.381 (0.015)
0.635 (0.025)
PAD LOCATION (FOR REFERENCE ONLY)
1.080 ± 0.320
(0.043 ± 0.013)
4.19
(0.165)MAX.
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
Package Outline Drawings
HCPL-3120 Outline Drawing (Standard DIP Package)
HCPL-3120 Gull Wing Surface Mount Option 300 Outline Drawing
9.65 ± 0.25
(0.380 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A XXXXZ
YYWW
DATE CODE
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
5678
4321
5° TYP.
OPTION CODE*
0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
TYPE NUMBER
* MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
4
Package Outline Drawings
HCPL-J312 Outline Drawing (Standard DIP Package)
HCPL-J312 Gull Wing Surface Mount Option 300 Outline Drawing
9.80 ± 0.25
(0.386 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A XXXXZ
YYWW
DATE CODE
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
5678
4321
5° TYP.
OPTION CODE*
0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
TYPE NUMBER
* MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
0.635 ± 0.25
(0.025 ± 0.010) 12° NOM.
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.80 ± 0.25
(0.386 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
1.016 (0.040)
1.194 (0.047)
1.194 (0.047)
1.778 (0.070)
9.398 (0.370)
9.906 (0.390)
4.826
(0.190)
TYP.
0.381 (0.015)
0.635 (0.025)
PAD LOCATION (FOR REFERENCE ONLY)
1.080 ± 0.320
(0.043 ± 0.013)
4.19
(0.165)MAX.
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
5
1.00 ± 0.15
(0.039 ± 0.006)
7° NOM.
12.30 ± 0.30
(0.484 ± 0.012)
0.75 ± 0.25
(0.030 ± 0.010)
11.00
(0.433)
5
6
7
8
4
3
2
1
11.15 ± 0.15
(0.442 ± 0.006)
9.00 ± 0.15
(0.354 ± 0.006)
1.3
(0.051)
12.30 ± 0.30
(0.484 ± 0.012)
6.15
(0.242)
TYP.
0.9
(0.035)
PAD LOCATION (FOR REFERENCE ONLY)
1.78 ± 0.15
(0.070 ± 0.006)
4.00
(0.158)MAX.
1.55
(0.061)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.254 + 0.076
- 0.0051
(0.010+ 0.003)
- 0.002)
MAX.
HCNW3120 Outline Drawing (8-Pin Wide Body Package)
HCNW3120 Gull Wing Surface Mount Option 300 Outline Drawing
5
6
7
8
4
3
2
1
11.15 ± 0.15
(0.442 ± 0.006)
1.78 ± 0.15
(0.070 ± 0.006)
5.10
(0.201)MAX.
1.55
(0.061)
MAX.
2.54 (0.100)
TYP.
DIMENSIONS IN MILLIMETERS (INCHES).
7° TYP. 0.254 + 0.076
- 0.0051
(0.010+ 0.003)
- 0.002)
11.00
(0.433)
9.00 ± 0.15
(0.354 ± 0.006)
MAX.
10.16 (0.400)
TYP.
A 
HCNWXXXX
YYWW
DATE CODE
TYPE NUMBER
0.51 (0.021) MIN.
0.40 (0.016)
0.56 (0.022)
3.10 (0.122)
3.90 (0.154)
6
Reflow Temperature Profile
Regulatory Information
Agency/Standard HCPL-3120 HCPL-J312 HCNW3120
Underwriters Laboratory (UL) ✔✔✔
Recognized under UL 1577, Component Recognition
Program, Category, File E55361
Canadian Standards Association (CSA) ✔✔✔
File CA88324, per Component Acceptance
Notice #5
Verband Deutscher Electrotechniker (VDE) ✔✔✔
DIN VDE 0884 (June 1992) Option 060
British Standards Institute (BSI) Pending
Certification According to BS EN60065: 1994
(BS415:1994), BS EN60950: 1992 (BS7002:1992)
240
∆T = 115°C, 0.3°C/SEC
0
∆T = 100°C, 1.5°C/SEC
∆T = 145°C, 1°C/SEC
TIME – MINUTES
TEMPERATURE – °C
220
200
180
160
140
120
100
80
60
40
20
0
260
123456789101112
MAXIMUM SOLDER REFLOW THERMAL PROFILE
(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
Insulation and Safety Related Specifications
Value
HCPL- HCPL- HCNW
Parameter Symbol 3120 J312 3120 Units Conditions
Minimum External L(101) 7.1 7.4 9.6 mm Measured from input terminals to
Air Gap (Clearance) output terminals, shortest distance
through air.
Minimum External L(102) 7.4 8.0 10.0 mm Measured from input terminals to
Tracking (Creepage) output terminals, shortest distance
path along body.
Minimum Internal 0.08 0.5 1.0 mm Insulation thickness between emitter
Plastic Gap and detector; also known as distance
(Internal Clearance) through insulation.
Tracking Resistance CTI >175 >175 >200 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative
Tracking Index)
Isolation Group IIIa IIIa IIIa Material Group (DIN VDE 0110, 1/89,
Table 1)
7
VDE0884 Insulation Related Characteristics
HCPL-3120
Description Symbol Option 060 HCPL-J312 HCNW3120 Unit
Installation classification per
DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤150 V rms I-IV I-IV I-IV
for rated mains voltage ≤300 V rms I-IV I-IV I-IV
for rated mains voltage ≤450 V rms I-III I-III I-IV
for rated mains voltage ≤600 V rms I-III I-IV
for rated mains voltage ≤1000 V rms I-III
Climatic Classification 55/100/21 55/100/21 55/100/21
Pollution Degree (DIN VDE 0110/1.89) 2 2 2
Maximum Working Insulation Voltage VIORM 630 891 1414 Vpeak
Input to Output Test Voltage, Method b* VPR 1181 1670 2652 Vpeak
VIORM x 1.875 = VPR, 100% Production
Test, tm = 1 sec, Partial Discharge < 5pC
Input to Output Test Voltage, Method a* VPR 945 1336 2121 Vpeak
VIORM x 1.5 = VPR, Type and Sample
Test, tm = 60 sec, Partial Discharge < 5pC
Highest Allowable Overvoltage* VIOTM 6000 6000 8000 Vpeak
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values – maximum values
allowed in the event of a failure,
also see Figure 37.
Case Temperature TS175 175 150 °C
Input Current IS INPUT 230 400 400 mA
Output Power PS OUTPUT 600 600 700 mW
Insulation Resistance at TS, VIO = 500 V RS≥109≥109≥109Ω
*Refer to the VDE0884 section (page 1-6/8) of the Isolation Control Component Designer's Catalog for a detailed description of
Method a/b partial discharge test profiles.
Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data
shall be ensured by means of protective circuits. Surface mount classification is Class A in accordance with CECC 00802.
All Agilent data sheets report the
creepage and clearance inherent
to the optocoupler component
itself. These dimensions are
needed as a starting point for the
equipment designer when
determining the circuit insulation
requirements. However, once
mounted on a printed circuit
board, minimum creepage and
clearance requirements must be
met as specified for individual
equipment standards. For creep-
age, the shortest distance path
along the surface of a printed
circuit board between the solder
fillets of the input and output
leads must be considered. There
are recommended techniques
such as grooves and ribs which
may be used on a printed circuit
board to achieve desired creepage
and clearances. Creepage and
clearance distances will also
change depending on factors such
as pollution degree and insulation
level.
8
Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Power Supply Voltage (VCC - VEE) 15 30 Volts
Input Current (ON) HCPL-3120
IF(ON) 716 mA
HCPL-J312
HCNW3120 10
Input Voltage (OFF) VF(OFF) -3.0 0.8 V
Operating Temperature T
A-40 100 °C
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Note
Storage Temperature TS-55 125 °C
Operating Temperature T
A-40 100 °C
Average Input Current IF(AVG) 25 mA 1
Peak Transient Input Current IF(TRAN) 1.0 A
(<1 µs pulse width, 300 pps)
Reverse Input Voltage HCPL-3120 VR5 Volts
HCPL-J312 3
HCNW3120
“High” Peak Output Current IOH(PEAK) 2.5 A 2
“Low” Peak Output Current IOL(PEAK) 2.5 A 2
Supply Voltage (VCC - VEE) 0 35 Volts
Input Current (Rise/Fall Time) tr(IN) / tf(IN) 500 ns
Output Voltage VO(PEAK) 0V
CC Volts
Output Power Dissipation PO250 mW 3
Total Power Dissipation PT295 mW 4
Lead Solder HCPL-3120 260°C for 10 sec., 1.6 mm below seating plane
Temperature HCPL-J312
HCNW3120 260°C for 10 sec., up to seating plane
Solder Reflow Temperature Profile See Package Outline Drawings section
9
Electrical Specifications (DC)
Over recommended operating conditions (TA = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V,
VCC = 15 to 30 V, VEE = Ground) unless otherwise specified.
Parameter Symbol Device Min. Typ.* Max. Units Test Conditions Fig. Note
High Level IOH 0.5 1.5 A VO = (VCC - 4 V) 2, 3, 5
2.0 A VO = (V
CC - 15 V) 17 2
Low Level IOL 0.5 2.0 A VO = (VEE + 2.5 V) 5, 6, 5
2.0 A VO = (VEE + 15 V) 18 2
High Level V
OH (V
CC - 4) (V
CC - 3) V IO = -100 mA 1, 3, 6, 7
Output Voltage 19
Low Level VOL 0.1 0.5 V IO = 100 mA 4, 6,
Output Voltage 20
High Level ICCH 2.5 5.0 mA Output Open, 7, 8
Supply Current IF = 7 to 16 mA
Low Level ICCL 2.5 5.0 mA Output Open,
Supply Current VF = -3.0 to +0.8 V
Threshold Input IFLH HCPL-3120 2.3 5.0 mA IO = 0 mA, 9, 15,
Current Low HCPL-J312 1.0 VO > 5 V 21
to High HCNW3120 2.3 8.0
Threshold Input VFHL 0.8 V
Voltage High
to Low
Input Forward VFHCPL-3120 1.2 1.5 1.8 V IF = 10 mA 16
Voltage HCPL-J312 1.6 1.95
HCNW3120
Temperature ∆VF/∆TAHCPL-3120 -1.6 mV/°CI
F
= 10 mA
Coefficient HCPL-J312 -1.3
of Forward HCNW3120
Voltage
Input Reverse BVRHCPL-3120 5 V IR = 10 µA
Breakdown HCPL-J312 3 IR = 100 µA
Voltage HCNW3120
Input CIN HCPL-3120 60 pF f = 1 MHz,
Capacitance HCPL-J312 70 VF = 0 V
HCNW3120
UVLO Threshold VUVLO+ 11.0 12.3 13.5 V VO > 5 V, 22,
IF = 10 mA 34
VUVLO– 9.5 10.7 12.0
UVLO Hysteresis UVLOHYS 1.6
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
Output Current
Output Current
10
Switching Specifications (AC)
Over recommended operating conditions (T
A = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V,
VCC = 15 to 30 V, VEE = Ground) unless otherwise specified.
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Propagation Delay tPLH 0.10 0.30 0.50 µs Rg = 10 Ω, 10, 11, 16
Time to High Cg = 10 nF, 12, 13,
Output Level f = 10 kHz, 14, 23
Propagation Delay tPHL 0.10 0.30 0.50 µs
Time to Low
Output Level
Pulse Width PWD 0.3 µs17
Distortion
Propagation Delay PDD -0.35 0.35 µs 35, 36 12
Difference Between (tPHL - tPLH)
Any Two Parts
Rise Time tr0.1 µs23
Fall Time tf0.1 µs
UVLO Turn On tUVLO ON 0.8 µsV
O
> 5 V, IF = 10 mA 22
Delay
UVLO Turn Off tUVLO OFF 0.6 VO < 5 V, IF = 10 mA
Delay
Output High Level |CMH| 15 30 kV/µsT
A
= 25°C, 24 13, 14
Common Mode IF = 10 to 16 mA,
Transient VCM = 1500 V,
Immunity VCC = 30 V
Output Low Level |CML| 15 30 kV/µsT
A
= 25°C, 13, 15
Common Mode VCM = 1500 V,
Transient VF = 0 V,
Immunity VCC = 30 V
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
Duty Cycle = 50%
11
Package Characteristics
Over recommended temperature (TA = -40 to 100°C) unless otherwise specified.
Parameter Symbol Device Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output VISO HCPL-3120 2500 VRMS RH < 50%, 8, 11
Momentary HCPL-J312 3750 t = 1 min., 9, 11
Withstand Voltage** HCNW3120 5000 TA = 25°C 10, 11
Resistance RI-O HCPL-3120 1012 ΩVI-O = 500 VDC 11
(Input-Output) HCPL-J312
HCNW3120 1012 1013 TA = 25°C
1011 TA = 100°C
Capacitance CI-O HCPL-3120 0.6 pF f = 1 MHz
(Input-Output) HCPL-J312 0.8
HCNW3120 0.5 0.6
LED-to-Case θLC 467 °C/W Thermocouple 28
Thermal Resistance
LED-to-Detector θLD 442 °C/W
Thermal Resistance
Detector-to-Case θDC 126 °C/W
Thermal Resistance
*All typicals at TA = 25°C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Agilent Application
Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
located at center
underside of
package
Notes:
1. Derate linearly above 70°C free-air
temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs,
maximum duty cycle = 0.2%. This
value is intended to allow for
component tolerances for designs
with IO peak minimum = 2.0 A. See
Applications section for additional
details on limiting IOH peak.
3. Derate linearly above 70°C free-air
temperature at a rate of 4.8 mW/°C.
4. Derate linearly above 70°C free-air
temperature at a rate of 5.4 mW/°C.
The maximum LED junction tempera-
ture should not exceed 125°C.
5. Maximum pulse width = 50 µs,
maximum duty cycle = 0.5%.
6. In this test V
OH is measured with a dc
load current. When driving capacitive
loads VOH will approach VCC as IOH
approaches zero amps.
7. Maximum pulse width = 1 ms,
maximum duty cycle = 20%.
8. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥3000 Vrms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
9. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥4500 Vrms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
10. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥6000 Vrms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
11. Device considered a two-terminal
device: pins 1, 2, 3, and 4 shorted
together and pins 5, 6, 7, and 8
shorted together.
12. The difference between tPHL and tPLH
between any two HCPL-3120 parts
under the same test condition.
13. Pins 1 and 4 need to be connected to
LED common.
14. Common mode transient immunity in
the high state is the maximum
tolerable dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in the high state
(i.e., VO> 15.0 V).
15. Common mode transient immunity in
a low state is the maximum tolerable
dVCM/dt of the common mode pulse,
VCM, to assure that the output will
remain in a low state (i.e., V
O< 1.0 V).
16. This load condition approximates the
gate load of a 1200 V/75A IGBT.
17. Pulse Width Distortion (PWD) is
defined as |tPHL-tPLH| for any given
device.
12
Figure 7. ICC vs. Temperature. Figure 8. ICC vs. VCC.
Figure 4. VOL vs. Temperature. Figure 5. IOL vs. Temperature. Figure 6. VOL vs. IOL.
Figure 1. VOH vs. Temperature. Figure 2. IOH vs. Temperature. Figure 3. VOH vs. IOH.
(V
OH
– V
CC
) – HIGH OUTPUT VOLTAGE DROP – V
-40
-4
T
A
– TEMPERATURE – °C
100
-1
-2
-20
0
02040
-3
60 80
I
F
= 7 to 16 mA
I
OUT
= -100 mA
V
CC
= 15 to 30 V
V
EE
= 0 V
I
OH
– OUTPUT HIGH CURRENT – A
-40
1.0
T
A
– TEMPERATURE – °C
100
1.8
1.6
-20
2.0
02040
1.2
60 80
I
F
= 7 to 16 mA
V
OUT
= (V
CC
- 4 V)
V
CC
= 15 to 30 V
V
EE
= 0 V
1.4
(V
OH
– V
CC
) – OUTPUT HIGH VOLTAGE DROP – V
0
-6
I
OH
– OUTPUT HIGH CURRENT – A
2.5
-2
-3
0.5
-1
1.0 1.5
-5
2.0
I
F
= 7 to 16 mA
V
CC
= 15 to 30 V
V
EE
= 0 V
-4
100 °C
25 °C
-40 °C
V
OL
– OUTPUT LOW VOLTAGE – V
-40
0
T
A
– TEMPERATURE – °C
-20
0.25
020
0.05
100
0.15
0.20
0.10
40 60 80
V
F
(OFF) = -3.0 TO 0.8 V
I
OUT
= 100 mA
V
CC
= 15 TO 30 V
V
EE
= 0 V
I
OL
– OUTPUT LOW CURRENT – A
-40
0
T
A
– TEMPERATURE – °C
-20
4
020
1
100
2
3
40 60 80
V
F
(OFF) = -3.0 TO 0.8 V
V
OUT
= 2.5 V
V
CC
= 15 TO 30 V
V
EE
= 0 V
V
OL
– OUTPUT LOW VOLTAGE – V
0
0
I
OL
– OUTPUT LOW CURRENT – A
2.5
3
0.5
4
1.0 1.5
1
2.0
V
F(OFF)
= -3.0 to 0.8 V
V
CC
= 15 to 30 V
V
EE
= 0 V
2
100 °C
25 °C
-40 °C
I
CC
– SUPPLY CURRENT – mA
-40
1.5
T
A
– TEMPERATURE – °C
100
3.0
2.5
-20
3.5
02040
2.0
60 80
V
CC
= 30 V
V
EE
= 0 V
I
F
= 10 mA for I
CCH
I
F
= 0 mA for I
CCL
I
CCH
I
CCL
I
CC
– SUPPLY CURRENT – mA
15
1.5
V
CC
– SUPPLY VOLTAGE – V
30
3.0
2.5
3.5
20
2.0
25
I
F
= 10 mA for I
CCH
I
F
= 0 mA for I
CCL
T
A
= 25 °C
V
EE
= 0 V
I
CCH
I
CCL
13
Figure 9. IFLH vs. Temperature.
Figure 10. Propagation Delay vs. VCC. Figure 11. Propagation Delay vs. IF. Figure 12. Propagation Delay vs.
Temperature.
Figure 14. Propagation Delay vs. Cg.Figure 13. Propagation Delay vs. Rg.
I
FLH
– LOW TO HIGH CURRENT THRESHOLD – mA
-40
0
T
A
– TEMPERATURE – °C
100
3
2
-20
4
02040
1
60 80
5V
CC
= 15 TO 30 V
V
EE
= 0 V
OUTPUT = OPEN
HCPL-3120
I
FLH
– LOW TO HIGH CURRENT THRESHOLD – mA
-40
0
T
A
– TEMPERATURE – °C
-20
5
020
1
100
2
3
40 60 80
V
CC
= 15 TO 30 V
V
EE
= 0 V
OUTPUT = OPEN
4
HCPL-J312
IFLH – LOW TO HIGH CURRENT THRESHOLD – mA
-40
0
TA – TEMPERATURE – °C
-20
5
020
1
100
2
3
40 60 80
VCC = 15 TO 30 V
VEE = 0 V
OUTPUT = OPEN
4
HCNW3120
T
p
– PROPAGATION DELAY – ns
15
100
V
CC
– SUPPLY VOLTAGE – V
30
400
300
500
20
200
25
I
F
= 10 mA 
T
A
= 25 °C
Rg = 10 Ω
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
T
PLH
T
PHL
T
p
– PROPAGATION DELAY – ns
6
100
I
F
– FORWARD LED CURRENT – mA
16
400
300
500
10
200
12
V
CC
= 30 V, V
EE
= 0 V
Rg = 10 Ω, Cg = 10 nF
T
A
= 25 °C
DUTY CYCLE = 50%
f = 10 kHz
T
PLH
T
PHL
148
T
p
– PROPAGATION DELAY – ns
-40
100
T
A
– TEMPERATURE – °C
100
400
300
-20
500
02040
200
60 80
T
PLH
T
PHL
I
F
= 10 mA 
V
CC
= 30 V, V
EE
= 0 V
Rg = 10 Ω, Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
T
p
– PROPAGATION DELAY – ns
0
100
Rg – SERIES LOAD RESISTANCE – Ω
50
400
300
10
500
30
200
40
T
PLH
T
PHL
V
CC
= 30 V, V
EE
= 0 V
T
A
= 25 °C
I
F
= 10 mA 
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
20
T
p
– PROPAGATION DELAY – ns
0
100
Cg – LOAD CAPACITANCE – nF
100
400
300
20
500
40
200
60 80
T
PLH
T
PHL
V
CC
= 30 V, V
EE
= 0 V
T
A
= 25 °C
I
F
= 10 mA 
Rg = 10 Ω
DUTY CYCLE = 50%
f = 10 kHz
14
Figure 15. Transfer Characteristics.
Figure 16. Input Current vs. Forward Voltage.
Figure 17. IOH Test Circuit.
V
O
– OUTPUT VOLTAGE – V
0
0
I
F
– FORWARD LED CURRENT – mA
5
25
15
1
30
2
5
34
20
10
HCPL-3120 / HCNW3120
V
O
– OUTPUT VOLTAGE – V
0
0
I
F
– FORWARD LED CURRENT – mA
1
35
2
5
5
15
25
34
10
20
HCPL-J312
30
I
F
– FORWARD CURRENT – mA
1.10
0.001
V
F
– FORWARD VOLTAGE – VOLTS
1.60
10
1.0
0.1
1.20
1000
1.30 1.40 1.50
T
A
= 25°C
I
F
V
F
+
–
0.01
100
HCPL-3120
V
F
– FORWARD VOLTAGE – VOLTS
1.2 1.3 1.4 1.5
I
F
– FORWARD CURRENT – mA
1.71.6
1.0
I
F
+
T
A
= 25°C
–
HCPL-J312/HCNW3120
V
F
0.1
0.01
0.001
10
100
1000
0.1 µF
V
CC
= 15
to 30 V
1
3
I
F
= 7 to
16 mA +
–
2
4
8
6
7
5
+
–4 V
I
OH
15
Figure 20. VOL Test Circuit. Figure 21. IFLH Test Circuit.
Figure 19. VOH Test Circuit.Figure 18. IOL Test Circuit.
Figure 22. UVLO Test Circuit.
0.1 µF
V
CC
= 15
to 30 V
1
3
+
–
2
4
8
6
7
5
2.5 V
I
OL
+
–
0.1 µF
V
CC
= 15
to 30 V
1
3
I
F
= 7 to
16 mA +
–
2
4
8
6
7
5
100 mA
V
OH
0.1 µF
V
CC
= 15
to 30 V
1
3
+
–
2
4
8
6
7
5
100 mA
V
OL
0.1 µF
V
CC
= 15
to 30 V
1
3
I
F
+
–
2
4
8
6
7
5
V
O
> 5 V
0.1 µF
V
CC
1
3
I
F
= 10 mA +
–
2
4
8
6
7
5
V
O
> 5 V
16
Figure 24. CMR Test Circuit and Waveforms.
Figure 23. tPLH, tPHL, tr, and tf Test Circuit and Waveforms.
0.1 µF V
CC
= 15
to 30 V
10 Ω
1
3
I
F
= 7 to 16 mA
V
O
+
–
+
–
2
4
8
6
7
5
10 KHz
50% DUTY
CYCLE
500 Ω
10 nF
I
F
V
OUT
t
PHL
t
PLH
t
f
t
r
10%
50%
90%
0.1 µF
V
CC
= 30 V
1
3
I
F
V
O
+
–
+
–
2
4
8
6
7
5
A
+
–
B
V
CM
= 1500 V
5 V
V
CM
∆t
0 V
V
O
SWITCH AT B: I
F
= 0 mA
V
O
SWITCH AT A: I
F
= 10 mA
V
OL
V
OH
∆t
V
CM
δV
δt=
17
Applications Information
Eliminating Negative IGBT
Gate Drive (Discussion applies
to HCPL-3120, HCPL-J312, and
HCNW3120)
To keep the IGBT firmly off, the
HCPL-3120 has a very low
maximum VOL specification of
0.5 V. The HCPL-3120 realizes
this very low VOL by using a
DMOS transistor with 1 Ω
(typical) on resistance in its pull
down circuit. When the HCPL-
3120 is in the low state, the IGBT
gate is shorted to the emitter by
Rg + 1 Ω. Minimizing Rg and the
lead inductance from the HCPL-
3120 to the IGBT gate and
emitter (possibly by mounting the
HCPL-3120 on a small PC board
directly above the IGBT) can
eliminate the need for negative
IGBT gate drive in many applica-
tions as shown in Figure 25. Care
should be taken with such a PC
board design to avoid routing the
IGBT collector or emitter traces
close to the HCPL-3120 input as
this can result in unwanted
coupling of transient signals into
the HCPL-3120 and degrade
performance. (If the IGBT drain
must be routed near the HCPL-
3120 input, then the LED should
be reverse-biased when in the off
state, to prevent the transient
signals coupled from the IGBT
drain from turning on the
HCPL-3120.)
Figure 25. Recommended LED Drive and Application Circuit.
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF V
CC
= 18 V
1
3
+
–
2
4
8
6
7
5
270 Ω
HCPL-3120
+5 V
CONTROL
INPUT
Rg
Q1
Q2
74XXX
OPEN
COLLECTOR
18
Selecting the Gate Resistor
(Rg) to Minimize IGBT
Switching Losses. (Discussion
applies to HCPL-3120, HCPL-
J312 and HCNW3120)
Step 1: Calculate Rg Minimum
from the IOL Peak Specifica-
tion. The IGBT and Rg in Figure
26 can be analyzed as a simple
RC circuit with a voltage supplied
by the HCPL-3120.
(VCC – VEE - VOL)
Rg
≥
–––––––––––––––
IOLPEAK
(VCC – VEE - 2 V)
= –––––––––––––––
IOLPEAK
(15 V + 5 V - 2 V)
= ––––––––––––––––––
2.5 A
=7.2
Ω
≅ 8
Ω
The VOL value of 2 V in the pre-
vious equation is a conservative
value of VOL at the peak current
of 2.5A (see Figure 6). At lower
Rg values the voltage supplied by
the HCPL-3120 is not an ideal
voltage step. This results in lower
peak currents (more margin)
than predicted by this analysis.
When negative gate drive is not
used VEE in the previous equation
is equal to zero volts.
Figure 26. HCPL-3120 Typical Application Circuit with Negative IGBT Gate Drive.
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF V
CC
= 15 V
1
3
+
–
2
4
8
6
7
5
HCPL-3120
Rg
Q1
Q2
V
EE
= -5 V
–
+
270 Ω
+5 V
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
19
Step 2: Check the HCPL-3120
Power Dissipation and Increase Rg
if Necessary. The HCPL-3120 total
power dissipation (PT) is equal to the
sum of the emitter power (PE) and the
output power (PO):
PT = PE + PO
PE = IF•V
F•Duty Cycle
PO = PO(BIAS) + PO (SWITCHING)
= ICC•(V
CC - VEE)
+ ESW(RG, QG)•f
For the circuit in Figure 26 with IF
(worst case) = 16 mA, Rg = 8 Ω, Max
Duty Cycle = 80%, Qg = 500 nC,
f = 20 kHz and T
A max = 85C:
PE = 16 mA•1.8 V•0.8 = 23 mW
PO = 4.25 mA•20 V
+ 5.2
µ
J•20 kHz
= 85 mW + 104 mW
= 189 mW
> 178 mW (PO(MAX) @ 85C
= 250 mW−15C*4.8 mW/C)
The value of 4.25 mA for ICC in the
previous equation was obtained by
derating the ICC max of 5 mA
(which occurs at -40°C) to ICC max
at 85C (see Figure 7).
Since PO for this case is greater
than PO(MAX), Rg must be increased
to reduce the HCPL-3120 power
dissipation.
PO(SWITCHING MAX)
= PO(MAX) - PO(BIAS)
= 178 mW - 85 mW
= 93 mW
PO(SWITCHINGMAX)
ESW(MAX) = –––––––––––––––
f
93 mW
= ––––––– = 4.65
µ
W
20 kHz
For Qg = 500 nC, from Figure 27,
a value of ESW = 4.65 µW gives a
Rg = 10.3 Ω.
PE
Parameter Description
IFLED Current
VFLED On Voltage
Duty Cycle Maximum LED
Duty Cycle
PO Parameter Description
ICC Supply Current
VCC Positive Supply Voltage
VEE Negative Supply Voltage
ESW(Rg,Qg) Energy Dissipated in the HCPL-3120 for each
IGBT Switching Cycle (See Figure 27)
f Switching Frequency
Figure 27. Energy Dissipated in the
HCPL-3120 for Each IGBT Switching
Cycle.
Esw – ENERGY PER SWITCHING CYCLE – µJ
0
0
Rg – GATE RESISTANCE – Ω
50
6
10
14
20
4
30 40
12 Qg = 100 nC
Qg = 500 nC
Qg = 1000 nC
10
8
2
V
CC
= 19 V
V
EE
= -9 V
20
Thermal Model
(Discussion applies to
HCPL-3120, HCPL-J312
and HCNW3120)
The steady state thermal model
for the HCPL-3120 is shown in
Figure 28. The thermal resistance
values given in this model can be
used to calculate the tempera-
tures at each node for a given
operating condition. As shown by
the model, all heat generated
flows through θCA which raises
the case temperature TC
accordingly. The value of θCA
depends on the conditions of the
board design and is, therefore,
determined by the designer. The
value of θCA = 83°C/W was
obtained from thermal measure-
ments using a 2.5 x 2.5 inch PC
board, with small traces (no
ground plane), a single HCPL-
3120 soldered into the center of
the board and still air. The
absolute maximum power
dissipation derating specifications
assume a θCAvalue of 83°C/W.
From the thermal mode in Figure
28 the LED and detector IC
junction temperatures can be
expressed as:
TJE = PE •
(θLC||(θLD + θDC) + θCA)
θLC * θDC
+ PD•(–––––––––––––––– + θCA)
+ TA θLC + θDC + θLD
θLC • θDC
TJD = PE (––––––––––––––– + θCA)
θLC + θDC + θLD
+ PD•(θDC||( θLD + θLC) + θCA) + TA
Inserting the values for θLC and
θDC shown in Figure 28 gives:
TJE = P
E•(256°C/W + θCA)
+ P
D•(57°C/W + θCA) + TA
TJD = P
E•(57°C/W + θCA)
+ P
D•(111°C/W + θCA) + TA
For example, given PE = 45 mW,
PO = 250 mW, TA = 70°C and θCA
= 83°C/W:
TJE = PE•339°C/W + PD•140°C/W +
TA = 45 mW•339°C/W + 250 mW
•140°C/W + 70°C = 120°C
TJD = PE•140°C/W + PD•194°C/W +
TA = 45 mW•140C/W + 250 mW
•194°C/W + 70°C = 125°C
TJE and TJD should be limited to
125°C based on the board layout
and part placement (θCA) specific
to the application.
TJE = LED junction temperature
TJD = detector IC junction temperature
TC= case temperature measured at the center of the package bottom
θLC = LED-to-case thermal resistance
θLD = LED-to-detector thermal resistance
θDC = detector-to-case thermal resistance
θCA = case-to-ambient thermal resistance
∗θCA will depend on the board design and the placement of the part.
Figure 28. Thermal Model.
θ
LD
= 442 °C/W
T
JE
T
JD
θ
LC
= 467 °C/W θ
DC
= 126 °C/W
θ
CA
= 83 °C/W*
T
C
T
A
21
LED Drive Circuit
Considerations for Ultra
High CMR Performance.
(Discussion applies to HCPL-
3120, HCPL-J312, and
HCNW3120)
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC as
shown in Figure 29. The HCPL-
3120 improves CMR performance
by using a detector IC with an
optically transparent Faraday
shield, which diverts the capaci-
tively coupled current away from
the sensitive IC circuitry. How-
ever, this shield does not
eliminate the capacitive coupling
between the LED and optocoup-
ler pins 5-8 as shown in
Figure 30. This capacitive
coupling causes perturbations in
the LED current during common
mode transients and becomes the
major source of CMR failures for
Figure 29. Optocoupler Input to Output
Capacitance Model for Unshielded Optocouplers. Figure 30. Optocoupler Input to Output
Capacitance Model for Shielded Optocouplers.
1
3
2
4
8
6
7
5
CLEDP
CLEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
C
LEDO1
C
LEDO2
a shielded optocoupler. The main
design objective of a high CMR
LED drive circuit becomes
keeping the LED in the proper
state (on or off) during common
mode transients. For example,
the recommended application
circuit (Figure 25), can achieve
15 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in
the proper state are discussed in
the next two sections.
22
CMR with the LED On
(CMRH).
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED cur-
rent of 10 mA provides adequate
margin over the maximum IFLH of
5 mA to achieve 15 kV/µs CMR.
CMR with the LED Off
(CMRL).
A high CMR LED drive circuit
must keep the LED off (VF ≤
VF(OFF)) during common mode
transients. For example, during a
-dVcm/dt transient in Figure 31,
the current flowing through CLEDP
also flows through the RSAT and
VSAT of the logic gate. As long as
the low state voltage developed
across the logic gate is less than
VF(OFF), the LED will remain off
and no common mode failure will
occur.
The open collector drive circuit,
shown in Figure 32, cannot keep
the LED off during a +dVcm/dt
transient, since all the current
flowing through CLEDN must be
supplied by the LED, and it is not
recommended for applications
requiring ultra high CMRL
performance. Figure 33 is an
alternative drive circuit which,
like the recommended application
circuit (Figure 25), does achieve
ultra high CMR performance by
shunting the LED in the off state.
Rg
1
3
V
SAT
2
4
8
6
7
5
+
V
CM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dV
CM
/dt.
+5 V
+
–V
CC
= 18 V
• • •
• • •
0.1
µF
+
–
–
Figure 33. Recommended LED Drive
Circuit for Ultra-High CMR.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Figure 31. Equivalent Circuit for Figure 25 During
Common Mode Transient. Figure 32. Not Recommended Open
Collector Drive Circuit.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1
I
LEDN
23
Under Voltage Lockout
Feature. (Discussion applies to
HCPL-3120, HCPL-J312, and
HCNW3120)
The HCPL-3120 contains an
under voltage lockout (UVLO)
feature that is designed to protect
the IGBT under fault conditions
which cause the HCPL-3120
supply voltage (equivalent to the
fully-charged IGBT gate voltage)
to drop below a level necessary to
keep the IGBT in a low resistance
state. When the HCPL-3120
output is in the high state and the
supply voltage drops below the
HCPL-3120 VUVLO– threshold
(9.5 < VUVLO– < 12.0) the opto-
coupler output will go into the
low state with a typical delay,
UVLO Turn Off Delay, of 0.6 µs.
When the HCPL-3120 output is in
the low state and the supply
voltage rises above the HCPL-
3120 VUVLO+ threshold (11.0 <
VUVLO+ < 13.5) the optocoupler
output will go into the high state
(assumes LED is “ON”) with a
typical delay, UVLO Turn On
Delay of 0.8 µs.
Figure 34. Under Voltage Lock Out.
V
O
– OUTPUT VOLTAGE – V
0
0
(V
CC
- V
EE
) – SUPPLY VOLTAGE – V
10
5
14
10 15
2
20
6
8
4
12
(12.3, 10.8)
(10.7, 9.2)
(10.7, 0.1) (12.3, 0.1)
Figure 37. Thermal Derating Curve, Dependence of Safety Limiting Value
with Case Temperature per VDE 0884.
t
PLH
MIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t
PHL MAX
-
t
PHL MIN
) + (t
PLH MAX
-
t
PLH MIN
)
= (t
PHL MAX
-
t
PLH MIN
) – (t
PHL MIN
-
t
PLH MAX
)
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT1
I
LED2
V
OUT2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
t
PHL MIN
t
PHL MAX
t
PLH MAX
PDD* MAX
(t
PHL-
t
PLH
)
MAX
Figure 35. Minimum LED Skew for Zero Dead Time.
Figure 36. Waveforms for Dead Time.
tPHL MAX
tPLH MIN
PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
VOUT1
ILED2
VOUT2
ILED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
IPM Dead Time and
Propagation Delay
Specifications. (Discussion
applies to HCPL-3120, HCPL-
J312, and HCNW3120)
The HCPL-3120 includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
designs. Dead time is the time
period during which both the
high and low side power
transistors (Q1 and Q2 in Figure
25) are off. Any overlap in Q1
and Q2 conduction will result in
large currents flowing through
the power devices between the
high and low voltage motor rails.
OUTPUT POWER – P
S
, INPUT CURRENT – I
S
0
0
T
S
– CASE TEMPERATURE – °C
175
1000
50
400
12525 75 100 150
600
800
200
100
300
500
700
900
HCNW3120
P
S
(mW)
I
S
(mA)
OUTPUT POWER – P
S
, INPUT CURRENT – I
S
0
0
T
S
– CASE TEMPERATURE – °C
200
600
400
25
800
50 75 100
200
150 175
P
S
(mW)
125
100
300
500
700 I
S
(mA) FOR HCPL-3120
OPTION 060
I
S
(mA) FOR HCPL-J312
HCPL-3120 OPTION 060/HCPL-J312
To minimize dead time in a given
design, the turn on of LED2
should be delayed (relative to the
turn off of LED1) so that under
worst-case conditions, transistor
Q1 has just turned off when
transistor Q2 turns on, as shown
in Figure 35. The amount of delay
necessary to achieve this condi-
tions is equal to the maximum
value of the propagation delay
difference specification, PDDMAX,
which is specified to be 350 ns
over the operating temperature
range of -40°C to 100°C.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but it
does not tell a designer what the
maximum dead time will be. The
maximum dead time is equivalent
to the difference between the
maximum and minimum propaga-
tion delay difference specifica-
tions as shown in Figure 36. The
maximum dead time for the
HCPL-3120 is 700 ns (= 350 ns -
(-350 ns)) over an operating
temperature range of -40°C to
100°C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal tempera-
tures and test conditions since
the optocouplers under consider-
ation are typically mounted in
close proximity to each other and
are switching identical IGBTs.
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Data subject to change.
Copyright © 2003 Agilent Technologies, Inc.
Obsoletes 5965-7875E
February 10, 2003
5988-8710EN