General Description
The MAX5079 ORing MOSFET controller replaces
ORing diodes in high-reliability redundant, parallel-con-
nected power supplies. Despite their low forward-volt-
age drop, ORing Schottky diodes cause excessive
power dissipation at high currents. The MAX5079
allows for the use of low-on-resistance n-channel power
MOSFETs to replace the Schottky diodes. This results
in low power dissipation, smaller size, and elimination
of heatsinks in high-power applications.
The MAX5079 operates from 2.75V to 13.2V and includes
a charge pump to drive the high-side n-channel MOSFET.
Operation down to 1V is possible if an auxiliary voltage of
at least 2.75V is available. When the controller detects a
positive voltage difference between IN and BUS, the
n-channel MOSFET is turned on. The MOSFET is turned
off as soon as the MAX5079 sees a negative potential at
IN with respect to the BUS voltage, and is automatically
turned back on when the positive potential is restored.
Under fault conditions, the ORing MOSFET’s gate is
pulled down with a 1A current, providing an ultra-fast
200ns turn-off. The reverse voltage turn-off threshold is
externally adjustable to avoid unintentional turn-off of the
ORing MOSFET due to glitches at IN or BUS caused by
hot plugging the power supply.
Additional features include an OVP flag to facilitate
shutdown of a failed power supply due to an overvolt-
age condition, and a PGOOD signal that indicates if VIN
is either below the undervoltage lockout or VBUS is in
an overvoltage condition. The MAX5079 operates over
the -40°C to +85°C temperature range and is available
in a space-saving 14-pin TSSOP package.
Applications
Paralleled DC-DC Converter Modules
N+1 Redundant Power Systems
Servers
Base-Station Line Cards
RAID
Networking Line Cards
Features
o2.75V to 13.2V Input ORing Voltage
o1V to 13.2V Input ORing Voltage with 2.75V Aux
Voltage Present
o2A MOSFET Gate Pulldown Current During Fault
Condition
oUltra-Fast 200ns, MOSFET Turn-Off During Fault
Condition
oSupply Undervoltage and Bus Overvoltage
Detection
oPower-Good (PGOOD) and Overvoltage (OVP)
Outputs for Fault Detection
oSpace-Saving 14-Pin TSSOP Package
o-40°C to +85°C Operating Temperature Range
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX5079EUD -40°C to +85°C 14 TSSOP
19-3584; Rev 1; 3/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
BUS
COMMON
GATE BUSIN
POWER SUPPLY 1
(PS1)
POWER SUPPLY 2
(PS2)
1V TO 13.2V
VOUT1
VOUT2
UVLO OVI
GND
U1
STH
AUXIN
>2.75V
FTH
PGOOD
VBUS
RSTH
RFTH
RFTH
CSTH
RSTH CSTH
CEXT
CEXT
CBUS
N1
VIN
C+ C-
OVP
GATE BUSIN
1V TO 13.2V
UVLO OVI
U2
STH
AUXIN
>2.75V PGOOD
VBUS
N2
VIN
C+ C-
OVP
MAX5079
MAX5079
GNDFTH
SUB 75N 03-04
SUB 75N 03-04
Typical Operating Circuit
Pin Configuration appears at end of data sheet.
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
((VIN = 2.75V to 13.2V and VAUXIN = 0V) or (VIN = 1V and VAUXIN = 2.75V to 13.2V), RSTH = open, RFTH = 0, VUVLO = 1V, VOVI = 0V,
TA= -40°C to +85°C, unless otherwise noted. Typical values are at VIN = 12V and TA= +25°C. See the
Typical Operating Circuit
.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
GATE to GND ..............................................-0.3V to (VIN + 8.5V)
All Other Pins to GND.............................................-0.3V to +15V
Continuous Current Into Any Pin ......................................±50mA
Continuous Power Dissipation (TA= +70°C)
14-Pin TSSOP (derate 9.1mW/°C above +70°C) ......727.3mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
2.75 13.20 V
IN Input Voltage Range VIN VAUXIN ≥ 2.75V 1.0 13.2 V
AUXIN Input Voltage Range VAUXIN 0 13.2 V
(VAUXIN - VIN) High Threshold
(When GATE Connects Directly
to AUXIN) (Note 2)
VAUXIN_
THRESHOLD VAUXIN rising, IGATE = 10µA 4.2 4.9 5.7 V
(VAUXIN - VIN) Hysteresis (When
GATE Connects Directly To
AUXIN)
VAUXIN_
HYSTERESIS 40 mV
IN Supply Current IIN VUVLO = 1V, VIN > VBUS 4mA
AUXIN Leakage Current ILEAK_AUX VAUXIN = 0 20 µA
AUXIN Supply Current IAUXIN VUVLO = 1V, VAUXIN = VIN, = 3V;
VIN > VBUS 4mA
BUS Leakage Current ILEAK_BUS VIN = 13.2V, VBUS = 0 1 mA
BUS Supply Current IBUS VBUS = 13.2V, VBUS > VIN,
VBUS > VAUXIN 3mA
IN TO AUXIN SWITCHOVER
Switchover High Threshold VAUXIN_HIGH (VIN - VAUXIN), VAUXIN falling -60 +25 +200 mV
Switchover Low Threshold VAUXIN_LOW (VIN - VAUXIN), VAUXIN rising -200 -25 +50 mV
IN UNDERVOLTAGE LOCKOUT
Internal UVLO High Threshold VINTUVLO_HIGH VIN rising, VAUXIN = 0 or VAUXIN rising,
VIN = 1V, VBUS = 2.75V 2.0 2.25 2.5 V
Internal UVLO Hysteresis VINTUVLO_HYST VIN falling, VAUXIN = 0 or VAUXIN
falling, VIN = 1V 30 mV
External UVLO Threshold VUVLO VUVLO falling 0.568 0.6 0.632 V
External UVLO Hysteresis VUVLO_HYST 60 mV
External UVLO Input Bias IUVLO 500 nA
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
((VIN = 2.75V to 13.2V and VAUXIN = 0V) or (VIN = 1V and VAUXIN = 2.75V to 13.2V), RSTH = open, RFTH = 0, VUVLO = 1V, VOVI = 0V,
TA= -40°C to +85°C, unless otherwise noted. Typical values are at VIN = 12V and TA= +25°C. See the
Typical Operating Circuit
.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ORing MOSFET CONTROL
ORing MOSFET Turn-On Time tON CGATE = 10nF, CEXT = 100nF,
MOSFET gate threshold = 2V 10 25 µs
ORing MOSFET Forward Voltage
Threshold (Fast Comparator) VDTH (VIN - VBUS) rising, VAUXIN ≥ 2.75V 5 12.5 20 mV
RFTH = 0 -12 -24 -31
RFTH = 12kΩ-63 -104 -150
ORing MOSFET Reverse Voltage
Turn-Off Threshold (Fast
Comparator (VIN - VBUS))
VFTH
RFTH = 27kΩ, VIN ≥
VAUXIN ≥
2.75V -126 -204 -300
mV
ORing MOSFET Reverse Voltage
Blanking Time (Fast Comparator) tFBL VBUS = 2.8V, RFTH = 0,
VBUS - VIN = 0.3V 50 ns
Slow-Comparator Output Voltage
Threshold on STH VO_STH VIN ≥ 2.75V 0.95 1 1.05 V
RSTH open -0.1 -12 -24.0
RSTH = 500kΩ-25
ORing MOSFET Reverse Voltage
Turn-Off Threshold (Slow
Comparator (VIN - VBUS))
VSTH
RSTH = 64kΩ-100
mV
(VIN - VBUS) to ISTH
Transconductance (Slow
Comparator)
GM_STH VSTH = 0V 0.17 mS
STH floating 0.5 0.9 1.5
CSTH = 0.047µF 5
ORing MOSFET Reverse Voltage
Blanking Time (Slow
Comparator)
tSBL
CSTH = 0.22µF 14
ms
ORing MOSFET DRIVER
Gate-Charge Current IGATE CEXT = 100nF, VIN ≥ 2.75V 0.7 2 mA
VGATE = VIN, VIN = 5.1V, VBUS = 5V;
VOUT = 1V 0.9 2 6.8
VGATE ≥ VIN, VIN = 2.75V, VBUS = 3.5V 1.3
Gate Discharge Current (Note 3) IGATE.DIS_MIN
VGATE ≥ VIN, VIN = 12V, VBUS = 13.2V 3.2
A
VBUS = 3.5V, CGATE = 0.1µF 600
Gate Fall Time tFGATE VBUS = 3.5V, CGATE = 0.01µF 200 ns
Gate Discharge Current Delay
Time (Time from VIN Falling from
3.7V to 3V to VGATE = VIN)
tDIS_GATE VBUS = 3.5V 70 200 ns
Gate to IN Resistance RGATE_IN (VGATE - VIN) = 100mV; VIN ≥ 2.75V 900 Ω
Gate to IN Clamp Voltage VGAT E _ IN _ C L AM P IGATE = 10mA, VIN ≥ VBUS 8.5 11 V
2.7V < VIN < 13.2V 3.8
VIN = 13.2V 6.5 7 7.7
Gate-Drive Voltage (Measured
with Respect to VIN)(VGATE - VIN)
VIN = 2.75V 4.5 5 5.5
V
VIN Switchover Threshold to
Higher GATE Voltage (Note 4) VIN_SOTH+ 7.4 8 8.5 V
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
4 _______________________________________________________________________________________
Note 1: All devices are production tested at +25°C. Limits over temperature are guaranteed by design.
Note 2: Threshold is reached when charge pump turns off.
Note 3: Gate discharge current is guaranteed through the testing of gate fall time.
Note 4: VIN switchover threshold is VIN at which the gate-drive voltage (VGATE - VIN) goes from 5V to 7V, VIN rising and (VIN ≥VBUS).
ELECTRICAL CHARACTERISTICS (continued)
((VIN = 2.75V to 13.2V and VAUXIN = 0V) or (VIN = 1V and VAUXIN = 2.75V to 13.2V), RSTH = open, RFTH = 0, VUVLO = 1V, VOVI = 0V,
TA= -40°C to +85°C, unless otherwise noted. Typical values are at VIN = 12V and TA= +25°C. See the
Typical Operating Circuit
.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VIN Switchover Hysteresis
(Note 4) VIN_SOHYS 40 mV
External 70
Charge-Pump Frequency fCP Internal, VIN < 5V, VAUXIN < 5V 1100 kHz
PROTECTION
OVI Input Bias Current IOVI 500 nA
OVI Threshold VOVI_TH OVI rising 0.568 0.6 0.632 V
OVP Output Low Voltage VOVP_LOW VOVI = 1V, ISINK = 10mA 0.2 0.4 V
OVP Leakage Current IOVP_LEAK VIN = 2.75V, VOVP = 13.2V 1 µA
PGOOD Leakage Current IPG_LEAK VPGOOD = 13.2V 1 µA
PGOOD Output Low Voltage VPG_LOW ISINK = 2mA 0.2 0.4 V
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted. See the
Typical Operating Circuit
.)
AUXIN SUPPLY CURRENT
vs. TEMPERATURE (VIN = VBUS = 1V)
MAX5079 toc01
TEMPERATURE (°C)
IAUXIN (mA)
1109580655035205-10-25
1
2
3
0
-40 125
VAUXIN = 5V
VAUXIN = 10V
VAUXIN = 2.7V
GATE-CHARGE CURRENT vs. VIN
MAX5079 toc02
VIN (V)
IGATE (mA)
14128 104 62
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
015
131179351
TA = +25°C
TA = -40°C
TA = +125°C
TA = +85°C
SLOW-COMPARATOR REVERSE VOLTAGE
THRESHOLD (VSTH vs. RSTH)
MAX5079 toc03
RSTH (kΩ)
VSTH (V)
100
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0
10 1000
TA = -40°C, TA = +25°C,
TA = +85°C, TA = +125°C
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
_______________________________________________________________________________________
5
0
20
10
40
30
60
50
70
90
80
100
0 0.2 0.3 0.40.1 0.5 0.6 0.7 0.90.8 1.0
SLOW-COMPARATOR BLANKING TIME
tSTH vs. CSTH (RSTH = 180kΩ)
MAX5079 toc04
CSTH (µF)
tSTH (ms)
75mV OVERDRIVE
FAST-COMPARATOR REVERSE VOLTAGE
THRESHOLD (VFTH vs. RFTH)
MAX5079 toc05
RFTH (kΩ)
VFTH (V)
14012080 10040 6020
0.1
0.3
0.5
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
0
0
TA = +125°C
TA = +85°C
TA = -40°C
FAST-COMPARATOR RESPONSE TIME
MAX5079 toc06
TEMPERATURE (°C)
tRESPONSE (ns)
1109565 80-10 5 20 35 50-25
8
16
24
32
40
48
56
64
72
80
0
-40 125
VIN = 5V, VAUXIN = 0V
VIN = 1V, VAUXIN = 5V
VIN = 2.75V,
VAUXIN = 12V
VIN = 12V,
VAUXIN = 0V
CHARGE-PUMP FREQUENCY
vs. INPUT VOLTAGE
MAX5079 toc07
VIN (V)
fCP (kHz)
141210 11 1397 82 3 4 5 61
62
64
66
68
70
72
74
76
78
80
60
015
TA = +125°C
TA = +85°C
TA = +25°CTA = -40°C
GATE-CHARGE CURRENT vs. CEXT
MAX5079 toc08
CEXT (nF)
GATE-CHARGE CURRENT (mA)
10
0.5
1.0
1.5
2.0
2.5
3.5
4.0
4.5
5.0
6.0
0
1 100
VIN = 12V
3.0
5.5
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
MAX5079 toc09
VIN = 5V, VBUS = 5V,
VAUXIN = 0V, CSTH = 0,
RSTH = OPEN, RFTH = 0,
UVLO = IN
BUS
5V/div
IN
5V/div
GATE
10V/div
MOSFET REVERSE
CURRENT
5A/div
400ns/div
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted. See the
Typical Operating Circuit
.)
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted. See the
Typical Operating Circuit
.)
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
MAX5079 toc13
VIN = 5V, VBUS = 5V,
VAUXIN = 5V, CSTH = 0µF,
RSTH = OPEN, RFTH = 0,
UVLO = IN
BUS
5V/div
IN
5V/div
GATE
10V/div
MOSFET REVERSE
CURRENT
10A/div
1µs/div
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
MAX5079 toc12
VIN = 1V, VBUS = 1V,
VAUXIN = 5V, CSTH = 0µF,
RSTH = OPEN, RFTH = 0,
UVLO = IN
BUS
1V/div
IN
1V/div
GATE
5V/div
MOSFET REVERSE
CURRENT
10A/div
1µs/div
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
MAX5079 toc10
VIN = 2.75V, VBUS = 2.75V,
VAUXIN = 0V, CSTH = 0µF,
RSTH = OPEN, RFTH = 0,
UVLO = IN
BUS
2V/div
IN
2V/div
GATE
5V/div
MOSFET REVERSE
CURRENT
10A/div
1µs/div
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
MAX5079 toc11
VIN = 12V, VBUS = 12V,
VAUXIN = 0V, CSTH = 0µF,
RSTH = OPEN, RFTH = 0,
UVLO = IN
BUS
10V/div
IN
10V/div
GATE
20V/div
MOSFET REVERSE
CURRENT
10A/div
400ns/div
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted. See the
Typical Operating Circuit
.)
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
MAX5079 toc14
VIN = 12V, VBUS = 12V,
VAUXIN = 5V, CSTH = 0,
RSTH = OPEN, RFTH = 0,
UVLO = IN
BUS
10V/div
IN
10V/div
GATE
20V/div
MOSFET REVERSE
CURRENT
10A/div
1µs/div
POWER-UP WAVEFORM
MAX5079 toc15
VIN = 5.2V, VBUS = 4.9V,
IBUS = 5A
BUS
2V/div
CXN
10V/div
GATE
10V/div
IN
2V/div
40µs/div
POWER-UP WAVEFORM
MAX5079 toc16
VIN = 12.2V, VBUS = 11.9V,
IBUS = 5A
BUS
5V/div
CXN
10V/div
GATE
10V/div
IN
5V/div
20µs/div
POWER-UP WAVEFORM
MAX5079 toc17
VIN = 1.2V, VBUS = 1V,
VAUXIN = 5V, IBUS = 5A
BUS
500mV/div
CXN
10V/div
GATE
5V/div
IN
1V/div
20µs/div
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 CXN Negative Terminal of External Flying Charge-Pump Capacitor
2 CXP Positive Terminal of External Flying Charge-Pump Capacitor
3 OVP Open-Drain Active-Low Output. OVP sinks up to 10mA when VOVI ≥ 0.6V and VIN ≥ VBUS. OVP can be
used to drive an optodiode. Cycle power or pull UVLO low and then high to reset OVP.
4 PGOOD Open-Drain Active-Low Output. PGOOD pulls low when VUVLO ≤ 0.6V or VOVI ≥ 0.6V.
5 STH
ORing MOSFET Slow-Comparator Reverse Voltage Threshold and Blanking Time Setting Input. Connect
a resistor from STH to GND to set the threshold. Connect a capacitor from STH to GND to set the
blanking time. Leave STH floating to set the internal threshold (-12mV) and internal blanking time
(0.9ms).
6 FTH Fast-Comparator Reverse Threshold Setting. Connect a resistor from FTH to GND to set the fast-
comparator reverse voltage threshold from -24mV to -400mV.
7 OVI Overvoltage Comparator Input. Connect OVI to BUS through a resistive divider.
8 UVLO Undervoltage Lockout Comparator Input. Connect UVLO to IN through a resistive divider. The MAX5079
remains off until VUVLO rises above 0.66V. When VUVLO rises above 0.664V, VGATE is raised to VIN.
9 PGND Power Ground. Ground discharge path of the 2A GATE pulldown. Connect to external power ground
plane.
10 GATE Gate-Driver Output for n-Channel ORing MOSFET
11 BUS Bus Voltage-Sense Input. Connect BUS to the drain of the ORing MOSFET to sense the polarity of the
Bus Current. The MAX5079 receives its power from BUS when VIN and VAUXIN are not present.
12 GND Signal Ground. Connect to the low-level signal or analog ground.
13 IN Source Connection for ORing MOSFET and Supply Input for the MAX5079. Connect IN directly to the
power-supply voltage of 2.75V to 13.2V or 1V to 13.2V with VAUXIN ≥ 2.75V.
14 AUXIN Auxiliary Power-Supply Input. AUXIN supplies power to the IC when 1V ≤ VIN ≤ 2.75V. Connect AUXIN to
2.75V or higher if VIN is less than 2.75V.
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
_______________________________________________________________________________________ 9
AUXIN TO GATE
DIRECT CONNECTION
IN/AUXIN/BUS
SWITCHOVER
IN/AUXIN CHARGE-PUMP
SWITCHOVER
IN/AUXIN SUPPLY
SWITCHOVER
CHARGE
PUMP
0.6V
REFERENCE
IN
AUXIN
BUS
VSUPPLY
UVLO
OVI
PGOOD
LOGIC
OV
LOGIC
INTERNAL
UVLO
OVP PGOOD
0.9ms
DELAY
TOP LOGIC
VSUPPLY
CPOFF
UVLO OVI
N
PGND
CXP CXN GATE
PULLDOWN
REG
DRIVER
2A
PULLDOWN
PGOOD
GND
GATE TARGET SELECTOR
COMPARATOR VSUPPLY
VSUPPLY
VSUPPLY VSUPPLY
STH
20µA
GM
HYSTERESIS
CONTROL
FTH
BUS
IN
MAX5079
Figure 1. Block Diagram
Block Diagram
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
10 ______________________________________________________________________________________
Detailed Description
The MAX5079 ORing MOSFET controller drives an
external n-channel MOSFET and replaces ORing
diodes in high-reliability redundant power-management
systems or multiple paralleled power supplies. The
device has an internal charge pump to drive the high-
side n-channel ORing MOSFET. Additional features
include an adjustable undervoltage lockout threshold
(UVLO), output overvoltage detector (OVI/OVP), input
power-good detector (PGOOD), and two programma-
ble reverse voltage detectors to detect both fast and
slow rises in the reverse voltage across the ORing
MOSFET. The input power-supply range is from 2.75V
to 13.2V or down to 1V when an auxiliary supply of at
least 2.75V is available.
Operational Description
This section describes a detailed startup sequence and
behavior of the MAX5079 under different conditions of
VBUS and VIN. The MAX5079 powers up whenever VIN
is equal to or greater than 2.75V and VUVLO exceeds
the UVLO threshold of 0.66V. Operation with VIN down
to 1V is possible as long as VUVLO ≥0.6V and VAUXIN ≥
2.75V.
When VUVLO crosses the UVLO threshold, VGATE rises
to VIN and the charge pump turns on. The charge
pump delivers 2mA to charge the gate capacitance of
the external MOSFET connected to GATE. The constant
gate-charge current prevents large inrush currents from
the input supply. During turn-on, the MAX5079 will
ignore the reverse voltage at IN with respect to BUS.
This is necessary to avoid the unintentional turn-off of
the ORing MOSFET as the momentary inrush current
causes VIN to dip.
Figure 2 shows the MAX5079 in an ORing configuration
with three parallel power supplies (PS1, PS2, and PS3)
and three MAX5079s (U1, U2, and U3) provided by out-
puts VOUT1, VOUT2, and VOUT3. The following events
must be carefully considered to ensure proper function-
ality of the MAX5079 ICs.
1) VBUS is zero with a discharged capacitor (CBUS).
All three power supplies are turned ON simulta-
neously. VOUT1 comes up before VOUT2 and
VOUT3.
a. When VOUT1 turns on, the bus capacitors (CBUS)
begin charging from VOUT1 through N1’s body
diode. When VUVLO (U1) rises above the UVLO
threshold, the MAX5079 (U1) charge pump turns
on, and U1 monitors the positive potential from
VOUT1 to VBUS. When VOUT1 ≥VBUS the charge
pump brings GATE (U1) to 5.5V above VIN (U1) (or
7.5V above VIN depending on the magnitude of
VIN), by sourcing 2mA into N1’s gate capacitance.
This results in a less than 10µs turn-on time for the
FDB7045L used in the MAX5079 evaluation kit. The
fast turn-on is needed to assure that N1 is ON
before the rising VOUT1 reaches its steady-state
value. If the MOSFET is not turned on before VOUT1
reaches its steady state, VBUS may overshoot due
to the shorting of the 0.7V (forward drop) of N1’s
body diode. A higher VIN (U1) can more quickly
charge the charge-pump capacitor to 5V (or 7V),
while a lower VIN (U1) will take longer. Typically the
MOSFET turns on at VGS = 2.5V. Ensure that the
soft-start time of the power supply is large enough
(> 5ms) to avoid VOUT1 racing ahead and causing
VBUS to overshoot. Care must be taken to avoid the
overloading of VOUT1 by either limiting the source
current (using the current-sharing circuit) or delay
the loading of the BUS until all three power supplies
are up and running.
b. VOUT2 turns on and begins increasing the voltage
at IN (U2). VUVLO (U2) crosses the UVLO thresh-
old, the MAX5079 (U2) charge pump turns on and
U2 monitors the VOUT2 to VBUS voltage. When this
voltage difference becomes positive, GATE (U2)
begins sourcing 2mA into N2’s gate capacitance.
During turn-on, the reverse voltage turn-off circuit
is momentarily disabled. If VOUT2 is lower than
VOUT1, the external load-sharing controller circuit
of PS2 will try to increase VOUT2 to source current
from VOUT2. Assume VOUT2’s rise time is slow
enough not to cause any overshoot before N2
turns on and starts sharing the current.
c. VOUT3 turns on and U3 follows the same sequence
as U2. Eventually VOUT1, VOUT2, and VOUT3 reach
to equilibrium and sharing equal currents.
2) PS1 and PS2 are on and sharing the load when
PS3 is hot-inserted. PS3 will take the same
course as discussed in 1b above.
a. If VOUT3 is higher than VBUS, the BUS voltage will
increase to the new level determined by VOUT3.
The external load-sharing controller circuit of PS1
and PS2 will increase VOUT1 and VOUT2 to force
current sharing.
b. If VOUT3 is lower than VBUS, the load-sharing cir-
cuit of PS3 will increase VOUT3 to force the sharing
of current. This causes VOUT3 to increases above
VBUS. When this voltage difference becomes posi-
tive, GATE (U3) begins sourcing 2mA into N3’s
gate capacitance. Again, the reverse voltage turn-
off circuit is disabled momentarily, as discussed
before. The load-sharing circuit of PS3’s controller
will adjust VOUT3 so as to share the load current.
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
______________________________________________________________________________________ 11
c. During the hot insertion, a voltage spike can occur
at N1 and N2 and cause the (VOUT1 to VBUS) or
(VOUT2 to VBUS) voltage to go negative. If the
reverse voltage is below the fast-comparator
reverse voltage threshold (VFTH) but above the
programmed slow-comparator reverse voltage
threshold (VSTH), the spike is ignored for the pro-
grammed blanking time (tSTH). If the spike is
longer than 50ns (the fast-comparator internal
blanking time, tFBL) and larger than VFTH, then U1
and U2 will turn off N1 and N2 quickly. If the mag-
nitude of the voltage spike is above VSTH but less
than VFTH, and longer than the slow-comparator
blanking time (tSTH), U1 and U2 will turn off their
respective ORing MOSFETs (N1 and N2) by dis-
charging their GATE pins to PGND. The external
load-sharing circuit of PS1 and PS2 will force
VOUT1, VOUT2 above VBUS and N1, N2 will turn
back on through the 2mA current sourcing from
the GATE pins of U1 and U2. To avoid this situa-
tion the user can set the slow-comparator thresh-
old and blanking time depending on the
magnitude and duration of the voltage spikes.
d. PS3 fails to start. VUVLO (U3) threshold is not
crossed and U3 keeps N3 off.
e. PS3 goes into an overvoltage condition (no feed-
back). This causes VBUS to go into an overvoltage
condition increasing the loading on PS3 (provided
PS3 is able to supply all the required BUS cur-
rent). The current-sharing circuit will force the out-
puts of PS1 and PS2 to increase and eventually
saturate at their current-sharing voltage range.
Eventually only PS3 will have a positive voltage at
IN (U3) with respect to BUS. PS1 and PS2 will
have a negative voltage at VOUT1 and VOUT2 with
respect to BUS. All overvoltage inputs OVI (U1),
OVI (U2), and OVI (U3) sense the overvoltage, but
only OVP (U3) is asserted and latched low. GATE
(U3) is pulled to PGND and remains low as long
as VOVI ≥0.6V. When VOVI drops below 0.6V,
OVP remains low. However, U3 tries to turn on N3
unless VOUT3 is actively kept below the undervolt-
age lockout. Use OVP (U3) to either drive the
cathode of the optocoupler to shutdown PS3 from
the primary side or use OVP (U3) to fire an SCR
connected between VOUT3 and PGND.
3) PS1, PS2, PS3 are turned on with a shorted BUS.
Body diodes of N1, N2, and N3 conduct and short the
outputs of PS1, PS2, and PS3 to PGND. The power
supplies go into current limit (either in foldback or in
hiccup mode). The MAX5079s remain in undervoltage
lockout and keep all ORing MOSFETs off. The average
current sourced by PS1, PS2, or PS3 must be low
enough so as not to exceed the MOSFETs power dissi-
pation (PD= VFx ISHORT).
a. Use additional n-channel MOSFETs in series with
N1, N2, and N3 in the reverse direction to isolate
the power supplies from a shorted bus (Figure 3).
When power is turned on with a shorted bus, VIN_
(U1, U2, U3) increases and VUVLO rises above
the UVLO threshold. The MAX5079’s GATE out-
puts start charging the back-to-back ORing
MOSFET gates. The short-circuit condition at BUS
collapses VIN (U1), VIN (U2), and VIN (U3) send-
ing the MAX5079s into undervoltage lockout. This
turns off the MAX5079s entirely, including dis-
charging of the charge-pump storage capacitors.
The IN voltages come back up again crossing
UVLO (UVLO has 60mV hysteresis). A new cycle
starts and the time required to charge the charge-
pump capacitor and the turn-on time of the device
serves as a dead time. However, the dead time
may not be enough to reduce the dissipation in
the MOSFETs to an acceptable level. We advise
in keeping the short-circuit current low and pro-
viding hiccup current-limit protection to the power
supplies (PS1, PS2, and PS3).
b. Any other overload condition that would sustain the
IN voltage above UVLO, will keep the MOSFETs ON
continuously. Ensure the MOSFETs’ current
rating is higher than the maximum short-circuit
source current of the power supplies (PS1, PS2,
and PS3) to avoid damage to the ORing MOSFETs.
4) PS1, PS2, and PS3 are present and PS1 is short-
ed to GND.
VOUT1 drops below VBUS. The negative potential from
VIN (U1) to VBUS increases above the fast-comparator
threshold and lasts longer than the 50ns blanking time.
The MAX5079 (U1) takes its power from the voltage at
BUS (U1). Connect BUS close to CBUS, away from N1
so that U1 can receive power from BUS for a few
microseconds until N1 isolates BUS from IN. N1 is dis-
charged with 2A pulldown current, turning off N1 and
isolating PS1 from the BUS. The load-sharing circuit of
PS2 and PS3 will increase PS2 and PS3’s load current
until the total bus current requirement is satisfied.
For VIN (U1) < 2.75V, VAUXIN (U1) must come from an
independent source or remain on for some time (a few
microseconds) after VIN (U1) has failed. This minimum
on-time is needed to discharge the gate of the ORing
MOSFET and isolate PS1 from the BUS.
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
12 ______________________________________________________________________________________
5) PS1, PS2, PS3 are present and PS1 goes open.
PS1’s output capacitors discharge and VOUT1 drops
below VBUS. The MAX5079 (U1) senses a negative
potential from VOUT1 to VBUS. Depending upon how
fast PS1’s output capacitor discharges, N1 is turned off
due to the crossing of the fast- or slow-comparator
reverse voltage threshold. N1’s gate is discharged with
a 2A sink current into GATE (U1), turning off N1 and
isolating PS1 from the BUS. The load-sharing circuit of
PS2 and PS3 will increase PS2 and PS3’s load current
until the total BUS current requirement is satisfied.
6) PS1, PS2, PS3 are present and providing BUS
current. PS1 loses its feedback signal and goes
into an overvoltage condition.
VBUS increases and PS1 is loaded heavily. The current
share circuit forces VOUT2 and VOUT3 higher and they
will eventually saturate at their current-sharing voltage
range. Now only PS1 has a positive voltage at IN (U1)
with respect to BUS. All OVI inputs will sense the over-
voltage, but only OVP (U1) will be asserted and latched
low. GATE (U1) is pulled to PGND and remains low as
long as VOVI ≥0.6V. When VOVI drops below 0.6V, OVP
remains low, however, U1 tries to turn on N1 unless
VOUT1 is actively kept below the undervoltage lockout.
Use OVP (U1) to either drive the cathode of an opto-
coupler to shutdown PS1 from the primary, or fire an
SCR connected between IN (U1) and PGND.
Internal and External
Undervoltage Lockout
The internal undervoltage lockout monitors VIN and
VAUXIN and keeps the MAX5079 off until either voltage
reaches 2.75V. Once powered and VIN and/or VAUXIN
increase above 2.75V, the external UVLO is monitored.
The external undervoltage lockout feature monitors the
UVLO input and keeps the MAX5079 off (GATE shorted
to PGND) until VUVLO is greater than 0.66V. Connect a
resistive divider from IN to UVLO to GND or from
AUXIN to UVLO to GND to set the external undervolt-
age lockout threshold. We advise setting the external
UVLO ≥2.75V when AUXIN is not present.
Charge Pump
The MAX5079 has an internal charge pump that pumps
the gate-drive voltage (VGATE) high enough to fully
enhance the n-channel ORing MOSFET. The charge
pump is divided into two stages, a voltage doubler run-
ning at 70kHz using an external charge-pump capaci-
tor (CEXT), and a voltage tripler running at 1MHz using
an internal capacitor.
Connect an external capacitor (CEXT) between C+ and
C-. CEXT is charged from the higher of VIN or VAUXIN.
When the rising VIN becomes greater then VBUS (VUVLO
> 0.66V), CEXT is discharged through GATE into the
external MOSFET’s gate capacitance. The charge-
pump output is controlled by an internal regulator. The
charge-pump output at GATE sources typically 2mA.
This provides enough current drive to turn on a typical
ORing MOSFET in less than 10µs. When (VGATE - VIN)
reaches the target value (depending on VIN) the charge
pump is switched off (see the
Electrical Characteristics
table). Choose CEXT equal to 10 times the ORing
MOSFET gate capacitance. Too low of a capacitance
will delay the turn-on of the ORing MOSFET, while too
high of a capacitance can cause excessive ripple at
VIN. Bypass IN to GND with a 1µF ceramic capacitor to
avoid ripple at IN caused by the charge-pump switch-
ing. A clamp is placed internally between GATE and IN
to prevent (VGATE - VIN) from exceeding 11V. When VIN
is less than 5V, the charge pump (tripler) will increase
VGATE to 3x’s VIN to further reduce the RDSON of the
ORing MOSFET. The internal charge-pump booster
(voltage tripler) section is operational only when VIN and
VAUXIN are low and is turned off when VIN exceeds 5V.
When an additional supply is connected to AUXIN and
(VAUXIN - VIN) > 5V, both charge pumps are completely
disabled. In this case, the charging of the ORing gate
comes entirely from VAUXIN. In this case, the charge-
pump flying capacitor can be eliminated and C+, C-
can be left floating.
GATE Drive and Gate Pulldown
The MAX5079’s charge pump provides bias to charge
the ORing MOSFET gate above IN (the MOSFET’s
source). GATE source current and the turn-on speed
depends upon the value of CEXT (connected between
C+ and C-). Typically GATE can source up to 2mA with
CEXT = 0.1µF. This enables VGATE to rise to over 2V
above VIN in less than 10µs for an ORing MOSFET gate
capacitance of up to 10nF. With VIN < 5V, 12V MOSFETs
can be used for better RDSON characteristics. The
MAX5079 automatically selects the gate-drive voltage for
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
______________________________________________________________________________________ 13
VIN = 5V or VIN = 12V. For VIN ≤8V, the gate drive is 5V
above VIN and for VIN > 8V, the gate drive is 7V above
VIN. Lower gate drive means faster turn-off during faults,
while higher gatedrive means lower RDSON.
A fast and slow comparator monitor the voltage from IN
to BUS. When this voltage crosses the negative fast- or
slow-comparator threshold voltage for the blanking time
duration, GATE is pulled low by an internal 2A current
sink. Both comparators have an adjustable threshold
voltage. GATE is pulled low if any of the following con-
ditions are met.
1) VUVLO < 0.6V.
2) VAUXIN < 2.25V and VIN < 2.25V.
3) VOVI ≥0.6V.
4) VIN ≤(VBUS - VFTH) or VIN ≤(VBUS - VSTH) and
(VGATE - VIN) ≥1.8V.
When the above conditions are not true and VIN ≤
VBUS, GATE is shorted to IN. To insure that the external
MOSFET is quickly turned off, given the above condi-
tions, the GATE pulldown circuitry is powered by either
VIN, VAUXIN, or VBUS as long as any one is greater
then 2.75V.
Fast Comparator (FTH)
The fast comparator has a 50ns blanking time to avoid
unintentional turn-off of the ORing MOSFET during fast
transients. Additionally, the fast-comparator reverse
voltage threshold (VFTH) is programmable to suit the
need of an individual application. Higher VFTH thresh-
old allows for a larger glitch at BUS during a fault, but
improves the noise immunity. Lower VFTH reduces
glitches at BUS during a fault, however, with lower VFTH
spikes at BUS or glitches at IN can be read as faults,
unintentionally turning off the ORing MOSFET. Program
VFTH by connecting a resistor from FTH to GND. Adjust
VFTH to optimize the system performance using the fol-
lowing equation:
VFTH can be chosen from 24mV to 400mV. Connect
FTH to GND to choose the default 24mV threshold.
Slow Comparator (STH)
The MAX5079 includes a slow comparator to provide
glitch immunity during the hot insertion or removal of
paralleled power supplies. During the hot insertion,
BUS can see voltage spikes. These spikes can be
interpreted as a reverse voltage across the ORing
MOSFET. The amplitude of the spikes is proportional to
the load step seen by the parallel power supply while
the duration of the spikes depends on the loop
response of the load share and PWM controller.
The slow comparator has a programmable reverse volt-
age threshold (VSTH) as well as a programmable blank-
ing time (tSTH). An internal transconductance amplifier
converts the IN to BUS differential voltage to a current
and applies it to a parallel combination of resistor and
capacitor (RSTH and CSTH) from STH to GND. The
reverse threshold voltage (VSTH) for the slow compara-
tor is adjusted through RSTH. Use the following equa-
tion to calculate the RSTH for a required VSTH.
where GM_STH = 0.17mS.
The internal 500kΩresistance from the output of the
transconductance to GND can change the actual VSTH
if RSTH is above 50kΩ. In this case, see the
Typical
Operating Circuit
to select RSTH. Once RSTH is chosen,
the blanking time can be adjusted by CSTH. The delay
time is:
where tSBL = 0.9ms and is the default blanking time
generated by an internal digital delay. Leaving STH
floating results in a 12mV threshold voltage and a 0.9ms
blanking time. VOD (overdrive) is the difference between
actual reverse voltage (VBUS - VIN) and VSTH threshold.
Overvoltage Protection Latch (OVI/OVP)
OVI is the negative input to the overvoltage compara-
tor. The positive input of this comparator is connected
to the internal 0.6V reference and an open-drain output
is provided at OVP. The overvoltage sensing for over-
voltage protection is done at either IN or BUS. OVP
tRC V
VV t
DELAY STH STH STH
STH DD SBL
=××−−+
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥+ln 1
RV
VmVxG
STH STH M STH
=
()
−
1
12 _
RVmV
A
FTH FTH
=−24
667.µ
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
14 ______________________________________________________________________________________
latches low and the internal GATE pulldown circuitry is
activated and pulls GATE low only when both of the
conditions are satisfied:
1) VOVI ≥0.6V.
2) VIN ≥VBUS .
OVP can sink 10mA maximum. Cycle power or pull
UVLO low and then high again to reset the OVP latch.
GATE is pulled to PGND and remains low as long as
VOVI ≥0.6V. When VOVI drops below 0.6V, OVP remains
low. However, the MAX5079 tries to turn on the ORing
MOSFET unless VIN is actively kept below the undervolt-
age lockout. Use OVP to drive the cathode of an opto-
coupler to shut down the respective power supply from
the primary side (see the
Typical Application Circuit
of
Figure 2) or fire an SCR connected from IN to PGND.
Power-Good Comparator (PGOOD)
PGOOD output pulls low when VUVLO falls below 0.6V
or VOVI goes above 0.6V. PGOOD can sink a maximum
of 2mA.
Layout Guidelines
1) Place a 1µF ceramic input bypass capacitor physi-
cally close to IN and PGND. Connect IN as close as
possible to the source of the ORing MOSFET.
2) Sense the VBUS close to the bulk capacitor, away from
the drain of the ORing MOSFET. When IN is shorted to
ground during a fault, BUS is also pulled low through
the ORing MOSFET. In the absence of VAUXIN, the
MAX5079 loses both power inputs VIN and VBUS. This
can cause a delayed pulldown of the gate. Sensing
the BUS away from the ORing MOSFET drain, close to
the BUS bulk capacitor provides power to the
MAX5079 for a few microseconds, long enough to pull
down the ORing MOSFET gate and isolate BUS from a
shorted IN.
3) Place the charge-pump capacitor (CEXT) and the
slow-comparator blanking time adjustment capacitor
(CSTH) as close as possible to the MAX5079.
4) Run a thick trace from the gate of the ORing MOSFET
to GATE.
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
______________________________________________________________________________________ 15
Figure 2. Typical Application Circuit
BUS
COMMON
GATE BUSIN
POWER SUPPLY 1
(PS1)
TO PRIMARY-SIDE
SHUTDOWN
TO PRIMARY-SIDE
SHUTDOWN
POWER SUPPLY 2
(PS2)
1V TO 13.2V
VOUT1
VOUT2
UVLO OVI
U1
N1
N2
STH
AUXIN
>2.75V
PGOOD
VBUS
CBUS
VIN
C+ C-
MAX5079
OVP
GNDFTH
GATE BUSIN
1V TO 13.2V
UVLO OVI
U2
STH
AUXIN
>2.75V
PGOOD
VBUS
VIN
C+ C-
MAX5079
OVP
GNDFTH
TO PRIMARY-SIDE
SHUTDOWN
POWER SUPPLY 3
(PS3)
VOUT3
N3
GATE BUSIN
1V TO 13.2V
UVLO OVI
U3
STH
AUXIN
>2.75V
PGOOD
VBUS
VIN
C+ C-
MAX5079
OVP
GNDFTH
CSTH
RSTH
CEXT
RFTH
RFTH
CSTH
CEXT
RSTH
VBUS
VBUS
RFTH
CSTH
CEXT
RSTH
VBUS
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
16 ______________________________________________________________________________________
Figure 3. Parallel Supplies with Back-to-Back MOSFET
BUS
COMMON
GATE BUSIN
POWER SUPPLY 1
(PS1)
TO PRIMARY-SIDE
SHUTDOWN
TO PRIMARY-SIDE
SHUTDOWN
POWER SUPPLY 2
(PS2)
1V TO 13.2V
VOUT1
VOUT2
UVLO OVI
U1
STH
AUXIN
>2.75V
PGOOD
VBUS
CBUS
VIN
C+ C-
MAX5079
OVP
GNDFTH
GATE BUSIN
1V TO 13.2V
UVLO OVI
U2
STH
AUXIN
>2.75V
PGOOD
VBUS
VBUS
VIN
C+ C-
MAX5079
OVP
GNDFTH
CSTH
RSTH
CEXT
RFTH
CSTH
RSTH
CEXT
RFTH
VBUS
MAX5079
Chip Information
TRANSISTOR COUNT: 2,911
PROCESS: BiCMOS
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
______________________________________________________________________________________ 17
14
13
12
11
10
9
8
1
2
3
4
5
6
7
AUXIN
IN
GND
BUSPGOOD
OVP
CXP
CXN
TOP VIEW
MAX5079
GATE
PGND
UVLOOVI
FTH
STH
TSSOP
Pin Configuration
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
14 TSSOP U14-2 21-0066
MAX5079
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 2/05 Initial release —
1 3/09 Updated Electrical Characteristics table.2, 3
