KSZ8081MLX
10Base-T/100Base-TX
Physical Layer Transceiver
Revision 1.3
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August
19, 2015
Revision 1.3
General Description
The KSZ8081MLX is a single-supply 10Base-T/
100Base-TX Ethernet physical-layer transceiver for
transmission and reception of data over standard CAT-5
unshielded twisted pair (UTP) cable.
The KSZ808 1MLX is a hi gh l y-inte grat e d, c ompact s olution.
It reduces board cost and simplifies board layout by using
on-chip termination resistors for the differential pairs, by
integrating a low-noise regulator to supply the 1.2V core,
and by offering 1.8/2.5/3.3V digital I/O interface support.
The KSZ8081MLX offers the Media Independent Interface
(MII) for direct connection with MII-compliant Ethernet
MAC processors and switches.
The KSZ8 081 MLX provide s dia gnos t ic f eatures t o f ac ilitate
system bring-up and debugging in production testing and
in product deployment. Parametric NAND tree support
enables fault detection between KSZ8081MLX I/Os and
the board. Micrel LinkMD® TDR-based cable diagnostics
identify faulty copper cabling.
The KSZ8081MLX is available in the 48-pin, lead-free
LQFP package (see “Ordering Information”). Datasheets
and support documentation are available on website at:
www.micrel.com.
Features
• Single-chip 10Bas e-T/100Base-TX IEEE 802.3
compliant Ethernet transceiver
• MII interface support
• Back-to-back mode support for 100Mbps copper
repeater
• MDC/MDIO management interface for PHY register
configuration
• Programmable interrupt output
• LED outputs for link, activity, and speed status indication
• On-chip termination resistors for the differential pairs
• Baseline wander correction
• HP Auto MDI/MDI-X to reliably detect and correct
straight-through and crossover cable connections with
disable and en able opt ion
• Auto-negotiation to automaticall y select the highes t li n k -
up speed (10/100Mbps) and duplex (half/full)
• Power-down and power-saving modes
• LinkMD TDR-based cable diagnostics to identify faulty
copper cabling
• Parametric NAND Tree support for fault detection
between chip I/Os and the board
• HBM ESD rating (6kV)
Functional Diagram
Micrel, Inc.
KSZ8081MLX
August
19, 2015 2 Revision 1.3
Features (Continued)
• Loopback modes for diagnostics
• Single 3.3V power supply with VDD I/O options for 1.8V,
2.5V, or 3.3V
• Built-in 1.2V regulator for core
• Available in 48-pin 7mm x 7mm LQFP package
Applications
• Game consoles
• IP phones
• IP set-top boxes
• IP TVs
• LOM
• Printers
Ordering Information
Ordering Part Number Temperature
Range Package Lead
Finish Description
KSZ8081MLXCA 0°C to 70°C 48-Pin LQ FP Pb-Free MII, Commercial Temperature.
KSZ8081MLXIA(1) −40°C to 85°C 48-Pin LQFP Pb-Free MII, Industrial Temperature.
KSZ8081MLX-EVAL KSZ8081MLX Evaluation Board
(Mounted with KSZ8081MLX device in
commercial temperature)
Note:
1. Contact factory for lead time.
Micrel, Inc.
KSZ8081MLX
August
19, 2015 3 Revision 1.3
Revision History
Date Summary of Changes Revision
11/5/12 Initial release of new product datasheet. 1.0
2/6/14
Removed copper -wire bonding part numbers from Ordering Information.
Added note for TX C (Pin 33) and Register 16h, Bit [15] regarding a Reserved Factory Mode.
Removed TXC and RXC clock connections for MII Back-to-Back mode. This is a datasheet correction.
There is no change to the silicon.
Added series resistance and load capacitance for the crystal selection criteria.
1.1
11/25/14 Added silver-wire bonding part numbers to Ordering Information.
Updated Ordering Information to include Ordering Part Number and Device Marking. 1.2
08/19/15
Updated pin configurat ion dra wing, updated descriptions for pin 44 and NAND tree I/O testing section.
Add Max frequency for MDC in MII Management (MIIM) Interface section.
Updated Table 14 and Table 16.
Updated ordering information table for silver wire device as normal part number.
Updated pin 33 TXC and register 16h bit [15] description.
Updated description and add an equation in LinkMD section.
Add a note for Table 18.
Updated description for Figure 18.
Add a note for Figure 19.
Add HBM ESD rating in Features.
1.3
Micrel, Inc.
KSZ8081MLX
August
19, 2015 4 Revision 1.3
Contents
List of Figures .......................................................................................................................................................................... 6
List of Tables ........................................................................................................................................................................... 7
Pin Configuration ..................................................................................................................................................................... 8
Pin Description ........................................................................................................................................................................ 9
Strapping Options ................................................................................................................................................................. 12
Functional Description: 10Base-T/100Base-TX Transceiver ................................................................................................ 14
100Base-TX Transmit ........................................................................................................................................................ 14
100Base-TX Receive ......................................................................................................................................................... 14
Scrambler/De-Scrambler (100Base-TX Only) ................................................................................................................... 14
10Base-T Transmit ............................................................................................................................................................ 14
10Base-T Receive ............................................................................................................................................................. 15
SQE and Jabber Function (10Base-T Only) ...................................................................................................................... 15
PLL Clock Synthesizer ...................................................................................................................................................... 15
Auto-Negotiation ................................................................................................................................................................ 15
MII Interface .......................................................................................................................................................................... 17
MII Signal Definition ........................................................................................................................................................... 17
Transmit Clock (TXC) .................................................................................................................................................... 17
Transmit Enable (TXEN) ................................................................................................................................................ 17
Transmit Data[3:0] (TXD[3:0]) ........................................................................................................................................ 18
Receive Clock (RXC) ..................................................................................................................................................... 18
Receive Data Valid (RXDV) ........................................................................................................................................... 18
Receive Data[3:0] (RXD[3:0]) ........................................................................................................................................ 18
Receive Error (RXER) .................................................................................................................................................... 18
Carrier Sense (CRS) ...................................................................................................................................................... 18
Collision (COL) ............................................................................................................................................................... 18
MII Signal Diagram ............................................................................................................................................................ 18
Back-to-Back Mode – 100Mbps Copper Repeater ............................................................................................................... 20
MII Back-to-Back Mode ..................................................................................................................................................... 20
MII Management (MIIM) Interface ......................................................................................................................................... 21
Interrupt (INTRP) ................................................................................................................................................................... 21
HP Auto MDI/MDI-X .............................................................................................................................................................. 21
Straight Cab le .................................................................................................................................................................... 22
Crossover Cable ................................................................................................................................................................ 23
Loopback Mode ..................................................................................................................................................................... 24
Local (Digital) Loopback .................................................................................................................................................... 24
Remote (Analog) Loopback ............................................................................................................................................... 25
LinkMD® Cab le Di agn os tic .................................................................................................................................................... 26
Usage ............................................................................................................................................................................. 26
NAND Tree Support .............................................................................................................................................................. 27
NAND Tree I/O Testing ..................................................................................................................................................... 28
Power Manag ement .............................................................................................................................................................. 29
Power-Saving Mode .......................................................................................................................................................... 29
Energy-Detect Power-Down Mode .................................................................................................................................... 29
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KSZ8081MLX
August
19, 2015 5 Revision 1.3
Power-Down Mode ............................................................................................................................................................ 29
Slow-Oscillator Mode ......................................................................................................................................................... 29
Reference Circuit for Power and Ground Connections ......................................................................................................... 30
Typical Current/Power Consumption .................................................................................................................................... 31
Register Map ......................................................................................................................................................................... 33
Register Description .............................................................................................................................................................. 34
Absolute Maximum Ratings .................................................................................................................................................. 44
Operating Ratings ................................................................................................................................................................. 44
Electrical Characteristics ....................................................................................................................................................... 44
Timing Diagrams ................................................................................................................................................................... 46
MII SQE Timing (10Base-T) .............................................................................................................................................. 46
MII Transmit Timing (10Base-T) ........................................................................................................................................ 47
MII Receive Timing (10Base-T) ......................................................................................................................................... 48
MII Transmit Timing (100Base-TX) ................................................................................................................................... 49
MII Receive Timing (100Base-TX) .................................................................................................................................... 50
Auto-Negotiation Timing .................................................................................................................................................... 51
MDC/MDIO Timing ............................................................................................................................................................ 52
Power-Up/Reset Timing .................................................................................................................................................... 53
Reset Circuit .......................................................................................................................................................................... 54
Reference Circuits − LED Strap-In Pins ................................................................................................................................ 55
Reference Clock − Connection and Selection ...................................................................................................................... 56
Magnetic − Connection and Selection .................................................................................................................................. 57
Package Information and Recommended Land Pattern ....................................................................................................... 59
Micrel, Inc.
KSZ8081MLX
August
19, 2015 6 Revision 1.3
List of Figures
Figure 1. Auto-Negotiation Flow Chart ................................................................................................................................ 16
Figure 2. KSZ8081MLX MII Interface ................................................................................................................................. 19
Figure 3. KSZ8081MLX to KSZ8081MLX Back-to-Back Copper Repeater ........................................................................ 20
Figure 4. T ypical Stra ig ht Cabl e Co nnect io n ...................................................................................................................... 22
Figure 5. Typical Crossover Cable Connection .................................................................................................................. 23
Figure 6. Local (Digital) Loopback ...................................................................................................................................... 24
Figure 7. Remote (Analog) Loopback ................................................................................................................................. 25
Figure 8. KSZ8081MLX Power and Ground Connections .................................................................................................. 30
Figure 9. MII SQE Timing (10Base-T) ................................................................................................................................ 46
Figure 10. MII Transmit Timing (10Base-T) .......................................................................................................................... 47
Figure 11. MII Receive Timing (10Base-T) ........................................................................................................................... 48
Figure 12. MII Transmit Timing (100Base-TX) ...................................................................................................................... 49
Figure 13. MII Receive Timing (100Base-TX) ....................................................................................................................... 50
Figure 14. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................. 51
Figure 15. MDC/ MDIO Timing ............................................................................................................................................... 52
Figure 16. Power -Up/Reset Timing ....................................................................................................................................... 53
Figure 17. Recom mended Res et Circ uit ............................................................................................................................... 54
Figure 18. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ...................................................... 54
Figure 19. Reference Circuits for LED Strapping Pins ......................................................................................................... 55
Figure 20. 25MHz Crystal/Oscillator Reference Clock Connection ...................................................................................... 56
Figure 21. Typical Magnetic Interface Circuit ........................................................................................................................ 57
Micrel, Inc.
KSZ8081MLX
August
19, 2015 7 Revision 1.3
List of Tables
Table 1. MII Signal Definition .............................................................................................................................................. 17
Table 2. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater) ........................................... 20
Table 3. MII Management Frame Format for the KSZ8081MLX ........................................................................................ 21
Table 4. MDI/MDI-X Pin Definition ...................................................................................................................................... 22
Table 5. NAND Tree Test Pin Order for KSZ8081MLX ...................................................................................................... 27
Table 6. KSZ80 81 Po wer Pin Desc r iption ........................................................................................................................... 30
Table 7. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V) ........................................................... 31
Table 8. Typical Current/Power Consumption (VDDA _3.3 = 3.3 V, VDDIO = 2.5V ) ........................................................... 31
Table 9. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V) ........................................................... 32
Table 10. MII SQE Timing (10Base-T) Parameters .............................................................................................................. 46
Table 11. MII Transmit Timing (10Base-T) Parameters ....................................................................................................... 47
Table 12. MII Receive Timing (10Base-T) Parameters ........................................................................................................ 48
Table 13. MII Transmit Timing (100Base-TX) Parameters ................................................................................................... 49
Table 14. MII Receive Timing (100Base-TX) Parameters .................................................................................................... 50
Table 15. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ................................................................................ 51
Table 16. MDC/MDIO Timing Parameters ............................................................................................................................ 52
Table 17. Power-Up/Reset Timing Parameters .................................................................................................................... 53
Table 18. 25MHz Crystal / Reference Clock Selection Criteria ............................................................................................ 56
Table 19. Magnetics Selection Criteria ................................................................................................................................. 58
Table 20. Compatible Single-Port 10/100 Magnetics ........................................................................................................... 58
Micrel, Inc.
KSZ8081MLX
August
19, 2015 8 Revision 1.3
Pin Configuration
48-Pin 7mm × 7mm LQFP
Micrel, Inc.
KSZ8081MLX
August
19, 2015 9 Revision 1.3
Pin Description
Pin Number Pin Name Type
(2)
Pin Function
1 GND GND Ground.
2 GND GND Ground.
3 GND GND Ground.
4 VDD_1.2 P 1.2V Core VDD (power supplied by KSZ8081MLX). Decouple with 2.2µF and 0.1µF
capacitors to ground, and join with Pin 31 by power trace or plane.
5 NC − No Connect. This pin is not bonded and can be left floating.
6 NC − No Connect. This pin is not bonded and can be left floa tin g.
7 VDDA_3.3 P 3.3V Analog VDD.
8 NC − No Connect. This pin is not bonded and can be left floating.
9 RXM I/O Physical Receive or Transmit S ignal (− differential).
10 RXP I/O Physical Receive or Transmit Signal (+ differential).
11 TXM I/O Physical Transmit or Receiv e Signal (− differential).
12 TXP I/O Physical Transmit or Receiv e Signal (+ differential).
13 GND Gnd Ground.
14 XO O Crystal Feedback for 25MHz Crystal. This pin is a no connect if an oscillator or
external clock source is used.
15 XI I Crystal / Oscillator / External Clock Input (25MHz ±50ppm).
16 REXT I Set PHY Transmit Output Current. Con ne ct a 6.49 kΩ resistor to ground on this pin.
17 GND GND Ground.
18 MDIO Ipu/Opu M anagement Int erf ac e (MII) Data I/O. This pin has a weak pull-up, is ope n-drain, and
requires an external 1.0kΩ pull-up resistor.
19 MDC Ipu Management Inter f ac e (M I I) Clock Input . This clock pin is synchronous to the MDIO
data pin.
20 RXD3/
PHYAD0 Ipu/O MII Mod e: MII Receive Data Output[3]
(
3
)
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] at the de-
assertion of reset. See the Strapping Options section for details.
21 RXD2/
PHYAD1 Ipd/O MII Mod e: MII Receive Data Output[2](3)
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] at the de-
assertion of reset. See the Strapping Options section for details.
Notes:
2. P = Power supply.
GND = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull -up (see El ect ric al Characteris t ics for value).
Ipd = Input with internal pull -down (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electri cal Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characterist i cs for value) during power-up/reset; output pi n otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Charact eri st ics f or value) and output with int ernal pull-up (s ee Elect rical Charact erist ic s for
value).
3. MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] pres ents valid dat a to the MAC.
Micrel, Inc.
KSZ8081MLX
August
19, 2015 10 Revision 1.3
Pin Description (Continued)
Pin Number Pin Name Type
(2)
Pin Function
22 RXD1/
PHYAD2 Ipd/O MII Mod e: MII Receive Data Output[1]
(
3
)
.
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de-
assertion of reset. See the Strapping Options section for details.
23 RXD0/
DUPLEX Ipu/O MII Mod e: MII Receive Data Output[0]
(
3
)
Config. Mode: The pull-up/pull-down value is latched as DUPLEX at the de-assertion
of reset. See the Strapping Options section for details.
24 GND Gnd Ground.
25 VDDIO P 3.3V, 2.5V, or 1.8V Digital VDD.
26 NC - No Connect. This pin is not bonded and can be left floating.
27 RXDV/
CONFIG2 Ipd/O MI I Mo de : MII Receive Data Valid Output.
Config. Mode: The pull-up/pull-down value is latched as CONFIG2 at the de-assertion
of reset. See the Strapping Options section for details.
28 RXC/
B-CAST_OFF Ipd/O MII Mo d e: MII Receive Clock Output.
Config. Mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de-
assertion of reset. See the Strapping Options section for details.
29 RXER/
ISO Ipd/O MII Mo d e: MII Receive Error output
Config. Mode: The pull-up/pull-down value is latched as ISOLATE at the de-assertion
of reset See the Strapping Options section for details.
30 GND Gnd Ground.
31 VDD_1.2 P 1.2V Core VDD (power supplied by KSZ8081MLX). Decouple with 0.1µF capacitor to
ground, and join with Pin 4 by power trace or plane.
32 INTRP/
NAND_Tree# Ipu/Opu
Interrupt Output: Programmab l e inter rupt outp ut .
This pin has a weak pull-up, is open drain, and requires an external 1.0kΩ pull-up
resistor.
Config. Mode: The pull-up/pull-down value is latched as NAND Tree# at the de-
assertion of reset. See the Strapping Options section for details.
33 TXC Ipd/O
MII Mode: MII Transmit Clock Output.
At the de-assertion of reset, this pin needs to latch in a pull-down value for normal
operation. If MAC side pulls this pin high, see Register 16h, Bit [15] for solution. It i s
better having an external pull-down resistor to avoid MAC side pulls this pin high.
34 TXEN I MII Mode: MII Transmit Enable input.
Micrel, Inc.
KSZ8081MLX
August
19, 2015 11 Revision 1.3
Pin Description (Continued)
Pin Number Pin Name Type
(2)
Pin Function
35 TXD0 I MII Mode: MII Transmit Data Input[0]
(
4
)
36 TXD1 I MII Mode: MII Transmit Data Input[1]
(
4
)
37 GND GND Ground.
38 TXD2 I MII Mode: MII Transmit Data Input[2]
(
4
)
39 TXD3 I MII Mode: MII Transmit Data Input[3]
(
4
)
40 COL/
CONFIG0 Ipd/O MII Mode: MII Collision Detect output
Config. Mode: The pull-up/pull-down value is latched as CONFIG0 at the de-assertion
of reset. See the Strapping Options section for details.
41 CRS/
CONFIG1 Ipd/O MII Mode: MII Carrier Sense Output
Config. Mode: The pull-up/pull-down value is latched as CONFIG1 at the de-assertion
of reset. See the Strapping Options section for details.
42 LED0/
NWAYEN Ipu/O
LED Output: Programmable LED0 Output
Config. Mode: Latched as auto -negotiation enable (Register 0h, Bit [12]) at the de-
assertion of reset. See the Strapping Options section for details.
The LED0 pin is programmable using Register 1Fh Bits [5:4] , and is defined as
follows:
LED Mode = [00]
Link/Activity Pin State LED Definition
No link High OFF
Link Low ON
Activity Toggle Blinking
LED Mode = [01]
Link Pin State LED Definition
No link High OFF
Link Low ON
LED Mode = [10], [11] Reserved
Note:
4. MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents vali d data from the MAC.
Micrel, Inc.
KSZ8081MLX
August
19, 2015 12 Revision 1.3
Pin Description (Continued)
Pin Number Pin Name Type
(1)
Pin Function
43 LED1/
SPEED Ipu/O
LED Output: Programmable LED1 output
Config. Mode: Latched as Speed (Register 0h, Bit [13]) at the de-assertion of reset.
See the Strapping Options section for details.
The LED1 pin is programmable using Register 1Fh Bits [5:4] , and is defined as
follows:
LED Mode = [00]
Speed Pin State LED Definition
10Base-T High OFF
100Base-TX Low ON
LED Mode = [01]
Activity Pin State LED Definition
No activity High OFF
Activity Toggle Blinking
LED Mode = [10], [11]
Reserved
44 TEST/NC Ipd No Connect for normal operation, an external pull-up resistor for NAND tree testing.
45 NC - No Connect. This pin is not bonded and can be left floating.
46 NC - No Connect. This pin is not bonded and can be left floating.
47 RST# Ipu Chip Reset (active low )
48 NC - No Connect. This pin is not bonded and can be left floating.
Strapping Options
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7kΩ) or pull-downs (1.0kΩ) should be added on these PHY
strap-in pins to ensure the intended values are strapped-in correctly.
Pin Number Pin Name Type
(5)
Pin Function
22
21
20
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
The PHY address is latched at de-assertion of reset and is configurable to any value
from 0 to 7. The default PHY address is 00001. PHY address 00000 is enabled only if
the B-CAST_OFF strapping pin is pulled high. PHY address Bits [4:3] are set to 00 by
default.
27
41
40
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
CONFIG[2:0] Mode
000 MII (default)
110 MII back-to-back
001 – 101, 111 Reserved – not us ed
Note:
5. Ipu/O = Input with internal pull -up (see Electrical Characteristics for value) during power-up/reset; out put pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Charact eri st ics f or value) and output with int ernal pull-up (s ee Elect rical Charact erist ic s for
value).
Micrel, Inc.
KSZ8081MLX
August
19, 2015 13 Revision 1.3
Strapping Options (Continued)
Pin Number Pin Name Type
(5)
Pin Function
29 ISO Ipd/O
Isolate Mode:
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [10].
43 SPEED Ipu/O
Speed Mode:
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [13] as the
speed select, and also is latched into Register 4h (auto-negotiation advertisement) as
the speed capability support.
23 DUPLEX Ipu/O
Duplex Mode:
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8].
42 NWAYEN Ipu/O
Nway Auto-Negotiation Enable:
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12].
28 B-CAST_OFF Ipd/O
Broadcast Off – for PHY Address 0:
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
32 NAND_Tree# Ipu/Opu
NAND Tree Mode:
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
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KSZ8081MLX
August
19, 2015 14 Revision 1.3
Functional Description: 10Base-T/100Base-TX Transceiver
The KSZ8081MLX is an integrated single 3.3V supp ly Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3
Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two
differential pairs and by integrating the regulator to supply the 1.2V core.
On the co pper media side, the KSZ808 1MLX sup ports 10B ase-T and 1 00Base-TX for tr ansmission and r eception of data
over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and
correction for straight-through and crossover cables.
On the M AC pr ocess or si de, th e KSZ 808 1MLX of f ers the Media Indep endent Int erf ace ( MII) f or direct c onn ec tion with MII
compliant Ethernet MAC processors and switches.
The MII management bus option gives the MAC processor complete access to the KSZ8081MLX control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The c ircuitry starts with a p arallel-to-serial convers ion, whic h converts the MII data from the MAC into a 125MH z serial bit
stream. The data and c ontr ol s tr eam is then conver t ed into 4 B/5 B coding and f ollowed b y a scr am bler. T he serial i zed dat a
is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by
an external 6.49kΩ 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX
transmitter.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The rec eiving side s tarts with the equal ization filter to c ompens ate for inter-s ymbol interf erence (ISI) over th e twisted pair
cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
compar isons of incom ing si gnal str ength a gains t som e k nown cable charac ter istic s, then tunes its elf for optim ization. T his
is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit
compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit
converts MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock-recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert t he NRZI si gnal i nto NRZ f orm at. This signal is s ent throug h the de-s cram bler, t hen the 4B/5 B decoder . Final ly,
the NRZ serial data is converted to MII format and provided as the input data to the MAC.
Scrambler/De-Scramble r ( 100Ba se-TX Only)
The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and
baseline wander. The de-scrambler recovers the scrambled signal.
10Base-T Transmit
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers perform internal wave-s haping and pr e-emphasis , and output 1 0Base-T signals w ith typical am plitude of 2.5V
peak. The 10Base-T s igna l s have har monic cont e nts that are at least 27d B b elo w the f und amental f r equency when dri ven
by an all-ones Manchester-encoded signal.
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10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a
phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch c ircuit rejec ts signals with levels less t han 400mV, or with short puls e widths , to prevent
noise at t he RXP and RX M inputs fr om f alsely triggeri ng the decoder. W hen the input exceeds t he squelch li mit, the PLL
locks onto the incoming signal and the KSZ8081MLX decodes a data frame. The receive clock is kept active during idle
periods between data receptions.
SQE and Jabber Fu nction (10Base-T Only)
In 10Base-T operat ion , a s hor t pu ls e is put o ut o n th e CO L pi n af ter each frame is transmitted. T his SQ E test is needed to
test the 10Base-T transm it/receive path. If transm it enable (TXEN) is high for more than 20m s (jabbering), the 10 Base-T
transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250ms, the 10Base-T
transmitter is re-enabled and COL is de-asserted (returns to low).
PLL Clock Synthesizer
The KSZ8 081MLX generat es all interna l clocks and all external cl ocks for s ystem tim ing from an exter nal 25MH z cr ystal,
oscillator, or reference clock.
Auto-Negotiation
The KSZ8081MLX conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.
During auto-n egoti ation, l ink par tners advert ise c apabilit ies acr oss the UTP link to each other an d then c om pare their own
capabil ities with those the y received from their link partners . The highest speed a nd duplex setting th at is common to the
two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority.
• Priorit y 1: 100Base-TX, full-duplex
• Priorit y 2: 100Base-TX, half-duplex
• Priorit y 3: 10Base-T, full-duplex
• Priorit y 4: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8081MLX link partner is forced to bypass auto-negotiation, then the
KSZ8081MLX sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and
allows the KSZ8081MLX to establish a link by listening for a fixed signal protocol in the absence of the auto-negotiation
advertisement protocol.
Auto-negotiation is enabled by either hardware pin strapping (NWAYEN, Pin 42) or software (Register 0h, Bit [12]).
By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or
disabled by Register 0h, Bit [12]. If au to-ne got iat ion is disabled , the spee d is s et b y Register 0h, Bit [13], and the duplex is
set by Register 0h, Bit [8].
The auto-negotiation link-up process is shown in Figure 1.
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Figure 1. Auto-Negotiation Flow Chart
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MII Interface
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
• Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision
indication).
• 10Mbps and 100Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 4 bits wide, a nibble.
By default, the KSZ8081MLX is configured to MII mode after it is powered up or hardware reset with the following:
• A 25MHz crystal connected to XI, XO (Pins 15, 14), or an external 25MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (Pins 27, 41, 40) set to 000 (default setting).
MII Signal Definition
Table 1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
Table 1. MII Signal Definition
MII Signal Name Direction
(with respect to PHY,
KSZ8081MLX signal)
Direction
(with respect to MAC) Description
TXC Output Input Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
TXEN Input Output Transmit Enable
TXD[3:0] Input Output Transmit Data[3:0]
RXC Output Input Receive Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
RXDV Output Input Receive Data Valid
RXD[3:0] Output Input Receive Data[3:0]
RXER Output Input, or (not required) Receive Error
CRS Output Input Carrier Sense
COL Output Input Collis ion D etection
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0].
TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indic ates th at th e M AC is pr esenting ni bb les on T X D[3:0] f or tr ansmission. It is ass er ted synchronously wit h the f irs t
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII. It is negated
before the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
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Transmit Data[3:0] (TXD[3:0])
When TXEN is asserted, TXD[3:0] are the data nibbles accepted by the PHY for transmission. TXD[3:0] is 00 to indicate
idle when TXEN is de-asserted.
TXD[3:0] transitions synchronously with respect to TXC.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
In 10Mbps mode, RXC is recovered from the line while the carrier is active. RXC is derived from the PHY’s reference
clock when the line is idle or the link is down.
In 100Mbps mode, RXC is continuously recovered from the line. If the link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
In 10Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains asserted
until the end of the frame.
In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
Receive Data[3:0] (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data from the PHY.
Receive Error (RXER)
RXER is asserted for one or more RXC periods to indicate that a symbol error (for example, a coding error that a PHY can
detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being
transferred from the PHY.
RXER transitions synchronously with respect to RXC.
Carrier Sense (CRS)
CRS is asserted and de-asserted as follows:
In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the
reception of an end-of-frame (EOF) marker.
In 100Mbps m ode, CRS is asserted when a start-of-stream delimiter or /J/K s ymbol pair is detected. CRS is de-asserted
when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts CRS if IDLE
symbols are received without /T/R.
Collision (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This
informs the MAC that a collision has occurred during its transmission to the PHY.
COL transitions asynchronously with respect to TXC and RXC.
MII Signal Diagram
The KSZ8081MLX MII pin connections to the MAC are shown in Figure 2.
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Figure 2. KSZ8081MLX MII Interface
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Back-to-Back Mode – 100Mbps Copper Repeater
Two KSZ8081MLX devices can be connected back -to-back to form a 100Base-TX to 100Base-TX copper repeater.
Figure 3. KSZ8081MLX to KSZ8081MLX Back-to-Back Copper Repeater
MII Back-to-Back Mode
In MII back -to-back mode, a K SZ8081MLX int erfaces with another KSZ8081 MLX to pro vide a complete 100Mbps cop per
repeater solution.
The KSZ8081MLX devices are configured to MII back-to-back mode after power-up or reset with the following:
Strapping pin CONFIG[2:0] (Pins 27, 41, 40) set to 110
A common 25MHz reference clock connected to XI (Pin 15) of both KSZ8081MLX devices
MII signals connected as shown in Table 2.
Table 2. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater)
KSZ8081MLX (100Base-TX copper)
[Device 1] KSZ8081MLX (100Base-TX copper)
[Device 2]
Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type
RXDV 27 Output TXEN 34 Input
RXD3 20 Output TXD3 39 Input
RXD2 21 Output TXD2 38 Input
RXD1 22 Output TXD1 36 Input
RXD0 23 Output TXD0 35 Input
TXEN 34 Input RXDV 27 Output
TXD3 39 Input RXD3 20 Output
TXD2 38 Input RXD2 21 Output
TXD1 36 Input RXD1 22 Output
TXD0 35 Input RXD0 23 Output
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MII Management (MIIM) Interface
The KSZ8081MLX supports the IEEE 802.3 MII management interface, also known as the Management Data
Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and
control the state of the KSZ8081MLX. An external device with MIIM capability is used to read the PHY status and/or
configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3
Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the physical connection mentioned earlier, which allows the external controller
to communicate with one or more PHY devices.
• A set of 16-bit MD IO registers . Supported registers [0:8] ar e standard reg isters , and their functions ar e defined in the
IEEE 802.3 Specification. The additional registers are provided for expanded functionality. See the Register Map
section for details.
As the default, the KSZ8081MLX supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter is
defined in the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8081MLX device, or write to
multiple KSZ8081MLX devices simultaneously.
PHY addr ess 0 can opt ionall y be disab led as the br oadcast ad dress b y either har dware pin str apping ( B-CAST_OFF, Pin
28) or software (Register 16h, Bit [9]), and assigned as a unique PHY address.
The PHYAD[2:0] strapping pins are used to assign a unique PHY address between 0 and 7 to each KSZ8081MLX device.
The MIIM interface can operates up to a maximum clock speed of 10MHz MAC clock.
Table 3 shows the MII management frame format for the KSZ8081MLX.
Table 3. MII Management Frame Format for the KSZ8081MLX
Preamble Start of
Frame Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0] TA Data
Bits [15:0] Idle
Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z
Interrupt (INTRP)
INTRP (Pin 32) is an optional interrupt signal that is used to inform the external controller that there has been a status
update t o the KSZ8081 MLX PHY Register. Bits [15:8] of Register 1Bh are the interrupt contr ol bits to en able and d isable
the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate which
interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh.
Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ8081MLX control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable
between the KSZ8081MLX and its link partner. This feature allows the KSZ8081MLX to use either type of cable to
connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive
pairs from the link partner and assigns transmit and receive pairs of the KSZ8081MLX accordingly.
HP Auto MD I/MDI-X is ena bled b y def ault. It is d isable d by writin g a ‘1’ to Register 1Fh, Bit [1 3]. MDI and MDI-X m ode is
selected by Register 1Fh, Bit [14] if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.
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Table 4 shows how the IEEE 802.3 Standard defines MDI and MDI-X.
Table 4. MDI/MDI-X Pin Definition
MDI MDI-X
RJ-45 Pin Signal RJ-45 Pin Signal
1 TX+ 1 RX+
2 TX− 2 RX−
3 RX+ 3 TX+
6 RX− 6 TX−
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 4 shows a
typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).
Figure 4. Typical Straight Cable Connection
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Crossover C able
A cross over cable conn ects an MDI de vice to anoth er MDI device, or an MDI -X device to an other MDI -X devic e. Figure 5
shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
Figure 5. Typical Crossover Cable Connection
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Loopback Mode
The KSZ8081MLX supports the following loopback operations to verify analog and/or digital data paths.
• Local (digital) loopback
• Remote (analog) loopback
Local (Di gital) Loopback
This loopback mode checks the MII transmit and receive data paths between the KSZ8081MLX and the external MAC,
and is supported for both speeds (10/100Mbps) at full-duplex.
The loopback data path is shown in Figure 6.
1. The MII MAC transmits frames to the KSZ8081MLX.
2. Frames are wrapped around inside the KSZ8081MLX.
3. The KSZ8081MLX transmits frames back to the MII MAC.
Figure 6. Local (Digital) Loopback
The following programming action and register settings are used for local loopback mode.
For 10/100Mbps loopbac k,
Set Register 0h,
Bit [14] = 1 // Enable l ocal loo pbac k mode
Bit [13] = 0/1 // Select 10Mbps/100Mbps speed
Bit [12] = 0 // Disable auto-negotiation
Bit [8] = 1 // Select full-duplex mode
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Remote (Ana log) Loopback
This loopb ack m ode checks the li ne (diff erenti al pairs , trans form er, RJ-45 c onnector, Eth ernet c able) tr ansm it and rece ive
data paths between the KSZ8081MLX and its link partner. It is supported for 100Base-TX full-duplex mode only.
The loopback data path is shown in Figure 7.
1. The Fast Ethernet (100Base-TX) PHY link partner transmits frames to the KSZ8081MLX.
2. Frames are wrapped around inside the KSZ8081MLX.
3. The KSZ8081MLX transmits frames back to the Fast Ethernet (100Base-TX) PHY link partner.
Figure 7. Remote (Analog) Loopback
The following programming steps and register settings are used for remote loopback mode:
1. Set Register 0h,
Bits [13] = 1 // Se lec t 100M bps spe ed
Bit [12] = 0 // Disable auto-negotiation
Bit [8] = 1 // Selec t f ull-duplex mode
Or just auto-negotiate and link up at 100Base-TX full-duplex mode with the link partner
2. Set Register 1Fh,
Bit [2] = 1 // Enable remote loopback mode
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LinkMD® Cable Diagnostic
The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.
These include open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape
of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the
approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as a
numerical value that can be translated to a cable distance.
LinkMD is initiated by accessing Register 1Dh, the LinkMD Control/Status register, in conjunction with Register 1Fh, the
PHY Control 2 register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as the
cable differential pair for testing.
Usage
The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh:
3. Disable auto MDI/MDI-X by writing a ‘1’ to Register 1Fh, bit [13].
4. Start cable diagnostic test by writing a ‘1’ to Register 1Dh, bit [15]. This enable bit is self-clearing.
5. Wait (poll) for Register 1Dh, bit [15] to return a ‘0’, and indicating cable diagnostic test is completed.
6. Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test is
not run, since it would be impossible for the device to determine if the detected signal is a reflection of the signal
generated or a signal from another source.
7. Get distance to fault by concatenating Register 1Dh, bits [8:0] and multiplying the result by a constant of 0.38. The
distance to the cable fault can be determined by the following formula:
D (distance to cable fault) = 0.38 x (Regi ster 1Dh, bits [8:0])
D (distance to cable fault) is expressed in meters.
Concatenated value of Registers 1Dh bits [8:0] shou ld be converted to decimal before multiplying by 0.38.
The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation
that varies significantly from the norm.
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NAND Tree Support
The KSZ8081MLX provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND
tree is a chain of nested NAND gates in which each KSZ8081MLX digital I/O (NAND tree input) pin is an input to one
NAND gate along the chain. At the end of the chain, the CRS/CONFIG1 pin provides the output for the nested NAND
gates.
The NAND tree test process includes:
• Enabling NAND tree mode
• Pulling all NAND tree input pins high
• Driving each NAN D tree in put pin lo w, sequ ent ia ll y, accor ding to the NAND tree pi n order
• Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
Table 5 lists the NAND tree pin order.
Table 5. NAND Tree Test Pin Order for KSZ 8081MLX
Pin Number Pin Name NAND Tree Description
18 MDIO Input
19 MDC Input
20 RXD3 Input
21 RXD2 Input
22 RXD1 Input
23 RXD0 Input
27 RXDV Input
28 RXC Input
29 RXER Input
32 INTRP Input
33 TXC Input
34 TXEN Input
35 TXD0 Input
36 TXD1 Input
38 TXD2 Input
39 TXD3 Input
42 LED0 Input
43 LED1 Input
40 COL Input
41 CRS Output
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NAND Tree I/O Testing
Use the following procedure to check for faults on the KSZ8081MLX digital I/O pin connections to the board:
1. Enable NAND tree mode using either a hardware strap-in pin (NAND_Tree#, Pin 32) or software (Register 16h, Bit
[5]). Pin 44 TEST/NC has to use a pull-up resistor for normal NAND tree testing.
2. Use board logic to drive all KSZ8081MLX NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, in KSZ8081MLX NAND tree pin order, as follows:
a. Toggle the first pin (MDIO) from high to low, and verify that the CRS/CONFIG1 pin switches from high to low to
indicate that the first pin is connected properly.
b. Leave the first pin (MDIO) low.
c. Toggle the s ec ond pin ( MD C ) f r om high to l o w, and ve r ify that the CR S/CO NFIG1 pin s witc hes f rom low to hi gh to
indicate that the second pin is connected properly.
d. Leave the first pin (MDIO) and the second pin (MDC) low.
e. Toggle the third pin (RXD3) from high to low, and verify that the CRS/CONFIG1 pin switches from high to low to
indicate that the third pin is connected properly.
f. Continue with this sequence until all KSZ8081MLX NAND tree input pins have been toggled.
Each K SZ8081M LX N AND tree inp ut pi n m ust c ause t he CRS/C ONF IG1 output pin t o tog gle h igh-to-low or low-to-high to
indicate a good connection. If the CRS pin fails to toggle when the KSZ8081MLX input pin toggles from high to low, the
input pin has a fault.
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Power Management
The KSZ8081MLX incorporates a number of power-managem ent modes and features that provide methods to consume
less energy. These are discussed in the following sections.
Power-Saving Mode
Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by
writing a ‘1’ to Register 1Fh, Bit [10], and is in effect when auto-negotiation mode is enabled and the cable is disconnected
(no link).
In this mode, the KSZ8081MLX shuts down all transceiver blocks, except for the transmitter, energy detect, and PLL
circuits.
By default, power-saving mode is disabled after power-up.
Energy-Detect Power-Down Mode
Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is
unplugged. It is e nabled by writing a ‘0’ to Register 18h, Bit [11], and is in effect when auto-negotiation mode is enabled
and the cable is disconnected (no link).
EDPD m ode works with the P LL off ( set by writing a ‘ 1’ to Register 10h, Bit [4] t o automatic ally turn the PLL off in EDPD
mode) to turn off all KSZ8081MLX transceiver blocks, except for the transmitter and energy-detect circuits.
Power can be reduced further by extending the time interval between transmissions of link pulses to check for the
presence of a li nk partner. T he periodic tr ans m ission of link puls es is neede d to ensure t wo link par tners in the s am e low-
power state, with Au to MDI / MDI-X disabled, can wake up when the cable is connected between them.
By default, energy-detect power-down mode is disabled after power-up.
Power-Down Mode
Power-d own mode is used to power do wn the K SZ8081MLX d evice when it is n ot in use aft er power-up. It is enabled b y
writing a ‘1’ to Register 0h, Bit [11].
In this mode, the KSZ8081MLX disables all internal functions except the MII management interface. The KSZ8081MLX
exits (disables) power-down mode after Register 0h, Bit [11] is set back to ‘0’.
Slow-Oscillator Mode
Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (Pin 15) and select the on-chip slow
oscillator when the K SZ80 8 1MLX dev ice is not in use after power-up. It is enabled by writing a ‘1’ to Register 11h, Bit [5].
Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8081MLX device in the lowest power
state with all internal functions disabled except the MII management interface. To properly exit this mode and return to
normal PHY operation, use the following programming sequence:
1. Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5].
2. Disable power-down mode by writing a ‘0’ to Register 0h, Bit [11].
3. Initiate software reset by writing a ‘1’ to Register 0h, Bit [15].
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Reference Circuit for Power and Ground Connections
The KSZ80 81MLX is a single 3.3V supply de vice with a bui lt-in regulator to supply the 1. 2V core. The po wer and ground
connections are shown in Figure 8 and Table 6 for 3.3V VDDIO.
Figure 8. KSZ8081MLX Power and Ground Connections
Table 6. KSZ8081 Power Pin Description
Power Pin Pin Number Description
VDD_1.2 4 Connect with Pin 31 by power trace or plane. Decouple w ith 2.2µF and 0.1µF capacitors to ground.
VDDA_3.3 7 Connect to board’s 3.3V suppl y through a ferrit e bead . Decouple with 22µF and 0.1µF capacitors to
ground.
VDDIO 25 Connect to board’s 3.3V supply for 3.3V VDDIO. Decouple with 22µF and 0.1µF capacit or s to
ground.
VDD_1.2 31 Connect with Pin 4 by power trace or plane. Decouple with 0.1µF capacitor to ground.
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Typical Current/Power Consumption
Table 7, Table 8, and Tabl e 9 show t ypica l values for current cons umption b y the tr ansceiver (VDD A_3.3) and di gital I/O
(VDDIO) power pins and typical values for power consumption by the KSZ8081MLX device for the indicated nominal
operatin g v oltages . These c urr ent an d p o wer c ons umption val ues include the tra nsmit driver c ur rent and on-c hip re gul ator
current for the 1.2V core.
Table 7. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V)
Transceiver (3.3V), Digital I/Os (3.3V)
Condition 3.3V Transceiver
(VDDA_3.3) 3.3V Digital I/Os
(VDDIO) Total Chip Power
mA mA mW
100Base-TX Link-up (no traffic) 34 12 152
100Base-TX Full -duplex @ 100% utilization 34 13 155
10Base-T Link-up ( no traffic) 14 11 82.5
10Base-T Ful l-duplex @ 100% utilization 30 11 135
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 14 10 79.2
EDPD mode (Reg. 18h, Bit [11] = 0) 10 10 66.0
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1) 3.77 1.54 17.5
Software power-down mode (Reg. 0h, Bit [11] =1) 2.59 1.51 13.5
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.36 0.45 5.97
Table 8. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V)
Transceiver (3.3V), Digital I/Os (2.5V)
Condition 3.3V Transceiver
(VDDA_3.3)
2.5V Digital I/Os
(VDDIO)
Total Chip Power
mA mA mW
100Base-TX Link-up (no traffic) 34 11 140
100Base-TX Full -duplex @ 100% utilization 34 12 142
10Base-T Link-up ( no traffic) 15 10 74.5
10Base-T Ful l-duplex @ 100% utilization 27 10 114
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 15 10 74.5
EDPD mode (Reg. 18h, Bit [11] = 0) 11 10 61.3
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1) 3.55 1.35 15.1
Software power-down mode (Reg. 0h, Bit [11] =1) 2.29 1.34 10.9
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.15 0.29 4.52
Micrel, Inc.
KSZ8081MLX
August
19, 2015 32 Revision 1.3
Table 9. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V)
Transceiver (3.3V), Digital I/Os (1.8V)
Condition 3.3V Transceiver
(VDDA_3.3) 1.8V Digital I/Os
(VDDIO) Total Chip Power
mA mA mW
100Base-TX Link-up (no traffic) 34 11 132
100Base-TX Full -duplex @ 100% utilization 34 12 134
10Base-T Link-up ( no traffic) 15 9.0 65.7
10Base-T Ful l-duplex @ 100% utilization 27 9.0 105
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 15 9.0 65.7
EDPD mode (Reg. 18h, Bit [11] = 0) 11 9.0 52.5
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1) 4.05 1.21 15.5
Software power-down mode (Reg. 0h, Bit [11] =1) 2.79 1.21 11.4
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.65 0.19 5.79
Micrel, Inc.
KSZ8081MLX
August
19, 2015 33 Revision 1.3
Register Map
Register Number (Hex) Description
0h Basic Control
1h Basic Status
2h PHY Identifier 1
3h PHY Identifier 2
4h Auto-Negotiation Advertisement
5h Auto-Negotiation Lin k Part ner A bility
6h Auto-Negotiation Expansion
7h Auto-Negotiation Next Page
8h Link Partner Next Page Ability
9h – Fh Reserved
10h Digital Reserved Control
11h AFE Control 1
12h – 14h Reserved
15h RXER Counter
16h Operation Mode Strap Override
17h Operation Mode Strap Status
18h Expanded Control
19h – 1Ah Reserved
1Bh Interrupt Control/Status
1Ch Reserved
1Dh LinkMD Control/Status
1Eh PHY Control 1
1Fh PHY Control 2
Micrel, Inc.
KSZ8081MLX
August
19, 2015 34 Revision 1.3
Register Description
Address Name Description Mode
(6)
Default
Register 0h – Basic Control
0.15 Reset 1 = Software reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it. RW/SC 0
0.14 Loopback 1 = Loopback mode
0 = Normal operation RW 0
0.13 Speed Select
1 = 100Mbps
0 = 10Mbps
This bit is ignored if auto-negotiation is enabled
(Register 0. 12 = 1).
RW Set by the SPEED strapping pin.
See the Strapping Options
section for details.
0.12 Auto-Negotiation
Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
If enabled, the auto-negotiation result overrides
the settings in Register 0.13 a nd 0.8.
RW
Set by the NWAYEN strapping
pin.
See the Strapping Options
section for details.
0.11 Power-Down
1 = Power-down mode
0 = Normal operation
If software reset (Register 0.15) is used to exit
power-down mode (Register 0.11 = 1), two
software reset writes (Register 0.15 = 1) are
required. The first write clears power-down
mode; the second write resets the chip and re-
latches the pin strapping pin values.
RW 0
0.10 Isolate 1 = Electrical isol ation of PHY from MII
0 = Normal operation RW Set by the ISO strapping pin.
See the Strapping Options
section for details.
0.9 Restart Auto-
Negotiation
1 = Restart auto-nego tiation proce ss
0 = Normal operation.
This bit is self-cleared after a ‘1’ is written to it. RW/SC 0
0.8 Duplex Mode 1 = Full-duplex
0 = Half-duplex RW
The inver se of the DUPLEX
strapping pin value.
See the Strapping Options
section for details.
0.7 Collision Test 1 = Enable COL test
0 = Disable COL test RW 0
0.6:0 Reserved Reserved RO 000_0000
Note:
6. RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
Micrel, Inc.
KSZ8081MLX
August
19, 2015 35 Revision 1.3
Register Description (Continued)
Address Name Description Mode
(6)
Default
Register 1h – Basic Status
1.15 100Base-T4 1 = T4 capable
0 = Not T4 capable RO 0
1.14 100Base-TX Full-
Duplex 1 = Capable of 100Mbps full-duplex
0 = Not capable of 100Mbps full-duplex RO 1
1.13 100Base-TX Half-
Duplex 1 = Capable of 100Mbps half-duplex
0 = Not capable of 100Mbps half-duplex RO 1
1.12 10Base-T
Full-Duplex 1 = Capable of 10Mbps full-duplex
0 = Not capable of 10Mbps full-duplex RO 1
1.11 10Base-T
Half-Duplex 1 = Capable of 10Mbps half-duplex
0 = Not capable of 10Mbps half-duplex RO 1
1.10:7 Reserved Reserved RO 000_0
1.6 No Preamble 1 = Preamble suppression
0 = Normal preamble RO 1
1.5 Auto-Negotiation
Complete 1 = Auto-neg otia t io n proce ss compl et ed
0 = Auto-negot iation process not completed RO 0
1.4 Remote Fault 1 = Remote fault
0 = No remote fault RO/LH 0
1.3 Auto-Negotiation
Ability 1 = Can perform auto-negotiation
0 = Cannot perform auto-negotiation RO 1
1.2 Link Status 1 = Link is up
0 = Link is down RO/LL 0
1.1 Jabber Detect 1 = Jabber detected
0 = Jabber not detected (default is low) RO/LH 0
1.0 Extended
Capability 1 = Supports extended capability registers RO 1
Register 2h – PHY Identifier 1
2.15:0 PHY ID Number
Assigned to the 3rd through 18th bits of the
Organizationally Unique Identifier (OUI).
KENDIN Communication’s OUI is 0010A1
(hex).
RO 0022h
Register 3h – PHY Identifier 2
3.15:10 PHY ID Number
Assigned to the 19th through 24th bits of the
Organizationally Unique Identifier (OUI).
KENDIN Communication’s OUI is 0010A1
(hex).
RO 0001_01
3.9:4 Model Number Six-bit manufacturer’s model number RO 01_0110
3.3:0 Revision Number Four-bit manufacturer’s revision number RO Indicates silicon revision
Micrel, Inc.
KSZ8081MLX
August
19, 2015 36 Revision 1.3
Register Description (Continued)
Address Name Description Mode
(6)
Default
Register 4h – Auto-Negotiation Advertisement
4.15 Next Page 1 = Next page capable
0 = No next page capability RW 0
4.14 Reserved Reserved RO 0
4.13 Remote Fault 1 = Remote fault supported
0 = No remote fault RW 0
4.12 Reserved Reserved RO 0
4.11:10 Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RW 00
4.9 100Base-T4 1 = T4 capable
0 = No T4 capability RO 0
4.8 100Base-TX Full-
Duplex 1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability RW Set by the SPEED strapping pin.
See the Strapping Options
section for details.
4.7 100Base-TX Half-
Duplex 1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability RW Set by the SPEED strapping pin.
See the Strapping Options
section for details.
4.6 10Base-T
Full-Duplex 1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability RW 1
4.5 10Base-T
Half-Duplex 1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability RW 1
4.4:0 Selector Field [00001] = IEEE 802.3 RW 0_0001
Register 5h – Auto-Negotiation Link Partner Ability
5.15 Next Page 1 = Next page capable
0 = No next page capability RO 0
5.14 Acknowledge 1 = Link code word received from partner
0 = Link code word not yet received RO 0
5.13 Remote Fault 1 = Remote fault detected
0 = No remote fault RO 0
5.12 Reserved Reserved RO 0
5.11:10 Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RO 00
5.9 100Base-T4 1 = T4 capable
0 = No T4 capability RO 0
5.8 100Base-TX Full-
Duplex 1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability RO 0
Micrel, Inc.
KSZ8081MLX
August
19, 2015 37 Revision 1.3
Register Description (Continued)
Address Name Description Mode
(6)
Default
Register 5h – Auto-Negotiation Link Partner Ability
5.7 100Base-TX Half-
Duplex 1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability RO 0
5.6 10Base-T
Full-Duplex 1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability RO 0
5.5 10Base-T
Half-Duplex 1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability RO 0
5.4:0 Selector Field [00001] = IEEE 802.3 RO 0_0001
Register 6h – Auto-Negotiation Expansion
6.15:5 Reserved Reserved RO 0000_0000_000
6.4 Parallel Detection
Fault 1 = Fault detected by parallel detection
0 = No fault detected by parallel detection RO/LH 0
6.3 Link Partner Next
Page Able
1 = Link partner has next page capability
0 = Link partner does not have next page
capability RO 0
6.2 Next Page Able 1 = Local device has next page capability
0 = Local device does not have next page
capability RO 1
6.1 Page Received 1 = New page received
0 = New page not received yet RO/LH 0
6.0 Link Partner Auto-
Negotiation Able
1 = Link partner has auto-neg otiation capabi lity
0 = Link partner do es not have auto-negotiation
capability RO 0
Register 7h – Auto-Negotiation Next Page
7.15 Next Page 1 = Additional next pages will follow
0 = Last page RW 0
7.14 Reserved Reserved RO 0
7.13 Message Page 1 = Message page
0 = Unformatted page RW 1
7.12 Acknowledge2 1 = Will comply with message
0 = Cannot comply with message RW 0
7.11 Toggle 1 = Previous value of the transmitted link code
word equaled logic 1
0 = Logic 0 RO 0
7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 000_0000_0001
Micrel, Inc.
KSZ8081MLX
August
19, 2015 38 Revision 1.3
Register Description (Continued)
Address Name Description Mode
(6)
Default
Register 8h – Link Partner Next Page Ability
8.15 Next Page 1 = Additional next pages will follow
0 = Last page RO 0
8.14 Acknowledge 1 = Successful receipt of link word
0 = No successful receipt of link word RO 0
8.13 Message Page 1 = Message page
0 = Unformatted page RO 0
8.12 Acknowledge2 1 = Can act on the information
0 = Cannot act on the information RO 0
8.11 Toggle
1 = Previous value of transmitted link code word
equal to logic 0
0 = Previous value of transmitted link code word
equal to logic 1
RO 0
8.10:0 Message Field 11-bit wide field to encode 2048 messages RO 000_0000_0000
Register 10h – Digital Reserved Control
10.15:5 Reserved Reserved RW 0000_0000_000
10.4 PLL Off 1 = Turn PLL off automatically in EDPD mode
0 = Keep PLL on in EDPD mode.
See also Register 18h, Bit [11] for EDPD mode RW 0
10.3:0 Reserved Reserved RW 0000
Register 11h – AFE Control 1
11.15:6 Reserved Reserved RW 0000_0000_00
11.5 Slow-Oscillator
Mode Enable
Slow-oscillator mode is used to disconnect the
input reference crystal/clock on the XI pin and
select the on-chip slow oscillator when the
KSZ8081M LX device is not in use after power-
up.
1 = Enable
0 = Disable
This bit automatic ally sets software power-down
to the analog side when enabled.
RW 0
11.4:0 Reserved Reserved RW 0_0000
Register 15h – RXER Counter
15.15:0 RXER Counter Receive error counter for symbol error frames RO/SC 0000h
Micrel, Inc.
KSZ8081MLX
August
19, 2015 39 Revision 1.3
Register Description (Continued)
Address Name Description Mode
(6)
Default
Register 16h – Operation Mode Strap Override
16.15 Reserved
Factory Mode
0 = Normal operation
1 = Factory test mode
If TXC (Pin 33) latches in a pull-up value at the
de-assertion of reset, write a ‘0’ to this bit to
clear Reserved Factory Mode.
RW 0
Set by the pull-up / pull-down
value of TXC (Pin 33).
16.14:11 Reserved Reserved RW 000_0
16.10 Reserved Reserved RO 0
16.9 B-CAST_OFF
Override 1 = Override strap-in for B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-broadcast. RW 0
16.8 Reserved Reserved RW 0
16.7 MII B-to-B
Override 1 = Override strap-in for MII back-to-back mode
(also set Bit 0 of this register to ‘1’) RW 0
16.6 Reserved Reserved RW 0
16.5 NAND Tree
Override 1 = Override strap-in for NAND tree mode RW 0
16.4:1 Reserved Reserved RW 0_000
16.0 MII Override 1 = Override strap-in for MII mode RW 1
Register 17h – Operation Mode Strap Status
17.15:13 PHYAD[2:0] Strap-
In Status
[000] = Strap to PHY Address 0
[001] = Strap to PHY Address 1
[010] = Strap to PHY Address 2
[011] = Strap to PHY Address 3
[100] = Strap to PHY Address 4
[101] = Strap to PHY Address 5
[110] = Strap to PHY Address 6
[111] = Strap to PHY Address 7
RO
17.12:10 Reserved Reserved RO
17.9 B-CAST_OFF
Strap-In Status 1 = Strap to B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-broadcast. RO
17.8 Reserved Reserved RO
17.7 MII B-to-B Strap-In
Status 1 = Strap to MII back-to-bac k mode RO
17.6 Reserved Reserved RO
17.5 NAND Tree Strap-
In Status 1 = Strap to NAND tree mode RO
17.4:1 Reserved Reserved RO
17.0 MII Strap-In Status 1 = Strap to MII mode RO
Micrel, Inc.
KSZ8081MLX
August
19, 2015 40 Revision 1.3
Register Description (Continued)
Address Name Description Mode
(6)
Default
Register 18h – Expanded Control
18.15:12 Reserved Reserved RW 0000
18.11 EDPD Disabled
Energy-detect power-down mode
1 = Disable
0 = Enable
See also Register 10h, Bit [4] for PLL off.
RW 1
18.10 100Base-TX
Latency
1 = MII output is random latency
0 = MII output is fixed latency
For both settings, all bytes of received preamble
are passed to the MII output.
RW 0
18.9:7 Reserved Reserved RW 00_0
18.6 10Base-T
Preamble Restore
1 = Restore received preamble to MII output
0 = Remove all seven bytes of preamble before
sending frame (starting with SFD) to MII output RW 0
18.5:0 Reserved Reserved RW 00_0000
Register 1Bh – Interrupt Control/Status
1B.15 Jabber Interrupt
Enable 1 = Enable jabber interrupt
0 = Disable jabber interrupt RW 0
1B.14 Receive Error
Interrupt Enable 1 = Enable receive error interrupt
0 = Disable receive error interrupt RW 0
1B.13 Page Received
Interrupt Enable 1 = Enable page received interrupt
0 = Disable page received interrupt RW 0
1B.12 Parallel Detect
Fault Interr upt
Enable
1 = Enable parallel detect fault interrupt
0 = Disable parallel detect fault interrupt RW 0
1B.11 Link Partner
Acknowledge
Interrupt Enable
1 = Enable link partner acknowledge interrupt
0 = Disable link partner acknowledge interrupt RW 0
1B.10 Link-Down
Interrupt Enable 1= Enab le lin k-down interrupt
0 = Disable link-down interrupt RW 0
1B.9 Remote Fault
Interrupt Enable 1 = Enable remote fault interrupt
0 = Disable remote fault interrupt RW 0
1B.8 Link-Up Interrupt
Enable 1 = Enable link-up interrupt
0 = Disable link-up interrupt RW 0
1B.7 Jabber Interrupt 1 = Jabber occurred
0 = Jabber did not occur RO/SC 0
1B.6 Receive Error
Interrupt 1 = Receive error occurred
0 = Receive error did not occur RO/SC 0
1B.5 Page Receive
Interrupt 1 = Page receive occurred
0 = Page receive did not occur RO/SC 0
Micrel, Inc.
KSZ8081MLX
August
19, 2015 41 Revision 1.3
Register Description (Continued)
Address Name Description Mode
(6)
Default
Register 1Bh – Interrupt Control/Status (Continued)
1B.4 Parallel Detect
Fault Interr upt 1 = Parallel detect fault occurred
0 = Parallel detect fault did not occur RO/SC 0
1B.3 Link Partner
Acknowledge
Interrupt
1 = Link partner acknowledge occurred
0 = Link partner acknowledge did not occur RO/SC 0
1B.2 Link-Down
Interrupt 1 = Link-down occurred
0 = Link-down did not occur RO/SC 0
1B.1 Remote Fault
Interrupt 1 = Remote fault occurred
0 = Remote fault did not occur RO/SC 0
1B.0 Link-Up Interrupt 1 = Link-up occurred
0 = Link-up did not occur RO/SC 0
Register 1Dh – LinkMD Control/Status
1D.15 Cable Diagnostic
Test Enable
1 = Enable cable diagnostic test. After test has
completed, this bit is self-cleared.
0 = Indicates cable diagnostic test (if enabled)
has completed and the stat us i nfor m atio n is
valid for read.
RW/SC 0
1D.14:13 Cable Diagnostic
Test Result
[00] = Normal condition
[01] = Open condition has been detected in
cable
[10] = Short condition has bee n detected in
cable
[11] = Cable diagnostic test has failed
RO 00
1D.12 Short Cable
Indicator 1 = Short cable (<10 meter) has been detected
by LinkMD RO 0
1D.11:9 Reserved Reserved RW 000
1D.8:0 Cable Fault
Counter D istan ce to fault RO 0_0000_0000
Register 1Eh – PHY Control 1
1E.15:10 Reserved Reserved RO 0000_00
1E.9 Enable Pause
(Flow Control) 1 = Flow control capable
0 = No flow control capability RO 0
1E.8 Link Status 1 = Link is up
0 = Link is down RO 0
1E.7 Polarity Status 1 = Polarity is reversed
0 = Polarity is not reversed RO
1E.6 Reserved Reserved RO 0
1E.5 MDI/MDI-X State 1 = MDI-X
0 = MDI RO
Micrel, Inc.
KSZ8081MLX
August
19, 2015 42 Revision 1.3
Register Description (Continued)
Address Name Description
Mode
(6)
Default
Register 1Eh – PHY Control 1 (Continued)
1E.4 Energy Detect
1 = Presence of signal on receive differential
pair
0 = No signal detected on receive differential
pair
RO 0
1E.3 PHY Isolate 1 = PHY in isolate mode
0 = PHY in normal operation RW 0
1E.2:0 Operation Mode
Indication
[000] = Still in auto-negotiation
[001] = 10Base-T half-duplex
[010] = 100Base-TX half-duplex
[011] = Reserved
[100] = Reserved
[101] = 10Base-T full-duplex
[110] = 100Base-TX full-duplex
[111] = Reserved
RO 000
Register 1Fh – PHY Control 2
1F.15 HP_MDIX 1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode RW 1
1F.14 MDI/MDI-X Select
When A uto MDI/MDI-X is disabled,
1 = MDI-X mode
Transmit on RXP,RXM (Pins 10, 9) and
Receive on TXP, TXM (Pins 12, 11)
0 = MDI mode
Transmit on TXP,TXM (Pins 12, 11) and
Receive on RXP,RXM (Pins 10, 9)
RW 0
1F.13 Pair Swap Disable 1 = Disable Auto MDI/MDI-X
0 = Enable Auto MDI/MDI-X RW 0
1F.12 Reserved Reserved RW 0
1F.11 Force Lin k
1 = Force link pass
0 = Normal link operation
This bit bypasses the control logic and allows
the transmitter to send a pattern even if there is
no link.
RW 0
1F.10 Power Saving 1 = Enable power saving
0 = Disable power saving RW 0
1F.9 Interrupt Level 1 = Interrupt pin active high
0 = Interrupt pin active low RW 0
1F.8 Enable Jabber 1 = Enable jabber coun ter
0 = Disable jabber counter RW 1
1F.7:6 Reserved Reserved RW 00
Micrel, Inc.
KSZ8081MLX
August
19, 2015 43 Revision 1.3
Register Description (Continued)
Address Name Description Mode
(6)
Default
Register 1Fh – PHY Control 2 (Continued)
1F.5:4 LED Mode
[00] = LED1: Speed
LED0: Link/Ac tivity
[01] = LED1: Activity
LED0: Lin k
[10], [11] = Reserved
RW 00
1F.3 Disable
Transmitter 1 = Disable transmitter
0 = Enable transmitter RW 0
1F.2 Remote Loopback 1 = Remote (analog) loopback is enabled
0 = Normal mode RW 0
1F.1 Enable SQE Test 1 = Enable SQE test
0 = Disable SQE test RW 0
1F.0 Disable Data
Scrambling 1 = Disable scrambler
0 = Enable scrambler RW 0
Micrel, Inc.
KSZ8081MLX
August
19, 2015 44 Revision 1.3
Absolute Maximum Ratings(7)
Supply Voltage (VIN)
(VDD_1.2) .................................................. −0.5V to +1.8V
(VDDIO, VDDA_3.3) ....................................... −0.5V to +5.0V
Input Voltage (all inputs) .............................. −0.5V to +5.0V
Output Volta ge (all out puts ) ......................... −0.5V to +5.0V
Lead Temperature (soldering, 10s) ............................ 260°C
Storage Temperature (TS) ......................... –55°C to +150°C
Operating Ratings(8)
Suppl y Voltage
(VDDIO_3.3, VDDA_3.3) .......................... +3.135V to +3.465V
(VDDIO_2.5) ........................................ +2.375V to +2.625V
(VDDIO_1.8) ........................................ +1.710V to +1.890V
Ambient Temperature
(TA , Commercial) ...................................... 0°C to +70°C
(TA , Industrial) ...................................... –40°C to +85°C
Maximum Junction Temperature (TJ maximum) ........ 125°C
Thermal Resistance (θJA) ......................................... 76°C/W
Thermal Resistance (θJC) ......................................... 15°C/W
Electrical Characteristics(9)
Symbol Parameter Condition Min. Typ. Max. Units
Supply Current (VDDIO, VDDA_3.3 = 3.3V)(10)
IDD1_3.3V 10Base-T Full-duplex traffic @ 100% utilization 41 mA
IDD2_3.3V 100Base-TX Full-duplex traffic @ 100% utilization 47 mA
IDD3_3.3V EDPD Mode Ethernet cable disconnected (reg. 18h.11 = 0) 20 mA
IDD4_3.3V Power-Down Mode Software power-down (reg. 0h.11 = 1) 4 mA
CMOS Level Inputs
VIH Input High Voltage
VDDIO = 3.3V 2.0
V VDDIO = 2.5V 1.8
VDDIO = 1.8V 1.3
VIL Input Low Voltag e
VDDIO = 3.3V 0.8
V VDDIO = 2.5V 0.7
VDDIO = 1.8V 0.5
|IIN| Input Current VIN = GND ~ VDDIO 10 µA
CMOS Level Outputs
VOH Output High Voltage
VDDIO = 3.3V 2.4
V VDDIO = 2.5V 2.0
VDDIO = 1.8V 1.5
VOL Output Low Voltage
VDDIO = 3.3V 0.4
V
VDDIO = 2.5V 0.4
VDDIO = 1.8V 0.3
|Ioz| Output Tri-State Leakage 10 µA
LED Outputs
ILED Output Drive Current Each LED pin (LED0, LED1) 8 mA
Notes:
7. Exceeding the absolute maximum rating can damage the device. Stresses greater than the absolute maximum rati ng can cause permanent damage
to the device. Operation of the device at these or any other conditions above those specif i ed in the operating sections of this specif ication is not
implied. Maximum conditions f or extended periods may affect reliability.
8. The device is not guarant eed to function outside its operat i ng rating.
9. TA = 25°C. Specification is for packaged product only.
10. Current consumption is for the single 3.3V supply KSZ8081MLX device only, and includes the transmit driver current and the 1.2V supply voltage
(VDD_1.2) that are s uppl i ed by the KSZ8081MLX.
Micrel, Inc.
KSZ8081MLX
August
19, 2015 45 Revision 1.3
Electrical Characteristics(9) (Continued)
Symbol Parameter Condition Min. Typ. Max. Units
All Pull-Up/Pull-Down Pins (including strapping pins)
pu Internal Pull-Up Resistance
VDDIO = 3.3V 30 45 73
kΩ VDDIO = 2.5V 39 61 102
VDDIO = 1.8V 48 99 178
pd Internal Pull-Down Resistance
VDDIO = 3.3V 26 43 79
kΩ VDDIO = 2.5V 34 59 113
VDDIO = 1.8V 53 99 200
100Base-TX Transmit (measured differentially after 1:1 transformer)
VO Peak Differential Output
Voltage 100Ω termination across differential output 0.95 1.05 V
VIMB Output Voltage Imbalance 100Ω termination across differential output 2 %
tr, tf Rise/Fall Time 3 5 ns
Rise/Fall Time Imbalance 0 0.5 ns
Duty Cycle Di stortion ±0.25 ns
Overshoot 5 %
Output Jitter Peak-to-peak 0.7 ns
10Base-T Transmit (measured differentially after 1:1 transformer)
VP Peak Differential Output
Voltage 100Ω termination across differential output 2.2 2.8 V
Jitter Added Peak-to-peak 3.5 ns
tr, tf Rise/Fall Time 25 ns
10Base-T Receive
VSQ Squelch Threshold 5MHz square wave 400 mV
Transmitter – Drive Setting
VSET Reference Voltage of ISET R(ISET) = 6.49kΩ 0.65 V
100Mbps Mode – Industr ial Applications Para met ers
Clock Phase Delay – XI Input
to MII TXC Output
XI (25MHz clock input) to MII TXC (25MHz clock
output) delay, referenced to rising edges of both
clocks. 15 20 25 ns
tllr Link Loss Reaction
(Indication) Time
Link loss detected at receive differential inputs to
PHY signal indication time for each of the following:
1. For LED mode 00, Speed LED output changes
from low (100Mbps) to high (10Mbps, defau lt stat e
for link-down).
2. For LED mode 01, Link LED output changes
from low (link-up) to high (link-down).
3. INTRP pin asserts for link-down status change.
4.4 µs
Micrel, Inc.
KSZ8081MLX
August
19, 2015 46 Revision 1.3
Timing Diagrams
MII SQE Timing (10Base-T)
Figure 9. MII SQE Timing (10Base-T)
Table 10. MII SQE Timing (10Base-T) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP TXC period 400 ns
tWL TXC pulse width low 200 ns
tWH TXC pulse width high 200 ns
tSQE COL (SQE) delay after TXEN de-asserted 2.2 µs
tSQEP COL (SQE) pulse duration 1.0 µs
Micrel, Inc.
KSZ8081MLX
August
19, 2015 47 Revision 1.3
MII Transmit Timing (10Base-T)
Figure 10. MII Transmit Timing (10Base-T)
Table 11. MII Transmit Timing (10Base-T) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP TXC period 400 ns
tWL TXC pulse width low 200 ns
tWH TXC pulse width high 200 ns
tSU1 TXD[3:0] setup to rising edg e of T X C 120 ns
tSU2 TXEN setup to rising edge of TXC 120 ns
tHD1 TXD[3:0] hold from rising edge of TXC 0 ns
tHD2 TXEN hold from rising edge of TXC 0 ns
tCRS1 TXEN high to CRS asserted latency 600 ns
tCRS2 TXEN low to CRS de-asserted latency 1.0 µs
Micrel, Inc.
KSZ8081MLX
August
19, 2015 48 Revision 1.3
MII Receive Timing (10Base-T)
Figure 11. MII Receive Timing (10Base-T)
Table 12. MII Receive Timing (10Base-T) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP RXC period 400 ns
tWL RXC pulse width low 200 ns
tWH RXC pulse width high 200 ns
tOD (RXDV, RXD[3:0], RXER) output delay from rising edge of RXC 205 ns
tRLAT CRS to (RXDV, RXD[3:0]) latency 7.2 µs
Micrel, Inc.
KSZ8081MLX
August
19, 2015 49 Revision 1.3
MII Transmit Timing (100Base-TX)
Figure 12. MII Transmit Timing (100Base-TX)
Table 13. MII Transmit Timing (100Base-TX) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP TXC period 40 ns
tWL TXC pulse width low 20 ns
tWH TXC pulse width high 20 ns
tSU1 TXD[3:0] setup to rising edg e of T X C 10 ns
tSU2 TXEN setup to rising edge of TXC 10 ns
tHD1 TXD[3:0] hold from rising edge of TXC 0 ns
tHD2 TXEN hold from rising edge of TXC 0 ns
tCRS1 TXEN high to CRS asserted latency 72 ns
tCRS2 TXEN low to CRS de-asserted latency 72 ns
Micrel, Inc.
KSZ8081MLX
August
19, 2015 50 Revision 1.3
MII Receive Timing (100Base-TX)
Figure 13. MII Receive Timing (100Base-TX)
Table 14. MII Receive Timing (100Base-TX) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP RXC period 40 ns
tWL RXC pulse width low 20 ns
tWH RXC pulse width high 20 ns
tOD (RXDV, RXD[3:0], RXER) output delay from rising edge of RXC 16 21 25 ns
tRLAT CRS to (RXDV, RXD[3:0] latency 170 ns
Micrel, Inc.
KSZ8081MLX
August
19, 2015 51 Revision 1.3
Auto-Negotiation Timing
Figure 14. Auto-Negotiation Fast Link Pulse (FLP) Timing
Table 15. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
Timing Parameter Description Min. Typ. Max. Units
tBTB FLP burst to FLP burst 8 16 24 ms
tFLPW FLP burst width 2 ms
tPW Clock/Data pulse width 100 ns
tCTD Clock pulse to data pulse 55.5 64 69.5 µs
tCTC Clock pulse to clock pulse 111 128 139 µs
Number of clock/data pulses per FLP burst 17 33
Micrel, Inc.
KSZ8081MLX
August
19, 2015 52 Revision 1.3
MDC/MDIO Timing
Figure 15. M DC/MDIO Timing
Table 16. MDC/MDIO Timing Parameters
Timing Parameter Description Min. Typ. Max. Unit
fc MDC clock frequency 2.5 10 MHz
tP MDC period 400 ns
tMD1 MDIO (PHY input) setup to rising edge of MDC 10 ns
tMD2 MDIO (PHY input) hold from rising edge of MDC 4 ns
tMD3 MDIO (PHY output) delay from rising edge of MDC 5 222 ns
Micrel, Inc.
KSZ8081MLX
August
19, 2015 53 Revision 1.3
Power-Up/Reset Timing
The KSZ8081MLX reset timing requirement is summarized in Figure 16 and Table 17.
Figure 16. Power-Up/Reset Timing
Table 17. Power-Up/Reset Timing Parameters
Parameter
Description
Min.
Max.
Units
tVR Supply voltage (VDDIO, VDDA_3.3) rise tim e 300 µs
tSR Stable supply voltage (VDDIO, VDDA_3.3) to reset high 10 ms
tCS Configurat i on setu p time 5 ns
tCH Configuration hold time 5 ns
tRC Reset to strap-in pin output 6 ns
The supply voltage (VDDIO and VDDA_3.3) power-up waveform should be monotonic. The 300µs minimum rise time is from
10% to 90%.
For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500µs. The strap-in pin values are read
and updated at the de-assertion of reset.
After the de-assertion of reset, wait a minimum of 100µs before starting programming on the MIIM (MDC/MDIO) interface.
Micrel, Inc.
KSZ8081MLX
August
19, 2015 54 Revision 1.3
Reset Circuit
Figure 17 shows a reset circuit recommended for powering up the KSZ8081MLX if reset is triggered by the power supply.
Figure 17. Recommended Reset Circuit
Figure 18 Shows a reset circuit recommended for applications where reset is driven b y another device (for example, the
CPU or a n FPG A). T he res et out R ST _OUT _n fr om CPU/FPG A provi des th e war m res et after power up reset. D2 is used
if using different VDDIO between the switch and CPU/FPGA, otherwise, the different VDDIO will fight each other. If
different VDDIO have to use in a special case, a low VF (<0.3V) diode is required (For example, Vishay’s BAT54,
MSS1P2L and so on), or a level shifter device can be used too. If Ethernet device and CPU/FPGA use same VDDIO
voltage, D2 c an be remove d to connect both de vices directl y. Usually, Eth ernet device and CP U/FPGA sho uld use same
VDDIO voltag e.
Figure 18. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output
Micrel, Inc.
KSZ8081MLX
August
19, 2015 55 Revision 1.3
Reference Circuits
−
LED Strap-In Pins
The pull-up, float, and pull-do wn reference c ircuits f or the LED1/SPEE D and LED0/NWAYEN strappin g pins are sho wn in
Figure 19 for 3.3V and 2.5V VDDIO.
Figure 19. Reference Circuits for LED Strapping Pins
For 1.8V VDDIO, LED indication support is not recommended due to the low voltage. Without the LED indicator, the
SPEED and NWAYEN strapping pins are functional with a 4.7kΩ pull-up to 1.8V VDD IO or float for a value of ‘1’, and with
1.0kΩ pull-down to ground for a value of ‘0’.
Note: If using RJ 45 Jack s with integrated LEDs and 1.8V VDDIO , a level shif ting is re quired from LED 3.3V to 1.8V. For
example, use a bipolar transistor or a level shift device.
Micrel, Inc.
KSZ8081MLX
August
19, 2015 56 Revision 1.3
Reference Clock
−
Connection and Selection
A crystal or external clock source, suc h as an oscillat or, is used to pro vide the ref erence clock for the KSZ 8081MLX. For
the KSZ8081MLX in all operating modes, the reference clock is 25MHz. The reference clock connections to XI (Pin 15)
and XO (Pin 14), and the reference clock selection criteria, are provided in Figur e 20 and Table 18.
Figure 20. 25MHz Crystal/Oscillator Reference Clock Connection
Table 18. 25MHz Crystal / Reference Clock Selection Criteria
Characteristics Value Units
Frequency 25 MHz
Frequency tolerance (maximum)(11) ±50 ppm
Crystal series resistance (typical) 40 Ω
Crystal load capacitance (typical) 16 pF
Note:
11. ±60ppm for overtemperature crystal.
Micrel, Inc.
KSZ8081MLX
August
19, 2015 57 Revision 1.3
Magnetic
−
Connection and Selection
A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs
exceeding FCC requirements.
The KSZ8081MLX design incorporates voltage-mode transmit drivers and on-chip terminations.
With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential
pairs. Therefore, the two transformer center tap pins on the KSZ8081MLX side should not be connected to any power
supply source on the board; instead, the center tap pins should be separated from one another and connected through
separate 0.1µF common-mode capacitors to ground. Separation is required because the common-mode voltage is
different between transmitting and receiving differential pairs.
Figure 21 shows the typical magnetic interface circuit for the KSZ8081MLX.
Figure 21. Typical Magnetic Interface Circuit
Micrel, Inc.
KSZ8081MLX
August
19, 2015 58 Revision 1.3
Table 19 lists recommended magnetic characteristics.
Table 19. Magnetics Selection Criteria
Parameter Value Test Condition
Turns ratio 1 CT : 1 CT
Open-circuit inductance (min. ) 350µH 100mV, 100kHz, 8mA
Insertion lo ss (typ.) –1.1dB 100kHz to 100M Hz
HIPOT (min.) 1500Vrms
Table 20 is a l ist of com pati ble si ng le-port magnet ic s w ith sep ar ate d tr ans f ormer center tap p ins on t he PH Y chip s id e th at
can be used with the KSZ8081MLX.
Table 20. Compatible Single-Port 10/100 Magnetics
Manufacturer Part Number Temperature Range Magnetic + RJ-45
Bel Fuse S558-5999-U7 0°C to 70°C No
Bel Fuse SI-46001-F 0°C to 70°C Yes
Bel Fuse SI-50170-F 0°C to 70°C Yes
Delta LF8505 0°C to 70°C No
HALO HFJ11-2450E 0°C to 70°C Yes
HALO TG110-E055N5 –40°C to 85°C No
LANKom LF-H41S-1 0°C to 70°C No
Pulse H1102 0°C to 70°C No
Pulse H1260 0°C to 70°C No
Pulse HX1188 –40°C to 85°C No
Pulse J00-0014 0°C to 70°C Yes
Pulse JX0011D21NL –40°C to 85°C Yes
TDK TLA-6T718A 0°C to 70°C Yes
Transpower HB726 0°C to 70°C No
Wurth/Midcom 000-7090-37R-LF1 –40°C to 85°C No
Micrel, Inc.
KSZ8081MLX
August
19, 2015 59 Revision 1.3
Package Information and Recommended Land Pattern(12)
48-Pin 7mm × 7mm LQFP (MM)
Note:
12. Package i nformat i on is correct as of the publication date. For updat es and most current informati on, go to www.micrel.com.
Micrel, Inc.
KSZ8081MLX
August
19, 2015 60 Revision 1.3
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
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, Inc. is a leading global manufact urer of IC solutions for t he worldwide high performance linear and po wer, LAN, and tim ing
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markets. The Company’s products include advanced mixed
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