Spartan-3L - Xilinx, Inc.

DS313 (v1.0) November 3, 2004 www.xilinx.com 1

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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Introduction

Spartan™-3L Field-Programmable Gate Arrays (FPGAs)

consume less static current than corresponding members

of the standard Spartan-3 family. Spartan-3L devices pro-

vide the identical function, features, timing, and pinout of the

original Spartan-3 family. Features include programmable

I/Os, Configurable Logic Blocks (CLBs), RAM blocks, Digital

Clock Managers (DCMs), and Multiplier blocks. This rich

feature set taken together with low selling prices and

reduced quiescent current levels make the Spartan-3L fam-

ily the first choice for power-sensitive consumer electronic

applications.

Another power-saving benefit of the Spartan-3L family

beyond static current reduction is the Hibernate mode,

which lowers device power consumption to the lowest pos-

sible levels.

The three-member Spartan-3L family ranges in density

from one to four million system gates and offers as many as

633 I/Os. All devices are specified to meet the –4 speed

grade over the commercial temperature range.

This data sheet explains how the Spartan-3L family is differ-

ent from the Spartan-3 family. For specifications and other

technical information not contained in this document, refer

to the Spartan-3 data sheet (DS099).

Features

• Power current reduction compared to Spartan-3 family:

- Up to 68% less quiescent current

- Up to 98% less quiescent current in Hibernate

mode

• Low cost, low power logic solution for high-volume,

consumer-oriented applications

- Densities as high as 62,000 logic cells

• SelectIO™ signaling

- Up to 633 I/O pins

- Seventeen single-ended signal standards

- Seven differential signal standards including LVDS

and RSDS

- Double Data Rate (DDR) support

• Logic resources

- Abundant logic cells with shift register capability

- Wide multiplexers

- Fast look-ahead carry logic

- Dedicated 18 x 18 multipliers

- JTAG logic compatible with IEEE 1149.1/1532

• SelectRAM™ hierarchical memory

- Up to 1,728 Kbits of total block RAM

- Up to 432 Kbits of total distributed RAM

• Digital Clock Manager (four DCMs)

- Clock skew elimination

- Frequency synthesis

- High-resolution phase shifting

• Eight global clock lines and abundant routing

• Pin-compatible with Spartan-3 FPGAs

• Pb-free packaging options

• Fully supported by Xilinx ISE development system

- Synthesis, mapping, placement, and routing

• MicroBlaze™ processor, PCI, and other cores

• Power estimation using Web Power Tool and XPower

- Refer to http://www.xilinx.com/power

Spartan-3L Low Power FPGA

Family

DS313 (v1.0) November 3, 2004 00Advance Product Specification

Table 1: Summary of Spartan-3L FPGA Attributes

Device

System

Gates

Logic

Cells

CLB Array

(One CLB = Four Slices) Distributed

RAM bits(1)

Block RAM

bits(1)

Dedicated

Multipliers DCMs

Maximum

User I/O

Maximum

Differential

I/O PairsRows Columns Total CLBs

XC3S1000L 1M 17,280 48 40 1,920 120K 432K 24 4 333 149

XC3S1500L 1.5M 29,952 64 52 3,328 208K 576K 32 4 487 221

XC3S4000L 4M 62,208 96 72 6,912 432K 1,728K 96 4 633 300

Notes:

1. By convention, one Kb is equivalent to 1,024 bits.

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Architectural Overview

The Spartan-3L family architecture consists of five funda-

mental programmable functional elements:

•Configurable Logic Blocks (CLBs) contain

RAM-based Look-Up Tables (LUTs) to implement logic

and storage elements that can be used as flip-flops or

latches. CLBs can be programmed to perform a wide

variety of logical functions as well as to store data.

•Input/Output Blocks (IOBs) control the flow of data

between the I/O pins and the internal logic of the

device. Each IOB supports bidirectional data flow plus

3-state operation. Twenty-four different signal

standards, including seven high-performance

differential standards, are available, as shown in

Ta b l e 2 . Double Data-Rate (DDR) registers are

included. The Digitally Controlled Impedance (DCI)

feature provides automatic on-chip terminations,

simplifying board designs.

•Block RAM provides data storage in the form of

18-Kbit dual-port blocks.

•Multiplier Blocks accept two 18-bit binary numbers as

inputs and calculate the product.

•Digital Clock Manager (DCM) Blocks provide

self-calibrating, fully digital solutions for distributing,

delaying, multiplying, dividing, and phase-shifting clock

signals.

These elements are organized as shown in Figure 1. A ring

of IOBs surrounds a regular array of CLBs. The XC3S1000L

and XC3S1500L have two columns of block RAM. The

XC3S4000L has four RAM columns. Each column is made

up of several 18Kbit RAM blocks; each block is associated

with a dedicated multiplier. The DCMs are positioned at the

ends of the outer block RAM columns.

The Spartan-3L family features a rich network of traces that

interconnect all five functional elements, transmitting sig-

nals among them. Each functional element has an associ-

ated switch matrix that permits multiple connections to the

routing.

Configuration

Spartan-3L FPGAs are programmed by loading configura-

tion data into robust static memory cells that collectively

control all functional elements and routing resources.

Before powering on the FPGA, configuration data is stored

externally in a PROM or some other nonvolatile medium

either on or off the board. After applying power, the configu-

ration data is written to the FPGA using any of five different

modes: Master Parallel, Slave Parallel, Master Serial, Slave

Serial and Boundary Scan (JTAG). The Master and Slave

Parallel modes use an 8-bit wide SelectMAP™ port.

The recommended memory for storing the configuration

data is the low-cost Xilinx Platform Flash PROM family,

which includes the XCF00S PROMs for serial configuration

and the higher density XCF00P PROMs for parallel or serial

configuration.

Figure 1: Spartan-3L Family Architecture

DS099-1_01_032703

Notes:

1. The two additional block RAM columns of the XC3S4000L devices are shown

with dashed lines.

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I/O Capabilities

The SelectIO feature of Spartan-3L devices provides 17 sin-

gle-ended standards and seven differential standards as

listed in Tabl e 2 . Many standards support the DCI feature,

which uses integrated terminations to eliminate unwanted

signal reflections. Ta b l e 3 shows the number of user I/Os as

well as the number of differential I/O pairs available for each

device/package combination.

Table 2: Signal Standards Supported by the Spartan-3L Family

Standard

Category Description

VCCO

(V) Class Symbol

DCI

Option

Single-Ended

GTL Gunning Transceiver Logic N/A Terminated GTL Yes

Plus GTLP Yes

HSTL High-Speed Transceiver Logic 1.5 I HSTL_I Yes

III HSTL_III Yes

1.8 I HSTL_I_18 Yes

II HSTL_II_18 Yes

III HSTL_III_18 Yes

LVCMOS Low-Voltage CMOS 1.2 N/A LVCMOS12 No

1.5 N/A LVCMOS15 Yes

1.8 N/A LVCMOS18 Yes

2.5 N/A LVCMOS25 Yes

3.3 N/A LVCMOS33 Yes

LVTTL Low-Voltage Transistor-Transistor Logic 3.3 N/A LVTTL No

PCI Peripheral Component Interconnect 3.0 33 MHz PCI33_3 No

SSTL Stub Series Terminated Logic 1.8 N/A SSTL18_I Yes

2.5 I SSTL2_I Yes

II SSTL2_II Yes

Differential

LDT

(ULVDS)

Lightning Data Transport (HyperTransport™) 2.5 N/A LDT_25 No

LVDS Low-Voltage Differential Signaling Standard LVDS_25 Yes

Bus BLVDS_25 No

Extended Mode LVDSEXT_25 Yes

LVPECL Low-Voltage Positive Emitter-Coupled Logic 2.5 N/A LVPECL_25 No

RSDS Reduced-Swing Differential Signaling 2.5 N/A RSDS_25 No

Table 3: User I/O and Differential (Diff) I/O Counts

Device

FT256

FTG256

FG320

FGG320

FG456

FGG456

FG676

FGG676

FG900

FGG900

User Diff User Diff User Diff User Diff User Diff

XC3S1000L 173 76 221 100 333 149 ----

XC3S1500L - - 221 100 333 149 487 221 - -

XC3S4000L - - - - - - - - 633 300

Notes:

1. All Spartan-3L and Spartan-3 devices in the same package are pin-compatible.

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Package Marking

Figure 2 shows the package marking for Spartan-3L FPGAs. The markings on the Spartan-3L package are similar to those

on the Spartan-3 package. The ‘L’ in the last line, indicating low power, distinguishes the Spartan-3L device.

Ordering Information

Spartan-3L FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The

Pb-free packages include a ‘G’ character in the ordering code. Spartan-3L FPGAs are available in a single speed grade, –4,

and are specified over the Commercial temperature range.

Standard Packaging

Pb-Free Packaging

For additional information on Pb-free packaging, see XAPP427: Xilinx Lead Free Packages.

Figure 2: Spartan-3L Package Marking

Lot Code

Date Code

XC3S1500TM

FG676xxx0450

xxxxxxxxx

L4C

SPARTAN

Device Type

Package

Low Power

Speed Grade

Temperature Range

DS313_02_102204

XC3S1500L -4 FG 676 C

Device Type

Speed Grade

Temperature Range:

C = Commercial (TJ = 0oC to 85oC)

Package Type Number of Pins

Example:

DS313_03_101204

Device Speed Grade Package Type / Number of Pins Temperature Range (TJ)

XC3S1000L –4 FT(G)256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) C Commercial (0°C to 85°C)

XC3S1500L FG(G)320 320-ball Fine-Pitch Ball Grid Array (FBGA)

XC3S4000L FG(G)456 456-ball Fine-Pitch Ball Grid Array (FBGA)

FG(G)676 676-ball Fine-Pitch Ball Grid Array (FBGA)

FG(G)900 900-ball Fine-Pitch Ball Grid Array (FBGA)

XC3S1500L -4 FG 676 C

Device Type

Speed Grade

Temperature Range:

C = Commercial (TJ = 0oC to 85oC)

Package Type

Number of Pins

Pb-free

GExample:

DS313_04_101204

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Spartan-3L Low Power FPGA Family
DS313 (v1.0) November 3, 2004 www.xilinx.com 5
Advance Product Specification
R
Functional Description
The Spartan-3L FPGA family is identical to the Spartan-3
FPGA family with respect to device function. See the func-
tional description in Module 2 of the Spartan-3 data sheet
(DS099-2) for more information.
Achieving Low Quiescent Current Levels
Because of their lower quiescent current specifications,
Spartan-3L devices always consume less power than
Spartan-3 devices.
For power-sensitive applications that must manage con-
sumption over long periods with no FPGA activity, it is pos-
sible to achieve the quiescent current levels specified in
Ta b l e 4  of the DC and Switching Characteristics section
on page 8 by meeting the test conditions described below
the table. The easiest way to realize these conditions is by
pulling PROG_B Low. This action puts all I/Os into a
high-impedance state, ceases all internal switching, and
converts the bitmap held in internal memory to all zeros. In
this case, reconfiguration is necessary before the FPGA
can resume operation in the User mode. Disable internal
pull-up and pull-down resistors on all I/O pins to save addi-
tional power.
Hibernate Mode
Hibernate mode starts with the approach described above.
This takes power savings one step further by switching off
power rails. This mode reduces quiescent power consump-
tion to the lowest possible level. The FPGA is put into the
Hibernate mode by switching off the VCCINT (core) and
VCCAUX (auxiliary) power supplies. Power is supplied to
VCCO lines throughout the hibernation period. Figure 3,
page 6 is a block diagram that shows how to put Spartan-3L
FPGAs into the Hibernate mode.
During the Hibernation period, the VCCINT and VCCAUX rails
are turned off. It is recommended that power FETs with Low
on resistance be used to perform the switching action. Con-
figuration data is lost upon entering the Hibernate mode;
therefore, reconfiguration is necessary after exiting the
mode.
In general, it is safest to maintain VCCO power for all banks
throughout the Hibernation period. This keeps the power
diodes inside the IOBs off when signals are applied to the
pins. For each I/O, a power diode extends from the pin (the
anode side) to the associated VCCO rail (the cathode side).
Power diodes are present on all signal-carrying pins all of
the time. In Hibernate mode, powered VCCO rails account
for little current, because the I/Os are in a high-impedance
state. 
It is also possible to switch off the VCCO rail for a particular
bank. This action eliminates the VCCO current for those
banks—current on the order of a few milliamperes. There
are two ways to achieve this. One way is to keep the voltage
of all I/Os belonging to that bank under 0.5V. Another way is
to disable signals coming from external devices (such as
Device 1 in Figure 3)
Holding the PROG_B input Low during the transition into
Hibernation period keeps all output drivers in a high-imped-
ance state. Release PROG_B after re-applying power to the
VCCINT and VCCAUX rails. See Special Considerations,
page 7 for recommended levels on Dedicated and
Dual-Purpose pins.
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Figure 3: Hibernate Diagram

VCCAUX

VCCO

Supply

VCCO

Supply

VCCINT

I/O Bank

Spartan-3L

FPGA

2.5V 1.2V

Power

Control

PROG_B

LOW Device 1

Device 2

HSWAP_EN

I/O Bank

DS313_01_110304

Figure 4: Hibernate Mode Waveforms

PROG_B

I/Os

VCCINT

VCCAUX

VCCO (Banks 0 - 7)

INIT_B

DONE

CCLK Undefined

in Master Mode

DS313_05_110304

Hibernate

Undefined

startup cycles

Notes:

1. See Special Considerations, page 7 for recommended levels on Dedicated and Dual-Purpose pins.

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Figure 4, page 6 shows the waveforms for entering and exit-

ing the Hibernate mode.

The steps for entering the Hibernate mode are as follows:

1. Pull the PROG_B pin Low to put all I/Os into a

high-impedance state.

2. The FPGA drives the INIT_B and DONE pins Low.

3. External switches are used to turn off the VCCINT and

VCCAUX rails. This action resets the FPGA. As

described above, it is possible to switch off VCCO for a

given bank in cases where the I/O pins of the

associated bank are Low or disabled throughout the

Hibernation period.

4. The FPGA is now in the Hibernate mode. As long as the

FPGA is kept in this state, power consumption rests at

the lowest possible level.

The steps for exiting the Hibernate mode are as follows:

1. Before FPGA initialization can begin, it is necessary to

deassert PROG_B to a High logic level. The rising

transition must occur after turning all three power

supplies back on.

2. Reapply power to all rails that were switched off. Of the

three rails, do not apply power to the VCCINT rail last,

(i.e., after having powered the VCCAUX and VCCO rails).

The VCCINT ramp must reach its minimum

recommended operating voltage (1.14V) before the last

power ramp (either VCCAUX or VCCO) begins.

3. After logic initialization, the FPGA releases the

open-drain INIT_B signal. Now that INIT_B is High,

reconfiguration can begin.

4. When configuration is complete, the FPGA enters the

Startup phase, asserts DONE, and enables the I/Os,

according to how the BitGen options are set.

5. The FPGA is now ready for user operation.

Special Considerations

In the Hibernate mode, whenever one of the VCCO rails is

turned off, keep the voltage on the I/O pins of the associated

bank below 0.5V. As an alternative, it is possible to disable

any signals that an external device might apply to the bank’s

I/O pins. Voltages higher than 0.5V can turn on the power

diodes. Keeping the diode off prevents “reverse current”

from flowing into the VCCO rail.

VCCO Bank 4 powers the Dual-Purpose inputs: INIT_B, DIN,

BUSY, and D0-D3. VCCO Bank 5 powers the other Dual-Pur-

pose inputs: RDWR_B, CS_B, and D4-D7. The VCCO lines

of Banks 0, 1, 4, and 5 power the Global Clock inputs

GCLK0 - GCLK1, GCLK2 - GCLK3, GCLK4 - GCLK5, and

GCLK6 - GCLK7, respectively. In the Hibernate mode, if any

of these rails is turned off, do not apply voltages in excess of

0.5V to any of the associated Dual-Purpose pins. This mea-

sure keeps the power diodes off.

VCCAUX powers the Dedicated inputs: PROG_B,

HSWAP_EN, M0-M2, CCLK (in Slave mode), TDI, TCK,

and TMS. Once in the Hibernate mode, do not apply volt-

ages in excess of 0.5V to any of these pins. In this case,

keeping the power diode off prevents a “reverse current”

from flowing into the VCCAUX rail.

VCCAUX powers the Dedicated outputs: DONE, CCLK (in

Master mode), and TDO. Once in the Hibernate mode, the

states of these pins are undefined.

VCCO Bank 4 powers the Dual-Purpose outputs:

BUSY/DOUT. Whenever VCCO Bank 4 is turned off during

the Hibernation period, the state of this pin is undefined.

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DC and Switching Characteristics

Like-density Spartan-3L and Spartan-3 devices share the

same AC and DC specifications with the exceptions of

reduced quiescent supply current consumption and specifi-

cations for the Hibernate mode. The reduced quiescent cur-

rent levels are shown in Ta bl e 4 . At present all Spartan-3L

devices are classified as Revision 0. All specifications in this

document are for Revision 0 silicon.

When in the Hibernate mode, Spartan-3L devices consume

still less quiescent current, as shown in Table 5. In this

mode, the FPGA only dissipates ICCOH current. The VCCINT

and VCCAUX rails are electrically disconnected and will not

dissipate power.

For all other DC and AC specifications, refer to Module 3 of

the Spartan-3 data sheet (DS099-3).

Table 4: Quiescent Supply Current Characteristics

Symbol Description Device Typ Max Units

ICCINTQ Quiescent VCCINT supply current XC3S1000L 30.0 45.0 mA

XC3S1500L 50.0 90.0 mA

XC3S4000L 160.0 220.0 mA

ICCOQ Quiescent VCCO supply current XC3S1000L 2.0 6.0 mA

XC3S1500L 2.5 8.0 mA

XC3S4000L 4.0 10.0 mA

ICCAUXQ Quiescent VCCAUX supply current XC3S1000L 25.0 29.0 mA

XC3S1500L 40.0 46.0 mA

XC3S4000L 62.0 80.0 mA

Notes:

1. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O

pads disabled. For typical values, the ambient temperature (TA) is 25°C with VCCINT = 1.2V, VCCO (all banks) = 2.5V, and

VCCAUX =2.5V. For maximum I

CCINT and ICCO values, the junction temperature (TJ) is 85°C with VCCINT = 1.26V and VCCO = 3.45V,

respectively. For maximum ICCAUX values, TJ = 0°C with VCCAUX = 2.625V. In all quiescent measurements, the FPGA is programmed

with a "blank" configuration data file (i.e., a bitmap consisting of all zeros). For conditions other than those described above, (e.g., a

design including functional elements, the use of DCI standards, etc.), measured quiescent current levels may be slightly higher than

the values in the table. Use the Web Power Tool or XPower for more accurate estimates. See Note 2.

2. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The

Spartan-3 Web Power Tool at http://www.xilinx.com/power provides quick, approximate, typical estimates, and does not require a

netlist of the design. b) XPower, part of the Xilinx development software, takes a netlist as input to provide more accurate maximum

and typical estimates.

3. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on

successfully.

Table 5: Supply Current Characteristics for Hibernate Mode

Symbol Description Device Max Units

ICCOH Quiescent VCCO supply current in Hibernate mode XC3S1000L 6.0 mA

XC3S1500L 8.0 mA

XC3S4000L 10.0 mA

Notes:

1. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with pull-up/pull-down resistors at all I/O

pads disabled. For maximum ICCOH values, TJ= 85°C with VCCO (all banks) = 3.45V. VCCINT = 0V and VCCAUX = 0V. PROG_B is

Low.

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Pinout Descriptions

Spartan-3L and Spartan-3 devices that correspond in den-

sity and package have the same pinout. See the Pinout

Descriptions in Module 4 of the Spartan-3 data sheet

(DS099-4) for more information.