General Description
The Maxim ICL7116 and ICL7117 are 3½ digit monolithic
analog-to-digital converters. They differ from the Maxim
ICL7106 and ICL7107 in that the ICL7116 and ICL7117
have a Hold pin, which makes it possible to hold or
“freeze” a reading. These integrating ADCs have very
high input impedances and directly drive LCD (ICL7116)
and LED (ICL7117) displays.
Versatility and accuracy are inherent features of these
converters. The dual-slope conversion technique auto-
matically rejects interference signals common in industrial
environments. The true differential input is particularly
useful when making ratiometric measurements (ohms or
bridge transducers). Maxim has added a zero-integrator
phase to the ICL7116 and ICL7117, eliminating overrange
hangover and hysteresis effects. Finally, these devices
offer high accuracy by lowering rollover error to less than
one count and zero reading drift to less than 1µV/ºC.
Applications
These devices can be used in a wide range of digital
panel meter applications. Most applications, however,
involve the measurement and display of analog data:
Features
●Improved 2nd Source!
●Hold Pin Allows Indefinite Display Hold
●Guaranteed First Reading Recovery from Overrange
●On-Board Display Drive Capability—No External
Circuitry Required: LCD (ICL7116), LED (ICL7117)
●High-Impedance CMOS Differential Inputs
●Low Noise (< 15µVP-P) Without Hysteresis or
Overrange Hangover
●Clock and Reference On-Chip
●Zero Input Gives Zero Reading
●True Polarity Indication for Precision Null Applications
Ordering Information appears at end of data sheet.
●Pressure
●Voltage
●Resistance
●Temperature
●Conductance
●Current
●Speed
●Material Thickness
ANALOG
INPUT
ICL7116
+
-
LCD DISPLAY
V
REF
CLOSED = HOLD
OPEN = RUN
9V
TO ANALOG
COMMON PIN
[PIN 32]
TOP VIEW
C1
B1 TEST
1
2
40
39
HOLD
D1 OSC2
OSC3
OSC1
PDIP
3
4
38
37
G1
E1 C-REF
5
6
36
35
A1
F1 V+
C+REF
REF HI
7
8
34
33
D2 COMMON
9 32
C2 ON HI
10 31
B2 ON LO
11 30
A2
F2
E2
A/Z
BUFF
INT
12 29
13 28
14
D3
15
B316
F3
17
E3
AB4
POL
V-
G2
C3
A3
G3
BP/GND
18
19
20
27
26
25
24
23
22
21
ICL7116
ICL7117
Detailed Circuit Diagram - see Figure 1 Pin Configurations continued at end of data sheet
ICL7116/ICL7117 3½ Digit ADCs with Display Hold
19-0949; Rev 2; 1/17
Typical Operating Circuit
Pin Congurations
EVALUATION KIT AVAILABLE
Supply Voltage
ICL7116, V+ to V- ..................................................................15V
ICL7117, V+ to GND .............................................................+6V
ICL7117, V- to GND............................................................... -9V
Analog Input Voltage (either input) (Note 1)................... V+ to V-
Reference lnput Voltage (either input)............................ V+ to V-
Clock Input
ICL7116 ................................................................... Test to V+
ICL7117 ..................................................................GND to V+
Power Dissipation (Note 2)
Ceramic Package ..........................................................1000mW
CERDIP Package ............................................................800mW
Plastic Package ...............................................................800mW
Operating Temperature Range ............................... 0ºC to +70ºC
Storage Temperature Range .............................-65ºC to +160ºC
Lead Temperature (soldering, 60s) ................................. +300ºC
PARAMETER CONDITIONS MIN TYP MAX UNITS
Zero Input Reading VIN = 0V
Full Scale = 200.00mV -000.0 ±000.0 +000.0 Digital
Reading
Ratiometric Reading VIN = VREF = 100mV 999 999/
1000 1000 Digital
Reading
Rollover Error (Difference in Reading for Equal
Positive and Negative Reading Near Full
Scale)
-VIN = +VIN = 200mV -1 ±0.2 +1 Counts
Linearity (Max. Deviation from Best Straight
Line Fit)
Full Scale = 200mV
or Full Scale = 2.00mV -1 ±0.2 +1 Counts
Common-Mode Rejection Ratio (Note 4) VCM = 1V, VIN = 0V
Full Scale = 200.00mV 50 µV/V
Noise (Pk-Pk Value Not Exceeded 95% of the
Time)
VIN = 0V
Full Scale = 200.00mV 15 µV
Leakage Current at Input VIN = 0V 1 10 pA
Zero Reading Drift VIN = 0V, 0°C < TA < 70°C 0.2 1 µV/°C
Scale Factor Temperature Coefcient
VIN = 199.0mV
0°C < TA < 70°C
(Ext. Ref. 0ppm/°C)
1 5 ppm/°C
V+ Supply Current (Does Not Include LED
Current for ICL7117) VIN = 0V 0.8 1.8 mA
V- Supply Current for ICL7117 Only 0.6 1.8 mA
Analog Common Voltage (With Respect to
Positive Supply) 25Ω Between Common and Positive Supply 2.4 2.8 3.2 V
Temperature Coefcient of Analog Common
(With Respect to Pos. Supply) 25Ω Between Common and Positive Supply 80 ppm/°C
Input Resistance, Pin 1 (Note 6) 30 70 kΩ
VIL, Pin 1 (ICL7116 Only) TEST – 1.5 V
ICL7116/ICL7117 3½ Digit ADCs with Display Hold
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Note 1: Input voltage may exceed supply voltages, provided the input current is limited to 100µA.
Note 2: Dissipation rating assumes device is mounted with all leads soldered to the PCB.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics (Note 3)
This device conforms to the Absolute Maximum Ratings on adjacent page.
●Guaranteed Overload Recovery Time
● Signicantly Improved ESD Protection (Note 8)
●Low Noise
●Key Parameters Guaranteed Over Temperature
●Negligible Hysteresis
●Maxim Quality and Reliability
●Increased Maximum Rating for Input Current (Note 9)
Note 3: Unless otherwise noted, specifications apply to both the ICL7116 and ICL7117 at TA = +25°C, fCLOCK = 48kHz. ICL7116 is
tested in the circuit of Figure 1. ICL7117 is tested in the circuit of Figure 2.
Note 4: Refer to “Differential input” discussion (see Maxim’s ICL7106/ICL7107 data sheet).
Note 5: Backplane drive is in phase with segment drive for ‘off’ segment, 180º out of phase for on segment. Frequency is 20 times
the conversion rate. Average DC component is less than 50mV.
Note 6: The ICL7116 logic input has an internal pulldown resistor connected from HLDR, pin 1, to TEST, pin 37. The ICL7117 logic
input has an internal pulldown resistor connected from HLDR. Pin 1, to GROUND, pin 21.
(Specifications below satisfy or exceed all ‘tested’ parameters on adjacent page V+ = 9V, TA = +25ºC, fCLOCK = 48kHz; test circuit =
Figure 1 (ICL7116), Figure 2 (ICL7117), unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Zero Input Reading
VIN = 0V
Full Scale = 200.00mV
TA = +25°C (Note 7)
-000.0 ±000.0 +000.0 Digital
Reading
0°C ≤ TA ≤ +70°C (Note 11) -000.0 ±000.0 +000.0
Ratiometric Reading
VIN = VREF = 100mV
TA = +25°C (Note 7) 999 999/
1000 1000 Digital
Reading
0°C ≤ TA ≤ +70°C (Note 11) 999 999/
1000 1001
Rollover Error (Difference in Reading for
Equal Positive and Negative Reading Near
Full Scale)
-VIN = +VIN = 200mV
TA = +25°C (Note 7) -1 ±0.2 +1 Counts
0°C ≤ TA ≤ +70°C (Note 11) ±0.2
Linearity (Max. Deviation from Best Straight
Line Fit)
Full Scale = 200mV
or Full Scale = 2.00mV -1 ±0.2 +1 Counts
PARAMETER CONDITIONS MIN TYP MAX
VIL, Pin 1 (ICL7117 Only) GND +1.5 V
VIH, Pin 1 (Both) V+ - 1.5 V
ICL7116 Only (Note 5)
Pk-Pk Segment Drive Voltage,
Pk-Pk Backplane Drive Voltage
V+ to V- = 9V
4 5 6
V
4 5 6
ICL7117 Only (Except Pin 19) Segment
Sinking Current
V+ = 5.0V
Segment Voltage = 3V 5 8.0 mA
(Pin 19 Only) 10 16
ICL7116/ICL7117 3½ Digit ADCs with Display Hold
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Absolute Maximum Ratings
Electrical Characteristics (continued) (Note 3)
Maxim Advantages
Electrical Characteristics
Specifications below satisfy or exceed all ‘tested’ parameters on adjacent page V+ = 9V, TA = +25ºC, fCLOCK = 48kHz; test circuit =
Figure 1 (ICL7116), Figure 2 (ICL7117), unless otherwise noted.)
Note 7: Test condition is VIN applied between pins IN HI and IN LO i.e., 1MΩ resistor in Figure 1 and Figure 2.
Note 8: All pins are designed to withstand electrostatic discharge (ESD) levels in excess of 2000V (Test circuit per MIL. Std. 883C.
Method 3015 2).
Note 9: Input voltages may exceed the supply voltage provided the input current is limited to ±1mA (This revises Note 1 on the
adjacent page).
Note 10: Number of measurement cycles for display to give accurate reading.
Note 11: 1MΩ resistor is removed in Figure 1 and Figure 2.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Common-Mode Rejection Ratio (Note 4) VCM = ±1V, VIN = 0V
Full Scale = 200.00mV 50 µV/V
Noise (Pk-Pk Value Not Exceeded 95%
of the Time)
VIN = 0V
Full Scale = 200.00mV 15 µV
Input Leakage Current VIN = 0V, TA = +25°C (Note 7) 1 10 pA
0°C ≤ TA ≤ +70°C 20 200
Zero Reading Drift VIN = 0V, 0°C ≤ TA ≤ +70°C 0.2 1 µV/°C
Scale Factor Temperature Coefcient
VIN = 199.0mV
0°C ≤ TA ≤ +70°C
(Ext. Ref. 0ppm/°C)
1 5 ppm/°C
V+ Supply Current (Does Not Include LED
Current for ICL7117)
VIN = 0V, TA = +25°C 0.8 1.8 mA
0°C ≤ TA ≤ +70°C 2
V- Supply Current for ICL7117 Only 0.6 1.8 mA
Analog Common Voltage (With Respect to
Positive Supply) 25Ω Between Common and Positive Supply 2.4 2.8 3.2 V
Temperature Coefcient of Analog Common
(With Respect to Pos. Supply) 25Ω Between Common and Positive Supply 80 ppm/°C
Input Resistance, Pin 1 (Note 6) 30 70 kΩ
VIL, Pin 1 (ICL7116 Only) TEST + 1.5 V
VIL, Pin 1 (ICL7117 Only) GND + 1.5 V
VIH, Pin 1 (Both) V+ - 1.5 V
ICL7116 Only (Note 5)
Pk-Pk Segment Drive Voltage,
Pk-Pk Backplane Drive Voltage
V+ to V- = 9V 4 5 6 V
ICL7117 Only (Except Pin 19) Segment
Sinking Current
V+ = 5.0V
Segment Voltage = 3V 5 8.0 mA
(Pin 19 Only) 10 16
ICL7116 Only – Test Pin Voltage With respect to V+ 4 5 6 V
Overload Recovery Time
(Note 10) VIN changing from ±10V to 0V 0 1
Measur-
ement
Cycles
ICL7116/ICL7117 3½ Digit ADCs with Display Hold
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Electrical Characteristics (continued)
Detailed Description
The Maxim ICL7116 and ICL7117 3½ digit ADCs are
similar to the Maxim ICL7106 and ICL7107, except for the
addition of a Hold pin. For a detailed product description,
package dimensions, and applications information (other
than the operation of the Hold pin described below) refer
to Maxim’s ICL7106 and ICL7107 data sheet
Hold Input
The Hold input is a digital input with a logic threshold
approximately midway between V+ and Test (ICL7116)
or V+ and Ground (ICL7117). The ICL7116/ICL7117 con-
tinuously performs conversions, independent of the Hold
input. When the Hold input is connected to V+, however,
the display latch pulse is inhibited, and the the display
latches are not updated. The Hold input has a 70kΩ pull-
down resistor to Test (ICL7116) or Ground (ICL7117) and
the Hold input will be pulled low if it is left open. When
Hold is low the ICL7116/ICL7117 updates the display
at the end of each conversion. The Hold input is CMOS
compatible and can also be driven by a switch connected
to V+ (Figure 1 and Figure 2) or by a PNP transistor.
Unlike the ICL7106 and the ICL7107, the ICL7116 and
ICL7117 do not have a Reference Low input. Apply the
reference voltage between Reference High (REF HI) and
Common.
Figure 1. Maxim ICL7116 Typical Operating Circuit, 200mV Reference
ANALOG
INPUT
ICL7116
+
-
LCD DISPLAY
VREF
CLOSED = HOLD
OPEN = RUN
9V
TO ANALOG
COMMON PIN
[PIN 32]
IN HI
31
IN LO
30
32
1MΩ
0.01µF
COMMON
BUFF
28
A-Z
29
INT
29
0.47µF
0.22µF
47kΩ
39
34 33
0.1µF
C+REF C-REF
OSC2OSC3OSC1
38 COSC
100pF
100kΩ
40
ROSC
SEGMENT
DRIVE
2–19
22–25
POL
BP
20
21 MINUS SIGN
BACKPLANE
DRIVE
HOLD 1
V+
V-
REF HI
35
36
26
24kΩ
10kΩ
ICL7116/ICL7117 3½ Digit ADCs with Display Hold
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Figure 2. Maxim ICL7117 Typical Operating Circuit, 200mV Reference
D
3
E
2
F
2
A
2
B
2
C
2
D
2
E
1
G
1
F
1
B
3
F
3
E
3
AB
4
POL
4
BP/GND [7116/7117]
G
3
A
3
C
3
G
2
V
-
INT
BUFF
A/Z
IN LO
IN H1
COMMON
C
-REF
C
+REF
A
1
B
1
C
1
D
1
HLDR
OSC
1
OSC
2
OSC
3
TEST
REF HI
V
+
0.168"
(4.27mm)
0.130"
(3.30mm)
Chip Topography
ANALOG
INPUT
ICL7117
+
-
LCD DISPLAY
V
REF
CLOSED = HOLD
OPEN = RUN
TO ANALOG
COMMON PIN
[PIN 32]
IN HI
31
IN LO
30
32
1MΩ
0.01µF
COMMON
BUFF
28
A-Z
29
INT
29
0.47µF
0.22µF
47kΩ
39
34 33
0.1µF
C+REF C-REF
OSC
2
OSC
3
OSC
1
38 C
OSC
100pF
100kΩ
40
R
OSC
SEGMENT
DRIVE
2–19
22–25
POL
BP
20
21
BACKPLANE
DRIVE
1
V
+
V
-
REF HI
35
36
26
24kΩ
10kΩ
+5V
+5V
HOLD
ICL7116/ICL7117 3½ Digit ADCs with Display Hold
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+Denotes lead(Pb)-free/RoHS-compliant package.
PART TEMP RANGE PIN-PACKAGE
ICL7116CPL 0°C to +70°C 40 PDIP
ICL7116CJL 0°C to +70°C 40 CERDIP
ICL7116CQ 0°C to +70°C 44 LPCC
ICL7116C/D 0°C to +70°C Dice
ICL7117CPL 0°C to +70°C 40 PDIP
ICL7117CJL 0°C to +70°C 40 CERDIP
ICL7117CMH+ 0°C to +70°C 44 MQFP
ICL7117CQ 0°C to +70°C 44 LPCC
ICL7117C/D 0°C to +70°C Dice
N.C.
G2
C3
A3
G3
BP/GND
POL
AB4
E3
F3
B3
N.C.
N.C.
TEST
OSC3
N.C.
OSC2
OSC1
HOLD
D1
C1
B1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
REF HI
V+
C+ REF
C- REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
MQFP
ICL7117
TOP VIEW
+
441234 404142
43
5
21 24 26
25 27 2822 2319 20
8
9
10
11
12
13
14
15
16
17 29
30
31
32
33
34
35
36
37
38
D3
E3
B1
PLCC
TOP VIEW
C1
D1
HOLD
N.C.
OSC1
OSC2
OSC3
TEST
REF HI
F3
POL
AB4
BP/GND
N.C.
A3
G3
G2
C3
C+ REF
C- REF
COMMON
IN HI
N.C.
IN LO
A/Z
BUFF
INT
V-
E2
F2
A2
B2
N.C.
C2
D2
E1
G1
739 V+F1
6
18
A1B3
ICL7116
ICL7117
ICL7116/ICL7117 3½ Digit ADCs with Display Hold
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Chip Information
PROCESS: CMOS
Ordering Information
Pin Congurations (continued)
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 9/85 Initial release —
1 9/13 Added the 44 MQFP package to data sheet 1–8
2 1/17 Updated Figure 2 and Pin Conguration diagram 6, 7
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
ICL7116/ICL7117 3½ Digit ADCs with Display Hold
© 2017 Maxim Integrated Products, Inc.
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Revision History
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