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TDA7266P
July 2004
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1 FEATURES
■TECHNOLOG Y BI20II
■WIDE SUPPL Y VOLTAGE RA N GE (3.5 - 12V)
■OUTPUT POWER:
– 3+3W @THD = 10 % , RL = 8Ω, VCC = 7.5V
– 4+4W M usic Power @THD = 10%, RL = 8Ω,
VCC = 8.5V
■SI NGLE SU PPL Y
■MINIMUM EXTERNAL COMPONENTS:
– NO SVR CAPACIT O R
– NO B OOTST RAP
– NO BOUCHE ROT CELLS
– INTERNALLY FIXED GAIN
■STAND-BY & MUTE FUNCTIONS
■SHORT CIRCUIT PROTECTION
■THER MAL OVERLOAD PR OT ECTIO N
2 DESCRIPTION
The TDA7266P is a dual bridge amplifier specially
designed for LCD TV/Monitor, PC Motherboard, TV
and Portable Audio applications.
PRODUCT PREVIEW
3+3W DUAL BRIDGE AMPLIFIER
Figu re 2. Test and A pp li cat io n D i agram
5
6
8
Vref
ST-BY 11
C3 0.22µF
V
CC
187
D03AU1531A
+
-
-
+
OUT1+
OUT1-
20
19
17
MUTE 10
IN2
C5 0.22µF
+
-
-
+
OUT2+
OUT2-
24
14
S-GND
PW-GND
C1
470µFC2
100nF C7
100n
F
1
C4
10µF
C6
1µF
R3 10K
R4 10K
+5V
REV. 2
Figure 1. Package
T
able 1. Order Codes
Part Number Packa ge
TDA7266P PowerSSO24 (Slug Down)
PowerSSO24 (Slug Down)
TDA7266P
2/12
Table 2. Absolute Maximum Ratings
Figure 3. Pin Connection (Top view)
Symbol Parameter Value Unit
VsSupply Voltage 20 V
IOOutput Peak Current (internally limited) 1.5 A
Top Operating Temperature 0 to 70 °C
Tstg, TjStorage and Junction Temperature -40 to 150 °C
Table 3. Themal Data
Symbol Parameters Value Unit
R
th j-case
Thermal Resistance Junction to Case Typ. 1.5 °C/W
PW GN
D
N.C.N.C.
N.C.
N.C.
OUT2-
OUT2+
+VS
IN2
N.C.
N.C.10
8
9
7
6
5
4
3
2
17
18
19
20
21
23
22
24
16
1
15MUTE
D03AU1532
STBY
12
11
N.C.
SGND
N.C.
14
13
IN1
+VS
OUT1+
OUT1-
N.C.
N.C.
N.C.
P
W GND
3/12
TDA7266P
(*) Me asured on demoboard of figure 8 with gaussian nois e si gnal w hi ch simulates Music /Speech progr am m es.
Table 4.
Electrical Characteristcs
(R e fe r to te st circuit; V
CC
= 7.5V, R
L
= 8
Ω
, f = 1KHz, T
amb
= 25°C unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
VCC Supply Range 3.5 12 V
IqTotal Quiescent Current 40 mA
VOS Output Offset Voltage 120 mV
POOutput Power THD 10% 3 W
POOutput Music Power (*) 4 W
THD Total Harmonic Distortion PO = 1W 0.03 0.2 %
PO = 0.1W to 2W
f = 100Hz to 15KHz 1%
SVR Supply Voltage Rejection f = 100Hz, VR =0.5V 40 56 dB
CT Crosstalk 46 60 dB
AMUTE Mute Attenuation 60 80 dB
TwThermal Threshold 150 °C
GVClosed Loop Voltage Gain 25 26 27 dB
∆GVVoltage Gain Matching 0.5 dB
RiInput Resis tance 25 30 KΩ
VTMUTE Mute Threshold for VCC > 6.4V; Vo = -30dB 2.3 2.9 4.1 V
for VCC < 6.4V; Vo = -30dB VCC/2
-1 VCC/2
-0.75 VCC/2
-0.5 V
VTST-BY St-by Threshold 0.8 1.3 1.8 V
IST-BY St-by Current V6 = GND 100 µA
eNTotal Output Voltage A Curve 150 µV
TDA7266P
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3 APPLIC ATIVE SUG GESTIONS
3.1 STAND-BY AND MUTE FUNCTIONS
3.1.1 (A) Micro processor Application
In order to av oid annoying "Pop-Noi se" during T urn-On/Off transients, it is necessary to guarantee the right St-
by and m u te signals sequence.It is quite simple to obt ain this function using a microprocessor (Fig. 4 and 5).
At first St-by si gnal (from
µ
P) goes high and the voltage ac ross the St-by terminal (Pin 11) starts to increase
exponentially. The externa l RC netw o rk is intended to turn-on slowly the biasing circuits of the amplifier, this to
avoid "POP " and "CLIC K" on the outputs.
When this voltage reaches the St-by threshold level, the amplifier is switched-on and the ex ternal capacitors in
series to the input terminals (C 1, C3) start to charge.
It's necessary to mantain the mute signal low until the capacitors are fully charged, this to avoid that the device
goes in play mode causing a loud "Pop Noise" on the speakers.
A delay of 100-200ms between S t-by and mute signals is suitable for a p roper operation.
Figure 4. Micropr ocess or Application
5
6
8
Vref
ST-BY 11
IN1
C1 0.22µF
VCC
187
D03AU1533
+
-
-
+
OUT1+
OUT1-
20
19
17
MUTE 10
IN2
C3 0.22µF
+
-
-
+
OUT2+
OUT2-
24
14
S-GND
PW-GND
C5
470µFC6
100n
F
R1 10K
C2
10µF
µP
R2 10K
C4
1µF
1
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TDA7266P
Figure 5. Microprocessor Drivin g Signal s
3.1.2 B) Low Cost Application
In low cost applic ations where the
µ
P is not present, the suggested circuit is shown in fig.6.
The St-by and mute terminals are tied together and they are con nected to the supply line via an external voltage
divider.
The device is switched-on/off from the supply line and the external capacitor C4 is intended to delay the St-by
and m ute threshold exceeding, avoiding "Popping" problems.
So to avoid any popping or clicking sond, it is im portant to clock:
aCorrect Sequence: At turn-ON, the Stand-by must be removed a t first, then the M ute must be re-
leased af ter a delay of abo ut 100-200ms . On the contra ry at turn-OF F the Mute must be activated
as fir st and then the Stand-by.
With the values suggested in the A pplication circuit the right operation is guaranteed.
bCorrect Threshol d Vol tages: I n order t o av oid t hat due t o the spread in the internal thresholds (see
the above limits) a wrong e xternal v ol tage c auses unc ertain c om mu tations for t he two func tions we
sugg est to use the follo wing values:
Mute for V cc> 6 .4 V : VT = 2 .3 V
Mute fo r Vcc< 6 .4 V : VT = V cc/2 - 1
Stand-by : VT = 0.8V
+
VS(V)
VIN
(mV)
VST-BY
pin 11
Iq
(mA)
ST-BY MUTE
PLAY MUTE ST-BY
+7.5
1.8
0.8
VMUTE
pin 10
4.1
2.3
OFF
OFF
D03AU1535
A
VOUT
(V)
2.9
1.3
TDA7266P
6/12
Figu re 6. S ta nd-alone lo w-c o s t Ap pl ication
Fi gure 7. Ap plication C i rc uit
5
6
8
Vref
ST-BY 11
IN1
C3 0.22µF
VCC
187
D03AU1534A
+
-
-
+
OUT1+
OUT1-
20
19
17
MUTE 10
IN2
C5 0.22µF
+
-
-
+
OUT2+
OUT2-
24
14
S-GND
PW-GND
C1
470µFC2
100nF C7
100n
F
R1
24K
C4
10µF
R2
47K
1
5
6
8
Vref
ST-BY
JP1
11
IN1
C3 0.22µF
V
CC
187
D03AU1551
+
-
-
+
OUT1+
OUT1-
20
19
17
MUTE 10
IN2
C5 0.22µF
+
-
-
+
OUT2+
OUT2-
24
14
S-GND
PW-GND
C1
470µFC2
100nF C7
100n
F
1
C4
10µF
R1
R2
C6
1µF
R3 10K
R4 10K
+5V
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TDA7266P
Figure 8. PCB Component Layout
Figure 9. PCB Copper Top (Top view)
Figure 10. PCB Copper Bottom (Top view)
TDA7266P
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4 PCB LAYOUT AND EXTERNAL COMPONENTS
Regarding the PCB layout care must be taken for three main subjects:
1) Signal and Power Gnd separation
2) Dissipating Copper Area
3) Filter Capacitors positioning
1) Signal and Power Gnd separation:
To the Signal GND must be referred the A udio Input Si gnals, the Mut e and Stand-b y Voltages and t he
device PIN.14. This Gnd path must be as clean as possible in order to improve the device THD+Noise
and to avoid spurious oscillations across the speakers.
The P ower GN D is di re ctly con nected to th e Ou tput po wer S tag e trans istors (Em itters) and is cros sed
by larg e am oun t of current , this pat h is al so used in th is de vice t o d issipat e the heating generat ed (no
needs of external heatsinker).
Referring to the typical application circuit, the separation bet ween the two GND paths must be obt ained
connecting them separat ely (star routing) to the bulk
Electrolithic capacitor C1 (470µF).
Regarding the Power Gnd dime nsioning w e have to consider the Dissipated P ower the Thermal Pro-
tection Threshold and the Package thermal Characteristics.
2) Dissipating Copper A rea:
Dissipated Power:
The max dissipated power happens for a THD near 1% and is given by the formula:
This gives for: V cc = 7 .5 V, Rl = 8
Ω
,Iq = 40mA a dissipated pow er of Pd = 3W.
Thermal Protection:
The thermal protection threshold is placed at a junction temperature of 150°C.
Package Th erm al Characteristics:
The thermal resistance Junction to Ambient obtainable with a GND copper Area of 3x3 cm and with 16 via
holes (see picture) is about 25°C/W. This means that with the above mentioned max dissipated Power
(Pd=3W) w e can expect a 75°C, this gives a safety margin before the thermal protection intervention in the
consumer environments where a 50°C ambient is specified as max imum
Figure 11.
3)Filter Capacitors Position ing:
The two Ceramic capacitors C2/C7 (100nF ) must be placed as close as possible
respe ctively to the two Vcc pins ( 7 - 18) in orde r t o avoid the possibiltiy of oscillations arisi ng on t he
outpu t Audio signals.
P
dmax W() 2VCC
2
π2Rl
2
------
--------------IqVCC
+⋅=
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TDA7266P
5 TYPICAL CHARACTERISTICS
(Referred to application circ uit of figure 8 unless otherwise specified)
Figure 12. Distortion vs Frequency
Figure 13. Distortion vs Output Power
Figure 14. Distortion vs Output Power
Figure 15. Gain vs Frequency
Fi g ure 1 6 . Mut e A t t e n uatio n v s Vpin .1 0
Figure 17. Stand-By attenuation vs Vpin 11
0.010
0.1
1
10
100 1k 10k
20k
T
HD(%)
Vcc = 7.5V
Rl = 8 ohm
Pout = 100mW
Pout = 2W
frequency (Hz)
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
%
100m 3200m 300m 400m500m 700m 1 2
W
Vs= 7.5V
Rl= 8 Ohm
F= 1 KHz
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
%
100m 4200m 300m 400m 600m 800m 1 2 3
W
Vs= 8 .5V
Rl= 8 Ohm
F= 1 KHz
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
%
100m 4200m 300m 400m 600m 800m 1 2 3
W
Vs= 8 .5V
Rl= 8 Ohm
F= 1 KHz
-5.000
-4.000
-3.000
-2.000
-1.000
0.0
1.0000
2.0000
3.0000
4.0000
5.0000
10 100 1k 10k
100k
L
evel(dBr)
Vcc = 7.5V
Rl = 8 ohm
Pout = 1W
frequency (Hz)
11.522.533.544.5
5
0
10
-10
-20
-30
-40
-50
-60
-70
-80
-90
-1
00
Attenuation (dB)
Vpin.10(V)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.
4
0
10
-10
-20
-30
-40
-50
-60
-70
-80
-90
-
100
-
110
-
120
Attenuation (dB)
Vpin.11 (V)
TDA7266P
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Figure 18. PowerS SO24 Me chan ic al Data & Pack age Dim ension s
OUTLINE AND
M E CHANICAL DATA
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.15 2.47 0.084 0.097
A2 2.15 2.40 0.084 0.094
a100.07500.003
b 0.33 0.51 0.013 0.020
c 0.23 0.32 0.009 0.012
D (1) 10.10 10.50 0.398 0.413
E (1) 7.4 7.6 0.291 0.299
e 0.8 0.031
e3 8.8 0.346
G 0.10 0.004
G1 0.06 0.002
H 10.10 10.50 0.398 0.413
h 0.40 0.016
L 0.55 0.85 0.022 0.033
N 10˚ (max)
X 4.10 4.70 0.161 0.185
Y 6.50 7.10 0.256 0.279
(1) “D and E1 ” do not in clude mold flash or protusions.
Mold flash or protusions shall not exc eed 0.15mm (0.0 06”)
(2) No intrusion allowed inwards the leads.
(3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm
per side
PowerSSO24
7412828 A
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TDA7266P
Table 5. Revision History
Date Revision Description of Changes
May 2004 1 First Issue
July 2004 2 Electrical Characteristics: Deleted TYP. Value VCC
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TDA7266P
