–4–
SET-UP CONDITIONS
Care should be taken before applying power and signals
to the evaluation board to ensure that all link positions
are as per the required operating mode. Figure 5 shows
the silkscreen layout of the board in order to ease setup.
The following are the required link positions for the two
modes of operation.
External Clocking Mode
LK1 Both links in Position A configuring both SCLK and
RFS as inputs.
LK2 This link selects the reference input and can be
placed in any of the 3 positions. A–internal refer-
ence, B–AD780, C–external reference from SKT9.
LK3 This should be in place connecting MUX OUT to
SHA IN.
LK4 There should be a link inserted in each of the fol-
lowing positions to connect the analog inputs
from SKT1 to SKT8 to their respective input, B, D,
F, H, J, L, N and P.
LK5 This link is put in place for applications that require
data to be transmitted and received at the same
time, i.e., it ties TFS and RFS together. If this facil-
ity is not required then the link is omitted.
Internal Clocking Mode
LK1 Both links in Position B configuring both SCLK and
RFS as outputs.
All other links can be configured as for the external
clocking mode described above.
CONTROLLING THE AD7890
There are two modes (external clocking and self-
clocking) of operation applicable to the AD7890 and are
selected by the SMODE pin which is controlled from LK1
on the evaluation board. Channel selection is controlled
through a 5-bit control register which is accessible
through the serial port (SKT14). This control register
contains three bits for channel address, a software con-
version start bit and a bit to put the part into sleep mode.
There are two methods of initiating a conversion on the
AD7890, the software conversion start and a hardware
conversion start which can be applied through the con-
version start input (SKT10). A rising edge on this
CONVST input puts the track/hold into hold mode and a
conversion is initiated. The conversion time for the part
is determined from the clock signal applied to CLK IN
(SKT11) on the board. With a 2.5 MHz master clock, con-
version time for the AD7890 is 5.9 µs from the rising
edge of the CONVST signal. 2 µs is required for track/
hold acquisition time. An internal pulse is generated and
appears on CEXT whenever a multiplexer address is
loaded to the AD7890 control register, and its duration
will depend on the value of CEXT used. In applications
where the multiplexer is switched and conversion is ini-
tiated at the same time a 120 pF capacitor should be con-
nected to CEXT to allow for the acquisition time of the
track/hold before conversion is initiated.
Software conversion starts are initiated by writing a
logic 1 to the CONV bit of the control register. The inter-
nal pulse and the conversion process are initiated after
the sixth serial clock cycle of the write cycle if a 1 is writ-
ten to the CONV bit. With a 1 in the CONV bit the external
CONVST input is disabled. Writing a 0 to the CONV bit in
the control register enables the external convert start.
External Clocking Mode
The AD7890 is configured for its external clocking mode
by tying the SMODE pin of the device to a logic high
(LK1 on evaluation board in Position A). In this mode,
SCLK and RFS of the AD7890 are configured as inputs.
This external clocking mode is designed for direct inter-
face to systems which provide a serial clock output
which is synchronized to the serial data output including
microcontrollers such as the 80C51, 87C51, 68HC11 and
68HC05 and most digital signal processors. Figure 3
shows a timing and control sequence required to obtain
optimum performance from the part in external clocking
mode.
In the sequence shown in Figure 3, conversion is initi-
ated on the rising edge of CONVST, and new data is
available in the output register of the AD7890 5.9 µs
later. Once the read operation has taken place, a further
500 ns should be allowed before the next rising edge of
CONVST to optimize the settling of the track/hold before
the next conversion is initiated. The diagram shows the
read operation and the write operation taking place in
parallel. On the sixth falling edge of SCLK in the write
sequence, the internal pulse will be initiated. Assuming
MUX OUT is connected to SHA IN, 2 µs are required
between this sixth falling edge of SCLK and the rising
edge of CONVST to allow for the full acquisition time of
the track/hold amplifier. With the serial clock rate at its
maximum of 10 MHz, the achievable throughput rate
for the part is 5.9 µs (conversion time) plus 0.6 µs (six
serial clock pulses before internal pulse is initiated)
plus 2 µs (acquisition time). This results in a minimum
throughput time of 8.5 µs (equivalent to a throughput
rate of 117 kHz). If the part is operated with a slower
serial clock, it will impact the achievable throughput
rate.
Applications that want to achieve optimum performance
from the AD7890 will have to ensure that the data read
does not occur during conversion or during 500 ns prior
to the rising edge of CONVST. This can be achieved in
either of two ways. The first is to ensure in software that
the read operation is not initiated until 5.9 µs after the
rising edge of CONVST. This will only be possible if the
software knows when the CONVST command is issued.
The second scheme would be to use the CONVST signal
as both the conversion start signal and an interrupt sig-
nal. The simplest way to do this would be to generate a
square wave signal for CONVST with high and low times
of 5.9 µs (see Figure 4). Conversion is initiated on the
rising edge of CONVST. The falling edge of CONVST
occurs 5.9 µs later and can be used as either an active
low or falling edge-triggered interrupt signal to tell the