1
Data sheet acquired from Harris Semiconductor
SCHS250A
Features
• Buffered Inputs
• Typical Propagation Delay
- 10ns at VCC = 5V, TA = 25oC, CL = 50pF
• Exceeds 2kV ESD Protection per MIL-STD-883,
Method 3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
•±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
Description
The ’AC280 and ’ACT280 are 9-bit odd/even parity genera-
tor/checkers that utilize Advanced CMOS Logic technology.
Both even and odd parity outputs are available for checking
or generating parity for words up to nine bits long. Even par-
ity is indicated (∑E output is HIGH) when an even number of
data inputs is HIGH. Odd parity is indicated (∑O output is
HIGH) when an odd number of data inputs is HIGH. Parity
checking for words larger than nine bits can be accom-
plished by tying the ∑E output to any input of an additional
’AC280, ’ACT280 parity checker.
Pinout
CD54AC280, CD54ACT280
(CERDIP)
CD74AC280, CD74ACT280
(PDIP, SOIC)
TOP VIEW
Functional Diagram
Ordering Information
PART
NUMBER TEMP.
RANGE (oC) PACKAGE
CD54AC280F3A -55 to 125 14 Ld CERDIP
CD74AC280E 0 to 70oC, -40 to 85,
-55 to 125 14 Ld PDIP
CD74AC280M 0 to 70oC, -40 to 85,
-55 to 125 14 Ld SOIC
CD54ACT280F3A -55 to 125 14 Ld CERDIP
CD74ACT280E 0 to 70oC, -40 to 85,
-55 to 125 14 Ld PDIP
CD74ACT280M 0 to 70oC, -40 to 85,
-55 to 125 14 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local TI sales office or cus-
tomer service for ordering information.
I6
I7
NC
I8
∑E
∑O
GND
VCC
I5
I4
I3
I2
I1
I0
1
2
3
4
5
6
7
14
13
12
11
10
9
8
8
9
10
11
13
2
1
12
5
6∑ ODD
∑ EVEN
I0
I1
I2
I3
I5
I6
I7
I4
4
I8
GND = 7
VCC = 14
NC = 3
August 1998 - Revised May 2000
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © 2000, Texas Instruments Incorporated
CD54/74AC280,
CD54/74ACT280
9-Bit Odd/Even Parity Generator/Checker
2
F
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
Thermal Resistance (Typical, Note 5) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX
AC TYPES
High Level Input Voltage VIH - - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V
5.5 3.85 - 3.85 - 3.85 - V
Low Level Input Voltage VIL - - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V
5.5 - 1.65 - 1.65 - 1.65 V
High Level Output Voltage VOH VIH or VIL -0.05 1.5 1.4 - 1.4 - 1.4 - V
-0.05 3 2.9 - 2.9 - 2.9 - V
-0.05 4.5 4.4 - 4.4 - 4.4 - V
-4 3 2.58 - 2.48 - 2.4 - V
-24 4.5 3.94 - 3.8 - 3.7 - V
-75
(Note 6, 7) 5.5 - - 3.85 - - - V
-50
(Note 6, 7) 5.5----3.85 - V
CD54/74AC280, CD54/74ACT280
3
Low Level Output Voltage VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V
0.05 3 - 0.1 - 0.1 - 0.1 V
0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75
(Note 6, 7) 5.5 - - - 1.65 - - V
50
(Note 6, 7) 5.5-----1.65 V
Input Leakage Current IIVCC or
GND - 5.5 - ±0.1 - ±1-±1µA
Quiescent Supply Current
MSI ICC VCC or
GND 0 5.5 - 8 - 80 - 160 µA
ACT TYPES
High Level Input Voltage VIH - - 4.5 to
5.5 2-2-2-V
Low Level Input Voltage VIL - - 4.5 to
5.5 - 0.8 - 0.8 - 0.8 V
High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V
-24 4.5 3.94 - 3.8 - 3.7 - V
-75
(Note 6, 7) 5.5 - - 3.85 - - - V
-50
(Note 6, 7) 5.5----3.85 - V
Low Level Output Voltage VOL VIH or VIL 0.05 4.5 - 0.1 - 0.1 - 0.1 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75
(Note 6, 7) 5.5 - - - 1.65 - - V
50
(Note 6, 7) 5.5-----1.65 V
Input Leakage Current IIVCC or
GND - 5.5 - ±0.1 - ±1-±1µA
Quiescent Supply Current
MSI ICC VCC or
GND 0 5.5 - 8 - 80 - 160 µA
AdditionalSupplyCurrentper
Input Pin TTL Inputs High
1 Unit Load
∆ICC VCC
-2.1 - 4.5 to
5.5 - 2.4 - 2.8 - 3 mA
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.
ACT Input Load Table
INPUT UNIT LOAD
All 1.43
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX
CD54/74AC280, CD54/74ACT280
4
Switching Specifications Input tr, tf = 3ns, CL= 50pF (Worst Case)
PARAMETER SYMBOL VCC (V)
-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX
AC TYPES
Propagation Delay,
Any Input to ∑OtPLH, tPHL 1.5 - - 239 - - 263 ns
3.3
(Note 9) 7.5 - 26 7.3 - 29 ns
5
(Note 10) 5.4 - 19.1 5.3 - 21 ns
Propagation Delay,
Any Input to ∑EtPLH, tPHL 1.5 - - 227 - - 250 ns
3.3 7.2 - 25 7 - 28 ns
5 5.2 - 18.2 5 - 20 ns
Input Capacitance CI- - -10- -10pF
Power Dissipation Capacitance CPD
(Note 11) - - 115 - - 115 - pF
ACT TYPES
Propagation Delay,
Any Input to ∑OtPLH, tPHL 5
(Note 10) 5.6 - 19.6 5.4 - 21.6 ns
Propagation Delay,
Any Input to ∑EtPLH, tPHL 5 5.6 - 19.6 5.4 - 21.6 ns
Input Capacitance CI- - -10- -10pF
Power Dissipation Capacitance CPD
(Note 11) - - 115 - - 115 - pF
NOTES:
8. Limits tested 100%
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. CPD is used to determine the dynamic power consumption per package.
AC: PD = VCC2 fi(CPD + CL)
ACT: PD = VCC2 fi(CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
FIGURE 1.
10%
VS
tr = 3ns
VS
tPHL tPLH
VSVS
VS
VS
tf = 3ns
10%
INPUT
LEVEL
In
0V
ΣO
ΣE
0V
0V
tPLH tPHL
DUT
OUTPUT
RL (NOTE)
OUTPUT
LOAD
500Ω
CL
50pF
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
FIGURE 2. PROPAGATION DELAY TIMES
AC ACT
Input Level VCC 3V
Input Switching Voltage, VS0.5 VCC 1.5V
Output Switching Voltage, VS0.5 VCC 0.5 VCC
CD54/74AC280, CD54/74ACT280
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD54AC280F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
CD54ACT280F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
CD74AC280E ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74AC280EE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74AC280M ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC280M96 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC280M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC280M96G4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC280ME4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC280MG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74ACT280E ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74ACT280EE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74ACT280M ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74ACT280M96 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74ACT280M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74ACT280M96G4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74ACT280ME4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74ACT280MG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 1
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74AC280M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74ACT280M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74AC280M96 SOIC D 14 2500 367.0 367.0 38.0
CD74ACT280M96 SOIC D 14 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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