1
FEATURES
APPLICATIONS
CONTENTS
DESCRIPTION
1
2
3
4
19
18
17
16
SYNC
PGD
LVBP
RT
SA−
SAO
GND
SS
TPS40075
15
14
13
12
KFF
ILIM
VDD
HDRV
5
6
7
8
FB
COMP
PGND
LDRV
9 DBP
20
SA+
10
SW
11
BOOST
SYNC IN
PowerGood OUT
UDG−04075
VIN
VOUT+
VOUT−
VOUT−
(at Load) VOUT+
(at Load)
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007www.ti.com
MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLERWITH VOLTAGE FEED-FORWARD
The TPS40075 drives external N-channel MOSFETsusing second generation Predictive Gate Drive to2
•Operation Over 4.5-V to 28-V Input Range
minimize conduction in the body diode of the low side•Fixed-Frequency Voltage-Mode Controller
FET and maximize efficiency. Pre-biased outputs aresupported by not allowing the low side FET to turn on•Integrated Unity Gain Amplifier for Remote
until the voltage commanded by the closed loop softOutput Sensing
start is greater than the pre-bias voltage. Voltage•Predictive Gate Drive™ Generation II for
feed forward provides good response to inputImproved Efficiency
transients and provides a constant PWM gain over a•<1% Internal 700-mV Reference
wide input voltage operating range to easecompensation requirements. Programmable short•Input Voltage Feed Forward Control
circuit protection provides fault current limiting and•Prebiased Output Compatible
hiccup recovery to minimize power dissipation with a•Internal Gate Drive Outputs for High-Side and
shorted output. The 20-pin QFN package gives goodSynchronous N-Channel MOSFETs
thermal performance and a compact footprint.•Switching Frequency Programmable to 1 MHz
SIMPLIFIED APPLICATION DIAGRAM•20-Pin QFN Package•Thermal Shutdown Protection•Software Design Tool and EVM Available
•Power Modules•Networking/Telecom
•Industrial
•Servers
Device Ratings 2Electrical Characteristics 4Terminal Information 12Application Information 15Design Example 26Additional References 40
The TPS40075 is a mid voltage, wide input (4.5-V to28-V), synchronous, step-down controller, offeringdesign flexibility for a variety of user programmablefunctions, including; soft start, UVLO, operatingfrequency, voltage feed-forward and high-side FETsensed short circuit protection.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Predictive Gate Drive is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DEVICE RATINGS
ABSOLUTE MAXIMUM RATINGS
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
ORDERING INFORMATION
T
A
PACKAGE PART NUMBER
TPS40075RHLT
(1)40 °C to 85 °C Plastic QFN (RHL)
TPS40075RHLR
(2)
(1) The TPS40075 is available taped and reeled only. Add an T suffix (i.e. TPS40075RHLT) to the orderable part number for quantities of250 units per small reel. .(2) Add an R suffix (i.e. TPS40075RHLR) to the orderable part number for quantities of 3,000 units per large reel.
over operating free-air temperature range unless otherwise noted
(1)
TPS40075 UNIT
VDD, ILIM 30FB, KFF, PGD, SYNC – 0.3 to 6SW – 0.3 to 40 VV
DD
Input voltage range
SA+, SA- – 0.3 to 11SW, transient < 50 ns – 2.5SW, transient – 125 V ×nsCOMP, RT, SS – 0.3 to 6BOOST, HDRV 50V
OUT
Output voltage range VDBP, SAO, LDRV 10.5LVBP 6I
OUT
Output current source LDRV, HDRV 1.5
ALDRV, HDRV 2.0I
OUT
Output current sink
KFF 10RT 1 mAI
OUT
Output current source
LVBP 1.5T
J
Operating junction temperature range – 40 to 125
°CT
stg
Storage temperature – 55 to 150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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RECOMMENDED OPERATING CONDITIIONS
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
PACKAGE DISSIPATION RATINGS
(1)
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
MIN NOM MAX UNIT
V
DD
Input voltage 4.5 28 VT
A
Operating free-air temperature -40 85 °C
PARAMETER MIN TYP MAX UNIT
Human body model 1500 VCDM 1500
THERMAL IMPEDANCEAIRFLOW (LFM) JUNCTION-TO-AMBIENT T
A
= 25 °C POWER RATING (W) T
A
= 85 °C POWER RATING (W)(°C/W)
Natural Convection 42 2.38 0.95
200 35 2.85 1.14
400 31 3.22 1.29
(1) For more information on the RHL package and the test method, refer to TI technical brief, literature number SZZA017. The ratings in thistable are for the JEDEC High-K board.
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ELECTRICAL CHARACTERISTICS
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
T
A
= – 40 °C to 85 °C, V
IN
= 12 V
dc
, R
T
= 90.9 k Ω, I
KFF
= 300 µA, f
SW
= 500 kHz, all parameters at zero power dissipation(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
V
DD
Input voltage range, VIN 4.5 28 V
OPERATING CURRENT
I
DD
Quiescent current Output drivers not switching 2.5 3.5 mA
LVBP
V
LVBP
Output voltage T
A
= T
J
= 25 °C 3.9 4.2 4.5 V
OSCILLATOR/RAMP GENERATOR
f
OSC
Accuracy 450 500 550 kHzV
RT
RT voltage 2.23 2.40 2.58 Vt
ON(min)
Minimum output pulse time
(1)
C
HDRV
= 0 nF 150 nsV
IH
High-level input voltage, SYNC 2 5
VV
IL
Low-level input voltage, SYNC 0.8I
SYNC
Input current, SYNC 5 10 µAV
FB
= 0 V, 100 kHz ≤f
SW
≤500 kHz 84% 95%Maximum duty cycle
V
FB
= 0 V, f
SW
= 1 MHz 76% 93%V
KFF
Feed-forward voltage 0.35 0.40 0.45 VI
KFF
Feed-forward current operating range
(1)
20 1100 µA
SOFT START
I
SS
Charge current 9.5 12 14.5 µAt
DSCH
Discharge time C
SS
= 3.9 nF 25 75
µsC
SS
= 3.9 nF, V
SS
rising from 0.7 V to 1.6t
SS
Soft-start time 210 290 500VV
SSSD
Shutdown threshold, V
SS
falling 225 275 325V
SSEN
Enable threshold, V
SS
rising 310 410 mVV
SSSDHYS
Shutdown threshold hysteresis 35 130
DBP
V
DD
> 10 V 7 8 9V
DBP
Output voltage VV
VDD
= 4.5 V, I
OUT
= 25 mA 4.0 4.3
ERROR AMPLIFIER
T
A
= T
J
= 25 °C 0.698 0.700 0.704V
FB
Feedback regulation voltage total variation 0 °C≤T
A
= T
J
≤85 °C 0.690 0.700 0.707
V-40 °C≤T
A
= T
J
≤85 °C 0.690 0.700 0.715V
SS(offset)
Soft-start offset from VSS
(1)
Offset from V
SS
to error amplifier 1GBWP Gain bandwidth
(1)
5 10 MHzA
VOL
Open loop gain 50 dBI
SRC
Output source current 2.5 4.5
mAI
SINK
Output sink current 2.5 6I
BIAS
Input bias current V
FB
= 0.7 V – 250 0 nA
SHORT CIRCUIT CURRENT PROTECTION
I
ILIM
Current sink into ILIM pin 115 135 150 µAV
ILIM(ofst)
Current limit offset voltage V
ILIM
= 11.5 V, (V
SW
- V
ILIM
) V
VDD
= 12 V – 50 – 30 – 10 mVt
HSC
Minimum HDRV pulse width During short circuit 135 225 nsPropagation delay to output
(1)
50 nst
BLANK
Blanking time
(1)
50 ns
(1) Ensured by design. Not production tested.
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TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)T
A
= – 40 °C to 85 °C, V
IN
= 12 V
dc
, R
T
= 90.9 k Ω, I
KFF
= 300 µA, f
SW
= 500 kHz, all parameters at zero power dissipation(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
OFF
Off time during a fault (SS cycle times) 7 cyclesV
SW
Switching level to end precondition
(1)
(V
VDD
- V
SW
) 2 Vt
PC
Precondition time
(2)
100 nsV
ILIM(pre)
Current limit precondition voltage threshold
(2)
6.8 V
OUTPUT DRIVERS
t
HFALL
High-side driver fall time
(2)
36C
HDRV
= 2200 pF, (HDRV - SW) nst
HRISE
High-side driver rise time
(2)
48t
HFALL
High-side driver fall time
(2)
72C
HDRV
= 2200 pF, (HDRV - SW)
nsV
VDD
= 4.5 Vt
HRISE
High-side driver rise time
(2)
96t
LFALL
Low-side driver fall time
(2)
24C
LDRV
= 2200 pF nst
LRISE
Low-side driver rise time
(2)
48t
LFALL
Low-side driver fall time
(2)
48C
LDRV
= 2200 pF, V
DD
= 4.5 V nst
LRISE
Low-side driver rise time
(2)
96I
HDRV
= -0.01 A, (V
BOOST
- V
HDRV
) 0.7 1.0V
OH
High-level output voltage, HDRV VI
HDRV
= -0.1 A, (V
BOOST
- V
HDRV
) 0.95 1.35(V
HDRV
- V
SW
), I
HDRV
= 0.01A 0.06 0.10V
OL
Low-level output voltage, HDRV V(V
HDRV
- V
SW
), I
HDRV
= 0.1 A 0.65 1.00(V
DBP
- V
LDRV
), I
LDRV
= -0.01A 0.65 1.00V
OH
High-level output voltage, LDRV V(V
DBP
- V
LDRV
), I
LDRV
= -0.1 A 0.875 1.300I
LDRV
= 0.01 A 0.03 0.05V
OL
Low-level output voltage, LDRV VI
LDRV
= 0.1 A 0.3 0.5
BOOST REGULATOR
V
BOOST
Output voltage V
VDD
= 12 V 15.2 17.0 V
UVLO
V
UVLO
Programmable UVLO threshold voltage R
KFF
= 90.9 k Ω, turn-on, V
VDD
rising 6.2 7.2 8.2Programmable UVLO hysteresis R
KFF
= 90.9 k Ω1.10 1.55 2.00 VFixed UVLO threshold voltage Turn-on, V
VDD
rising 4.15 4.30 4.45Fixed UVLO hysteresis 275 365 mV
POWER GOOD
V
PGD
Powergood voltage I
PGD
= 1 mA 370 550V
FBH
High-level output voltage, FB 770 mVV
FBL
Low-level output voltage, FB 630
SENSE AMPLIFIER
V
SA+
= V
SA-
= 1.25 V, Offset referenced toV
IO
Input offset voltage -9 9 mVSA+ and SA-A
DIFF
Differential gain V
SA+
- V
SA-
= 4.5 V 0.995 1.000 1.005V
ICM
Input common mode range
(3)
0 6 VR
G
Internal resistance for setting gain 14 20 26 k Ω
I
OH
Output source current 2 10 15
mAI
OL
Output sink current 15 25 35GBWP Gain bandwidth
(4)
2 MHz
THERMAL SHUTDOWN
(2) Ensured by design. Not production tested.(3) 3 V at internal amplifier terminals, 6 V at SA+ and SA- pins.(4) Ensured by design. Not production tested.
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TYPICAL CHARACTERISTICS
TJ − Junction Temperature − °C
VLVPP − L VBP Voltage − V
−50 −25 50 100 1250
4.15
4.10
4.30
4.20
4.25
4.05
4.00 25 75
VDD = 28 V
VDD = 12 V
−50 −25 50 100 1250
8.00
7.90
8.15
8.05
8.10
7.85
7.80 25 75
7.95
VDBP − DBP Voltage − V
VDD = 28 V
VDD = 12 V
TJ − Junction Temperature − °C
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)T
A
= – 40 °C to 85 °C, V
IN
= 12 V
dc
, R
T
= 90.9 k Ω, I
KFF
= 300 µA, f
SW
= 500 kHz, all parameters at zero power dissipation(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Shutdown temperature threshold
(4)
165
°CHysteresis
(4)
15
LVBP VOLTAGE DBP VOLTAGEvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 1. Figure 2.
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−50 −25 50 100 1250
4.46
4.43
4.50
4.48
4.49
4.41
4.40 25 75
4.44
4.42
4.47
4.45
VDBP − DBP Voltage − V
VDD = 4.5 V
ILOAD = 25 mA
TJ − Junction Temperature − °C
VDROP − Bootstrap Diode Voltage Drop − V
TJ − Junction Temperature − °C
−50 −25 50 100 1250
1.6
1.3
2.0
1.7
1.9
1.1
1.0 25 75
1.4
1.8
1.5
1.2
−50 −25 50 100 1250
115
150
140
100 25 75
135
125
110
105
120
145
130
IILIM − Current Limit Sink Current − µA
TJ − Junction Temperature − °C
VDD
28 V
12 V
4.5 V
VILIM(offst) – Current Limit Offset V oltage Drop – mV
TJ – Junction Temperature – °C
−50 −25 50 100 1250
−40
0
−10
−60 25 75
−20
−30
−50
Average
+3 S
−3 S
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
DBP VOLTAGE BOOTSTRAP DIODE VOLTAGEvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 3. Figure 4.
CURRENT LIMIT OFFSET VOLTAGE CURRENT LIMIT SINK CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 5. Figure 6.
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−50 −25 50 100 1250
699
704
697 25 75
702
698
700
703
701
VFB − Feedback V oltage − V
TJ − Junction Temperature − °C
VDD
28 V
4.5 V
12 V
fSW − Switching Frequency − kHz
VVDD − Input Voltage − V
4 8 16 24 2812 20
500
490
497
491
493
498
496
494
499
495
492
RRT = 90.1kΩ
ADIFF − Sense Amplifier Gain − V/V
TJ − Junction Temperature − °C
−50 −25 50 100 1250 25 75
0.9965
0.9980
1.0005
0.9995
0.9970
0.9985
1.000
0.9990
0.9975
VDD = 4.5 V
VDD = 2.5 V
VDD = 1.25 V
VDD = 0.5 V
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
FEEDBACK REGULATION VOLTAGE SENSE AMPLIFIER OUTPUT CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 7. Figure 8.
CURRENT SENSE AMPLIFIER GAIN SWITCHING FREQUENCYvs vsJUNCTION TEMPERATURE INPUT VOLTAGE
Figure 9. Figure 10.
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−50 −25 50 100 1250 25 75
4.35
3.90
4.20
3.95
4.30
4.15
4.05
4.00
4.25
4.10
TJ − Junction Temperature − °C
VUVLO − Undervoltage Lockout Threshold − V
VUVLO(on)
VUVLO(off)
TJ − Junction Temperature − °C
DMAX − Maximum Duty Cycle − %
−50 −25 50 100 1250 25 75
93
83
90
84
86
92
89
87
85
91
88
fSW = 100 kHZ
fSW = 500 kHZ
fSW = 1 MHZ
−50 −25 50 100 1250 25 75
1.10
0.90
1.04
0.92
0.96
1.08
1.02
0.98
0.94
1.06
1.00
TJ − Junction Temperature − °C
VUVLO − Relative Programmable UVLO Threshold − %
VUVLO(on)
VUVLO(off)
TJ − Junction Temperature − °C
ISS − Soft−Start Charging Current − µA
−50 −25 50 100 1250 25 75
14.0
10.0
10.5
11.0
13.5
12.5
11.5
13.0
12.0
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
MAXIMUM DUTY CYCLE UNDERVOLTAGE LOCKOUTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 11. Figure 12.
PROGRAMMABLE UVLO THRESHOLD SOFTSTART CHARGING CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 13. Figure 14.
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100
1.5
0.5 200 300 400 500 600 700 800 900 1000
1.0
3.0
2.0
2.5
3.5
5.0
4.0
4.5
VIN = 28 V
VIN = 24 V
VIN = 18 V
VIN = 15 V
VIN = 12 V
VIN = 10 V
VIN = 8 V
VIN = 5 V
fOSC − Oscillator Frequency − kHz
VOUT − Output Voltage − V
TJ − Junction Temperature − °C
IBIAS − Error Amplifier Input Bias Current − nA
−50 −25 50 100 1250 25 75
0
−90
−80
−70
−10
−30
−60
−20
−40
−50
VDD − Input Voltage − V
fOSC − Frequency − kHz
2 6 18 26 3010
500
495
505
520
510
515
490
485
480 14 22
fSW − Switching Frequency − kHz
0
100
0200 400 600 800 1000
200
300
400
500
600
RT − T iming Resistance − k Ω
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
ERROR AMPLIFIER INPUT BIAS CURRENT MINIMUM OUTPUT VOLTAGEvs vsJUNCTION TEMPERATURE FREQUENCY
Figure 15. Figure 16.
SWITCHING FREQUENCY TYPICAL SWITCHING FREQUENCYvs vsTIMING RESISTANCE INPUT VOLTAGE
Figure 17. Figure 18.
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60 90 150 180 210 270120 240
4
2
8
6
10
14
12
18
16
20
RKFF − Feedforward Impedance − kΩ
VUVLO − Programmable UVLO Threshold − V
UVLOVON
fSW = 500 kHz
UVLOVOFF
RKFF − Feedforward Impedance − kΩ
100 150 250 300 350 450200 400
4
2
8
6
10
14
12
18
16
20
VUVLO − Programmable UVLO Threshold − V
UVLOVON
fSW = 300 kHz
UVLOVOFF
40 60 100 120 140 18080 160
4
2
8
6
10
14
12
18
16
20
RKFF − Feedforward Impedance − kΩ
VUVLO − Programmable UVLO Threshold − V
UVLOVON
fSW = 750 kHz
UVLOVOFF
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
UVLO THRESHOLD VOLTAGE UVLO THRESHOLD VOLTAGEvs vsFEEDFORWARD IMPEDANCE FEEDFORWARD IMPEDANCE
Figure 19. Figure 20.
UVLO THRESHOLD VOLTAGE TYPICAL MAXIMUM DUTY CYCLEvs vsFEEDFORWARD IMPEDANCE INPUT VOLTAGE
Figure 21. Figure 22.
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255 10 2015 30
4.10
4.00
4.05
4.15
4.20
4.35
4.25
4.30
4.40
4.45
4.50
VDD − Input Voltage − V
VDBP − Low Voltage Bypass Voltage − V
VDD − Input Voltage − V
VDBP − Driver Bypass Voltage − V
0
5
45 10 15 20 25
7
6
9
8
10
TERMINAL INFORMATION
SAO
GND
SS
FB
COMP
PGND
LDRV
DBP
RHL PACKAGE
(BOTTOM VIEW)
SYNC
PGD
LVBP
RT
KFF
ILIM
VDD
HDRV
SA+
SA−
BOOST
SW
20 1
11 10
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)
INPUT VOLTAGE INPUT VOLTAGEvs vsDBP VOLTAGE LOW VOLTAGE BYPASS VOLTAGE
Figure 23. Figure 24.
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TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
The BOOST voltage is 8-V greater than the input voltage. The peak voltage on BOOST is equal to the SW nodevoltage plus the voltage present at DBP less the bootstrap diode drop. This drop can be 1.4 V for the internalBOOST 11 I
bootstrap diode or 300 mV for an external schottkey diode. The voltage differential between this pin and SW is theavailable drive voltage for the high-side FET.Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to theCOMP 6 O FB pin to compensate the overall loop. This pin is internally clamped to a 3.4-V maximum output drive capabilityfor quicker recovery from a saturated feedback loop situation.8-V regulator output used for the gate drive of the N-channel synchronous rectifier and as the supply for chargingDBP 9 O
the bootstrap capacitor. This pin should be bypassed to ground with a 1.0-µF ceramic capacitor.Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal referenceFB 5 I
voltage, 0.7 V.GND 3 - Ground reference for the device.Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SWHDRV 12 O
(MOSFET off).Short circuit protection programming pin. This pin is used to set the overcurrent threshold. An internal current sinkfrom this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD. The voltageon this pin is compared to the voltage drop (V
VDD
-V
SW
) across the high side N-channel MOSFET duringILIM 14 I conduction. Just prior to the beginning of a switching cycle this pin is pulled to approximately V
VDD
/2 and releasedwhen SW is within 2 V of V
VDD
or after a timeout (the precondition time) - whichever occurs first. Placing acapacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch on time,effectively programming the ILIM blanking time. See Applications Information section.A resistor is connected from this pin to VDD programs the amount of input voltage feed-forward. The current fedKFF 15 I into this pin is used to control the slope of the PWM ramp and program undervoltage lockout. Nominal voltage atthis pin is maintained at 400 mV.Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to PGND (MOSFETLDRV 8 O
off). For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50nC.4.2-V reference used for internal device logic and analog functions. This pin should be bypassed to GND with aLVBP 17 O
0.1-µF ceramic capacitor. External loads less than 1 mA and electrically quiet may be applied.This is an open drain output that pulls to ground when soft start is active, or when the FB pin is outside a ± 10%PGD 18 O
band around the 700 mV reference voltage.Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of thePGND 7
lower MOSFET(s).RT 16 I A resistor is connected from this pin to GND to set the switching frequency.SA+ 20 I Noninverting input of the remote voltage sense amplifier.SA- 1 I Inverting input of the remote voltage sense amplifier.SAO 2 O Output of the remote voltage sense amplifier.Soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. Thecapacitor is charged with an internal current source of 12 µA. The resulting voltage ramp on the SS pin is used asa second non-inverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 Vless that that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on theSS 4 I
SS pin reaches the internal offset voltage of 1 V plus the internal reference voltage of 700 mV. If SS is below theinternal offset voltage of 1 V (300 mV minimum ensured), the resulting output voltage is zero. Also provides timingfor fault recovery attempts. Pulling this pin below 250 mV causes the controller to enter a shutdown state withHDRV and LDRV held in a low state.This pin is connected to the switched node of the converter and used for overcurrent sensing as well as gate driveSW 10 I timing. This pin is also the return path from the high-side FET for the floating high-side FET driver. A 1.5- Ωresistorin series with this pin is required for protection against substrate current issues.SYNC 19 I Logic input for pulse train to synchronize oscillator.VDD 13 I Supply voltage for the device.
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9
12
8
13
17
16
15
VDD
LVBP
RT
KFF
DBP
HDRV
LDRV
18
3
5
4
PGD
GND
FB
SS
6COMP
Reference
Regulator
Predictive
Gate Drive
Control
Logic
UVLO
Controller
Oscillator
14 ILIM
Pulse
Control
SW
CLK
10 SW
Overcurrent
Comparator
and Control
CLK
ILIM OC
7 PGND
11 BOOST
VDD
UVLO
Ramp
Generator
Power
Good
Logic
770 mV
FB
630 mV
SS Active
PWM
OC
CLK
UVLO
FAULT IZERO
DBP
+
+
700 mV
RAMP
Soft Start
and
Fault Control
OC
CLK
SW
PGND
LVBP
2SAO
20 SA+
1 SA−
R
R
R
+
R
UDG−04076
19SYNC
TPS40075
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
SIMPLIFIED BLOCK DIAGRAM
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APPLICATION INFORMATION
MINIMUM PULSE WIDTH
SLEW RATE LIMIT ON VDD
13
7
14
12
10
8
ILIM
HDRV
SW
LDRV
VDD
PGND
TPS40075
C
R
VIN
UDG−05058
+
_
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
The TPS40075 allows the user to construct synchronous voltage mode buck converters with inputs ranging from4.5 V to 28 V and outputs as low as 700 mV. Predictive gate drive circuitry optimizes switching delays forincreased efficiency and improved converter output power capability. Voltage feed-forward is employed to easeloop compensation for wide input range designs and provide better line transient response.
An on-board unity gain differential amplifier is provided for remote sensing in applications that require the tightestload regulation. The TPS40075 incorporates circuitry to allow startup into a pre-existing output voltage withoutsinking current from the source of the pre-existing output voltage. This avoids damaging sensitive loads atstartup. The controller can be synchronized to an external clock source or can free run at a user programmablefrequency. An integrated power good indicator is available for logic (open drain) output of the condition of theoutput of the converter.
The TPS40075 has limitations on the minimum pulse width that can be used to design a converter. Reliableoperation is guaranteed for nominal pulse widths of 150 ns and above. This places some restrictions on theconversion ratio that can be achieved at a given switching frequency. See Figure 16 .
The regulator that supplies power for the drivers on the TPS40075 requires a limited rising slew rate on VDD forproper operation if the input voltage is above 10 V. If the slew rate is too great, this regulator can over shoot anddamage to the part can occur. To ensure that the part operates properly, limit the slew rate to no more than0.12 V/ μs as the voltage at VDD crosses 8 V. If necessary, an R-C filter can be used on the VDD pin of thedevice. Connect the resistor from the VDD pin to the input supply of the converter. Connect the capacitor fromthe VDD pin to PGND. There should not be excessive (more than a 200-mV) voltage drop across the resistor innormal operation. This places some constraints on the R-C values that can be used. Figure 25 is a schematicfragment that shows the connection of the R-C slew rate limit circuit. Equation 1 and Equation 2 give values for Rand C that limits the slew rate in the worst case condition.
Figure 25. Limiting the Slew Rate
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Rt0.2 V
fSW Qg(TOT) )IIDD
(1)
CuVVIN *8 V
R SR
(2)
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
RT+ǒ1
fSW(kHz) 17.82 10*6*23ǓkW
(3)
PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO FUNCTION
RKFF +0.131 RT VUVLO(on) *1.61 10*3 VUVLO(on)2)1.886 VUVLO *1.363 *0.02 RT*4.87 10*5 R2
T
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
where
•V
VIN
is the final value of the input voltage ramp•f
SW
is the switching frequency•Q
g(TOT)
is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet)•I
IDD
is the TPS40075 input current (3.5 mA maximum)•SR is the maximum allowed slew rate [12 ×10
4
] (V/s)
The TPS40075 has independent clock oscillator and PWM ramp generator circuits. The clock oscillator serves asthe master clock to the ramp generator circuit. Connecting a single resistor from RT to ground sets the switchingfrequency of the clock oscillator. The clock frequency is related to R
T
by:
The ramp generator circuit provides the actual ramp used by the PWM comparator and provides voltagefeed-forward by varying the PWM ramp slope as the line voltage changes. As the input voltage to the converterincreases, the slope of the PWM ramp increase by a proportionate amount. The programmable UVLO circuitworks by monitoring the level reached by the PWM ramp during a clock cycle. The PWM ramp must reachapproximately 1 V in amplitude during a clock cycle, or the converter is not be allowed to start. Thisprogrammable UVLO point is set via a single resistor (R
KFF
) connected from KFF to VDD. R
KFF
, V
START
and R
RTare related by (approximately)
(4)
where
•V
UVLO(on)
is in volts•R
KFF
and R
T
are in k Ω
This yields typical numbers for the programmed startup voltage. The minimum and maximum values may vary up± 15% from this number. Figure 19 through Figure 21 show the typical relationship of V
UVLO(on)
, V
UVLO(off)
and R
KFFat three common frequencies.
The programmable UVLO circuit incorporates 20% hysteresis from the start voltage to the shutdown voltage. Forexample, if the startup voltage is programmed to be 10 V, the controller starts when V
DD
reaches 10 V and shutsdown when V
DD
falls below 8 V. The maximum duty cycle begins to decrease as the input voltage rises to twicethe startup voltage. Below this point, the maximum duty cycle is as specified in the electrical table. Note that withthis scheme, the theoretical maximum output voltage that the converter can produce is approximately two timesthe programmed startup voltage. For design, set the programmed startup voltage equal to or greater than thedesired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz and below). For example, a5-V output converter should not have a programmed startup voltage below 5.9 V. Figure 22 shows the theoreticalmaximum duty cycle (typical) for various programmed startup voltages
If the programmable UVLO voltage is set below 6.5V nominal, a possibility exists that the part may enter factorytest mode when powered down. This can cause an undesired output rise as power is removed from theconverter. To prevent this from happening, connect a 330 k Ωresistor from SS to GND. An example of this can beseen in Figure 37
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VDG−03172
RAMP
COMP
SW
VIN
VIN
SW
COMP
RAMP
VPEAK
VVALLEY
T2
tON1 > tON2 and d1 > d2
tON2
tON1
d+tON
T
T1
PROGRAMMING SOFT START
tSTART w2p L COUT
Ǹ(seconds)
(5)
CSS +tSS ISS
VFB
(6)
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
Figure 26 shows the effect of changing input voltage on the duty cycle, and how that change takes place. Thepulse width modulator (PWM) ramp input is generated using a current that is proportional to the current into theKFF pin. The TPS40075 holds this pin at a constant 400 mV, so connecting a resistor from KFF to the inputpower supply causes a current to flow into the KFF pin that is proportional to the input voltage. The slope of theramp signal to the PWM is therefore proportional to the input voltage. This allows the duty cycle to change withvariations in Vin without requiring much response from the error amplifier, resulting in very good line transientresponse. Another benefit is essentially constant PWM gain over the entire input voltage operating range. Thismakes the output control loop easier to design for a wide input range converter.
Figure 26. Voltage Feed-Forward and PWM Duty Cycle Waveforms
TPS40075 uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start isprogrammed by connecting an external capacitor (C
SS
) from the SS pin to GND. This capacitor is charged by afixed current, generating a ramp signal. The voltage on SS is level shifted down approximately 1 V and fed into aseparate non-inverting input to the error amplifier. The loop is closed on the lower of the level shifted SS voltageor the 700-mV internal reference voltage. Once the level shifted SS voltage rises above the internal referencevoltage, output voltage regulation is based on the internal reference. To ensure a controlled ramp-up of theoutput voltage the soft-start time should be greater than the L-C
OUT
time constant or:
where
•L is the value of the filter inductor•C
OUT
is the value of the output capacitance•t
START
is the output ramp up-time
For a desired soft-start time, the soft-start capacitance, C
SS
, can be found from:
Please note: There is a direct correlation between t
START
and the input current required during start-up. The lowert
START
is, the higher the input current required during start-up since the output capacitance must be chargedfaster.
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PROGRAMMING SHORT CIRCUIT PROTECTION
ILIM Threshold
T2
T1 ILIM Threshold
T3
T1
ILIM
ILIM
SW
SW
VIN − 2V
VIN − 2V
UDG−03173
Overcurrent
(A)
(B)
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
The TPS40075 uses a two-tier approach to short circuit protection. The first tier is a pulse-by-pulse protectionscheme. Short circuit protection is implemented by sensing the voltage drop across the high-side MOSFET whileit is turned on. The MOSFET drain to source voltage is compared to the voltage dropped across a resistor (R
ILIM
)connected from VDD to the ILIM pin. The voltage drop across this resistor is produced by a constant current sink.If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor the switching pulse isimmediately terminated. The MOSFET remains off until the next switching cycle is initiated.
In addition, just prior to the high-side MOSFET turning on, the ILIM pin is pulled down to approximately half ofVDD. The ILIM pin is allowed to return to its nominal value after one of two events occur:1. The SW node rises to within approximately 2 V of VDD2. An internal timeout occurs, approximately 125-ns after ILIM is initially pulled down
If the SW node rises to within approximately 2-V of VDD, the device allows ILIM to go back to its nominal value.This is illustrated in Figure 27 A. T1 is the delay time from the internal PWM signal being asserted and the rise ofSW. This includes the driver delay of 50 ns typical, and the turn on time of the high-side MOSFET. The MOSFETused should have a turn on time less than 75 ns. T2 is the reaction time of the sensing circuit that allows ILIM tostart to return to its nominal value, typically 20ns.
Figure 27. Switching and Current Limit Waveforms and Timing Relationship
The second event that can cause ILIM to return to its nominal value is for an internal timeout to expire. This isillustrated in Figure 27 B as T3. Here SW never rises to VDD-2, for whatever reason, and the internal timer timesout. This allows the ILIM pin to start its transition back to its nominal value.
Prior to ILIM starting back to its nominal value, short circuit sensing is not enabled. In normal operation, thisinsures that the SW node is at a higher voltage than ILIM when short circuit sensing starts, avoiding false tripswhile allowing for a quicker blanking delay than would ordinarily be possible. Placing a capacitor across R
ILIMsets an exponential approach to the normal voltage at the ILIM pin. This exponential “ decay ” of the short circuitthreshold can be used to compensate for ringing on the SW node after its rising edge and to help compensatefor slower turn-on MOSFETs. Choosing the proper capacitance requires care. If the capacitance is too large, thevoltage at ILIM does not approach the desired short circuit level quickly enough, resulting in an apparent shift inshort circuit threshold as pulse width changes.
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VDG−03174
tBLANKING
7 Current Limit Trips
(HDRV Cycle Terminated by Current Limit Trip) 7
Soft-Start
Cycles
HDRV
Clock
VILIM
VVIN−VSW
SS
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
The comparator that looks at ILIM and SW to determine if a short circuit condition exists has a clamp on its SWinput. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be as much as2 V at – 40 °C) below VDD. While ILIM is more than 1.4 V below VDD short circuit sensing is effectively disabled,giving a programmable absolute blanking time. As a general rule, it is best to make the time constant of the R-Cat the ILIM pin 20% or less of the nominal pulse width of the converter (See Equation 11 )
The second tier protection incorporates a fault counter. The fault counter is incremented on each cycle with anovercurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reachesseven (7) a fault condition is declared by the controller. When this happens, the output drivers turn bothMOSFETs off. Seven soft-start cycles are initiated (without activity on the HDRV and LDRV outputs) and thePWM is disabled during this period. The counter is decremented on each soft-start cycle. When the counter isdecremented to zero the PWM is re-enabled and the controller attempts to restart. If the fault has been removedthe output starts up normally. If the output fault is still present the counter counts seven overcurrent pulses andre-enters the second tier fault mode. Refer to Figure 28 for typical fault protection waveforms.
Figure 28. Typical Fault Protection Waveforms
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ISCP uCOUT VOUT
tSTART )ILOAD (A)
(7)
RILIM +ISCP RDS(onMAX) )VILIM (ofst)
IILIM
W
(8)
ISCP(max) +IILIM(max) RILIM )50 mV
RDS(onMIN) A
(9)
ISCP(min) +IILIM(min) RILIM )10 mV
RDS(onMAX) A
(10)
CILIM(max) +VOUT 0.2
VIN RILIM fSW (Farads)
(11)
BOOST AND DBP BYPASS CAPACITANCE
INTERNAL REGULATORS
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
The minimum short circuit limit threshold (I
SCP
) depends on t
START
, C
OUT
, V
OUT
, and the load current at turn-on(I
LOAD
).
The short circuit limit programming resistor (R
ILIM
) is calculated from:
where
•I
ILIM
is the current into the ILIM pin (135 μA typical)•V
ILIM(ofst)
is the offset voltage of the ILIM comparator (-30 mV typical)•I
SCP
is the short-circuit protection current•R
DS(on)MAX
is the drain-to-source resistance of the high-side MOSFET
To find the range of the short circuit threshold values use the following equations.
The TPS40075 provides short-circuit protection only. As such, it is recommended that the minimum short circuitprotection level be placed at least 20% above the maximum output current required from the converter. Themaximum output of the converter should be the steady state maximum output plus any transient specificationthat may exist.
The ILIM capacitor maximum value can be found from:
Note that this is a recommended maximum value. If a smaller value can be used, it should be to improveprotection. For most applications, consider using half the maximum value shown in Equation 11 .
The BOOST capacitance provides a local, low-impedance flying source for the high-side driver. The BOOSTcapacitor should be a good quality, high-frequency ceramic capacitor. A minimum value of 100-nF is suggested.
The DBP capacitor has to provide energy storage for switching both the synchronous MOSFET and the high-sideMOSFET (via the BOOST capacitor). The suggested value for this capacitor is 1- μF ceramic, minimum.
The internal regulators are linear regulators that provide controlled voltages for the drivers and the internalcircuitry to operate from. The low-side driver operates directly from the 8-V regulator supply while the high-sidedriver bootstrap capacitor is charged from this supply. The actual voltage delivered to the high-side driver is thevoltage on the DBP pin less any drop from the bootstrap diode. If the internal bootstrap diode is used, the dropacross that diode is nominally 1.4 V at room temperature. This regulator has two modes of operation. At voltagesbelow 8.5 V on VDD, the regulator is in a low dropout mode of operation and tries to provide as little impedanceas possible from VDD to DBP. When VDD is above 10 V, the regulator regulates DBP to 8 V. Between these twovoltages, the regulator is in whatever state it was in when VDD entered this region. The LVBP pin is connectedto a 4.2-V regulator that supplies power for the internal control circuitry. Small amounts of current can be drawnfrom these pins for other external circuit functions, as long as power dissipation in the controller chip remains atacceptable levels and junction temperature does not exceed 125 °C. Any external load connected to LVBP shouldbe electrically quiet to avoid degrading performance of the TPS40075. Typical output voltages for these tworegulators are shown in Figure 23 and Figure 24 .
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DIFFERENTIAL SENSE AMPLIFIER
SYNCHRONIZATION
POWERGOOD OPERATION
PRE-BIASED OUTPUTS
SHUTDOWN AND SEQUENCING
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
The TPS40075 has an on board differential amplifier intended for use as a remote sensing amplifier for theoutput voltage. Use of this amplifier for remote sensing eliminates load regulation issues due to voltage dropsthat occur between the converter and the actual point of load. The amplifier is powered from the DBP pin andcan be used to monitor output voltages up to 6 V with a DBP voltage of 8 V. For lower DBP voltages, the senseamplifier can be used to monitor output voltages up to 2-V below the DBP voltage. The internal resistors used toconfigure the amplifier for unity gain match each other closely, but their absolute values can vary as much as30%, so adding external resistance to alter the gain is not accurate in a production environment.
The SYNC pin accepts logic level signals and is used to synchronize the TPS40075 to an external clock source.Synchronization occurs on the rising edge of the signal at the SYNC pin. There is a fixed delay of approximately300 ns from the rising edge of the waveform at SYNC to the HDRV output turning on the high-side FET. The pinmay be left floating in this function is not used, or it may be connected to GND. The frequency of the externalclock must be greater than the free running frequency of the device as set by the resistor on the RT pin (R
RT
).This pin requires a totem pole drive, or open collector/drain if pull up resistor to either LVBP or a separate supplybetween 2.5 V and 5 V is used. Synchronization does not affect the modulator gain due to the voltage feedforward circuitry. The programmable UVLO thresholds are affected by synchronization. The thresholds areshifted by the ratio of the sync frequency to the free running frequency of the converter. For example,synchronizing to a frequency 20% higher than the free running frequency results in the programmable UVLOthresholds shifting up 20% from their calculated free run values. The synchronization frequency should be keptless than 1.5 times the free run frequency for best performance, although higher multiples can be used.
The PGD pin is an open drain output that actively pulls to GND if any of the following conditions are met(assuming that the input voltage is above 4.5 V)•Soft-start is active (V
VSS
< 3.5 V)•V
FB
< 0.63 V•V
FB
> 0.77 V•Programmable UVLO condition not satisfied (V
IN
below programmed level)•Overcurrent condition exists•Die temperature is greater than 165 °C
Some applications require that the converter not sink current during startup if a pre-existing voltage exists at theoutput. Since synchronous buck converters inherently sink current some method of overcoming this characteristicmust be employed. Applications that require this operation are typically power rails for a multi supply processoror ASIC. The method used in this controller, is to not allow the low side or rectifier FET to turn on until there theoutput voltage commanded by the start up ramp is higher than the pre-existing output voltage. This is detectedby monitoring the internal pulse width modulator (PWM) for its first output pulse. Since this controller uses aclosed loop startup, the first output pulse from the PWM does not occur until the output voltage is commanded tobe higher than the pre-existing voltage. This effectively limits the controller to sourcing current only during thestartup sequence.
If the pre-existing voltage is higher that the intended regulation point for the output of the converter, the converterstarts and sinks current when the soft-start time has completed
The TPS40075 can be shut down by pulling the SS pin to a level below 250 mV. Pulling the pin low resets theinternal pre-bias circuitry to ensure that the converter does not damage sensitive loads.
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TPS40075 POWER DISSIPATION
PD+Qg VDR fSW (Wattsńdriver)
(12)
PT+ǒ2 PD
VDR )IQǓ VIN (Watts)
(13)
PT+ǒ2 Qg fSW )IQǓ VIN (Watts)
(14)
PT+TJ*TA
qJA (Watts)
(15)
fSW +ǒƪǒTJ*TAǓ
ǒqJA VINǓƫ*IQǓ
ǒ2 QgǓ(Hz)
(16)
BOOST DIODE
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
Automatic startup sequencing can be accomplished by connecting the PGD pin of a master supply based on theTPS40075 to the SS pin of a slave supply. The master comes up first and release the salve SS pin to allow theslave to come up. Controlled shutdown of sequenced supplies can be accomplished by either pulling the SS pinof the master below the shutdown threshold and letting the PGD pin pull the slave SS pin down, or by pullingdown the SS pins of all supplies simultaneously.
The power dissipation in the TPS40075 is largely dependent on the MOSFET driver currents and the inputvoltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power(neglecting external gate resistance) can be calculated from:
where
•V
DR
is the driver output voltage
The total power dissipation in the TPS40075, assuming the same MOSFET is selected for both the high-side andsynchronous rectifier is described in Equation 13 .
or
where
•I
Q
is the quiescent operating current (neglecting drivers)
The maximum power capability of the TPS40075 PowerPAD package is dependent on the layout as well as airflow. The thermal impedance from junction to air ambient assuming 2-oz. copper trace and thermal pad withsolder and no air flow is θ
JA
= 60 °C/W
The maximum allowable package power dissipation is related to ambient temperature by Equation 15 .
Substituting Equation 15 into Equation 14 and solving for f
SW
yields the maximum operating frequency for theTPS4007x. The result is described in Equation 16 .
The TPS40075 has internal diodes to charge the boost capacitor connected from SW to BOOST. The dropacross this diode is rather large at 1.4-V nominal at room temperature resulting in the drive voltage to thehigh-side MOSFET being reduced by this amount from the DBP voltage. If this drop is too large for a particularapplication, an external diode may be connected from DBP (anode) to BOOST (cathode). This providessignificantly improved gate drive for the high-side MOSFET, especially at lower input voltages.
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GROUNDING AND BOARD LAYOUT
SYNCHRONOUS RECTIFIER CONTROL
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
The TPS40075 provides separate signal ground (GND) and power ground (PGND) pins. Care should be given toproper separation of the circuit grounds. Each ground should consist of a plane to minimize its impedance ifpossible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decouplingcapacitor (DBP), and the input capacitor should be connected to PGND plane.
Sensitive nodes such as the FB resistor divider and RT should be connected to the GND plane. The GND planeshould only make a single point connection to the PGND plane. It is suggested that the GND pin be tied to thecopper area for the PowerPAD underneath the chip. Tie the PGND to the PowerPAD copper area as well andmake the connection to the power circuit ground from the PGND pin. Reference the output voltage divider to theGND pin.
Component placement should ensure that bypass capacitors (LVPB and DBP) are located as close as possibleto their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be locatednear high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow careful layoutpractices results in sub-optimal operation.
Table 2 describes the state of the rectifier MOSFET control under various operating conditions.
Table 2. Synchronous Rectifier MOSFET States
SYNCHRONOUS RECTIFIER OPERATION DURING
FAULTSOFT-START NORMAL (FAULT RECOVERY IS SAME OVERVOLTAGEAS SOFT-START)
Off until first high-side pulse is Turns off at the start of a new
Turns OFF only at start of nextdetected, then on when high-side cycle. Turns on when the OFF
cycle ON if duty cycle is > 0MOSFET is off high-side MOSFET is turned off
For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50nC.
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DESIGN EXAMPLE
1. SPECIFICATIONS
2. SCHEMATIC
RP1
RZ1
RPGD
CO
CZ2
RSET2
RKFF
1
2
3
4
19
18
17
16
SYNC
PGD
LVBP
RT
SA−
SAO
GND
SS
TPS40075
15
14
13
12
KFF
ILIM
VDD
HDRV
5
6
7
8
FB
COMP
PGND
LDRV
9 DBP
20
SA+
10
SW
11
BOOST
UDG−04125
SYNC −SENSE
QSR
MLCCELCO
QSW
+SENSE
ELCO
0V
RLIM
CLIM
L
CO
VO
CVDD
CVLVBP
CPZ1
CIN
VIN
RPZ2
CP2
RSET1
CSS CDBP
DBOOST CBOOST
RT
1.5 Ω
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENT
V
IN
Input voltage 10.8 12.0 13.2V
O
Output voltage I
OUT
= 10 A 1.5 5 VRegulation 1.47 1.53V
RIPPLE
Output ripple voltage I
O(max)
= 15 A 30V
OVER
Output overshoot I
STEP
= 8 A 50 mVV
UNDER
Output undershoot I
STEP
= 8 A 50I
LOAD
Output current 0 15
AI
SCP
Short circuit current trip point 16 30
ηEfficiency V
IN
= 12 V, I
LOAD
= 15 A 85%f
SW
Switching frequency 400 kHz
Figure 29. TPS40075 Reference Design Schematic
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3. COMPONENT SELECTION
L+VO
VIN(max) ǒVIN(max) *VOǓ
fSW DI
(17)
ILOAD_RMS +ILOAD2)DI2
12
Ǹ+15.03 A
(18)
IPK +ILOAD )DI2
2+16.65 A
(19)
COuL ISTEP2
2 VUNDER DMAX ǒVIN *VOǓ
(20)
COuL ISTEP2
2 VOVER VO
(21)
ESR tVRIPPLE
DI
(22)
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
3. 1 Power Train Components
Designers familiar with the buck converter can skip to section 3.2 Component Selection for TPS40075.
3.1.1 Output Inductor, L
O
The output inductor is one of the most important components to select. It stores the energy necessary to keepthe output regulated when the switch MOSFET is turned off. The value of the output inductor dictates the peakand RMS currents in the converter. These currents are important when selecting other components. Equation 17can be used to calculate a value for L.
ΔI is the allowable ripple in the inductor. Selecting ΔI also sets the output current when the converter goes intodiscontinuous mode (DCM) operation. Since this converter utilizes MOSFETs for the rectifier, DCM is not a majorconcern. Select ΔI to be between 20% and 30% of maximum I
LOAD
. For this design, ΔI of 3 A was selected. Thecalculated L is 1.1 μH. A standard inductor with value of 1.0 μH was chosen. This increases ΔI by about 10% to3.3 A.
With this ΔI value, calculate the RMS and peak current flowing in L
O
. Note this peak current is also seen by theswitching MOSFET and synchronous rectifier.
3.1.2 Output Capacitor, C
O
, ELCO and MLCC
Several parameters must be considered when selecting the output capacitor. The capacitance value should beselected based on the output overshoot, V
OVER
, and undershoot, V
UNDER
, during a transient load, I
STEP
, on theconverter. The equivalent series resistance (ESR) is chosen to allow the converter meet the output ripplespecification, V
RIPPLE
. The voltage rating must be greater than the maximum output voltage. Other parameters toconsider are: equivalent series inductance which is important in fast transient load situations. Also size andtechnology can be factors when choosing the output capacitor. In this design a large capacitance electrolytic typecapacitor, C
O
ELCO, is used to meet the overshoot and under shoot specifications. Its ESR is chosen to meetthe output ripple specification. While a smaller multiple layer ceramic capacitor, C
O
MLCC, is used to filter highfrequency noise.
The minimum required capacitance and maximum ESR can be calculated using the equations below.
Using Equation 20 through Equation 22 , the capacitance for C
O
should be greater than 495 μF and its ESRshould be less than 9.1m Ω. The 1000 μF/25 V capacitor from Rubycon's MBZ or Panasonic's series EEU-FL waschosen. Its ESR is 19 m Ω, so two in parallel are used. The slightly higher ESR is offset by the four timesincrease in capacitance. A 2.2 μF/16 V MLCC is also added in parallel to reduce high frequency noise.
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ICAP(RMS) +ƪǒILOAD(max) *IIN(avg)2Ǔ)DI2
12ƫ D)IIN(avg)2 (1*D)
Ǹ
(23)
ID+VO
VIN(min) ǒILOAD(max)2)DI2
12Ǔ
Ǹ
(24)
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
3.1.3. Input Capacitor, C
IN
, ELCO and MLCC
The input capacitor is selected to handle the ripple current of the buck stage. Also a relative large capacitance isused to keep the ripple voltage on the supply line low. This is especially important where the supply line is highimpedance. It is recommended that the supply line be kept low impedance. The input capacitor ripple current canbe calculated using Equation 23 .
where
•I
IN(avg)
is the average input current
This is calculated simply by multiplying the output DC current by the duty cycle. The ripple current in the inputcapacitor is 5.05 A. A 1206 MLCC using X7R material has a typical dissipation factor of 5%. For a 2.2 μFcapacitor at 400 kHz the ESR is approximately 7.2 m Ω. If two capacitors are used in parallel the powerdissipation in each capacitor is less than 46 mW.
A 470 μF/16 V electrolytic capacitor is added to maintain the voltage on the input rail.
3.1.4 Switching MOSFET, QSW
The following key parameters must be met by the selected MOSFET.•Drain source voltage, V
DS
, must be able to withstand the input voltage plus spikes that may be on theswitching node. For this design a V
DS
rating of 25 V to 30 V is recommended.•Drain current, I
D
, at 25 °C, must be greater than that calculated using Equation 24 . For this design, I
D
shouldbe greater than 5 A.
•Gate source voltage, V
GS
must be able to withstand the gate voltage from the control device . For theTPS40075 this is 9 V.
Once the above boundary parameters are defined the next step in selecting the switching MOSFET is to selectthe key performance parameters. Efficiency is the performance characteristic which drives the other selectioncriteria. Target efficiency for this design is 90%. Based on 1.5-V output and 15 A this equates to a power loss inthe converter of 2.5 W. Using this figure a target of 0.5 W dissipated in the switching MOSFET was chosen.
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PQSW +PQSW(CON) )PQSW(SW) )PQSW(GATE)
(25)
PQSW(CON) +RDS(on) ID2+RDS(on) VO
VIN ǒILOAD2)DI2
12Ǔ
(26)
PQSW(SW) +VIN fSW ȧ
ȱ
Ȳ
ǒILOAD )DI
2Ǔ ǒQgs1 )QgdǓ
Ig)QOSS(SW) )QOSS(SR)
2ȧ
ȳ
ȴ
(27)
PQSW(GATE) +Qg(TOT) Vg FSW
(28)
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
Equation 25 through Equation 28 can be used to calculate the power loss, P
QSW
, in the switching MOSFET
where
•P
QSW(CON)
= conduction losses•P
QSW(SW)
= switching losses•P
QSW(GATE)
= gate drive losses•Q
gd
= drain source charge or miller charge•Q
gs1
= gate source post threshold charge•I
g
= gate drive current•Q
OSS(SW)
= switching MOSFET output charge•Q
OSS(SR)
= synchronous MOSFET output charge•Qg
(TOT)
= total gate charge from zero volts to the gate voltage•Vg = gate voltage
If the total estimated loss is split evenly between conduction and switching losses, Equation 25 and Equation 26yields preliminary values for R
DS(on)
and (Q
gs1
+ Q
gd
). Note output losses due to Q
OSS
and gate losses have beenignored here. Once a MOSFET is selected these parameters can be added.
The switching MOSFET for this design should have an R
DS(on)
of less than 9 m Ω. The sum of Q
gd
and Q
gs
shouldbe approximately 4 nC.
It is not always possible to get a MOSFET which meets both these criteria so a comprise may have to be made.Also by selecting different MOSFETs close to this criteria and calculating power loss the final selection can bemade. It was found that the PH6325L MOSFET from Philips semiconductor gave reasonable results. This devicehas an R
DS(on)
of 6.3 m Ωand a (Qgs1+Qgd) of 5.9 nC. The estimated conduction losses are 0.178 W and theswitching losses are 0.270 W. This gives a total estimated power loss of 0.448 W versus 0.5 W for our initialboundary condition. Note this does not include gate losses of approximately 10 mW and output losses of lessthan 1 mW.
3.1.5 Rectifier MOSFET, QSR
Similar criteria can be used for the rectifier MOSFET. There is one significant difference. Due to the body diodeconducting, the rectifier MOSFET switches with near zero voltage across its drain and source so effectively withnear zero switching losses. However, there are some losses in the body diode. These are minimized by reducingthe delay time between the transition from the switching MOSFET turn off to rectifier MOSFET turn on and viceversa. The TPS40075 incorporates TI's proprietary predictive gate drive which helps reduce this delay tobetween 10 ns and 20 ns.
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PQSR +PQSR(CON) )PDIODE )PQSR(GATE)
(29)
PQSW(CON) +RDS(on) ID2+RDS(on) VO
VIN ǒILOAD2)DI2
12Ǔ
(30)
PDIODE +Vf ILOAD ǒt1)t2Ǔ fSW
(31)
KPWM ^VUVLO
1 V
(32)
RT+1
fSW 17.82 10*6*23
(33)
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
The calculations for the losses in the rectifier MOSFET are show in Equation 29 through Equation 32 .
where
•P
DIODE
= body diode losses•t
1
= body diode conduction prior to turn on of channel = 10 ns for predictive gate drive•t
2
= body diode conduction after turn off of channel = 10 ns for predictive gate drive•V
f
= body diode forward voltage
Estimating the body diode losses based on a forward voltage of 1.2 V gives 0.142 W. The gate losses areunknown at this time so assume 0.1 W gate losses. This leaves 0.258 W for conduction losses. Using this figurea target R
DS(on)
of 1.1 m Ωwas calculated. This is an extremely low value. It is not possible to meet this withoutparalleling multiple MOSFETs. Paralleling MOSFETs increases the gate capacitance and slows down switchingspeeds. This increases body diode and gate losses.
The PH2625L from Philips was chosen. Using the parameters from its data sheet the actual expected powerlosses were calculated. Conduction loss is 0.527 W, body diode loss is 0.142 W and the gate loss was 0.174 W.This totals 0.843 W associated with the rectifier MOSFET. This is somewhat greater than the initial allowance.Because of this the converter may not hit its efficiency figure at the maximum load.
Two other criteria should be verified before finalizing on the rectifier MOSFET. One is the requirement to ensurethat predictive gate drive functions correctly. The maximum turn off delay of the PH2625L is 67 ns. The minimumturn on delay of the PH6325L is 25 ns. These devices easily meet the 100 ns difference requirement.
Secondly the ratio between C
gs
and C
gd
should be greater than 1. The C
gs
of the PH2625L is 2133 pF and theCgd is 1622 pF, so the C
gs
:C
gd
ratio is 1.3:1. This helps reduce the risk of dv/dt induced turn on of the rectifierMOSFET. If this is likely to be a problem a small resistor may be added in series with the boost capacitor,C
BOOST
.
3.2 Component Selection for TPS40075
3.2.1 Timing Resistor, R
T
The timing resistor is calculated using the following equation.
This gives a resistor value of 89.2 k Ω. Using the E24 range of resistor values a 118-k Ωresistor was selected.The nominal frequency using this resistor is 398 kHz.
3.2.2 Feed Forward and UVLO Resistor, R
KFF
A resistor connected to the KFF pin of the device feeds into the ramp generator. This resistor provides currentinto the ramp generator proportional to the input voltage. The ramp is then adjusted to compensate for differentinput voltages. Is provides the voltage feed forward feature of the TPS40075.
The same resistor also sets the under voltage lock out point. The input start voltage should be used to calculatea value for R
KFF
. For this converter the minimum input voltage is 10.8 V however due to tolerances in the device,a start voltage of 15% less than the minimum input voltage is selected. The start voltage for R
KFF
calculation is9.18 V. Using Equation 34 R
KFF
can be selected.
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RKFF +ǒVUVLO(on) *0.5Ǔ
ǒ0.018 )ǒ5
RTǓǓ
(34)
tSTART w2p L CO
Ǹ
(35)
CSS w12 10*6
0.7 tSTART
(36)
ISCP wCO VOUT
tSTART )ILOAD DI
2
(37)
RILIM wISCP RDS(on)MAX )VILIM(min)
ISINK(max)
(38)
ISCP(min) +ISINK(min) RILIM(min) *VILIM(max)
RDS(on)MIN
(39)
ISCP(max) +ISINK(max) RILIM(max) *VILIM(min)
RDS(on)MAX
(40)
CILIM(max) +VO 0.2
VIN RILIM fSW
(41)
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
This equation gives a R
KFF
value of 136 k Ω. The closest lower standard value should be selected. For this designand using E24 resistor range 133 k Ωwas chosen. This yields a typical start voltage of 8.52 V.
3.2.3 Soft Start Capacitor
It is good practice to limit the rise time of the output voltage. This helps prevent output overshoot and possibledamage to the load. The selection of the soft start time is arbitrary, but it must meet one condition; it should begreater than the time constant of the output filter, L and C
O
. This time is given by Equation 35
The soft-start time must be greater than 0.281 ms. A time of 1 ms was chosen, this time also helps keep theinitial input current during start up low. The value of C
SS
can be calculated using Equation 36 .
C
SS
should be greater than 17 nF, a 22 nF MLCC was chosen. The calculated start time using this capacitor is1.28 ms.
3.2.4 Short Circuit Protection, R
ILIM
and C
ILIM
Short circuit protection is programmed using the R
ILIM
resistor. Selection of this resistor depends on the R
DS(on)
ofthe switching MOSFET selected and the required short circuit current trip point, I
SCP
. The minimum I
SCP
is limitedby the inductor peak current, the output voltage, the output capacitor and the soft start time. Their relationship isgiven by Equation 37 . A short circuit current trip point greater than that calculated by this equation should beused.
The minimum short circuit current trip point for this design is 16.35 A. This value is used in Equation 38 tocalculate the minimum R
ILIM
value.
R
ILIM
is calculated to be 1.14 k Ω. The closest standard value greater than 1.14 k Ωis chose, this is 1.15 k Ω. Toverify that the short circuit current requirements are met the minimum and maximum short circuit current can becalculated using Equation 39 and Equation 40 .
The minimum I
SCP
is 17.09 A and the maximum is 29.45 A.
It is recommended to add a small capacitor, C
ILIM
, across R
ILIM
. The value of this capacitor should be less thanthat calculated in Equation 41 .
This equation yields a maximum C
ILIM
of 44 pF. A value half this is chosen, 22 pF.
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CBOOST uQg(TOTAL)
DVBOOST
(42)
KPWM ^VUVLO
1 V
(43)
KLC +ǒ1)s ESR COǓ
1)s ǒL
RLOADǓ)s2 L CO
(44)
Ge(s) +KPWM KLC +VUVLO
1 V ǒ1)s ESR COǓ
1)s ǒL
RLOADǓ)s2 L CO
(45)
DCGAIN +20 LOGǒVUVLO
1 V Ǔ+20 LOG(8.752) +18.8 dB
(46)
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
3.2.5 Voltage Decoupling Capacitors, C
DBP
, C
LVBP
and C
VDD
Several pins on the TPS40075 have DC voltages. It is recommended to add small decoupling capacitors to thesepins. Below is a list of the recommended values.•C
DBP
= 1.0 μF•C
LVBP
= 0.1 μF•C
VDD
= 4.7 μF
3.2.6 Boost Voltage, C
BOOST
and D
BOOST
(optional)
A capacitor charge pump or boost circuit is required to drive an N-channel MOSFET in the switch location of abuck converter . The TPS40075 contains the elements for this boost circuit. The designer just has to add acapacitor, C
BOOST
, from the switch node of the buck power stage to the BOOST pin of the device. Selection ofthis capacitor is based on the total gate charge of the switching MOSFET and the allowable ripple on the boostvoltage, ΔV
BOOST
. A ripple of 0.15 V is assumed for this design. Using these two parameters and Equation 42 theminimum value for C
BOOST
can be calculated.
The total gate charge of the switching MOSFET is 13.3 nC. A minimum C
BOOST
of 0.089 μF is required. A 0.1 μFcapacitor was chosen.
This capacitor must be able to withstand the maximum voltage on DBP (10 V in this instance ). A 50 V capacitoris used for expediancy.
To reduce losses in the TPS40075 and to increase the available gate voltage for the switching MOSFET anexternal diode can be added between the DBP pin and the BOOST pin of the device. A small signal schottkyshould be used here, such as the BAT54.
3.3 Closing the Feedback Loop, R
Z1
, R
P1
, R
PZ2
, R
SET1
, R
SET2
, C
Z2
, C
P2
and C
PZ1
A graphical method is used to select the compensation components. This is a standard feedforward buckconverter. Its PWM gain is shown in Equation 43 .
The gain of the output L-C filter is given by Equation 44
The PWM and LC gain is, shown in Equation 45 .
To describe this in a Bode plot, the DC gain must be expressed in dB. The DC gain is equal to K
PWM
. To expressthis in dB we take its LOG and multiple by 20. For this converter the DC gain is shown in Equation 46 .
The pole and zero frequencies should be calculated, also. A double pole is associated with the L-C and a zero isassociated with the ESR of the output capacitor. The frequency at where these occur can be calculated using thefollowing two equations.
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fLC_Pole +1
2p L CO
Ǹ+3559 Hz
(47)
fESR_Zero +1
2p ESR CO+8377 Hz
(48)
100 100 k10 k1 k 1 M
−40
−50
10
−20
−10
20
30
0
−60
Frequency − Hz
Gain − dB
ESR = 0 Ω
Slope = −40 dB / decade
ESR = 0.0095 Ω
Slope = −20 dB / decade
Double Pole
ESR Zero
RP1
2 SAO
TPS40075
5
6
FB
COMP
UDG−04126
CPZ1
RZ1
RPZ2
CP2 CZ2
RSET2 RSET1
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
The resulting bode plot is shown in Figure 30 .
Figure 30. PWM and LC Filter Gain
The next step is to establish the required compensation gain to achieve the desired overall system response.The target response is to have the crossover frequency between 1/10 to 1/4 times the switching frequency. Tohave a phase margin greater than 45 °and a gain margin greater than 6 dB.
A Type III compensation network, as shown in Figure 31 , was used for this design. This network gives the bestoverall flexibility for compensating the converter.
Figure 31. Type III Conpensation with TPS40075
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100 100 k10 k1 k 1 M
10
−20
−10
20
30
40
0
Frequency − Hz
Gain − dB
High Frequency Gain
fZ1 fZ2 fP2
fP1
VO+VFB RZ1 )RSET
RSET
(49)
RSET +RSET1 RSET2
RSET1 )RSET2
(50)
GAIN +RPZ2
ǒRZ1 RP1
RZ1)RP1Ǔ
(51)
fP1 +1
2p RP1 CPZ1
(52)
fP2 +CP2 )CZ2
2p RPZ2 CP2 CZ2 ^1
2p RPZ2 CP2
(53)
fZ1 +1
2p RZ1 CPZ1
(54)
fZ2 +1
2p ǒRPZ2 )RP1Ǔ CZ2 ^1
2p RPZ2 CZ2
(55)
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
A typical bode plot to this type of compensation network is shown in Figure 32 .
Figure 32. Type III Compensation Bode Plot
The high frequency gain and the break (pole and zero) frequencies are calculated using the following equations.
Using this PWM and L-C bode plot the following actions ensure stability.1. Place two zero ’ s close to the double pole, i.e. f
Z1
= f
Z2
= 3559 Hz2. Place a pole at one octave below the desired crossover frequency. The crossover frequency was selected asone quarter the switching frequency, f
CO
= 100 kHz, f
P1
= 50 kHz3. Place the second pole about an octave above f
co
. This ensures that the overall system gain falls off quickly togive good gain margin, f
P2
= 200 kHz4. The high-frequency gain is sufficient to ensure 0 dB at the required crossover frequency, GAIN = -1 GAINof PWM and LC at the crossover frequency, GAIN = 17.6 dB, or 7.586
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−40
−60
−50
0
−30
−20
10
40
20
30
−10
100 100 k10 k1 k 1 M
PWM and LC Response
ESR = 0 Ω
Frequency − Hz
Gain − dB
Overall System
Response
ESR = 0 Ω
fCO2 fCO1
Compensation
Response
Overall System
Response
ESR = 0.0095 Ω
GBWP
PWM and LC Response
ESR = 0.0095 Ω
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
Desired frequency response and resultant overall system response can be seen in Figure 33 .
Figure 33. Overall System Bode Plot
Using these values and the equations above the resistors and capacitors around the compensation network canbe calculated.
1. Set R
Z1
= 10 k Ω.2. Calculate R
SET
using Equation 49 ; R
SET
= 8750 Ω. Two resistors in parallel, R
SET1
and R
SET2
, are used tomake up R
SET
. R
SET1
= 9.53 k Ω, R
SET2
= 105 k Ω.3. Using Equation 54 and f
Z1
= 3559 Hz, C
PZ1
can be calculated to be 4.47 nF; C
PZ1
= 4.7 nF.4. F
P1
and Equation 52 yields R
P1
to be 677 Ω, R
P1
= 680 Ω.5. The required gain of 17.6 dB (7.586) and Equation 52 sets the value for R
PZ1
. Note actual gain used for thiscalculation was 20 dB (10), this ensures that the gain of the transfer function is high enough, R
PZ1
= 6.2 k Ω.6. C
Z2
is calculated using Equation 55 and the desired frequency for the second zero, C
Z2
= 6.8 nF.7. C
P2
is calculated using the second pole frequency and Equation 53 , C
P2
= 150 pF.
Using MathCAD the above values were used to draw the actual Bode plot for gain and phase. From these plotsthe crossover frequency, phase margin and gain margin can be recorded.
Table 3. Equivalent Series Resistance
ESR CROSSOVER FREQUENCY PHASE MARGIN GAIN MARGIN(Ω) (kHz) ( °) (dB)
0 23.1 72 > 460.0095 98.6 78.8 > 33
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Frequency − Hz
Gain − dB
20
60
40
0
100 100 k10 k 1 M1 k
−20
−40
−60
System Gain
ESR = 0.95 mΩ
System Gain
ESR = 0 Ω
60
140
200
160
100
80
40
20
180
120
0
100 100 k10 k 1 M1 k Frequency − Hz
Phase − °
System Phase
ESR = 0.95 mΩ
System Phase
ESR = 0 Ω
ALTERNATE APPLICATIONS
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
GAIN PHASEvs vsFREQUENCY FREQUENCY
Figure 34. Figure 35.
Some alternative applicaiton diagrams are shown in Figure 36 through Figure 38 .
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1
2
3
4
19
18
17
16
SYNC
PGD
LVBP
RT
SA−
SAO
GND
SS
TPS40075
15
14
13
12
KFF
ILIM
VDD
HDRV
5
6
7
8
FB
COMP
PGND
LDRV
9 DBP
20
SA+
10
SW
11
BOOST
22 pF
2 nF
75 pF
Si7390DP
External Logic Supply
UDG−04109
100 nF
Si7868DP
10 nF
2 nF
Power Good
1 µF
118 kΩ
1.2 V
10 A
22 µF
120 µF
120 µF
VDD
12 V
10 kΩ
1.27 kΩ
118 kΩ
1 µF
10 kΩ
14 kΩ
402 Ω
10 kΩ
100 nF
22 µF
COEV DXM1306
100 µF, TDK, C3225X5R0J107M (× 3)
TDK C4532X5R1C226M (× 2)
1.3 µH
1.5 Ω
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
Figure 36. 400 kHz, 12 V to 1.2 V Converter with Powergood Indication
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1
2
3
4
19
18
17
16
SYNC
PGD
LVBP
RT
SA−
SAO
GND
SS
TPS40075
15
14
13
12
KFF
ILIM
VDD
HDRV
5
6
7
8
FB
COMP
PGND
LDRV
9 DBP
20
SA+
10
SW
11
BOOST
39 pF
100 nF
3.3 nF
100 pF
Si7344DP
3.3 V
15 A
From 3.3 V
Logic Clock Source
UDG−04110
VDD
5 V to 12 V
100 nF
3.9 nF
10 nF
BAT54
120 µF
Coiltronics HC2LP−2R2 or
Vishay IHLP5050FDRZ2R2M01
Panasonic EEF−SE0J181R (× 2)
TDK C4532X5R1C226M (×2)
120 µF
1 µF
165 kΩ
88.7 kΩ
1.74 kΩ
22 µF22 µF
180 µF180 µF
1 µF
2.67 kΩ
11.3 kΩ
330 kΩ
294 Ω
10 kΩ
Si7868DP
2.2 µH
1.5 Ω
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
Figure 37. 300 kHz Intermediate Bus (5 V to 12 V) to 3.3 V Converter
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10 kΩ
1
2
3
4
19
18
17
16
SYNC
PGD
LVBP
RT
SA−
SAO
GND
SS
TPS40075
15
14
13
12
KFF
ILIM
VDD
HDRV
5
6
7
8
FB
COMP
PGND
LDRV
9 DBP
20
SA+
10
SW
11
BOOST
22 pF
100 n
2 nF
75 pF
Si7390DP
UDG−04111
VDD, 12 V
100 nF
Si7868DP
10 nF
2 nF
1
2 19
18
17
16
SYNC
PGD
LVBP
RT
SA−
SAO
TPS40075
15
14
13
12
KFF
ILIM
VDD
HDRV
5
6
7
8
FB
COMP
PGND
LDRV
9 DBP
20
SA+
10
SW
11
BOOST
47 pF
100 nF
3.9 nF
120 pF
Si7804DN
3.3 V
5 A
VDD
12 V
100 nF
Si7806DN
3.3 nF
3.3 V or
Other Logic Supply
Power
Good
SYNC Clock Input
300 kHz
3
4
GND
SS
10 nF
SN74LVC1G04
1 µF
215 kΩ
205 kΩ
120 µF120 µF
1.27 kΩ
22 µF22 µF
100 µF × 3
13 µH
1 µF
10 kΩ
402 Ω
10 kΩ
14 kΩ
1.2 V
10 A
1 µF
2.67 kΩ
8.06 kΩ
10 kΩ267 Ω10 kΩ
215 kΩ
205 kΩ
787 Ω
2.2 µH
180 µF180 µF
1 µF
22 µF
1.5 Ω
1.5 Ω
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
Figure 38. Sequenced Supplies, Synchronized 180 °Out of Phase
Copyright © 2006 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Link(s) :TPS40075
www.ti.com
ADDITIONAL REFERENCES
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
The following parts are similar to the TPS40075 and may be of interest:1. TPS40071 Mid Range Input (4.5 V to 28 V) up to 1-MHz Frequency Synchronous Buck Controller2. TPS40100 Wide Input Range Synchronous Buck Controller for Sequencing3. TPS40057 Wide Input (8 V to 40 V) up to 1MHz Frequency Synchronous Buck Controller, source/sink withprebias
4. TPS40190 Low Pin Count Synchronous Buck DC/DC Controller
38 Submit Documentation Feedback Copyright © 2006 – 2007, Texas Instruments Incorporated
Product Folder Link(s) :TPS40075
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS40075RHLR QFN RHL 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
TPS40075RHLT QFN RHL 20 250 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS40075RHLR QFN RHL 20 3000 346.0 346.0 29.0
TPS40075RHLT QFN RHL 20 250 190.5 212.7 31.8
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
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