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DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DExtended Temperature Performance of
−55°C to 125°C
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product Change Notification
DQualification Pedigree†
DPush-Pull CMOS Output Drives Capacitive
Loads Without Pullup Resistor,
IO = ± 8 mA
DVery Low Power . . . 100 µW Typ at 5 V
DFast Response Time ...t
PLH = 2.7 µs Typ
With 5-mV Overdrive
DSingle-Supply Operation ...4 V to 16 V
DOn-Chip ESD Protection
†Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
description
The TLC3702 consists of two independent micropower voltage comparators designed to operate from a single
supply and be compatible with modern HCMOS logic systems. They are functionally similar to the LM339 but
use one-twentieth of the power for similar response times. The push-pull CMOS output stage drives capacitive
loads directly without a power-consuming pullup resistor to achieve the stated response time. Eliminating the
pullup resistor not only reduces power dissipation, but also saves board space and component cost. The output
stage is also fully compatible with TTL requirements.
Texas Instruments LinCMOS process offers superior analog performance to standard CMOS processes.
Along with the standard CMOS advantages of low power without sacrificing speed, high input impedance, and
low bias currents, the LinCMOS process offers extremely stable input offset voltages with large differential
input voltages. This characteristic makes it possible to build reliable CMOS comparators.
ORDERING INFORMATION
TAPACKAGE‡ORDERABLE
PART NUMBER TOP-SIDE
MARKING
−55°C to 125°CSOP − D Tape and reel TLC3702MDREP 3702ME
‡Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2002, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments Incorporated.
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
VDD
2OUT
2IN−
2IN+
OUT
symbol (each comparator)
IN+
IN−
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functional block diagram (each comparator)
VDD
GND
OUT
Differential
Input
Circuits
IN+
IN−
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) −0.3 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI −0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO − 0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO (each output) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total supply current into VDD 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of GND 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN−.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING TA = 125°C
POWER RATING
D725 mW 5.8 mW/°C464 mW 377 mW 145 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VDD 4 5 16 V
Common-mode input voltage, VIC 0 VDD − 1.5 V
High-level output current, IOH −20 mA
Low-level output current, IOL 20 mA
Operating free-air temperature, TA−55 125 °C
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electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER TEST CONDITIONS†TAMIN TYP MAX UNIT
VIO
Input offset voltage
VDD = 5 V to 10 V,
25°C 1.2 5
mV
V
IO
Input offset voltage
VDD = 5 V to 10 V,
VIC = VICRmin, See Note 3 −55°C to 125°C 10
mV
IIO
Input offset current
VIC = 2.5 V
25°C 1 pA
IIO Input offset current VIC = 2.5 V 125°C 15 nA
IIB
Input bias current
VIC = 2.5 V
25°C 5 pA
IIB Input bias current VIC = 2.5 V 125°C 30 nA
VICR
Common-mode input voltage range
25°C0 to
VDD − 1
V
VICR Common-mode input voltage range −55°C to 125°C0 to
VDD − 1.5
V
25°C 84
CMRR Common-mode rejection ratio V
IC
= V
ICR
min 125°C 83 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
−55°C 82
dB
25°C 85
k
SVR
Supply-voltage rejection ratio V
DD
= 5 V to 10 V 125°C 85 dB
kSVR
Supply-voltage rejection ratio
VDD = 5 V to 10 V
− 55°C 82
dB
VOH
High-level output voltage
VID = 1 V,
IOH = −4 mA
25°C 4.5 4.7
V
VOH High-level output voltage VID = 1 V, IOH = −4 mA 125°C4.2 V
VOL
Low-level output voltage
VID = −1 V,
IOH = −4 mA
25°C 210 300
mV
VOL Low-level output voltage VID = −1 V, IOH = −4 mA 125°C500 mV
IDD
Supply current (both comparators)
Outputs low,
No load
25°C 18 40
µA
I
DD
Supply current (both comparators)
Outputs low,
No load
−55°C to 125°C 90 µ
A
†All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3. The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
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switching characteristics, VDD = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Overdrive = 2 mV 4.5
f = 10 kHz,
Overdrive = 5 mV 2.7
t
PLH
Propagation delay time, low-to-high-level output†f = 10 kHz,
CL = 50 pF
Overdrive = 10 mV 1.9 µs
tPLH
Propagation delay time, low-to-high-level output†
CL = 50 pF
Overdrive = 20 mV 1.4
µs
Overdrive = 40 mV 1.1
VI = 1.4 V step at IN+ 1.1
Overdrive = 2 mV 4
f = 10 kHz,
Overdrive = 5 mV 2.3
t
PHL
Propagation delay time, high-to-low-level output†f = 10 kHz,
CL = 50 pF
Overdrive = 10 mV 1.5 µs
tPHL
Propagation delay time, high-to-low-level output†
CL = 50 pF
Overdrive = 20 mV 0.95
µs
Overdrive = 40 mV 0.65
VI = 1.4 V step at IN+ 0.15
tfFall time f = 10 kHz,
CL = 50 pF Overdrive = 50 mV 50 ns
trRise time f = 10 kHz,
CL = 50 pF Overdrive = 50 mV 125 ns
†Simultaneous switching of inputs causes degradation in output response.
LinCMOS and Advanced LinCMOS are trademarks of Texas Instruments Incorporated.
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PRINCIPLES OF OPERATION
LinCMOSprocess
The LinCMOS process is a linear polysilicon-gate CMOS process. Primarily designed for single-supply
applications, LinCMOS products facilitate the design of a wide range of high-performance analog functions
from operational amplifiers to complex mixed-mode converters.
While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers.
This short guide is intended to answer the most frequently asked questions related to the quality and reliability
of LinCMOS products. Further questions should be directed to the nearest TI field sales office.
electrostatic discharge
CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only
for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to
CMOS devices. It can occur when a device is handled without proper consideration for environmental
electrostatic charges, e.g., during board assembly. If a circuit in which one amplifier from a dual op amp is being
used and the unused pins are left open, high voltages tend to develop. If there is no provision for ESD protection,
these voltages may eventually punch through the gate oxide and cause the device to fail. To prevent voltage
buildup, each pin is protected by internal circuitry.
Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more
transistors break down at voltages higher than the normal operating voltages but lower than the breakdown
voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the
shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are
small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as
tens of picoamps.
To overcome this limitation, TI design engineers developed the patented ESD-protection circuit shown in
Figure 1. This circuit can withstand several successive 2-kV ESD pulses, while reducing or eliminating leakage
currents that may be drawn through the input pins. A more detailed discussion of the operation of the TI
ESD-protection circuit is presented on the next page.
All input and output pins on LinCMOS and Advanced LinCMOS products have associated ESD-protection
circuitry that undergoes qualification testing to withstand 2000 V discharged from a 100-pF capacitor through
a 1500-Ω resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor
(charged device model). These tests simulate both operator and machine handling of devices during normal
test and assembly operations.
To Protect Circuit
D3
R2
Q2
D2D1
Q1
Input
GND
R1 VDD
Figure 1. LinCMOS ESD-Protection Schematic
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PRINCIPLES OF OPERATION
input protection circuit operation
Texas Instruments patented protection circuitry allows for both positive- and negative-going ESD transients.
These transients are characterized by extremely fast rise times and usually low energies, and can occur both
when the device has all pins open and when it is installed in a circuit.
positive ESD transients
Initial positive charged energy is shunted through Q1 to VSS. Q1 turns on when the voltage at the input rises
above the voltage on the VDD pin by a value equal to the VBE of Q1. The base current increases through R2
with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2
to exceed its threshold level (VT ∼ 22 to 26 V) and turn Q2 on. The shunted input current through Q1 to V SS is
now shunted through the n-channel enhancement-type MOSFET Q2 to VSS. If the voltage on the input pin
continues to rise, the breakdown voltage of the zener diode D3 is exceeded and all remaining energy is
dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the
gate-oxide voltage of the circuit to be protected.
negative ESD transients
The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1
and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is −0.3 V to −1 V (the forward
voltage of D1 and D2).
circuit-design considerations
LinCMOS products are being used in actual circuit environments that have input voltages that exceed the
recommended common-mode input voltage range and activate the input protection circuit. Even under normal
operation, these conditions occur during circuit power up or power down, and in many cases, when the device
is being used for a signal conditioning function. The input voltages can exceed VICR and not damage the device
only if the inputs are current limited. The recommended current limit shown on most product data sheets is
±5 mA. Figure 2 and Figure 3 show typical characteristics for input voltage versus input current.
Normal operation and correct output state can be expected even when the input voltage exceeds the positive
supply voltage. Again, the input current should be externally limited even though internal positive current limiting
is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current
to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input
current. This base current is forced into the VDD pin and into the device IDD or the VDD supply through R2
producing the current limiting effects shown in Figure 2. This internal limiting lasts only as long as the input
voltage is below the VT of Q2.
When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage
states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be
severely a f fected. External current limiting must b e used since this current is directly shunted by D1 and D2 and
no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is
required (see Figure 4).
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PRINCIPLES OF OPERATION
circuit-design considerations (continued)
Figure 2
VDD VDD + 4 VDD + 8 VDD + 12
INPUT CURRENT
vs
INPUT VOLTAGE
TA = 25° C
8
7
6
5
4
3
2
1
0
VI − Input Voltage − V
− Input Current − mAII
Figure 3
VDD − 0.3
VI − Input Voltage − V
INPUT CURRENT
vs
INPUT VOLTAGE
TA = 25° C
VDD − 0.5 VDD − 0.7 VDD − 0.9
10
9
8
7
6
5
4
3
2
1
0
− Input Current − mAII
+
−
1/2
TLC3702
Vref
VI
VDD
See Note A
RI
NOTE A: If the correct input state is required when the negative input exceeds GND, a Schottky clamp is required.
Negative Voltage Input Current Limit :
RI+
*VI*VDD *(*0.3 V)
5mA
RI+VI*VDD *0.3 V
5mA
Positive Voltage Input Current Limit :
Figure 4. Typical Input Current-Limiting Configuration for a LinCMOS Comparator
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PARAMETER MEASUREMENT INFORMATION
The TLC3702 contains a digital output stage which, if held in the linear region of the transfer curve, can cause
damage to the device. Conventional operational amplifier/comparator testing incorporates the use of a servo
loop which is designed to force the device output to a level within this linear region. Since the servo-loop method
of testing cannot be used, we offer the following alternatives for measuring parameters such as input offset
voltage, common-mode rejection, etc.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 5(a). With the noninverting input positive with respect to the inverting input, the output should be high.
With the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages
can be slewed to provide greater accuracy, as shown in Figure 5(b) for the VICR test. This slewing is done instead
of changing the input voltages.
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal,
but opposite in polarity, to the input offset voltage, the output changes states.
Figure 6 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator in the linear region. The circuit consists of a switching mode servo loop in which IC1a generates
a triangular waveform of approximately 20-mV amplitude. IC1b acts as a buffer, with C2 and R4 removing any
residual dc offset. The signal is then applied to the inverting input of the comparator under test, while the
noninverting input is driven by the output of the integrator formed by IC1c through the voltage divider formed
by R8 and R9. The loop reaches a stable operating point when the output of the comparator under test has a
duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when
the voltage at the noninverting input exactly equals the input offset voltage.
Voltage dividers R8 and R9 provide an increase in input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R7, R8, and R9 can significantly influence the accuracy of the reading; therefore, it
is suggested that their tolerance level be one percent or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current
and compensation for the leakage of the test socket and board. With a good picoammeter , the socket and board
leakage can be measured with no device in the socket. Subsequently, this open socket leakage value can be
subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the
device.
+
−
5 V
Applied VIO
Limit VO
+
−
1 V
Applied VIO
Limit VO
− 4 V
(a) VIO WITH VIC = 0 V (b) VIO WITH VIC = 4 V
Figure 5. Method for Verifying That Input Offset Voltage Is Within Specified Limits
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PARAMETER MEASUREMENT INFORMATION
−
+DUT
V
DD
+
−
−
+
−
+
C2
1 µF
R4
47 kΩ
R5
1.8 kΩ 1%
C3
0.68 µF
IC1c
1/4 TLC274CN
IC1a
1/4 TLC274CN
IC1b
1/4 TLC274CN
R6
1 MΩ
R7
1.8 kΩ 1%
R8
10 kΩ 1%
R1
240 kΩ
R2
10 kΩ
C1
0.1 µF
R3
100 Ω
C4
0.1 µF
Integrator
R9
100 Ω 1%
Buffer
Triangle
Generator
VIO
(X10
0)
Figure 6. Circuit for Input Offset Voltage Measurement
Response time is defined as the interval between the application of an input step function and the instant when
the output reaches 50% of its maximum value. Response time for the low-to-high-level output is measured from
the leading edge of the input pulse, while response time for the high-to-low-level output is measured from the
trailing edge of the input pulse. Response time measurement at low input signal levels can be greatly affected
by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input as
shown in Figure 7, so that the circuit is just at the transition point. A low signal, for example 105-mV or 5-mV
overdrive, causes the output to change state.
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PARAMETER MEASUREMENT INFORMATION
+
−
DUT
VDD
CL
(see Note A)
Pulse
Generator
10 Ω
10-Turn
Potentiometer
1 V
− 1 V
1 kΩ
50 Ω
1 µF
0.1 µF
TEST CIRCUIT
100 mVInput
Overdrive
90%
50%
10%
tr
tPLH
100 mVInput
Overdrive
90%
50%
10%
tf
tPHL
Low-to-High
Level Output High-to-Low
Level Output
VOLTAGE WAVEFORMS
NOTE A: CL includes probe and jig capacitance.
Figure 7. Response, Rise, and Fall Times Circuit and Voltage Waveforms
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TYPICAL CHARACTERISTICS†
Table of Graphs
FIGURE
VIO Input offset voltage Distribution 8
IIB Input bias current vs Free-air temperature 9
CMRR Common-mode rejection ratio vs Free-air temperature 10
kSVR Supply-voltage rejection ratio vs Free-air temperature 11
VOH
High-level output current
vs Free-air temperature
vs High-level output current
12
13
VOH High-level output current
vs Free-air temperature
vs High-level output current
12
13
VOL
Low-level output voltage
vs Low-level output current
vs Free-air temperature
14
15
VOL Low-level output voltage
vs Low-level output current
vs Free-air temperature
14
15
ttTransition time vs Load capacitance 16
Supply current response vs Time 17
Low-to-high-level output response Low-to-high level output propagation delay time 18
High-to-low level output response High-to-low level output propagation delay time 19
tPLH Low-to-high level output propagation delay time vs Supply voltage 20
tPHL High-to-low level output propagation delay time vs Supply voltage 21
vs Frequency
22
I
DD
Supply current
vs Frequency
vs Supply voltage
vs Free-air temperature
22
23
24
IDD
Supply current
vs Supply voltage
vs Free-air temperature
23
24
Figure 8
É
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
É
É
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
É
É
É
É
ÇÇ
ÇÇ
É
É
ÇÇ
Ç
Ç
Ç
É
É
É
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÇÇ
Number of Units
VDD = 5 V
VIC = 2.5 V
TA = 25° C
−5 −4 −3 −2 −1 0 1 2 3 4 5
VIO − Input Offset Voltage − mV
DISTRIBUTION OF INPUT
OFFSET VOLTAGE
200
180
160
140
120
100
80
60
40
20
0
698 Units Tested
From 4 Wafer Lots
Figure 9
I
TA − Free-Air Temperature − °C
IB
− Input Bias Current − nA
25 50 75 100 125
10
1
0.1
0.01
0.001
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
VDD = 5 V
VIC = 2.5 V
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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TYPICAL CHARACTERISTICS†
Figure 10
CMRR − Common-Mode Rejection Ratio − dB
TA − Free-Air Temperature − °C
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
−75 −50 −25 0 25 50 75 100 125
VDD = 5 V
90
88
86
84
82
80
78
76
74
72
70
Figure 11
−75 −50 −25 0 25 50 75 100 125
kSVR − Supply Voltage Rejection Ratio − dB
TA − Free-Air Temperature − °C
SUPPLY VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
VDD = 5 V to 10 V
90
88
86
84
82
80
78
76
74
72
70
Figure 12
5
TA − Free-Air Temperature − °C
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VOH − High-Level Outout Voltage − V
VDD = 5 V
IOH = − 4 mA
−75 −50 −25 0 25 50 75 100 125
4.9
4.8
4.7
4.6
4.5
4.55
4.65
4.75
4.85
4.95
Figure 13
VDD = 16 V
IOH − High-Level Output Current − mA
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VOH
TA = 25° C 3 V
4 V
5 V
10 V
0 −2.5 −5 −7.5 −10 −12.5 −15 −17.5 −20
− High-Input Level Output Voltage −V
VDD
−0.25
−0.5
−0.75
−1
−1.25
−1.5
−1.75
−2
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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TYPICAL CHARACTERISTICS†
Figure 14
IOL − Low-Level Output Current − mA
0 2 4 6 81012141618 20
VOL − Low-Level Output Voltage − V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
3 V 4 V
10 V
VDD = 16 V
5 V
1.5
1.25
1
0.75
0.5
0.25
0
TA = 25°C
Figure 15
−75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VOL − Low-Level Output Voltage − mV
400
350
300
250
200
150
100
50
0
VDD = 5 V
IOL = 4 mA
Figure 16
0 200 400 600 800 1000
CL − Load Capacitance − pF
tt − Transition Time − ns
OUTPUT TRANSITION TIME
vs
LOAD CAPACITANCE
250
225
200
175
150
125
100
75
50
25
0
VDD = 5 V
TA = 25°C
Rise Time
Fall Time
Figure 17
IDD − Supply
SUPPLY CURRENT RESPONSE
TO AN OUTPUT VOLTAGE TRANSITION
Current − mA
t − T ime
Output
Voltage − V
10
5
0
5
0
VDD = 5 V
CL = 50 pF
f = 10 kHz
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SGLS127 − JULY 2002
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 18
012345
VO − Output
Voltage − V
Input
Voltage − mV
Differential
LOW-TO-HIGH-LEVEL OUTPUT RESPONSE
FOR VARIOUS INPUT OVERDRIVES
tPLH − Low-to-High-Level Output
Response Time − µs
VDD = 5 V
TA = 25°C
CL = 50 pF
5
0
100
0
40 mV
20 mV
10 mV
5 mV
2 mV
Figure 19
40 mV
20 mV
10 mV
5 mV
2 mV
HIGH-TO-LOW-LEVEL OUTPUT RESPONSE
FOR VARIOUS INPUT OVERDRIVES
tPHL − High-to-Low-Level Output
Response Time − µs
VO − Output
Voltage − V
Input
Voltage − mV
Differential
5
0
100
0
012345
VDD = 5 V
TA = 25° C
CL = 50 pF
Figure 20
LOW-TO-HIGH-LEVEL
OUTPUT RESPONSE TIME
vs
SUPPLY VOLTAGE
Overdrive = 2 mV
5 mV
10 mV
20 mV
40 mV
6
5
4
3
2
1
00246810121416
VDD − Supply Voltage − V
CL = 50 pF
TA = 25°C
tPLH − Low-to-High-Level Output Response −µs
Figure 21
HIGH-TO-LOW-LEVEL
OUTPUT RESPONSE TIME
vs
SUPPLY VOLTAGE
6
5
4
3
2
1
00246810121416
5 mV
10 mV
20 mV
40 mV
CL = 50 pF
TA = 25°C
VDD − Supply Voltage − V
tPHL − High-to-Low-Level Output Response −µs
Overdrive = 2 mV
SGLS127 − JULY 2002
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 22
AVERAGE SUPPLY CURRENT
(PER COMPARATOR)
vs
FREQUENCY
10000
1000
100
10
V − Supply Current − µ
DD A
0.01 0.1 1 10 100
f − Frequency − kHz
VDD = 16 V
5 V
4 V
10 V
3 V
TA = 25°C
CL = 50 pF
Figure 23
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V
40
35
30
25
20
15
10
5
0012345678
Outputs Low
No Loads
V − Supply Current − µ
DD A
TA = − 25°C
TA = − 125°C
TA = − 40°C
TA = − 55°C
TA = 85°C
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
30
25
20
15
10
5
0
−75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C
IDD − Supply Current −µA
Outputs High
Outputs Low
VDD = 5 V
No Load
Figure 24
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SGLS127 − JULY 2002
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
The inputs should always remain within the supply rails in order to avoid forward biasing the diodes in the
electrostatic discharge (ESD) protection structure. If either input exceeds this range, the device is not damaged
as long as the input is limited to less than 5 mA. To maintain the expected output state, the inputs must remain
within the common-mode range. For example, at 25°C with VDD = 5 V, both inputs must remain between
−0.2 V and 4 V to ensure proper device operation.
To ensure reliable operation, the supply should be decoupled with a capacitor (0.1 µF) that is positioned as close
to the device as possible.
The TLC3702 has internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as
tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices as
exposure to ESD may result in the degradation of the device parametric performance.
Table of Applications
FIGURE
Pulse-width-modulated motor speed controller 25
Enhanced supply supervisor 26
Two-phase nonoverlapping clock generator 27
Micropower switching regulator 28
C1
0.01 µF
(see Note B)
5 V
1/2 TLC3702
Motor Speed Control
Potentiometer
+
−
+
−10 kΩ
100 kΩ
10 kΩ
10 kΩ
See
Note A
1/2 TLC3704
10 kΩ
5 V
DIR
EN
SN75603
Half-H Driver
12 V
Motor
DIR
EN
12 V
Direction
Control S1
SPDT
5 V
5 V
SN75604
Half-H Driver
NOTES: A. The recommended minimum capacitance is 10 µF to eliminate common ground switching noise.
B. Adjust C1 for change in oscillator frequency.
Figure 25. Pulse-Width-Modulated Motor Speed Controller
SGLS127 − JULY 2002
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
1/2 TLC3702
To µP Interrupt
Early Power Fail
+
−
+
−
1 kΩ
3.3 kΩ
CT
(see Note B)
1/2 TLC3702 10 kΩ
5 V
5 V
12-V
Sense
R2
R1
V(UNREG)
(see Note A)
1 µF
12 V
RESIN
REF CTGND
RESET
SENSEVCC
To µP
Reset
Monitors 5 VDC Rail
Monitors 12 VDC Rail
Early Power Fail Warnin
g
TL7705A
2.5 V
NOTES: A. V(UNREG) +2.5(R1 +R2)
R2
B. The value of CT determines the time delay of reset.
Figure 26. Enhanced Supply Supervisor
SGLS127 − JULY 2002
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
−
+22 kΩC1
0.01 µF
(see Note A)
1/2 TLC3702
R1
100 kΩ
(see Note B)
12 V
100 kΩ
1/2 TLC3702
2OUT
−
+
−
+
1/2 TLC3702
100 kΩ100 kΩ
12 V
1OUT
12 V
R2
5 kΩ
(see Note C)
R3
100 kΩ
(see Note B)
2OUT
1OUT
12 V
NOTES: A. Adjust C1 for a change in oscillator frequency where:
1/f = 1.85(100 kΩ)C1
B. Adjust R1 and R3 to change duty cycle
C. Adjust R2 to change deadtime
Figure 27. Two-Phase Nonoverlapping Clock Generator
SGLS127 − JULY 2002
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
+
−100 kΩC1
180 µF
(see Note A)
1/2 TLC3702
47 µF
Tantalum
100 kΩ
R2
100 kΩ
100 kΩ
100 kΩ
VI
VI
−
+
1/2 TLC3702
VI
+
−
TLC271
(see Note B)
270 kΩ
VI
100 kΩ
C2
100 pF
100 kΩ
IN5818
R = 6 Ω
L = 1 mH
(see Note D)
RL
470 µF
VI
VO
R1
GS
SK9504
(see Note C)
VI+6 V to 16 V
IL+0.01 mA to 0.25 mA
VO+2.5 (R1 )R2)
R2
LM385
2.5 V
D
+
NOTES: A. Adjust C1 for a change in oscillator frequency
B. TLC271 − Tie pin 8 to pin 7 for low bias operation
C. SK9504 − VDS = 40 V
IDS = 1 A
D. To achieve microampere current drive, the inductance of the circuit must be increased.
Figure 28. Micropower Switching Regulator
SGLS127 − JULY 2002
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°−ā8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC3702MDREP ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/03643-01XE ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC3702-EP :
•Catalog: TLC3702
•Automotive: TLC3702-Q1
•Military: TLC3702M
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC3702MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jul-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC3702MDREP SOIC D 8 2500 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jul-2008
Pack Materials-Page 2
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC3702MDREP ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/03643-01XE ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC3702-EP :
•Catalog: TLC3702
•Automotive: TLC3702-Q1
•Military: TLC3702M
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC3702MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC3702MDREP SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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