Features
•
64-Mbit Flash and 16-Mbit PSRAM
•
Single 66-ball (8 mm x 10 mm x 1.2 mm) CBGA Package
•
2.7V to 3.1V Operating Voltage
Flash
•
Single Voltage Read/Write Operation: 2.65V to 3.6V
•
Access Time – 70 ns
•
Sector Erase Architecture
– One Hundred Twenty-seven 32K Word Sectors with Individual Write Lockout
– Eight 4K Word Sectors with Individual Write Lockout
•
Fast Word Program Time – 10 µs
•
Typical Sector Erase Time: 32K Word Sectors – 700 ms; 4K Word Sectors – 100 ms
•
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
•
Low-power Operation
– 10 mA Active
– 15 µA Standby
•
VPP Pin for Write Protection and Accelerated Program Operation
•
WP Pin for Sector Protection
•
RESET Input for Device Initialization
•
Flexibel Sector Protection
•
Top or Bottom Boot Block Configuration Available
•
128-bit Protection Register
•
Minimum 100,000 Erase Cycles
•
Common Flash Interface (CFI)
PSRAM
•
16-megabit (1M x 16)
•
2.7V to 3.1V V
CC
•
70 ns Access Time
Device Number
Flash Boot
Location
Flash Plane
Configuration
PSRAM
Configuration
AT52BC6402D Bottom 64M (4M x 16) 16M (1M x 16)
AT52BC6402DT Top 64M (4M x 16) 16M (1M x 16)
Flash & PSRAM Datasheets
Datasheets PDF File
64M Flash Memory: AT49BV640D(T)
16M PSRAM: 2FHY64UD16161B
Acrobat Document
Acrobat Document
64-megabit
Flash +
16-megabit
PSRAM
Stack Memory
AT52BC6402D
AT52BC6402DT
Preliminary
3619A–STKD–7/06
2
3619A–STKD–7/06
AT52BC6402D(T) Preliminary
1. Pin Configuration
2. AT52BC6402D(T) (Top View)
Pin Name Function
A0 - A19, A21 Common Address Input for 16M PSRAM/Flash, Flash Address Input
CE Flash Chip Enable
OE Flash Output Enable
WE Flash Write Enable
RESET Flash Reset
PW Flash Write Protect
VPP Flash Power Supply for Accelerated Program Operation
VCC Flash Power
GND Flash Ground
I/O0 - I/O15 Data Inputs/Outputs
NC No Connect
LB PSRAM Lower Byte
UB PSRAM Upper Byte
PVCC PSRAM Power
PGND PSRAM Ground
PCS1 PSRAM Chip Select 1
PCS2 Low Power Modes
PWE PSRAM Write Enable
POE PSRAM Output Enable
A
B
C
D
E
F
G
H
123456789101112
NC
NC
NC
NC
A20
A16
WE
PGND
WP
LB
A18
NC
A11
A8
A21
RESET
VPP
UB
A17
A5
A15
A10
A19
POE
A7
A4
A14
A9
I/O11
A6
A0
A13
I/O15
I/O13
I/O12
I/O9
A3
CE
A12
PWE
I/O6
PCS2
I/O10
I/O8
A2
GND
GND
I/O14
I/O4
PVCC
I/O2
I/O0
A1
OE
NC
I/O7
I/O5
VCC
I/O3
I/O1
PCS1
NC
NC
NC
NC
NC
3
3619A–STKD–7/06
AT52BC6402D(T) Preliminary
3. Block Diagram
4. Description
The AT52BC6402D(T) combines a 64-megabit Flash (4M x 16) and an 16-megabit PSRAM
(organized as 1M x 16) in a stacked 66-ball CBGA package. The stacked modules operate at
2.7V to 3.1V in the extended temperature range.
64-Mbit
FLASH
16-Mbit
PSRAM
ADDRESS
DATA
RESET
CE
PCS1
PCS2
LB
UB
WE PWEPOEOE
PW
VPP
5. Absolute Maximum Ratings
Temperature under Bias ................................. -55°C to +85°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature .................................... -55°C to +150°C
All Input Voltages
except V
PP
(including NC Pins)
with Respect to Ground ..............................-0.2V to V
CC
+0.3V
Voltage on V
PP
with Respect to Ground ..................................-0.2V to + 10.0V
All Output Voltages
with Respect to Ground ..............................-0.2V to V
CC
+0.3V
6. DC and AC Operating Range
AT52BC6402D(T)-70CU
Operating Temperature (Case) -30°C - 85°C
V
CC
Power Supply 2.7V to 3.1V
4
3619A–STKD–7/06
AT52BC6402D(T) Preliminary
Notes: 1.
X can be V
IL
or V
IH
2. The VPP pin can be tied to V
CC
. For faster program operations, V
PP
can be set to 9.5V ± 0.5V.
3. V
IHPP
(min) = 1.65V
4. V
ILPP
(max) = 0.4V
Note: 1. X means don’t care (must be low or high state).
7. Flash Operating Modes
Mode CE OE WE RESET V
PP(2)
Ai I/O
PSRAM
Operation
Read V
IL
V
IL
V
IH
V
IH
XAi D
OUT
PSRAM
Must Be
High-Z
Program/Erase V
IL
V
IH
V
IL
V
IH
V
IHPP(3)
Ai D
IN
Program Inhibit V
IL
XV
IH
V
IH
X
V
IL
XX XV
ILPP(4)
Software Product
Identification V
IL
V
IL
V
IH
V
IH
XA0 = V
IL
, A1 - A19 = V
IL
Manufacturer
Code
A0 = V
IH
, A1 - A19 = V
IL
Device Code
Standby/Program
Inhibit V
IH
X
(1)
XV
IH
XX High Z
Any PSRAM
Operation is
Allowed
Output Disable X V
IH
XV
IH
X High Z
Reset X X X V
IL
XX High Z
8. Functional Description
PCS1 PCS2 POE PWE LB UB I/O0 - 7 I/O8 - 15 Mode Power
Flash
Operation
HHX
(1)
X
(1)
X
(1)
X
(1)
High-Z High-Z Deselected Standby Any Flash
Operation
Allowed
X
(1)
LX
(1)
X
(1)
X
(1)
X
(1)
High-Z High-Z Deselected Low-power
Modes
L
(1)
HX
(1)
X
(1)
H H High-Z High-Z Output Disabled Active
Flash Must
Be High Z
LHHHLX
(1)
High-Z High-Z Output Disabled Active
HHHX
(1)
L High-Z High-Z Output Disabled Active
LH
LH
LHD
OUT
High-Z Lower Byte
Read Active
H L High-Z D
OUT
Upper Byte
Read Active
LLD
OUT
D
OUT
Word Read Active
X
(1)
L
LH D
IN
High-Z Lower Byte
Write Active
H L High-Z D
IN
Upper Byte
Write Active
LL D
IN
D
IN
Word Write Active
5
3619A–STKD–7/06
AT52BC6402D(T) Preliminary
9. Ordering Information
9.1 Green Package (Pb/Halide-free)
t
ACC
(ns) Ordering Code
Flash Boot
Block Flash Plane Architecture PSRAM Package Operation Range
70
AT52BC6402D-70CU Bottom 64M – Single Bank
1M x 16 66C7 Extended
(-30° to 85°C)
AT52BC6402DT-70CU Top 64M – Single Bank
Package Type
66C7 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
6
3619A–STKD–7/06
AT52BC6402D(T) Preliminary
10. Packaging Information
10.1 66C7 – CBGA
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
66C7, 66-ball (12 x 8 Array), 10 x 8 x 1.2 mm Body, 0.8 mm Ball
Pitch Chip-scale Ball Grid Array Package (CBGA) A
66C7
5/01/06
Side View
A
A1
0.12
Seating Plane
C
C
Top View
Bottom View
0.60 REF
E
D
A1 Ball Corner
Øb
Marked A1 Identifier
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
89
101112
D1
1.20 REF
e
e
E1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
E 9.90 10.00 10.10
E1 8.75 8.80 8.85
D 7.90 8.00 8.10
D1 5.55 5.60 5.65
A – – 1.20
A1 0.25 – –
e 0.80 TYP
Øb – 0.40 –
7
3619A–STKD–7/06
AT52BC6402D(T) Preliminary
11. Revision History
Revision No. History
Revision A – July 2006 •Initial Release
Printed on recycled paper.
3619A–STKD–7/06
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