PCI64 SPARTAN-II - Xilinx, Inc.

January 31, 2000

PCI64 Spartan-II Interface V 3.0

Xilinx Inc.

2100 Logic Drive

San Jose, CA 95124

Phone: +1 408-559-7778

Fax: +1 408-377-3259

E-mail: Techsupport: support.xilinx.com

Feedback: logicore@xilinx.com

URL: http://www.xilinx.com

Introduction

With Xilinx LogiCORE PCI64 Spartan-II interface, a

designer can build a customiz ed, 64-bit, 0-33 MHz fully PCI

compliant system with the highest possible sustained per-

formance (264 Mbytes/sec), and up to 135,000 system

gates in the Spartan-II FPGAs.

Features

• Fully V2.2 PCI compliant 64-bit, 0-33 MHz PCI Initiator/

target Interface

• Zero wait-state burst operation

• Hot Swap CompactPCI friendly

• Programmable single-chip solution with customizable

back-end functionality

• Pre-deﬁned implementation for predictable timing in

Xilinx Spartan-II FPGAs

• Incorporates Xilinx Smart-IP Technology

• Universal PCI support in Spartan-II

• 3.3 V and 5 V operation at 0-33 MHz

• Master automatically handles 64-bit or 32-bit PCI

transactions without knowledge of target bus width

• Fully veriﬁed design tested with Xilinx testbench and

hardware

• Conﬁgurable on-chip dual-por t FIFOs can be added for

maximum burst speed

• Supported Initiator functions

- Memory Read, Memory Write, Memory Read

Multiple (MRM), Memory Read Line (MRL)

commands

- I/O Read, I/O Write commands

- Conﬁguration Read, Conﬁguration Write commands

- Bus Parking

- Special Cycles, Interrupt Acknowledge

- Basic Host Bridging

LogiCORE

™

Facts

Core Speciﬁcs

Device Family: Spartan-II

System Clock f

max

: 0-33MHz

Device Features

Used: Bi-directional data buses

SelectIO

Block SelectRAM+

™

(optional user FIFO)

Supported Devices

/Percent Resources Used

Devices I/O Slice

ﬂip

ﬂops

4 input

LUTs

bit

2S100FG456-6 46% 13% 24%

2S150FG456-6 35% 9% 17%

Provided with Core

Documentation;

PCI Design Guide

PCI Implementation Guide

PCI Data Book

Design File Formats: Verilog/VHDL Simulation Model

Verilog/VHDL Instantiation Code

NGO Netlist

Constraints Files: User Constraint File (UCF)

Guide files

Verification Tools: Verilog/VHDL Testbench

Reference designs &

application notes: Example designs:

PING Reference Design, Synthe-

sizable Asynchronous PCI FIFO

Design T ool Requirements

Xilinx Core Tools: 2.1i SP5

Tested Entry/Verifica-

tion Tools

:For Core Instantiation: Synopsys

FPGA Express, Synopsys FPGA

Compiler, Synplicity Synplify,

Examplar

For Core Verification:Leonardo,

Cadence Verilog XL, MTI Model-

Sim PE/Plus, Aldec Active-HDL

Xilinx provides technical support for this LogiCORE

™

product when

used as described in the User’s Guide and in the Application Notes.

Xilinx cannot guarantee timing, functionality, or support of product

if implemented in devices not listed above, or if customized beyond

that referenced in the product documentation, or if any changes are

made in sections of design marked as “DO NOT MODIFY”.

1. Re-targeting the PCI core to an unlisted device or package will

void the guarantee of timing. See “Smart-IP Technology - guar-

anteed timing” on page 3 for details.

2. Use -6 for 0-66 MHz operation and -5 for 0-33 MHz operation.

3. See Xilinx website for update on tested design tools.

January 31, 2000 Data Sheet

January 31, 2000

Features (cont.)

• Supported Target functions (PCI Master and Slave)

- Type 0 Conﬁguration Space Header

- Up to 3 Base Address Registers (memory or I/O with

adjustable block size from 16 Bytes to 2 GBytes,

medium decode speed)

- Parity Generation (PAR), Parity Error Detection

(PERR# and SERR#)

- Memory Read, Memory Write, Memory Read

Multiple (MRM), Memory Read Line (MRL), Memory

Write Invalidate (MWI) commands

- I/O Read, I/O Write commands

- Conﬁguration Read, Conﬁguration Write commands

- 64-bit and 32-bit data transfers, burst transfers with

linear address ordering

- Target Abort, Target Retry, Target Disconnect

- Full Command/Status Registers

• Available for conﬁguration and download on the web

- Web-based conﬁguration tool

- Generation of proven design ﬁles

- Instant access to new releases

Applications

• Embedded applications within telecommunication,

networking, and industrial systems

• PCI add-in boards such as graphic cards, video

adapters, LAN adapters and data acquisition boards

• Hot Swap CompactPCI boards

• Other applications that need PCI

General Description

The LogiCORE

™

PCI64 Interfaces are pre-implemented

and fully tested modules for the Xilinx Spartan-II FPGAs.

The pinout for the device and the relative placement of the

internal Conﬁgurable Logic Blocks (CLBs) are pre-deﬁned.

Critical paths are controlled by TimeSpecs and guide ﬁles

to ensure predictable timing. This signiﬁcantly reduces

engineering time required to implement the PCI por tion of

your design. Resources can instead be focused on the

unique back-end logic in the FPGA and on the system le v el

design. As a result, LogiCORE

™

PCI products can mini-

mize your product development time.

Xilinx Spartan-II FPGAs enable designs of fully PCI-compli-

ant systems. The devices meet all required electrical and

timing parameters including AC output drive characteris-

tics, input capacitance speciﬁcations (10pF), 7 ns setup

and 0 ns hold to system clock, and 6 ns system cloc k to out-

put. These devices meet all speciﬁcations f or PCI 3.3 V and

5 V.

The PCI Compliance Checklist has detailed information

about electrical compliance. Other features that enable efﬁ-

cient implementation of a complete PCI system in

Spartan-II includes:

• Block SelectRAM+™ memory: Blocks of on-chip ultra-

fast RAM with synchronous write and dual-port RAM

capabilities. Used in PCI Interfaces to implement FIFO

• Select-RAM™ memory: on-chip ultra-fast RAM with

synchronous write option and dual-port RAM option.

Used in PCI Interfaces to implement FIFO

• Individual output enable for each I/O

• Internal 3-state bus capability

• 8 global low-skew clock or signal distribution networks

• IEEE 1149.1-compatible boundary scan logic support

• Designed for CompactPCI Hot Swap support

The Master and Slave Interface module is carefully opti-

mized for best possible performance and utilization in the

Spartan-II FPGA architecture.

Smart-IP Technology: Guaranteed

Timing

Drawing on the architectural advantages of Xilinx FPGAs,

new Xilinx Smart-IP technology ensures highest perfor-

mance, predictability, repeatability, and ﬂexibility in PCI

designs. The Smar t-IP technology is incor porated in every

LogiCORE PCI core.

Xilinx Smart-IP technology leverages the Xilinx architec-

tural advantages, such as look-up tables (LUTs), distrib-

uted RAM, and segmented routing, as well as ﬂoor

planning information, such as logic mapping and relative

location constraints. This technology provides the best

physical layout, predictability, and performance. Addition-

ally, these predetermined features allow for signiﬁcantly

reduced compile times over competing architectures.

PCI cores made with Smart-IP technology are unique by

maintaining their performance and predictability regardless

of the device size.

To guarantee the critical setup, hold, and min. and max.

clock-to-out timing, the PCI core is delivered with Smart-IP

constraint ﬁles that are unique for a device and package

combination. These constraint ﬁles guide the implementa-

tion tools so that the critical paths always are within PCI

speciﬁcation. Retargeting the PCI core to an unsuppor ted

device will void the guarantee of timing. Contact one of the

Xilinx XPERTs partners for support of unlisted devices and

packages. See the XPERTs section in chapter 7 of the Xil-

inx PCI Data Book for contact information.

Universal PCI Support

Since Spartan-II FPGAs are capable of oper ating either 3.3

V or 5 V PCI environments, the designer can easily build

universal PCI cards. This requires loading one of the bit-

streams at power up. Refer to the

PCI Implementation

Guide

and

Building a Universal PCI Card using Xilinx

FPGAs Application Note

January 31, 2000

Functional Description

The LogiCORE PCI64 Master and Slave Interface is parti-

tioned into ﬁve major blocks and an user application as

shown in Figure 1. Each block is described below.

PCI Conﬁguration Space

This block provides the ﬁrst 64 Bytes of Type 0, version 2.1

Conﬁguration Space Header (CSH) (see Table 1) to sup-

por t software-driven “Plug-and Play” initialization and con-

ﬁguration. This includes infor mation for Command, Status,

and three Base Address Registers (BARs). These BARs

illustrate how to implement memory- or I/O-mapped

address spaces.

Table 1: PCI Conﬁguration Space Header

Each BAR sets the base address for the interface and

allows the system software to determine the addressable

range required by the interf ace. Every BAR designated as a

memory space can be made to represent a 32-bit or a 64-

bit space.

Using a combination of Conﬁgurable Logic Bloc k (CLB) ﬂip-

ﬂops for the read/write registers and CLB look-up tab les f or

the read-only registers results in optimized logic mapping

and placement.

The capability for extending conﬁguration space has been

built into the backend interface. This capability, including

the ability to implement a CapPtr in conﬁguration space,

allows the user to implement functions, such as Advanced

Conﬁguration and Power Interface (ACPI), in the backend

design.

PCI I/O Interface Block

The I/O interface block handles the physical connection to

the PCI bus including all signaling, input and output syn-

chronization, output three-state controls, and all request-

grant handshaking for bus mastering.

Parity Generator/Checker

This block generates/checks even parity across the AD

bus, the CBE lines, PAR and the PAR64 signal. It also

reports data parity errors via PERR- and address parity

errors via SERR-.

Target State Machine

This block controls the PCI interface for Target functions.

The states implemented are a subset of equations deﬁned

in “Appendix B” of the

PCI Local Bus Speciﬁcation

. The

controller is a high-performance state machine using

one-hot (state-per-bit) encoding for maximum perfor-

mance. State-per-bit encoding of the next-state logic func-

tions facilitates a high performance implementation in the

Xilinx FPGA architecture.

Initiator State Machine

This block controls the PCI interface for Initiator functions.

The states implemented are a subset of equations deﬁned

in “Appendix B” of the

PCI Local Bus Speciﬁcation

. The Ini-

tiator Control Logic also uses state-per-bit encoding for

maximum performance.

User Application with Optional Burst

FIFOs

The LogiCORE PCI64 Interface pro vides a simple, general-

purpose interface with a 64-bit data path and latched

address for de-multiplexing the PCI address/data bus. This

user interface allows the rest of the device to be used in a

wide range of 32-bit and 64/bit applications.

Typically, the user application contains burst FIFOs to

increase PCI system performance. An on-chip read/write

FIFO, built from the on-chip synchronous dual-port RAM

(Block SelectRAM+™) a vailab le in Spartan-II FPGAs, sup-

ports data transfers in excess of 66 MHz.

31 16 15 0

Device ID Vendor ID 00h

Status Command 04h

Class Code Rev ID 08h

BIST

Header

Type Latency

Timer

Cache

Line Size

0Ch

Base Address Register 0 (BAR0) 10h

Base Address Register 1 (BAR1) 14h

Base Address Register 2 (BAR2) 18h

Base Address Register 3 (BAR3)

1Ch

Base Address Register 4 (BAR5)

20h

Base Address Register 5 (BAR5)

24h

Cardbus CIS Pointer

28h

Subsystem ID Subsystem Vendor ID 2Ch

Expansion ROM Base Address

30h

Reserved CapPtr 34h

Reserved 38h

Max_Lat Min_Gnt Interrupt

Pin Interrupt

Line 3Ch

Reserved 40h-FFh

Note: Italicized address areas are not implemented in LogiCORE

PCI32 Spartan-II Interface default conﬁguration. These

locations return zero during conﬁguration read accesses.

PCI64 Spartan-II Interface V 3.0

January 31, 2000

Several synthesizable re-usable bridge designs including

commonly used backend functions, such as doorbells and

mailboxes, are provided with the core.

Interface Conﬁguration

The LogiCORE PCI64 Interface can easily be conﬁgured to

ﬁt unique system requirements by using Xilinx web-based

PCI conﬁguration tool or by changing the Ver ilog or VHDL

conﬁguration ﬁle. The following customization options are

supported by the LogiCORE product and described in

product documentation.

• Initiator or target functionality

• Base Address Register conﬁguration (1-3 Registers,

size and mode)

• Conﬁguration Space Header ROM

• Initiator and target state machine (e.g., termination

conditions, transaction types and request/transaction

arbitration)

• Burst functionality

• User Application including FIFO (back-end design)

Supported PCI Commands

Table 2 illustrates the PCI b us commands supported by the

LogiCORE

™

PCI64 Interface. The PCI Compliance Check-

list has more details on suppor ted and unsupported com-

mands.

Burst T ransfer

The PCI bus derives its performance from its ability to sup-

port burst transfers. The performance of any PCI applica-

tion depends largely on the size of the burst transfer. A

FIFO to support PCI burst transfer can efﬁciently be imple-

mented using the Spartan-II on-chip RAM features, both

Distributed and Block SelectRAM+™.

Each Spar tan-II CLB suppor ts four 16x1 RAM blocks. This

corresponds to 64 bits of single-ported RAM or 32 bits of

dual-ported RAM, with simultaneous read/write capability.

Bandwidth

Xilinx LogiCORE PCI64 Interface supports fully compliant

zero wait-state bust operations for both sourcing and

receiving data. This Interface supports a sustained band-

width of up to 264 MBytes/sec. The design can be conﬁg-

ured to take advantage of the ability of the LogiCORE

PCI64 Interface to do very long bursts. Since the FIFO is

not of ﬁxed siz e , b ursts can go on f or as long as the chipset

arbiter will allow. Furthermore, since the FIFOs and DMA

are decoupled from the prov en core, a designer can modify

these functions without affecting the critical PCI timing.

The ﬂexible Xilinx backend, combined with support for

many different PCI features, gives users a solution that

lends itself to being used in many high-performance appli-

cations. Xilinx is able to support different depths of FIFOs

as well as dual port FIFOs, synchronous or asynchronous

FIFOs and multiple FIFOs. The user is not locked into one

DMA engine, hence, a DMA that ﬁts a speciﬁc application

can be designed.

The theoretical maximum bandwidth of a 64-bit, 33 MHz

PCI bus is 264 MBytes/sec. Attaining this maximum band-

width will depend on several factors, including the PCI

design used, PCI chipset, the processor’ s ability to k eep up

with your data stream, the maximum capability of your PCI

design, and other trafﬁc on the PCI bus . Older chipsets and

processors will tend to allow less bandwidth than newer

ones.

No additional wait-states are inserted in response to a wait-

state from another agent on the bus. Either IRDY or TRDY

is kept asserted until the current data phase ends, as

required by the V2.2 PCI Speciﬁcation. See Table 3 for PCI

bus transfer rates for various operations.

Table 3: LogiCORE PCI64 Transfer Rates

Table 2: PCI Bus Commands

CBE [3:0] Command PCI

Master PCI

Slave

0000 Interrupt Acknowledge Yes Yes

0001 Special Cycle Yes Ignore

0010 I/O Read Yes Yes

0011 I/O Write Yes Yes

0100 Reserved Ignore Ignore

0101 Reserved Ignore Ignore

0110 Memory Read Yes Yes

0111 Memory Write Yes Yes

1000 Reserved Ignore Ignore

1001 Reserved Ignore Ignore

1010 Configuration Read Yes Yes

1011 Configuration Write Yes Yes

1100 Memory Read Multiple Yes Yes

1101 Dual Address Cycle No

Ignore

1110 Memory Read Line Yes Yes

1111 Memory Write Invalidate No

Yes

Note:

1. The Initiator can present these commands; however, they either

require additional user-application logic to suppor t them or are not

thoroughly tested.

Zero W ait-State Mode

Operation Transfer Rate

Initiator Write (PCI

←

LogiCORE) 3-1-1-1

Initiator Read (PCI

→

LogiCORE) 4-1-1-1

Target Write (PCI

→

LogiCORE) 5-1-1-1

Target Read (PCI

←

LogiCORE) 6-1-1-1

***Note: Initiator Read and Target Write operations ha v e effectively

the same bandwidth for burst transfer.

January 31, 2000

Timing Speciﬁcation

The Spartan-II FPGA de vices, together with the LogiCORE

PCI64 product enable design of fully compliant PCI sys-

tems. The maximum speed at which your bac k-end is capa-

ble of running can be affected by the size of the design as

well as by the loading of the hot signals coming directly

from the PCI bus . Table 4 shows the key timing parameters

for the LogiCORE PCI64 Interface that must be met for full

PCI compliance.

Veriﬁcation Methods

Xilinx has developed a system-level testbench that allows

simulation of an open PCI environment in which a Logi-

CORE-PCI-based design may be tested by itself or with

other simulatable PCI agents. Included in these agents are

a behavioral host and target, and several plug-in modules,

including a PCI signal recorder and a PCI protocol monitor.

Using these tools, the PCI de v elopers can write microcode-

style test scripts that can be used to verify different bus-

operation scenarios, including those in the PCI Compliance

Checklist.

The Xilinx PCI testbench is a powerful veriﬁcation tool that

is also used as the basis for veriﬁcation of the PCI Logi-

CORE. The PCI LogiCORE is also tested in hardware for

electrical, functional, and timing compliance.

Table 4: 33 MHz Timing Parameters

Parameter Ref. PCI Spec. LogiCORE

PCI32

Spartan-II-5

Min Max Min Max

CLK Cycle Time T

cyc

CLK High Time T

high

CLK Low Time Tl

CLK to Bus Sig-

nals Valid

ICKOF

2626

CLK to REQ# and

GNT# Valid

ICKOF

2626

Tri-state to Active T

CLK to Tri-state T

off

14 14

Bus Signal Setup

to CLK (IOB) T

PSD

Bus Signal Setup

to CLK (CLB) 55

GNT# Setup to

CLK T

PSD

GNT# Setup to

CLK (CLB) T

PSD

Input Hold Time

After CLK (IOB) T

PHD

Input Hold Time

After CLK (CLB) 00

RST# to Tri-state T

rst-off

40 40

Notes:

1. Controlled by TIMESPECS, included in product.

PCI64 Spartan-II Interface V 3.0

January 31, 2000

Ping64 Reference Design

The Xilinx PING64 Application example, delivered in Ver-

ilog and VHDL, has been developed to provide an easy-to-

understand example which demonstr ates man y of the prin-

ciples and techniques required to successfully use a Logi-

CORE PCI64 Interface in a System-on-a-Chip solution.

The PING64 design is also used as a test vehicle for PCI

core veriﬁcation.

Asynchronous PCI FIFO Design

Note

The ﬁrst-in ﬁrst-out memory queue with independent read

and write clocks and backup reference design is available

for use with the LogiCORE PCI64 Interface. It is delivered

in Verilog and VHDL as a drop-in module for the Spar tan-II

FPGAs.

This design suppor ts data widths of 32, 36, 64, or 72 bits

with memory depth of 63 locations implemented in

SelectRAM+. Figure 1 presents a block diagram of the

design. The pci_async_ﬁfo features fully synchronous and

independent clock domains f or the read and write ports and

back-up synchronous to the read clock. The design also

supports full and empty status, along with almost-full and

almost-empty ﬂags and invalid read or write requests are

rejected without affecting the FIFO state.

The pci-async-ﬁfo data sheet lists the features and specif-

ics of the PCI FIFO design.

Device Utilization

The Target/Initiator options require a variable amount of

CLB resources for the PCI64 Interface.

Utilization of the device can vary slightly, depending on the

conﬁguration choices made by the designer. Factors that

can affect the size of the core are:

• Number of Base Address Registers Used: Turning off

any unused BARs will save resources.

• Size of the BARs: Setting the BAR to a smaller size

requires more ﬂip-ﬂops. A smaller address space

requires more ﬂip-ﬂops to decode.

• Latency timer: Disabling the latency timer will save

resources. It must be enabled for bursting.

Recommended Design Experience

The LogiCORE PCI64 Interface is pre-implemented;

thereby allowing engineering focus at the unique back-end

functions of a PCI design. Regardless, PCI is a high-perfor-

mance system that is challenging to implement in any tech-

nology, ASIC or FPGA. Therefore , previous e xperience with

building high-performance, pipelined FPGA designs using

Xilinx implementation software, TIMESPECs, and guide

ﬁles is recommended. The challenge to implement a com-

plete PCI design including back-end functions varies

depending on the conﬁguration and the functionality of your

application. Contact your local Xilinx representative for a

closer revie w and estimation f or your speciﬁc requirements.

PCI Bus

LogiCORE PCI 64/32 Spartan-II Interface

FIFO Controller

Power Management Module

Reference Design

Custom DMA Module

PCI Asynchronous Read FIFO

Reference Design

PCI Asynchronous Write FIFO

Reference Design

x9097

Figure 1: LogiCORE™ PCI Interface Block Diagram