Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 LM5023 AC-DC Quasi-Resonant Current Mode PWM Controller 1 Features 3 Description * * * * * The LM5023 is a quasi-resonant pulse width modulated (PWM) controller which contains all of the features needed to implement a highly efficient offline power supply. The LM5023 uses the transformer auxiliary winding for demagnetization detection to ensure critical conduction mode (CrCM) operation. The LM5023 features a hiccup mode for overcurrent protection with an auto restart to reduce the stress on the power components during an overload. A skipcycle mode reduces power consumption at light loads for energy conservation applications (ENERGY STAR(R), CEPCP, and so forth). The LM5023 also uses the transformer auxiliary winding for output overvoltage protection (OVP); if an OVP fault is detected the LM5023 latches off the controller. 1 * * * * * * * * * * Critical Conduction Mode Peak-Current Mode Control Skip-Cycle Mode for Low-Standby Power Hiccup Mode for Continuous Overload Protection Cycle-by-Cycle Overcurrent Protection Maintains Accuracy Over the Universal AC Line Line-Voltage Feedforward OVP Protection by Sensing the Auxiliary Winding Integrated 0.7-A Peak Gate Driver Direct Opto-Coupler Interface Leading Edge Blanking of Current Sense Signal Maximum Frequency Clamp 130 kHz Programmable Soft-Start Thermal Shutdown 8-Pin VSSOP Package Create a Custom Design using the LM5023 with the WEBENCH Power Designer Device Information(1) PART NUMBER LM5023 PACKAGE VSSOP (8) BODY SIZE (NOM) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications * * * * Universal Input AC-to-DC Notebook Adapters from 10 W to 65 W High-Efficiency Housekeeping and Auxiliary Power Supplies Battery Chargers Consumer Electronics (DVD Players, Set-Top Boxes, DTV, Gaming, Printers) Simplified Schematic VOUT 19 V VAC High Voltage Start-Up Depletion Mode FET 1 QR 8 OUT 7 VCC CS LM5023 2 VSD 3 SS 5 Output Voltage Regulation COMP 4 GND 6 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 5 5 7 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 9 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 18 8 Application and Implementation ........................ 19 8.1 Application Information............................................ 19 8.2 Typical Application .................................................. 19 9 Power Supply Recommendations...................... 29 10 Layout................................................................... 29 10.1 Layout Guidelines ................................................. 29 10.2 Layout Example .................................................... 30 11 Device and Documentation Support ................. 31 11.1 11.2 11.3 11.4 11.5 11.6 Custom Design with WEBENCH Tools................. Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 31 31 31 31 31 31 12 Mechanical, Packaging, and Orderable Information ........................................................... 31 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (January 2014) to Revision E * Page Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision C (August, 2013) to Revision D Page * Added LM5023 Pin Configuration........................................................................................................................................... 3 * Changed FUNCTIONAL BLOCK DIAGRAM. ......................................................................................................................... 9 * Added VCC < VCC(on) the current consumption................................................................................................................. 11 * Changed IQR equation from ROFFSET to R1.......................................................................................................................... 24 * Changed Current Feed Forward resistor value from 1 k to 6.6 k. .................................................................................. 25 2 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 5 Pin Configuration and Functions DGK Package 8-Pin VSSOP Top View QR 1 8 VCC VSD 2 7 OUT SS 3 6 GND COMP 4 5 CS Pin Functions PIN TYPE DESCRIPTION 4 I Control input for the pulse width modulator and skip cycle comparators. COMP pullup is provided by an internal 42-k resistor which may be used to bias an opto-coupler transistor. CS 5 I Current sense input for current-mode control and over-current protection. Current limiting is accomplished using a dedicated current sense comparator. If the CS comparator input exceeds 0.5 V, the OUT pin switches low for cycle-by-cycle current limit. CS is held low for 130 ns after OUT switches high to blank the leading edge current spike. GND 6 G Ground connection return for internal circuits. OUT 7 O High current output to the external MOSFET gate input with source/sink current capability of 0.3 A and 0.7 A respectively. QR 1 I The auxiliary flyback winding of the power transformer is monitored to detect the quasi-resonant operation. The peak-auxiliary voltage is sensed to detect an output overvoltage (OVP) fault and shuts down the controller. SS 3 O An external capacitor and an internal 22-A current source sets the soft-start ramp. VSD 2 O Connect this pin to the gate of the external start-up circuit FET; it disables the start-up FET after VCC is valid. VCC 8 P VCC provides bias to controller and gate drive sections of the LM5023. An external capacitor must be connected from this pin to ground. NAME NO. COMP Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 3 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT 4 mA IQR Negative injection current when the QR pin is being driven below ground VSD Maximum voltage IVSD VSD clamp continuous current VIN Voltage range OUT Gate-drive voltage at DRV IOUT Peak OUT current, source IOUT Peak OUT current sink VCC Bias supply voltage -0.3 16 V TJ Operating junction temperature -40 125 C Tstg Storage temperature -55 150 C (1) (2) -0.3 45 V 500 A 7 V SS, COMP, QR -0.3 CS -0.3 1.25 V -0.3 Self-limiting V 0.3 A 0.7 A Stresses beyond those listed under may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) Charged-device model (CDM), per JEDEC specification JESD22C101 (2) VALUE UNIT 2000 V 1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN MAX VCC Bias supply voltage 8 14 V IVSD VSD Current 2 100 A IQR QR pin current 1 4 mA TJ Junction temperature -40 125 C 4 Submit Documentation Feedback UNIT Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 6.4 Thermal Information LM5023 THERMAL METRIC (1) DGK (VSSOP) UNIT 8 PINS RJA Junction-to-ambient thermal resistance 168.6 C/W RJC(top) Junction-to-case (top) thermal resistance 59.6 C/W RJB Junction-to-board thermal resistance 88.8 C/W JT Junction-to-top characterization parameter 7.1 C/W JB Junction-to-board characterization parameter 87.5 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics Minimum and maximum apply over the junction temperature range of -40 to +125C. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at +25C, and are provided for reference purposes only. Unless otherwise specified, the following conditions apply: VCC = 10 V, FSW = 100 kHz 50% duty cycle, no load on OUT. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BIAS SUPPLY INPUT VCCON Controller enable threshold 12 12.8 13.5 V VCCOFF Minimum operating voltage 7 7.5 8 V VRST Internal logic reset (fault latch) VCC falling < VRST 4.5 5 5.5 V ICCST ICC current while in standby mode COMP = 0.5 V, CS = 0 V, no switching 340 420 A ICCOP Operating supply current COMP = 2.25 V, OUT switching 800 A 0.1 A SHUTDOWN CONTROL (VSD PIN) IVSD OFF Off state leakage current VVSD ON1 ON state pulldown voltage at 10 A After VCCON (IVSD = 10 A) 0.65 V VVSD_ON2 ON state pulldown voltage at 100 A After VCCON (IVSD = 100 A) 0.84 V SKIP CYCLE MODE COMPARATOR VSKIP Skip cycle mode enable threshold VSK-HYS Skip cycle mode hysteresis COMP falling 70 120 170 12 mV mV QR DETECT VOVP Overvoltage comparator threshold 2.85 3 3.17 V TOVP Sample delay for OVP 870 1050 1270 ns VDEM VDEM demagnetization threshold FMAX Maximum frequency 114 130 148 kHz TRST TRESTART 9.4 12 15.7 s 0.35 V PWM COMPARATORS TPPWM COMP to OUT propagation delay COMP set to 2 V, CS stepped 0 to 0.4 V, time to OUT transition low, CLOAD = 0 DMIN Minimum duty cycle COMP = 0 V GCOMP COMP to PWM comparator gain VCOMP-O COMP open circuit voltage VCOMP-H COMP at maximum VCS ICOMP COMP short circuit current RCOMP R pullup 20 ns 0% 0.33 ICOMP = 20 A 4.3 COMP = 0 V 41 4.9 5.8 V 2.25 V -132 A 45 49 k Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 5 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com Electrical Characteristics (continued) Minimum and maximum apply over the junction temperature range of -40 to +125C. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at +25C, and are provided for reference purposes only. Unless otherwise specified, the following conditions apply: VCC = 10 V, FSW = 100 kHz 50% duty cycle, no load on OUT. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 450 500 550 mV CURRENT LIMIT VCS Cycle-by-cycle sense voltage limit threshold TLEB Leading edge blanking time TPCS Current limit to OUT delay RLEB CS blanking sinking impedance GCM Current mirror gain IQR = 2 mA 100 A/A VFF Line-current feedforward IQR = 2 mA 140 mV CS step from 0 to 0.6 V time to onset of OUT transition low, CLOAD = 0 130 ns 22 ns 15 35 HICCUP MODE TOL_10 Over load detection timer IVSD= 10 A 12 ms TOL_100 Over load detection timer IVSD= 100 A 1.2 ms OUTPUT GATE DRIVER VOH OUT high saturated IOUT = 50 mA, VCC-OUT 0.3 1.1 V VOL OUT low saturated IOUT = 100 mA 0.3 1 V IPH Peak OUT source current OUT = VCC/2 0.3 IPL Peak OUT sink current OUT = VCC/2 0.7 A tr Rise time CLOAD = 1 nF 25 ns tf Fall time CLOAD = 1 nF 15 ns A SOFT-START ISS Soft-start current 17 22 30 A THERMAL TSD 6 Thermal shutdown temperature 165 Submit Documentation Feedback C Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 6.6 Typical Characteristics 7.6 14 7.55 13.5 7.5 VCCOFF (V) VCCON(V) 13 12.5 12 7.45 7.4 7.35 7.3 11.5 7.25 7.2 11 -50 -25 0 25 50 75 100 TEMPERATURE (C) -50 125 -25 0 25 50 75 100 TEMPERATURE (C) C001 Figure 2. VCCON vs. Temperature 125 C002 Figure 3. VCCOFF vs. Temperature 5.1 400 390 5.05 380 370 ICCST(A) VRST(V) 5 4.95 4.9 360 350 340 330 320 4.85 310 4.8 300 -50 -25 0 25 50 75 100 TEMPERATURE (C) 125 -50 0 25 50 75 100 TEMPERATURE (C) Figure 4. VRST vs. Temperature 125 C004 Figure 5. ICCST vs. Temperature 800 132 790 131 780 130 FMAX(kHz) ICCOP(A) -25 C003 770 760 129 128 750 127 740 730 126 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 -50 C005 Figure 6. ICCOP vs. Temperature -25 0 25 50 75 100 TEMPERATURE (C) 125 C006 Figure 7. FMAX vs. Temperature Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 7 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com Typical Characteristics (continued) 550 CS THRESHOLD (mV) 540 530 520 510 500 490 480 470 460 450 -50 -25 0 25 50 75 100 TEMPERATURE (C) 125 C007 Figure 8. CS Threshold vs. Temperature 7 Detailed Description 7.1 Overview The LM5023 is a quasi-resonant PWM controller which contains all of the features needed to implement a highly efficient off-line power supply. The LM5023 uses the transformer auxiliary winding for demagnetization detection to ensure quasi-resonant operation (valley-switching) to minimize switching losses. For applications that need to meet the ENERGY STAR low standby power requirements, the LM5023 features an extremely low lq current (346 A) and skip-cycle mode which reduces power consumption at light loads. The LM5023 uses a feedback signal from the output to provide a very accurate output-voltage regulation <1%. To reduce overheating and stress during a sustained overload conditions the LM5023 offers a hiccup mode for over-current protection and provides a current-limit restart timer to disable the outputs and forcing a delayed restart (hiccup mode). For offline start-up, an external depletion mode N-channel MOSFET can be used. This method is recommended for applications where a very low standby power (<50 mW) is required. For application where a low standby power is not as critical, an enhancement mode, N-channel MOSFET can be used. If an OV is detected on the auxiliary winding (QR pin), the device permanently latches off, requiring recycling of power to restart. VCC voltage must be brought lower than VRST to reset the latch. Additional features include line-current feedforward, pulse-by-pulse current limit, and a maximum frequency clamp of 130 kHz. 8 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 7.2 Functional Block Diagram VSD IVSD= 2 VCC RVSD OLDT OLDTS 4 Counter VCC VCCON 12.5-V Rising VCCOFF 7.5-V Falling 8 S Q R Q S Q R Q EN R Q S Q + VRST 5.0 V Thermal Shutdown OVP + D Q VOVP 3 V Time Delay Q Maximum Frequency Clamp EN DEMAG QR 1 tRESTART + VDEMAG 0.35 V IQR/100 Auto Zero Comp S Q R Q 7 OUT 6 GND + 6.6 k: VCS 0.5 V CS 5 OLDT OLDTS Standby LEB S 5V PWM 42 k: OLDTS = + 2R COMP Overload Detection Timer 2x60x10-9 IVSD s R 4 R Sleep Mode Standby + VSKIP 120 mV + SS 22 PA 3 EN Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 9 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com 7.3 Feature Description 7.3.1 Detailed Pin Description 7.3.1.1 QR Pin The QR pin is connected to the auxiliary winding voltage divider and valley-switching delay capacitor which are also connected to GND. The auxiliary winding is monitored to detect quasi-resonant operation. The pin is also used to detect an output OV fault, which results in shutdown of the converter. Connect the capacitor and divider low-side resistor with short traces to the QR and GND pins. Avoid high dV/dt traces close to the QR pin connection and net. 7.3.1.2 VSD Pin The VSD pin is connected to the gate of an external high-voltage start-up MOSFET. The VDS pin controls the gate of the external start-up MOSFET. When the VCC exceeds VCC(on), the VSD pin is pulled low which turns off the start-up MOSFET. Avoid high frequency or high dV/dt traces close to this net. 7.3.1.3 SS Pin The SS pin is connected to a capacitor selected to control the start-up soft-start time. Place a high quality ceramic capacitor with short traces to SS and GND. 7.3.1.4 COMP Pin The COMP pin is the input to the pulse width modulator, and skip cycle comparators. There is an internal pull up resistance of 42-k on the COMP pin. Traces from the opto-coupler to the COMP pin should have minimal loop area. It is recommended to shield the COMP trace with ground planes to minimize noise pick up. If a capacitor connects to COMP and GND use short traces. 7.3.1.5 CS Pin CS is the current sense input for current mode control, and peak current limit. A small ceramic filter capacitor may be placed on CS to GND with short traces, to filter any ringing present during the MOSFET turn on. The current sense resistor current should be returned to the bulk capacitor ground terminal to minimize the primary high current loop area. 7.3.1.6 GND Pin The GND pin is the signal and power reference for the controller. The GND pin should be connected to the VCC capacitor with a short trace, and be kelvin connected to be the ground reference for components connected to the signal pins. 7.3.1.7 OUT Pin The OUT pin is connected to the primary MOSFET typically through a small resistance to limit switching speed of the MOSFET. This pin generates high dV/dt signals and should be routed as far away from the signal pins as possible. 7.3.1.8 VCC Pin The VCC pin must be decoupled to GND with a good quality, low ESR, low ESL ceramic bypass capacitors with short traces to the VCC and GND pins. Additional bulk capacitance may be required to maintain VCC during start-up, but always use a ceramic bypass capacitor as well. 10 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 Feature Description (continued) 7.3.2 Start-Up Referring to Figure 9, when the AC rectified line voltage is applied to the bulk-energy-storage capacitor; the Nchannel depletion mode MOSFET is turned on and supplies the charging current to the VCC capacitor. When the voltage on the VCC pin reaches 12.5-V typical, the PWM controller, soft-start circuit and gate driver are enabled. When the LM5023 is enabled and the OUT drive signal starts switching the flyback MOSFET, energy is being stored and then transferred from the transformer primary to the secondary windings. A bias winding, shown in Figure 9, delivers energy to the VCC capacitor to sustain the voltage on the VCC pin. The voltage supplied from the auxiliary winding should be within the range of 10 V to 14 V (where 16 V is the absolute maximum rating). After reaching the VCCON threshold, the LM5023 VSD open drain output, which is pulled up to VCC during startup, goes low. This applies a negative gate to source voltage on the depletion mode MOSFET turning it off. This disables the high-voltage start-up circuit. The high-voltage start-up circuit can be implemented in either of two ways; the first is shown in Figure 9, which uses an N-channel depletion modle FET, the second is shown in Figure 10, which uses an N-channel enhancement mode FET. The circuit using the depletion mode FET will have the lowest standby power. The standby power consumption of the FET is the voltage across the start-up FET multiplied by the drain-to-source cutoff current with gate negatively biased, this is typically 0.1 A. Standby power of the start-up FET calculation is shown in Equation 1 through Equation 5. VIN 230 VAC (1) VCC 10 V (2) VDC(max) (3) ID(off ) 230 VAC u 2 325 VDC 0.1 PA where * ID(off) is the depletion mode FETs leakage current Pd ID(off) u VDC(max) 0.1PA u 325 VDC (4) 32.5 PW (5) When VCC < VCCON the standby current consumption of the IC = ICC(st), nominally 340 A. High Voltage Start-Up VAC Depletion Mode FET 1 QR 8 VCC OUT 7 LM5023 CVCC CS 2 5 VSD GND 6 Figure 9. Start-Up With a Depletion Mode FET Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 11 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com Feature Description (continued) An alternative start-up circuit employs an enhancement mode FET with pull-up resistors connected from the rectified DC bus to the gate of the FET, Figure 10. After the input AC power is applied, the enhancement mode FET supplies the charging current to the VCC capacitor CVCC. After reaching the VCCON threshold, the LM5023 VSD open drain output, which is pulled up to VCC during start-up, goes low. This grounds the gate of the startup MOSFET, turning it off. The start-up resistors are always in the circuit, therefore the standby power consumed will be higher than if a depletion mode FET were used. VIN 230 VAC (6) VCC 10 V VDC(max) RSTART (7) 230 VAC u 2 UP PRESISTORS 325 VDC (8) 10M: VDC (9) 2 RSTART 2 UP 325 10M: VAC 10.56mW (10) High Voltage Start-Up Enhancement Mode FET 1 QR 8 VCC OUT 7 LM5023 CVCC CS 2 5 VSD GND 6 Figure 10. Start-Up With an Enhancement Mode FET 12 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 Feature Description (continued) 7.3.3 Quasi-Resonant Operation A quasi-resonant controlled flyback converter operates by storing energy in the transformer's primary during the MOSFET's on-time. During the on-time (tON) VIN is applied across the primary of the transformer. The primary current starts out at zero and ramps towards a peak value (IPEAK). When the peak-primary current reaches the feedback compensation error voltage the PWM comparator resets the output drive, turning off the MOSFET. Due to the phasing of the transformer, the output diode is reverse-biased during the MOSFET on-time. During the MOSFET's off time the output diode is forward biased and the stored energy in the transformer primary inductor is transferred to the output. The voltage seen on the secondary winding is VOUT plus the output diode's forward voltage drop, VF. The current in the secondary winding linearly decreases from IPEAK x Np/Ns to zero, refer to Figure 12. When the current in the secondary reaches zero, the transformer is demagnetized, and there is an open circuit on the secondary, and with the primary MOSFET also turned off, there is an open on the primary. A resonant circuit is formed between the transformers primary inductance and the MOSFET output capacitance. The resonant frequency is calculated by Equation 11. 1 FRES 2 u S Lp u COSS (11) During the resonant period the drain voltage of the MOSFET will ring down towards ground, refer to Figure 11. When the drain voltage is at its minimum the flyback MOSFET is turned back on. The point where the voltage is at its minimum is calculated by Equation 12. td S u Lp u COSS (12) Transformer is Demagnetized Figure 11. The Flyback Drain Voltage Waveform Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 13 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com Feature Description (continued) Transformer demagnetization is detected by sensing the transformers auxiliary winding. When the transformer is demagnetized the auxiliary winding voltage follows the drain of the MOSFET and changes from VOUT x NAUX/Ns to -VIN x NAUX/Np. Internal to the LM5203 QR pin is a comparator with a 0.35-V reference. As the auxiliarywinding voltage falls below 0.35 V, the voltage is sensed and the comparator sets the PWM flip-flop turning on the flyback MOSFET. Figure 12 shows the QR converter typical waveforms; the auxiliary winding voltage, and primary and secondary current waveforms. It is possible to adjust the delay on the auxiliary winding with a resistor and external capacitor to ensures that the MOSFET switches when its drain voltage is at its minimum. Refer to the schematic in Figure 16 and the section on Valley Switching for details. The benefits of QR operation are reduced EMI, and reduced turn-on switching losses. VAUX = VOUT x NAUX/NS 0.35 V 0V VAUX = -VIN x NAUX/Np The Auxiliary Winding voltage TOVP The Peak Primary Current The Peak Secondary Current tON tOFF tdly Tp Figure 12. QR Converter Typical Waveforms 14 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 Feature Description (continued) 7.3.4 Quasi-Resonant Operating Frequency When the primary-side flyback MOSFET turns on, the current ramps up until the peak-primary current exceeds the feedback compensation error voltage. When this occurs the PWM comparator resets the output drive, turning off the MOSFET. The current ramps up with a slope shown in Equation 13. VIN di Lp dt (13) The tON time of the switch is calculated by Equation 14. Lp tON u IPK VIN (14) When the primary-side flyback MOSFET is turned off, the energy stored in the primary inductance is transfer to the secondary inductance, the off time to transfer all of the energy is shown in Equation 15. N u Lp tOFF IPK u SP VO Vf where * NSP = NS/NP (15) The total switching period is shown in Equation 15. tp tON tOFF tDLY (16) The resonant circuit created by the transformer primary inductance and the MOSFETs switch node capacitance is the tDLY time, refer to Figure 12. tDLY POUT S u Lp u CSWN (17) 1 u Lp u IPK 2 u FREQ u K 2 (18) Equation 19 represents the relationship of switching frequency, LP, and NPS. 1 FREQ 2 VIN VO Vf u NPS * 2 u POUT Lp tDLY u u V Vf N u K VIN2 O PS (c) (19) The QR flyback converter does not operate at a fixed frequency. The frequency varies with the output load, input line voltage, or a combination of the two. In order to keep LM5023 frequency below the EMI starting limit of 150 kHz per CISPR--22, the LM5023 has an internal timer which prevents the output drive from restarting within 7.69 s of the previous driver output (OUT) low-to-high transition. This timer clamps the maximum switching frequency at 130 kHz (typical). Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 15 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com Feature Description (continued) 7.3.5 PWM Comparator The PWM comparator compares the current sense signal with the loop error voltage from the COMP pin. The COMP pin voltage is reduced by a fixed 0.75-V offset and then attenuated by a 3:1 resistor divider. The PWM comparator input offset voltage is designed such that less than 0.75 V at the COMP pin will result in a zero duty cycle at the controller output. 7.3.6 Soft-Start The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thereby reducing start-up stresses and current surges. At power on, after the VCC reaches the VCCON threshold, an internal 22-A current source charges an external capacitor connected to the SS pin. The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and the duty cycle of the output pulses. 7.3.7 Gate Driver The LM5023 driver (OUT) was designed to drive the gate of an N-channel MOSFET and is capable of sourcing a peak current of 0.4 A and sinking 0.7 A. 7.3.7.1 Skip-Cycle Operation During light-load conditions, the efficiency of the switching power supply typically drops as the losses associated with switching and operating bias currents of the converter become a significant percentage of the power delivered to the load. The largest component of the power loss is the switching loss associated with the gate driver and external MOSFET gate charge and the switched-node capacitance energy. Each PWM cycle consumes a finite amount of energy as the MOSFET is turned on and then turned off. These switching losses are proportional to the frequency of operation. To improve the light-load efficiency the LM5023 enters a skip-cycle mode during light-load conditions. As the output load is decreased, the COMP pin voltage is reduced by the voltage feedback loop to reduce the flyback converters peak-primary current. Referring to the Functional Block Diagram, the PWM comparator input tracks the COMP pin voltage through a 0.75-V level-shift circuit and a 3:1 resistor divider. As the COMP pin voltage falls, the input to the PWM comparator falls proportionately. When the PWM comparator input falls to 120 mV, the skip cycle comparator detects the light-load condition and disables output pulses from the controller. The LM5023 also reduces all internal bias currents, while in skip mode, to further reduce quiescent power. The controller continues to skip switching cycles until the power supply output falls and the COMP pin voltage increases to demand more output current. The number of cycles skipped will depend on the load and the response time of the frequency voltage loop compensation network. Eventually the COMP voltage will increase when the voltage loop requires more current to sustain the regulated output voltage. When the PWM comparator input exceeds 155 mV (30-mV hysteresis), normal fixed-frequency switching resumes. Typical light-load operation power-supply designs will produce a short burst of output pulses followed by a long skip-cycle interval (no drive pulses). The result is a large reduction in the average input power. 16 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 Feature Description (continued) Figure 13. LM5023 Modulation Curve 7.3.8 Current Limit and Current Sense The LM5023 provides a cycle-by-cycle over current protection feature. Current limit is triggered by an internal current sense comparator with a threshold of 500 mV. If the CS pin voltage plus the current limit feedforward signal voltage exceeds 500 mV, the MOSFET drive signal (OUT) will be terminated. An RC filter, located near the LM5023 CS pin is recommended to attenuate the noise coupled from the power FET's gate to source switching. The CS pin capacitance is discharged at the end of each PWM cycle by an internal switch. The discharge switch remains on for an additional 130 ns for leading edge blanking (LEB). LEB prevents the LM5023 current sense comparator from being falsely triggered due to the noise generated by the switch currents initial spike. The LM5023 current sense comparator is very fast and may respond to short-duration noise pulses. Layout considerations are critical for the current-sense filter and sense resistor. The capacitor associated with the CS filter must be placed very close to the device and connected directly to the pins of the device (CS and GND). If a current sense transformer is used, both leads of the transformer secondary should be routed to the sense resistor, which should also be located close to the device. If a current sense resistor located in the power FET's source is used for current sense, a low inductance resistor is required. In this case, all of the noisesensitive low-current grounds should be connected in common near the device and then a single connection should be made. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 17 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com 7.4 Device Functional Modes According to the input voltage, the VCC voltage, and the output load conditions, the device can operate in different modes: * At start-up, when VCC is less than the VCCON threshold, the VSD open drain output is pulled up to VCC which turns on the depletion mode MOSFET. The depletion mode MOSFET charges the VCC capacitor. * When VCC exceeds the VCCON threshold, the VSC open drain output is pulled to ground which turns off the depletion mode MOSFET, disabling the high-voltage start-up circuit as long as VCC > VCC(off). * At power on, when VCC reaches the VCCON threshold, the device starts switching to deliver power to the converter output. On initial power up soft-start is initiated by a 22-A current source that charges a capacitor on the SS pin. The SS pin limits the voltage on the COMP pin voltage and the duty cycle of the OUT pulses. * Soft-start ends based on the voltage required on the COMP pin to deliver the required power to achieve voltage regulation. Depending on the load condition, the converter operates in normal or skip-cycle mode. - Normal mode is the full-load to light-load condition where the controller output is enabled every cycle. - Skip-cycle mode occurs at light to no-load where the controller output is disabled based on the COMP pin voltage. The ICC current is reduced to ICCST when the output is disabled in skip cycle mode. * The device operation can be stopped by the events listed below: - If VCC drops below VCCOFF threshold, the device stops switching and the start-up sequence repeats. - If a fault is detected the driver is latched off until VCC reduces to VCCOFF, and the start-up sequence is initiated. - If an overload condition exceeds the overload timer duration, the output is turned off until VCC reduces to VCCOFF, and the start-up sequence is initiated. 18 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM5023 is a quasi-resonant PWM controller optimized for isolated flyback converters with secondary-side regulation. The controller can be used with single or multiple output converters. Applications include notebook adapters and a variety of consumer and industrial applications. The skip-cycle operation, reduced device bias current and control for high-voltage start-up circuit facilitates achieving low-standby input power. 8.2 Typical Application This AC-to-DC adapter, 19.2-V, 65-W design example describes the design of a 65-W off-line flyback converter providing 19.2 V at 3.43-A maximum load and operating from a universal AC input. The design uses the LM5023 AC-to-DC quasi-resonant primary-side controller in a DCM type flyback converter and achieves 88% full load efficiency. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 19 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 FH1 PCB Rule i PCB Rule i www.ti.com PCB Rule i D1 DF06SA-E3/77 3 56000001009 R7 1.00Meg VIN C2 0.01uF 4 C1 0.01uF 2 2 3 - + 1 0.70 mH R1 499k ~ R9 1.00Meg 770W-X2/10 PCB Rule i ~ L1 1 GND i PCB Rule D6 4 J1 C5 68F i PCB Rule C18 R4 470pF 20.0k C6 68F R5 20.0k SS5P10-M3/86A D3 R2 499k 3 T2 D2 MURS360T3 2 C15 TP4 2200pF C7 120F C8 10F 7 8,9 2 1 C17 120F 750313417 SGND GND R3 10k ,4 2 100 SGND 1N4148W-7-F C4 22F C9 0.1F - D4 R8 Q1 BSP135 L6433 19V @ 3.43A J2 6 VIN GND + SS5P10-M3/86A 1 5 i PCB Rule GND TP3 10 11,12 i PCB Rule TP5 1 R10 14.7k GND 3 GND 1 R14 10.0 D5 MMSZ5245B-7-F 15V 2 R15 2.00Meg R12 10.0k C10 QR 2 C12 0.01F VCC R13 4.42k 8 C11 160pF 2 1 TP6 4.7F U1 GND R16 7 VSD OUT 3 SS GND 6 4 COMP CS 5 Q2 IPP65R190CFD 1 4.75 3 GND R18 150k GND R17 499 LM5023MMX-2/NOPB C16 1000pF C13 100pF 0.5W R19 0.15 R20 GND GND 0 GND C14 0.01F U2 GND 4 R21 10.2k 1 3 2 PS2811-1-M-A U3 LMV431BIMF/NOPB GND SGND Figure 14. LM5023 Typical Application 20 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 8.2.1 Design Requirements Table 1 lists the design requirements for the LM5023. Table 1. LM5023 Performance Specifications PARAMETER TEST CONDITION MIN TYP MAX UNITS 90 115/230 264 VAC INPUT CHARACTERISTICS VIN Input voltage VIN No load input power VIN = 230 V 30 mW OUTPUT CHARACTERISTICS VOUT Output voltage VIN = 115 V, IOUT = 3.43 A VOUT Line regulation VIN = min to max, IOUT = max VOUT Load regulation VIN = nom, IOUT = no load to max load VOUT Output voltage ripple VIN = nom, IOUT = max load IOUT Output current VOVP Output OVP M Load step response 19.0 19.2 19.4 V 1.0% 1.0% 100 mVPP 3.43 24 IOUT = 0.343 A to 3.09 A, 3.09 A to 0.343 A 18.7 VIN = 115/230 V, IOUT = 3.43 A 88% A V 19.6 V SYSTEMS CHARACTERISTICS Switching frequency Full load 130 kHz 8.2.2 Detailed Design Procedure 8.2.2.1 Custom Design with WEBENCH Tools Click here to create a custom design using the LM5023 device with the WEBENCH(R) Power Designer. 1. Start by entering your VIN, VOUT and IOUT requirements. 2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments. 3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability. 4. In most cases, you will also be able to: - Run electrical simulations to see important waveforms and circuit performance, - Run thermal simulations to understand the thermal performance of your board, - Export your customized schematic and layout into popular CAD formats, - Print PDF reports for the design, and share your design with colleagues. 5. Get more information about WEBENCH tools at www.ti.com/webench. 8.2.2.2 Line Current-Limit Feedforward In a peak-current mode controlled when the power supply is in an overload, the peak current (measured across the current sense resistor VCS) is compared to a voltage reference for overload protection. If the peak current exceeds the reference the LM5023 controller will turn off the primary-side flyback MOSFET on a cycle-by-cycle basis. However, the primary switch can't be turned off instantly, as there are several unavoidable delays. The first delay is caused by the LEB circuit which provides leading-edge blanking. The second delay is caused by the propagation delay between the detecting point of VCS and the actual turn off of the power MOSFET. The total delay time (tPROP) refer to Figure 15, includes the current limit comparator, the logic, the gate driver, and the power MOSFET turning off. The propagation delay causes the peak-primary current to overshoot, the overshoot increase the maximum peak current beyond the calculated value. The peak-current overshoot increase as the AC line voltage increase because of the increase in the slope of the primary current, shown in Equation 20. VIN di Lp tPROP (20) Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 21 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com This increase in the peak-input-current overshoot causes a wide variation of overpower limit in a flyback converter. In Figure 5, the overpower limit increases with the input line voltage because of IPK(max) increase shown in Equation 21 through Equation 23. IPK(max) PIN POUT POUT u 2 Lp u FREQ u K VIN u tPROP Lp (21) 1 u IPK(max) u Lp u FREQ 2 PIN K (22) (23) VIN Lp 'IHL High Line 'ILL IPK/RSENSE Low Line tPROP_HL Gate Drive tPROP_LL Figure 15. Line-Current Feedforward To improve the overpower limit accuracy over the full universal input line, the LM5023 integrates line current limit feedforward. Line current limit feedforward improve the overpower limit by summing a current proportional to the input rectified line into the current sense resistor (RSENSE), refer to Figure 16. The current proportional to the input line biases up the CS pin, this turns off the flyback MOSFET earlier at high input line. This feature compensates for the propagation delays creating a overpower protection that is nearly constant over the universal input line. To implement line current limit feedforward, the first step is to calculate the QR switching frequency at low line and then at high line when the power supply is operating in current limit. For this example: * Lp = 400 H * RSENSE = 0.15 * VDC(min) = 127 V * VDC(max) = 325 V * TPROP = 160 ns * VCS = 0.5 V * NAUX = 10.9 22 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com * * SNVS961E - APRIL 2013 - REVISED JANUARY 2016 NPS = NP/NS = 6 tDLY = 580 ns 1 FREQ _ LL * VCS * 1 u Lp u V (c) RSENSE (c) DC(min) VOUT 1 t Vf u NPS DLY 1/4 1 FREQ _ LL 1 * 0.5 V * 0.15 : u 400 PH u 127 V (c) (c) 1 580ns 19 V 0.7 V u 6 1/4 (24) 49.6kHz (25) 1 FREQ _ HL * VCS * 1 u Lp u V (c) RSENSE (c) DC(max) VOUT 1 t Vf u NPS DLY 1/4 1 FREQ _ HL 1 * 0.5 V * 0.15 : u 400 PH u 325 V (c) (c) 1 580ns 19 V 0.7 V u 6 1/4 (26) 62.3kHz (27) The next step is to calculate the uncompensated output power at the minimum and maximum input line voltage while in current limit. 2 VCS * 1 u Lp u u FREQ _ LL u K 2 (c) RSENSE POUT _ LL (28) 2 1 0.5 * u 400 PH u u 49.6kHz u 0.86 2 (c) 0.15 POUT _ LL 94.9 W (29) 2 VCS * 1 u Lp u u FREQ _ HL u K 2 (c) RSENSE POUT _ HL (30) 2 1 0.5 * u 400 PH u u 62.3kHz u 0.86 119.1W 2 (c) 0.15 POUT _ HL (31) Step three is to calculate the peak current at high line so it does not deliver more power than while it is operating at low line (94.9 W). One thing that complicates the line current limit feedforward calculation is that with quasiresonant operation the switching frequency changes with line and load. We have two equations and two unknowns, the peak-primary current and the QR frequency. NS NSP NP (32) FREQ _ COMP 4 4 u t DLY (c) 2 u Lp u POUT _ LL u VOUT Vf NSP u VDC(max) K u VDC(max)2 u VOUT Vf 2 2 * 2 u Lp u VOUT Vf NSP u VDC(max) u VDC(max) u VOUT Vf POUT _ LL K u Lp 1/4 2 (33) FREQ _ COMP 4 4 u 580ns (c) 2 u 400 PH u 94.9 W u 19 V 0.7 V 0.167 u 325 V 0.86 u 325 V 2 u 19 V 0.7 V 2 2 * 2 u 400 PH u 19 V 0.7 V 0.167 u 325 V u 325 V u 19 V 0.7 V 94.9 W 0.86 u 400 PH 1/4 =77.41kHz 2 (34) Step four is to calculate the peak current. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 23 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com 2 u POUT _ LL IL(max) _ LL K u Lp u FREQ _ COMP 2 u 94.9 W 0.86 u 400 PH u 77.41kHz IL(max) _ LL (35) 2.67 A (36) VCS _ CL RSENSE u IL(max) _ CL VDC(max) * u tPROP Lp 1/4 (c) VCS _ CL 325 V * 0.15 : u 2.67 A u 160ns (c) 400 PH 1/4 (37) 0.38 V (38) For the power supply to go into pulse-by-pulse current limit the voltage across the current sense resistor must be 0.5 V. VCS _ OFFSET : VCS VCS _ CL (39) VCS_OFFSET is the required voltage offset that must be injected across the current sense resistor, RSENSE. VCS _ OFFSET : VCS VCS _ CL 0.5 V 0.38 V 0.12 V (40) After calculating the required offset voltage, use Equation 41 and Equation 42 to calculate the required current feedforward. While the main flyback switch is on, Q1, the voltage on the auxiliary winding will be negative and proportional to the rectified line. VDC VAUX NAUX (41) IQR VAUX R1 (42) IQR should be chosen in the range of 1 mA to 4 mA. The demagnetization circuit impedance should be calculated to limit the maximum current flowing through QR pin to less than 4 mA. ROFFSET = 6.6 k + REXTERNAL where * NAUX is the number of turns on the Flyback primary (Np) divided by the number of turns on the transformer Auxiliary (NAUX) winding. (43) The 6.6-k resistance is internal to the LM5023. The current mirror in the QR pin input has a gain of 100; this will offset the voltage on the current sense pin shown in Equation 44. IQR VCS(offset) u 6.6k: REXTERNAL 100 (44) Set IQR = 1.75 mA VDC(max) R1 NAUX IQR ROFFSET ROFFSET REXTERNAL 325 V 10.9 1.75 mA 17.0k: (45) VOFFSET 0.12 V u 100 u 100 IQR 1.75mA RINTERNAL REXTERNAL ROFFSET 6.6k: 6857 : 6857 : 6.6k: (46) (47) 257 : (48) No external resistor is required based on the applications describe above, so a 499- resistor and 100-pF capacitor are installed in the CS pin input as a noise filter. 24 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 VCC + VD 0V -VDC/NAUX VAUX NAUX R1 Np Ns R2 Cd IQR 1 LM5023 8 VAUX QR VCC Q1 OUT 7 CS 6.6 k: REXTERNAL 5 IQR/100 GND VCSOFFSET RSENSE 6 Figure 16. Current Feedforward 8.2.2.2.1 Overvoltage Protection Output overvoltage protection is implemented with the LM5023 by monitoring the QR pin during the time when the main flyback MOSFET is off and the energy stored in the transformer primary is being transferred to the secondary. There is a delay prior to sampling the QR pin during the MOSFETs off time, TOVP. There are two reasons for the delay, the first is to blank the voltage spike which is a result of the transformers leakage inductance. The second is to improve the accuracy of the output voltage sensing, referring to the transformer auxiliary winding voltage shown in Figure 12. It is clear there is a down slope in the voltage which represents the decreasing VF of the output rectifier and resistance voltage drop (IS x RS) as the secondary current decreases to zero, so by delaying the sampling of the QR voltage a more accurate representation of the output voltage is achieved. Connected to the QR pin is a comparator with a 3.0-V reference. The transformers auxiliary voltage is proportional to VOUT by the transformers turns ratio: N VAUX VO VF u AUX NS (49) To set the OVP, a voltage divider is connected to the transformers auxiliary winding, refer to Figure 15. In Line Current-Limit Feedforward equations were developed to improve the power limit. Resistor R1 was calculated for line current limit feedforward; to implement OVP we now need to calculate R2. R2 VOVP VAUX _ OVP u R1 R2 (50) R1 R2 3.0 V u VAUX _ OVP 3 V (51) Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 25 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com When an OVP fault has been detected, the LM5023 OUT driver is latched-off. VCC will discharge to VCCMIN and the VSD pin will be asserted high, allowing the depletion mode FET to turn-on and charge up the VCC capacitor to VCCON. The VSD pin will be toggled on-off-on to maintain VCC to the controller. The only way to clear the fault is to removed the input power and allow the controllers VCC voltage to drop below VRST, 5.0 V. 8.2.2.3 Valley Switching For QR operation the flyback MOSFET is turned on with the minimum drain voltage. The delay on the auxiliary winding can be adjusted with an external resistor and capacitor to improve valley switching. The delay-time, tDLY, must equal half of the natural oscillation in Equation 52 S u Lp u COSS tDLYQR (52) 2 By substituting Equation 53. tDLYQR RFF u Cd (53) We can calculate the RC time constant to achieve the minimum drain voltage when the LM5023 turns on the Flyback MOSFET. S * 2 u LpUSED u COSS (c) 1/4 Cd : (54) RFF The LM5023 QR pin's capacitance is approximately 20 pF, so CdUSED = Cd -20 pF R1u R2 RFF : R1 R2 (55) R1 and R2 were previously calculated to set the line current limit feedforward and overvoltage protection. 8.2.2.4 Hiccup Mode Hiccup Mode is a method to prevent the power supply from over-heating during and extended overload condition. In an overload fault, the current limit comparator turns off the driver output on pulse-by-pulse basis. This starts the over load detection timer, after the over load detection timer (OLDT) times out, the current limit comparator is rechecked, if the power supply is still in an overload condition, the OUT drive is latched-off and VCC is allowed to drop to VCCOFF (7.5 V). When VCC reaches VCCOFF, the VSD open drain output is disabled allowing the depletion mode start-up FET to turn-on, charging up the VCC capacitor to VCCON (12.5 V). When VCC reaches VCCON, the VSD output goes low turning-off the depletion mode FET. The VCC capacitor is discharged from VCCON to VCCOFF at a rate proportional to the VCC capacitor and the ICCST current (340-A typical). The charging and discharging of the VCC capacitor is repeated four times (refer to Figure 17) use Equation 56 to figure the total Hiccup time. tHICCUP tCHARGE u 4 tDISCHARGE u 4 (56) After allowing VCC to charge and discharge four times, the LM5023 goes through an auto restart sequence, enabling the LM5023 soft-start and driver output. It is important to set the over load detection timer long enough so that under low input-line and full-load conditions that the power supply will have enough time to start-up. The over load detection timer can be set with the resister in series with the VSD pin VCC 10 V IVSD 10 PA RVSD 1M: 2 u 60nA 2 u 60nA OVER _ LOAD _ DETECTION _ TIMER 12ms IVSD 10 PA VSD), refer to Figure 9. (57) (58) Normally it is recommended that RVSD > 1 M, if a lower value is used then the standby power will be higher. Assuming the depletion mode FET charges the VCC capacitor with 2 mA, VCC capacitor is 10 F. VCCON VCCOFF 12.5 V 7.5 V u CVCC u 10 PF 25ms tCHARGE ICHARGE 2mA 26 Submit Documentation Feedback (59) Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 tDISCHARGE tHICCUP VCCON VCCOFF u CVCC ICCST 25ms u 4 145ms u 4 12.5 V 7.5 V u 10 PF 145ms 340 PA (60) 680ms (61) The depletion FET charging current into the VCC cap 2 mA The current consumption of the LM5023 while the OCP flag is set ICCST = 346 PA VCCON 12.5 V VCCAUX 10 V VCCOFF 7.5 V VCCOFF OLDTS OUT VSD SS 25 ms 145 ms Hiccup Mode Figure 17. Hiccup Mode Timing Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 27 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com 8.2.3 Application Curves 0.90 115Vac 230Vac 0.88 Efficiency 0.86 0.84 0.82 0.80 0.78 0.000 0.857 1.713 2.570 3.426 IOUT C001 CH1: OUT, 10 V/div CH3: VCC, 5 V/div Figure 19. 115-V Start-Up, 0.1-A Load Figure 18. LM5023 EVM Efficiency CH1: OUT, 10 V/div CH3: VCC, 5 V/div CH2: SS, 2 V/div CH4: VOUT, 5 V/div CH1: OUT, 10 V/div CH3: VCC, 5 V/div Figure 20. 115-V Start-Up, 3.43-A Load CH1: OUT, 10 V/div CH3: VCC, 5 V/div CH2: SS, 2 V/div CH4: VOUT, 5 V/div Figure 22. 230-V Start-Up, 3.43-A Load 28 CH2: SS, 2 V/div CH4: VOUT, 5 V/div CH2: SS, 2 V/div CH4: VOUT, 5 V/div Figure 21. 230-V Start-Up, 0.1-A Load CH1: OUT, 10 V/div CH2: CS, 200 mV/div CH4: VDS, 100 V/div Figure 23. QR Waveforms VIN 115 VAC, IOUT 3.43 A Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 CH1: OUT, 10 V/div CH2: CS, 200 mV/div CH4: VDS, 100 V/div Figure 24. QR Waveforms VIN 230 VAC, IOUT 3.43 A 9 Power Supply Recommendations The LM5023 device is intended for AC-to-DC adapters and power supplies with input voltage range of 85 VAC(rms) to 265 VAC(rms) using the flyback topology. It can also be used in other applications and convertor topologies with different input voltages. Be sure that all voltages and currents are within the recommended operating conditions and absolute maximum ratings of the device. 10 Layout 10.1 Layout Guidelines TI recommends all high-current loops be kept as short as possible. Keep all high-current and high-frequency traces away from other traces in the design. If necessary, high-frequency and high-current traces should be perpendicular to signal traces, not parallel to them. It is good practice to shield signal traces with ground traces to help reduce noise pick up. The ground reference for components connected to the signal pins should be a kelvin connection to the VCC bypass capacitor and GND pin. Always consider appropriate clearances between highvoltage nets and low-voltage nets. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 29 LM5023 SNVS961E - APRIL 2013 - REVISED JANUARY 2016 www.ti.com 10.2 Layout Example To Optocoupler C CVCC R VCC QR OUT VSD G R R RG LM5023 GND SS CS D COMP Primary Winding CCS C RCS R S R C PGND To Bulk Capacitor+ AUX Winding R BULK AUX To Bulk Capacitor Figure 25. LM5023 Layout Example 30 Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961E - APRIL 2013 - REVISED JANUARY 2016 11 Device and Documentation Support 11.1 Custom Design with WEBENCH Tools Click here to create a custom design using the LM5023 device with the WEBENCH(R) Power Designer. 1. Start by entering your VIN, VOUT and IOUT requirements. 2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments. 3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability. 4. In most cases, you will also be able to: - Run electrical simulations to see important waveforms and circuit performance, - Run thermal simulations to understand the thermal performance of your board, - Export your customized schematic and layout into popular CAD formats, - Print PDF reports for the design, and share your design with colleagues. 5. Get more information about WEBENCH tools at www.ti.com/webench. 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. ENERGY STAR is a registered trademark of EPA. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2013-2016, Texas Instruments Incorporated Product Folder Links: LM5023 31 PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM5023MM-2/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SK9B LM5023MMX-2/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SK9B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5023MM-2/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5023MMX-2/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5023MM-2/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM5023MMX-2/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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