TPS75201M-EP www.ti.com SGLS325A - JANUARY 2006 - REVISED JULY 2013 Fast-Transient-Response 2-A Low-Dropout Voltage Regulator with Reset Check for Samples: TPS75201M-EP FEATURES 1 * 2 * * * * * * (1) Controlled Baseline - One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) 2-A Low-Dropout (LDO) Voltage Regulator Open-Drain Power-On Reset With 100-ms Delay Ultralow 75-A Typ Quiescent Current Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over the specified temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. * * * * Fast Transient Response 2% Tolerance Over Specified Conditions for Fixed-Output Versions 20-Pin TSSOP (PWP) PowerPADTM Package Thermal Shutdown Protection PWP PACKAGE (TOP VIEW) GND/HEATSINK NC IN IN EN RESET FB/SENSE OUTPUT OUTPUT GND/HEATSINK 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GND/HEATSINK NC NC GND NC NC NC NC NC GND/HEATSINK NC - No internal connection DESCRIPTION The TPS75201M-EP is a low dropout regulator with an integrated power-on reset (RESET) function. This device is capable of supplying 2 A of output current with a dropout of 210 mV. Quiescent current is 75 A at full load and drops down to 1 A when the device is disabled. The TPS75201M-EP is designed to have fast transient response for larger load current changes. Because the PMOS device operates like a low-value resistor, the dropout voltage is very low (typically 210 mV at an output current of 2 A) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (75 A typ over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled when the enable (EN) input is connected to a low-level input voltage. This low-dropout (LDO) device also features a sleep mode; applying a TTL high signal to EN shuts down the regulator, reducing the quiescent current to 1 A at TJ = 25C. The RESET (SVS, POR, or power-on reset) output of the TPS75201M-EP initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS75201M-EP monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., overload condition) of its regulated voltage. The TPS75201M-EP is adjustable (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006-2013, Texas Instruments Incorporated TPS75201M-EP SGLS325A - JANUARY 2006 - REVISED JULY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. LOAD TRANSIENT RESPONSE VO - Change in Output Voltage - mV DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 300 IO = 2 A 200 IO = 1.5 A 50 0 -50 -100 I O - Output Current - A VDO - Dropout Voltage - mV 250 IL = 2 A CL = 100 F (Tantalum) VO = 3.3 V 150 100 IO = 0.5 A 50 -150 2 1 0 0 0 -40 10 60 110 1 2 3 4 5 6 t - Time - ms 7 8 9 10 160 TJ - Junction Temperature - C ORDERING INFORMATION (1) (1) (2) TJ OUTPUT VOLTAGE (TYP) -55C to 125C Adjustable 1.5 V to 5 V PACKAGE (2) TSSOP - PWP ORDERABLE PART NUMBER Tape and reel TPS75201MPWPREP The TPS75201M-EP is programmable using an external resistor divider (see Application Information). Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. VI 3 RESET IN 4 SENSE IN OUT 0.22 F 5 EN OUT 6 RESET Output 7 8 VO 9 + GND CO 47 F 17 See application information section for capacitor selection details. Figure 1. Typical Application Configuration (for Fixed-Output Options) 2 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP TPS75201M-EP www.ti.com SGLS325A - JANUARY 2006 - REVISED JULY 2013 FUNCTIONAL BLOCK DIAGRAM IN EN RESET _ + OUT + _ 100-ms Delay (for RESET) R1 Vref = 1.1834 V FB R2 GND External to the Device PIN FUNCTIONS PIN NAME EN NO. I/O DESCRIPTION 5 I Enable FB/SENSE 7 I Feedback input voltage for adjustable device (sense input for fixed-voltage option) GND 17 Regulator ground 1, 10, 11, 20 Ground/heat sink GND/HEATSINK IN 3, 4 NC 2, 12, 13, 14, 15, 16, 18, 19 OUTPUT RESET I Input voltage No connection 8, 9 O Regulated output voltage 6 O Reset Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP 3 TPS75201M-EP SGLS325A - JANUARY 2006 - REVISED JULY 2013 www.ti.com RESET TIMING DIAGRAM VI Vres (see Note A) Vres t VO VIT + (see Note B) Threshold Voltage VIT - (see Note B) VIT + (see Note B) Less Than 5% of the Output Voltage VIT - (see Note B) t RESET Output 100-ms Delay 100-ms Delay Output Undefined Output Undefined t A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT - Trip voltage typically is 5% lower than the output voltage (95% VO) VIT- to VIT+ is the hysteresis voltage. ABSOLUTE MAXIMUM RATINGS over operating junction temperature range (unless otherwise noted) (1) MIN VI Input voltage range (2) Voltage range at EN MAX -0.3 6 V -0.3 16.5 V 16.5 V Maximum RESET voltage Peak output current VO Internally limited Output voltage (OUTPUT, FB) V 5.5 Continuous total power dissipation UNIT V See Dissipation Rating Table TJ Operating virtual junction temperature range -55 125 Tstg Storage temperature range -65 150 C 2 kV ESD rating, Human-Body Model (1) (2) C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE - FREE-AIR TEMPERATURES PACKAGE PWP (1) (1) 4 AIR FLOW (CFM) TA < 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING 0 2.9 W 23.5 mW/C 1.9 W 1.5 W 300 4.3 W 34.6 mW/C 2.8 W 2.2 W This parameter is measured with the recommended copper heat- sink pattern on a one-layer PCB, 5-in x 5-in PCB, 1-oz copper, 2-in x 2-in coverage (4 in2). Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP TPS75201M-EP www.ti.com SGLS325A - JANUARY 2006 - REVISED JULY 2013 DISSIPATION RATING TABLE - FREE-AIR TEMPERATURES (continued) PACKAGE PWP (2) (2) AIR FLOW (CFM) TA < 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING 3 3w 23.6 mW/C 1.9 W 1.5 W 300 7.2 W 57.9 mW/C 4.6 W 3.8 W This parameter is measured with the recommended copper heat-sink pattern on an eight-layer PCB, 1.5-in x 2-in PCB, 1-oz copper with layers 1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in2), and layers 3 and 6 at 100% coverage (6 in2). For more information, refer to TI technical brief SLMA002. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN MAX VI Input voltage (1) 2.7 5.5 V VO Output voltage range 1.5 5 V IO Output current 0 2.0 A TJ Operating virtual junction temperature -55 125 C (1) UNIT To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP 5 TPS75201M-EP SGLS325A - JANUARY 2006 - REVISED JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range (TJ = -55C to 125C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, mm Co = 47 F (unless otherwise noted) PARAMETER Output voltage (1) (2) TEST CONDITIONS 1.5 V VO 5 V Adjustable voltage Quiescent current (GND current) (1) MIN TJ = 25C (1) (3) VO + 1 V < VI 5 V 1.02VO 75 125 TJ = 25C 0.01 0.1 Load regulation (2) Output noise voltage BW = 300 Hz to 50 kHz, VO = 1.5 V, CO = 100 F Output current limit VO = 0 V TJ = 25C FB input current FB = 1.5 V 1 2 60 Minimum input voltage for valid RESET IO(RESET) = 300 A, V(RESET) 0.8 V Trip threshold voltage VO decreasing Hysteresis voltage Measured at VO Output low voltage VI = 2.7 V, IO(RESET) = 1 mA Leakage current V(RESET) = 5 V 1 92 A V dB 1.3 V 98 0.5 0.15 RESET time-out delay A V 0.7 Power-supply ripple rejection (3) A C -1 Low-level enable input voltage (1) (2) (3) 4.5 10 f = 100 Hz, CO = 100 F, TJ = 25C, IO = 2 A, (1) %/V Vrms 1 High-level enable input voltage A 60 150 EN = VI V mV TJ = 25C Standby current UNIT 1 3.3 Thermal shutdown junction temperature Reset MAX VO 0.98VO TJ = 25C (2) Output voltage line regulation (VO/VO) TYP %VO 0.4 V 1 A 100 ms Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum IN voltage is 5 V. IO = 1 mA to 2 A If VO 1.8 V, Vimin = 2.7 V, Vimax = 5 V: V ( Vimax - 2.7 V ) O Line regulation (mV) = (% / V) 1000 100 If VO 2.5 V, Vimin = VO + 1 V, Vimax = 5 V: Line regulation (mV) = (% / V) ( - V +1V V eV O e i max O )uu 1000 100 ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range (TJ = -40C to 125C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, mm Co = 47 F (unless otherwise noted) PARAMETER Input current (EN) TEST CONDITIONS MIN EN = VI -1 EN = 0 V -1 High-level EN input voltage TYP 0 6 A 1 A V 0.7 IO = 2 A, VI = 3.2 V, TJ = 25C IO = 2 A, VI = 3.2 V Submit Documentation Feedback UNIT 1 2 Low-level EN input voltage Dropout voltage (3.3-V output) MAX 210 400 V mV Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP TPS75201M-EP www.ti.com SGLS325A - JANUARY 2006 - REVISED JULY 2013 TYPICAL CHARACTERISTICS spacer Table of Graphs FIGURE VO Zo VDO Output voltage Figure 2 and Figure 3 vs Junction temperature Figure 4 and Figure 5 Ground current vs Junction temperature Figure 6 Power-supply ripple rejection vs Frequency Figure 7 Output spectral noise density vs Frequency Figure 8 Output impedance vs Frequency Figure 9 vs Input voltage Figure 10 vs Junction temperature Figure 11 Dropout voltage Input voltage (min) VO vs Output current vs Output voltage Figure 12 Line transient response Figure 13 and Figure 16 Load transient response Figure 14 and Figure 16 Output voltage vs Time (startup) Figure 17 Equivalent series resistance (ESR) vs Output current Figure 19 and Figure 20 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 3.305 1.503 VI = 2.7 V TJ = 25C VI = 4.3 V TJ = 25C 1.502 3.303 VO - Output Voltage - V VO - Output Voltage - V VO VO 3.301 3.299 3.297 1.501 1.5 1.499 1.498 3.295 0 500 1000 1500 2000 1.497 0 IO - Output Current - mA Figure 2. 500 1000 1500 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP 2000 IO - Output Current - mA Figure 3. 7 TPS75201M-EP SGLS325A - JANUARY 2006 - REVISED JULY 2013 www.ti.com OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 3.37 1.53 3.35 1.52 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE VO - Output Voltage - V VO - Output Voltage - V 1 mA 3.33 1 mA 3.31 3.29 2A 3.27 1.51 1.50 1.49 1.48 3.25 3.23 -50 0 50 100 TJ - Junction Temperature - C Figure 4. 1.47 -40 150 GROUND CURRENT vs JUNCTION TEMPERATURE Power Supply Ripple Rejection - dB 75 70 65 PSRR 60 55 50 -40 10 60 110 160 90 VI = 4.3 V CO = 100 F IO = 1 mA TJ = 25C 80 60 50 40 VI = 4.3 V CO = 100 F IO = 2 A TJ = 25C 30 20 10 0 10 TJ - Junction Temperature - C Figure 6. 8 160 100 VI = 5 V IO = 2 A 80 Ground Current - A 10 60 110 TJ - Junction Temperature - C Figure 5. POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY 90 85 2A Submit Documentation Feedback 100 1k 10k 100k 1M 10M f - Frequency - Hz Figure 7. Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP TPS75201M-EP www.ti.com SGLS325A - JANUARY 2006 - REVISED JULY 2013 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 101 2 VI = 4.3 V VO = 3.3 V CO = 100 F TJ = 25C 1.6 CO = 100 F IO = 1 mA Zo - Output Impedance - Vn - Voltage Noise - nV/ Hz 1.8 OUTPUT IMPEDANCE vs FREQUENCY 1.4 1.2 IO = 2 A 1 0.8 0.6 1 10-1 CO = 100 F IO = 2 A 0.4 0.2 IO = 1 mA 0 10 100 1k f - Frequency - Hz Figure 8. 10k 10-2 10 50k DROPOUT VOLTAGE vs INPUT VOLTAGE 100 100k 1k 10k f - Frequency - Hz Figure 9. 1M 10M DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 350 300 IO = 2 A 250 TJ = 125C VDO - Dropout Voltage - mV VDO - Dropout Voltage - mV 300 250 TJ = 25C 200 150 TJ = -40C 100 IO = 2 A 200 IO = 1.5 A 150 100 IO = 0.5 A 50 50 0 2.5 3 3.5 4 VI - Input Voltage - V Figure 10. 4.5 5 0 -40 10 60 110 160 TJ - Junction Temperature - C Figure 11. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP 9 TPS75201M-EP SGLS325A - JANUARY 2006 - REVISED JULY 2013 www.ti.com INPUT VOLTAGE (MIN) vs OUTPUT VOLTAGE LINE TRANSIENT RESPONSE VO - Change in Output Voltage - mV 4 TA = 25C TA = 125C IO = 2 A CO = 100 F VO = 1.5 V TA = -40C 2.7 2 1.5 1.75 2 3 2.25 2.5 2.75 VO - Output Voltage - V Figure 12. 3.25 3.5 0 4 3 0 0.1 VO - Change in Output Voltage - mV VO - Change in Output Voltage - mV IL = 2 A CL = 100 F (Tantalum) VO = 1.5 V 50 0.2 0.3 0.4 0.5 0.6 0.7 t - Time - ms Figure 13. 0.8 0.9 1 LINE TRANSIENT RESPONSE 0 -50 IO = 2 A CO = 100 F VO = 3.3 V dv dt 1V s 100 0 -100 VI - Input Voltage - V -100 I O - Output Current - A 1V s 100 LOAD TRANSIENT RESPONSE -150 2 1 5.3 4.3 0 0 10 dv dt -100 3 VI - Input Voltage - V VI - Input Voltage (Min) - V IO = 2 A 1 2 3 4 5 6 t - Time - ms Figure 14. 7 8 9 10 0 0.1 Submit Documentation Feedback 0.2 0.3 0.4 0.5 0.6 0.7 t - Time - ms Figure 15. 0.8 0.9 1 Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP TPS75201M-EP www.ti.com SGLS325A - JANUARY 2006 - REVISED JULY 2013 OUTPUT VOLTAGE vs TIME (STARTUP) VO - Output Voltage - V VO - Change in Output Voltage - mV LOAD TRANSIENT RESPONSE IO = 2 A CO = 100 F (Tantalum) VO = 3.3 V 50 0 -50 Enable Voltage - V I O - Output Current - A -100 -150 2 1 VI = 4.3 V TJ = 25C 3.3 0 4.3 0 0 0 1 2 3 4 5 6 t - Time - ms Figure 16. 7 8 9 TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT 1 - 0.1 ESR 0.05 Region of Instability 0.01 1 Region of Stability 0.1 - Region of Stability VO = 3.3 V CO = 47 F VI = 4.3 V TJ = 25C - Equivalent Series Resistance 1 - Equivalent Series Resistance 0.8 10 VO = 3.3 V CO = 100 F VI = 4.3 V TJ = 25C Region of Instability 0.01 0 0.5 1 1.5 2 0 0.5 1 1.5 2 IO - Output Current - A Figure 20. IO - Output Current - A Figure 19. (1) 0.4 0.6 t - Time - ms Figure 17. TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT 10 ESR 0.2 0 10 Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP 11 TPS75201M-EP SGLS325A - JANUARY 2006 - REVISED JULY 2013 www.ti.com APPLICATION INFORMATION The TPS75201M-EP is an adjustable regulator (from 1.5 V to 5 V). MINIMUM LOAD REQUIREMENTS The TPS75201M-EP is stable, even at no load; no minimum load is required for operation. PIN FUNCTIONS Enable (EN) The EN input enables or shuts down the device. If EN is a logic high, the device is in shutdown mode. When EN goes to logic low, the device is enabled. Reset (RESET) The RESET terminal is an open-drain, active-low output that indicates the status of VO. When VO reaches 95% of the regulated voltage, RESET goes to a low-impedance state after a 100-ms delay. RESET goes to a highimpedance state when VO is below 95% of the regulated voltage. The open-drain output of RESET requires a pullup resistor. Sense (SENSE) The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network, and noise pickup feeds through to the regulator output. It is essential to route the SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between SENSE and VO to filter noise is not recommended because it may cause the regulator to oscillate. Feedback (FB) FB is an input used for the adjustable-output options and must be connected to an external feedback resistor divider. The FB connection should be as short as possible. It is essential to route it in such a way to minimize/avoid noise pickup. Adding RC networks between FB and VO to filter noise is not recommended because it may cause the regulator to oscillate. Ground/Heat Sink (GND/HEATSINK) All GND/HEATSINK terminals are connected directly to the mount pad for thermal-enhanced operation. These terminals could be connected to GND or left floating. Input Capacitor For a typical application, an input bypass capacitor (0.22 F-1 F) is recommended for device stability. This capacitor should be as close to the input pins as possible. For fast transient condition, where droop at the input of the LDO may occur due to high in-rush current, it is recommended to place a larger capacitor at the input as well. The size of this capacitor is dependant on the output current and response time of the main power supply, as well as the distance to the load (LDO). Output Capacitor As with most LDO regulators, the TPS75201M-EP requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 47 F, and the ESR must be between 100 m and 10 . Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described in this section. Larger capacitors provide a wider range of stability and better load transient response. This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the user's application. When necessary to achieve low height requirements along with high output current and/or high load capacitance, several higher ESR capacitors can be used in parallel to meet these guidelines. 12 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP TPS75201M-EP www.ti.com SGLS325A - JANUARY 2006 - REVISED JULY 2013 ESR and Transient Response LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors are used to support the load current while the LDO amplifier is responding. In most applications, one capacitor is used to support both functions. Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any capacitor therefore can be drawn as shown in Figure 21. RESR LESL C Figure 21. ESR and ESL In most cases, the effect of inductive impedance ESL can be neglected. Therefore, the following application focuses mainly on the parasitic resistance ESR. Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage. IO LDO + VESR RESR - VI RLOAD VO CO Figure 22. LDO Output Stage With Parasitic Resistances ESR and ESL In steady state (dc state condition), the load current is supplied by the LDO (solid arrow), and the voltage across the capacitor is the same as the output voltage [V(CO) = VO]. This means no current is flowing into the CO branch. If IO suddenly increases (transient condition), the following occurs: * The LDO is not able to supply the sudden current need due to its response time (t1 in Figure 24). Therefore, capacitor CO provides the current for the new load condition (dashed arrow). CO now acts like a battery with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at RESR. This voltage is shown as VESR in Figure 23. * When CO is conducting current to the load, initial voltage at the load is VO = V(CO) - VESR. Due to the discharge of CO, the output voltage VO drops continuously until the response time, t1, of the LDO is reached and the LDO resumes supplying the load. From this point, the output voltage starts rising again until it reaches the regulated voltage. This period is shown as t2 in Figure 24. Figure 23 also shows the impact of different ESRs on the output voltage. The left brackets show different levels of ESRs, where number 1 displays the lowest and number 3 displays the highest ESR. From the previous paragraphs, the following conclusions can be drawn: * The higher the ESR, the larger the droop at the beginning of load transient. * The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the LDO response period. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP 13 TPS75201M-EP SGLS325A - JANUARY 2006 - REVISED JULY 2013 www.ti.com Conclusion To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the minimum output voltage requirement. IO VO 1 2 ESR 1 3 ESR 2 ESR 3 t1 t2 Figure 23. Correlation of Different ESRs and Their Influence to Regulation of VO at Load Step From Low-to-High Output Current Programming the Adjustable LDO Regulator The output voltage of the TPS75201M-EP adjustable regulator is programmed using an external resistor divider (see Figure 24). The output voltage is calculated using: R1 o ae VO = Vref c 1 + / e R2 o (1) Where: Vref = 1.1834 V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 40-A divider current. Lower-value resistors can be used, but offer no inherent advantage and waste more power. Higher values should be avoided, as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 k to set the divider current at 40 A and then calculate R1 using: ae V o R1 = c O - 1/ R2 V e ref o 14 (2) Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP TPS75201M-EP www.ti.com SGLS325A - JANUARY 2006 - REVISED JULY 2013 OUTPUT VOLTAGE PROGRAMMING GUIDE VI 0.22 F RESET Output RESET IN 250 k 2 V EN OUT VO 0.7 V R1 FB/SENSE GND CO OUTPUT VOLTAGE R1 R2 UNIT 2.5 V 33.2 30.1 k 3.3 V 53.6 30.1 k 3.6 V 61.9 30.1 k NOTE: To reduce noise and prevent oscillation, R1 and R2 must be as close as possible to the FB/SENSE terminal. R2 Figure 24. Adjustable LDO Regulator Programming REGULATOR PROTECTION The TPS75201M-EP PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS75201M-EP also features internal current limiting and thermal protection. During normal operation, the TPS75201M-EP limits output current to approximately 3.3 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130C (typ), regulator operation resumes. POWER DISSIPATION AND JUNCTION TEMPERATURE Specified regulator operation is assured to a junction temperature of 125C; the maximum junction temperature should be restricted to 125C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum power dissipation limit is determined by using Equation 3: T max - TA PD(max) = J RqJA (3) Where: TJmax is the maximum allowable junction temperature. RJA is the thermal resistance junction-to-ambient for the package, i.e., 34.6C/W for the 20-terminal PWP with no airflow (see Dissipation Rating Table). TA is the ambient temperature. The regulator dissipation is calculated using: PD = (VI - VO ) IO (4) Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP 15 TPS75201M-EP SGLS325A - JANUARY 2006 - REVISED JULY 2013 www.ti.com THERMAL INFORMATION THERMALLY-ENHANCED TSSOP-20 (PWP - PowerPADTM) The thermally-enhanced PWP package is based on the 20-pin TSSOP, but includes a thermal pad [see Figure 25(c)] to provide an effective thermal contact between the IC and the PWB. Traditionally, surface mount and power have been mutually-exclusive terms. A variety of scaled-down TO220type packages have leads formed as gull wings to make them applicable for surface-mount applications. These packages, however, suffer from several shortcomings - they do not address the very low-profile requirements (<2 mm) of many of today's advanced systems, and they do not offer a pin-count high enough to accommodate increasing integration. Conversely, traditional low-power surface-mount packages require power dissipation derating that severely limits the usable range of many high-performance analog circuits. The PWP package (thermally-enhanced TSSOP) combines fine-pitch surface-mount technology, with thermal performance comparable to much larger power packages. The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that remove heat from the component. The thermal pad is formed using a lead-frame design (patent pending) and manufacturing technique to provide the user with direct connection to the heat-generating IC. When this pad is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the ultra-thin, fine-pitch, surface-mount package can be reliably achieved. DIE (a) Side View Thermal Pad DIE (b) End View (c) Bottom View Figure 25. Views of Thermally-Enhanced PWP Package Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal considerations in the PWB design. For example, simply adding a localized copper plane (heat-sink surface), which is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air [reference Figure 27(a), 8 cm2 of copper heat sink and natural convection]. Increasing the heat-sink size increases the power-dissipation range for the component. The power-dissipation limit can be further improved by adding airflow to a PWB/IC assembly (see Figure 26 and Figure 27). The line drawn at 0.3 cm2 in Figure 26 and Figure 27 indicates performance at the minimum recommended heat-sink size (see Figure 29). The thermal pad is connected directly to the substrate of the IC, which for the TPS75201MPWPREP is a secondary electrical connection to device ground. The heat-sink surface that is added to the PWP can be a ground plane or left electrically isolated. In TO220-type surface-mount packages, the thermal connection also is the primary electrical connection for a given terminal, which is not always ground. The PWP package provides up to 16 independent leads that can be used as inputs and outputs (Note: leads 1, 10, 11, and 20 are connected internally to the thermal pad and the IC substrate). 16 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP TPS75201M-EP www.ti.com SGLS325A - JANUARY 2006 - REVISED JULY 2013 THERMAL RESISTANCE vs COPPER HEAT-SINK AREA 150 Natural Convection R JA - Thermal Resistance - C/W 125 50 ft/min 100 ft/min 100 150 ft/min 200 ft/min 75 50 250 ft/min 300 ft/min 25 0 0.3 1 2 3 4 5 6 7 8 Copper Heat-Sink Area - cm2 Figure 26. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP 17 TPS75201M-EP SGLS325A - JANUARY 2006 - REVISED JULY 2013 www.ti.com 3.5 3.5 TA = 55C 300 ft/min 3 PD - Power Dissipation Limit - W PD - Power Dissipation Limit - W TA = 25C 150 ft/min 2.5 2 Natural Convection 1.5 1 0.5 0 3 300 ft/min 2.5 2 150 ft/min 1.5 Natural Convection 1 0.5 0 0.3 2 4 0 8 6 Copper Heat-Sink Size - cm2 0 0.3 2 4 6 8 Copper Heat-Sink Size - cm2 (a) (b) 3.5 TA = 105C PD - Power Dissipation Limit - W 3 2.5 2 1.5 150 ft/min 300 ft/min 1 Natural Convection 0.5 0 0 0.3 2 4 Copper Heat-Sink Size - 6 8 cm2 (c) Figure 27. Power Ratings of PWP Package at TA = 25C, 55C, and 105C Figure 28 is an example of a thermally-enhanced PWB layout for use with the new PWP package. This board configuration was used in the thermal experiments that generated the power ratings shown in Figure 26 and Figure 27. As discussed earlier, copper has been added on the PWB to conduct heat away from the device. RJA for this assembly is shown in Figure 26 as a function of heat-sink area. A family of curves is included to show the effect of airflow introduced into the system. 18 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP TPS75201M-EP www.ti.com SGLS325A - JANUARY 2006 - REVISED JULY 2013 Heat-Sink Area 1-oz Copper Board thickness Board size Board material Copper trace/heat sink Exposed pad mounting 62 mil 3.2 in x 3.2 in FR4 1 oz 63/67 tin/lead solder Figure 28. PWB Layout (Including Copper Heat-Sink Area) for Thermally-Enhanced PWP Package From Figure 26, RJA for a PWB assembly can be determined and used to calculate the maximum powerdissipation limit for the component/PWB assembly, with the equation: T max - TA PD(max) = J RqJA(system) (5) Where: TJmax is the maximum specified junction temperature (150C absolute maximum limit, 125C recommended operating limit) and TA is the ambient temperature. PD(max) should then be applied to the internal power dissipated by the TPS75201M-EP regulator. The equation for calculating total internal power dissipation of the TPS75201M-EP is: PD(total) = (VI - VO ) IO + VI IQ (6) Since the quiescent current of the TPS75201M-EP is very low, the second term is negligible, further simplifying the equation to: PD(total) = (VI - VO ) IO (7) For the case where TA = 55C, airflow = 200 ft /min, copper heat-sink area = 4 cm2, the maximum powerdissipation limit can be calculated. First, from Figure 26, the system RJA is 50C/W, therefore, the maximum power-dissipation limit is: T max - TA 125C - 55C = = 1.4W PD(max) = J RqJA(system) 50C / W (8) If the system implements a TPS75201M-EP regulator, where VI = 5 V and IO = 800 mA, the internal power dissipation is: PD(total) = (VI - VO ) IO = (5 - 3.3 ) 0.8 = 1.36 W (9) Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the calculated limit. When it does, one of two corrective actions should be made - raising the power-dissipation limit by increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by reducing the input voltage or the load current. In either case, the previous calculations should be repeated with the new system parameters. Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP 19 TPS75201M-EP SGLS325A - JANUARY 2006 - REVISED JULY 2013 www.ti.com MOUNTING INFORMATION The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted. Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The data included in Figure 26 and Figure 27 is for soldered connections with voiding between 20% and 50%. The thermal analysis shows no significant difference resulting from the variation in voiding percentage. Figure 29 shows the solder-mask land pattern for the PWP package. The minimum recommended heat-sink area also is shown. This is simply a copper plane under the body extent of the package, including metal routed under terminals 1, 10, 11, and 20. Minimum Recommended Heat-Sink Area Location of Exposed Thermal Pad on PWP Package Figure 29. PWP Package Land Pattern 20 Submit Documentation Feedback Copyright (c) 2006-2013, Texas Instruments Incorporated Product Folder Links :TPS75201M-EP PACKAGE OPTION ADDENDUM www.ti.com 31-May-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS75201MPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 75201EP V62/03635-11XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 75201EP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS75201MPWPREP Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 20 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS75201MPWPREP HTSSOP PWP 20 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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