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Device Highlights
Flexible Programmable Logic
• As low as 14 µA standby current
• 0.18 µm, six layer metal CMOS process
• 1.8 V VCC, 1.8/2.5/3.3 V drive capable I/O
• Up to 4,002 dedicated flip-flops
• Up to 55.3 K embedded SRAM bits
• Up to 310 I/O
• Up to 335 user available pins
• Up to 320 K system gates
• IEEE 1149.1 boundary scan testing compliant
Embedded Dual Port SRAM
• Up to twenty-four 2,304 bit dual port high
performance SRAM blocks
• RAM/ROM/FIFO wizard for automatic
configuration
• Configurable and cascadable aspect ratio
Programmable I/O
• High performance I/O cell
• Programmable slew rate control
• Programmable I/O standards:
LVTTL, LVCMOS, LVCMOS18, PCI, GTL+,
SSTL2, and SSTL3
Independent I/O banks capable of supporting
multiple standards in one device
I/O register configurations: Input, Output,
Output Enable (OE)
Advanced Clock Network
• Multiple dedicated low skew clock networks
• High drive input-only networks
• Quadrant-based segmentable clock networks
• User programmable Phase Locked Loops (PLL)
Embedded Computational Units
(ECUs)
Hardwired DSP building blocks with integrated
Multiply, Add, and Accumulate functions.
Security Features
The QuickLogic products come with secure
ViaLink® technology that protects intellectual
property from design theft and reverse engineering.
No external configuration memory needed;
instant-on at power-up.
Figure 1: Eclipse II Block Diagram
Embedded RAM BlocksPLL PLL
Fabric
Embeded Computational Units
Embedded RAM BlocksPLL PLL
Ultra-Low Power FPGA Combining Performance, Density, and
Embedded RAM
Eclipse II Family Data Sheet
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Eclipse II Family Data Sheet Rev. R
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QuickWorks® Design Software
The QuickWorks package provides the most complete ESP and FPGA software solution from design entry to
logic synthesis, to place and route, to power calculation, and simulation. The package provides a solution for
designers who use third-party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic, and other third-
party tools for design entry, synthesis, or simulation.
Process Data
Eclipse II is fabricated on a 0.18 μ, six layer metal CMOS process. The core voltage is 1.8 V and the I/Os are
up to 3.3 V drive/tolerant. The Eclipse II product line is available in commercial, industrial, and military
temperature grades.
Table 1: Eclipse II Product Family Members
QL8025 QL8050 QL8150 QL8250 QL8325
Max Gates 47,052 63,840 188,946 248,160 320,640
Logic Array 16 x 8 16 x 16 32 x 20 40 x 24 48 x 32
Logic Cells 128 256 640 960 1,536
Max Flip-Flops 532 884 1,709 2,670 4,002
Max I/O 92 124 165 250 310
RAM Modules 4 4 16 20 24
RAM Bits 9,216 9,216 36,864 46,100 55,300
PLLs - - - 4 4
ECUs - - - 10 12
Packages
VQFP 100 100 - - -
CTBGA (0.5 mm) -101 - - -
TQFP 144 144 144 - -
TFBGA (0.8 mm) 196 196 196 - -
TFBGA (0.5 mm) - - 196 - -
PQFP - - 208 208 208
LFBGA (0.8 mm) - - 280 280 280
PBGA (1.0 mm) - - - 484 484
Table 2: Max I/O per Device/Package Combination
Device 100 VQFP 101 CTBGA
(0.5 mm) 144 TQFP 196 TFBGA
(0.8 mm)
196 TFBGA
(0.5 mm) 208 PQFP 280 LFBGA 484 PBGA
QL8025 62 -92 92 - - -
QL8050 62 72 100 124 - - -
QL8150 - - 100 124 148 143 165 -
QL8250 - - - - - 115 163 250
QL8325 - - - - - 115 163 310
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Eclipse II Family Data Sheet Rev. R
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Programmable Logic Architectural Overview
The Eclipse II logic cell structure is presented in Figure 2. This architectural feature addresses today's register-
intensive designs.
The Eclipse II logic cell structure presented in Figure 2 is a dual register, multiplexer-based logic cell. It is
designed for wide fan-in and multiple, simultaneous output functions. Both registers share CLK, SET, and
RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be
loaded from the NZ output or directly from a dedicated input.
NOTE: The input PP is not an “input” in the classical sense. It is a static input to the logic cell and selects
which path (NZ or PS) is used as an input to the Q2Z register. All other inputs are dynamic and can
be connected to multiple routing channels.
The complete logic cell consists of two six-input AND gates, four two-input AND gates, seven two-to-one
multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30
(including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six
outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell
accommodates many user functions with a single level of logic delay while other architectures require two or
more levels of delay.
Table 3: Performance Standards
Function Description Slowest Speed Grade Fastest Speed Grade
Multiplexer 16:1 2.8 ns 2.4 ns
Parity Tree 24 3.4 ns 2.9 ns
36 4.6 ns 3.9 ns
Counter 16 bit 275 MHz 328 MHz
32 bit 250 MHz 300 MHz
FIFO
128 x 32 197 MHz 235 MHz
128 x 64 188 MHz 266 MHz
256 x 16 208 MHz 248 MHz
Clock-to-Out 4 ns 3.3 ns
System clock 200 MHz 300 MHz
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Eclipse II Family Data Sheet Rev. R
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Figure 2: Eclipse II Logic Cell
RAM Modules
The Eclipse II Product Family includes up to 24 dual-port 2,304-bit RAM modules for implementing RAM,
ROM, and FIFO functions. Each module is user-configurable into two different block organizations and can be
cascaded horizontally to increase their effective width, or vertically to increase their effective depth as shown
in Figure 4.
Figure 3: 2,304-bit RAM Module
The number of RAM modules varies from 4 to 24 blocks for a total of 9.2 K to 55.3 K bits of RAM. Using
the two “mode” pins, designers can configure each module into 128 x 18 and 256 x 9. The blocks are also
easily cascadable to increase their effective width and/or depth (see Figure 4).
QS
A1
A2
A3
A4
A5
A6
OS
OP
B1
B2
C1
C2
MS
D1
E1
N
P
E2
D2
N
S
F1
F3
F5
F6
F2
F4
PS
PP
MP
AZ
OZ
QZ
N
Z
FZ
Q2Z
QC
QR
MODE[1:0]
WA[7:0]
WD[17:0]
WE
WCLK
A
SYNCRD
RA[7:0]
RD[17:0]
RE
RCLK
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Eclipse II Family Data Sheet Rev. R
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Figure 4: Cascaded RAM Modules
The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ
and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE
ports support synchronous operation. Each port has 18 data lines and 8 address lines, allowing word lengths
of up to 18 bits and address spaces of up to 256 words. Depending on the mode selected, however, some
higher order data or address lines may not be used.
The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts
as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for
asynchronous READ operation (ASYNCRD input high).
Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by
connecting corresponding address lines together and dividing the words between modules.
A similar technique can be used to create depths greater than 256 words. In this case address signals higher
than the MSB are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs
are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.
The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with
data from an external PROM (typically for ROM functions).
Embedded Computational Unit (ECU)
Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively—
these functions require high logic cell usage while garnering only moderate performance results.
The Eclipse II architecture allows for functionality above and beyond that achievable using programmable logic
devices. By embedding a dynamically reconfigurable computational unit, the Eclipse II device can address
various arithmetic functions efficiently. This approach offers greater performance and utilization than
traditional programmable logic implementations. The embedded block is implemented at the transistor level
as shown in Figure 5.
WDATA
RDATA
RDATA
WADDR
WDATA
RADDR
RAM
Module
(2,304 bits)
RAM
Module
(2,304 bits)
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Eclipse II Family Data Sheet Rev. R
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Figure 5: ECU Block Diagram
The Eclipse II ECU blocks (Table 4) are placed next to the SRAM circuitry for efficient memory/instruction
fetch and addressing for DSP algorithmic implementations.
Up to twelve 8-bit MAC functions can be implemented per cycle for a total of 1 billion MACs/s when clocked
at 100 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic.
The modes for the ECU block are dynamically re-programmable through the programmable logic.
Table 4: Eclipse II ECU Blocks
Device ECUs
QL8325 12
QL8250 10
QL8150 0
QL8050 0
QL8025 0
A[0:15]
B[0:15]
SIGN2
SIGN1
CIN
S1
S2
S3 A
B
C
D
3-4
decoder
8-bit
Multiplier
16-bit
Adder 17-bit
Register
2-1
mux
2-1
mux
3-1
mux
Q[16:0]
CLK
RESET
DQ
00
01
10
A[7:0]
A[15:8]
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Eclipse II Family Data Sheet Rev. R
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NOTE: Timing numbers in Table 5 represent -8 Worst Case Commercial conditions.
Phase Locked Loop (PLL) Information
Instead of requiring extra components, designers simply need to instantiate one of the pre-configured models
(described in this section). The QuickLogic built-in PLLs support a wider range of frequencies than many other
PLLs. These PLLs also have the ability to support different ranges of frequency multiplications or divisions,
driving the device at a faster or slower rate than the incoming clock frequency. When PLLs are cascaded, the
clock signal must be routed off-chip through the PLLPAD_OUT pin prior to routing into another PLL; internal
routing cannot be used for cascading PLLs.
Figure 6 illustrates a QuickLogic PLL.
Figure 6: PLL Block Diagram
Table 5: ECU Mode Select Criteria
Instruction Operation ECU Performancea, -8 WCC
a. tPD, tSU and tCO do not include routing paths in/out of the ECU block.
S1 S2 S3 tPD tSU tCO
0 0 0 Multiply 6.6 ns max
0 0 1 Multiply-Add 8.8 ns max
0 1 0 Accumulateb
b. Internal feedback path in ECU restricts max clk frequency to 238 MHz.
3.9 ns min 1.2 ns max
0 1 1 Add 3.1 ns max
1 0 0 Multiply (registered)c
c. B [15:0] set to zero.
9.6 ns min 1.2 ns max
1 0 1 Multiply- Add (registered) 9.6 ns min 1.2 ns max
1 1 0 Multiply - Accumulate 9.6 ns min 1.2 ns max
1 1 1 Add (registered) 3.9 ns min 1.2 ns max
vco
Filter
FIN
FOUT
+
-
1st Quadrant
2nd Quadrant
3rd Quadrant
4th Quadrant
Clock
Tree
Frequency Divide
Frequency Multiply
1
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_
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2
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_
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4
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_
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4
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_
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2
.
_
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1
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.
_
PLL Bypass
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Eclipse II Family Data Sheet Rev. R
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Fin represents a very stable high-frequency input clock and produces an accurate signal reference. This signal
can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself.
Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external Fin signal and the
local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that a
phase detector (the crossed circle in Figure 6) can compare the two signals. If the phases of the external and
local signals are not within the tolerance required, the phase detector sends a signal through the charge pump
and loop filter (Figure 6). The charge pump generates an error voltage to bring the VCO back into alignment,
and the loop filter removes any high frequency noise before the error voltage enters the VCO. This new VCO
signal enters the clock tree to drive the chip's circuitry.
Fout represents the clock signal emerging from the output pad (the output signal PLLPAD_OUT is explained
in Table 7). The PLL always drives the PLLPAD_OUT signal, regardless of whether the PLL is configured for
on-chip use. The PLLPAD_OUT will not oscillate if PLL_RESET is asserted, or if the PLL is powered down.
The QL8325 and QL8250 devices contain four PLLs, the remaining Eclipse II devices do not contain PLLs.
There is one PLL located in each quadrant of the FPGA. QuickLogic PLLs compensate for the additional delay
created by the clock tree itself, as previously noted, by subtracting the clock tree delay through the feedback
path.
PLL Modes of Operation
QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output frequency—
Table 6 indicates the features of each mode.
NOTE: “HF” stands for “high frequency” and “LF” stands for “low frequency.”
The input frequency can range from 12.5 MHz to 440 MHz, while output frequency ranges from 25 MHz to
220 MHz. When adding PLLs to the top-level design, be sure that the PLL mode matches the desired input
and output frequencies.
Table 6: PLL Mode Frequencies
PLL Model Output Frequency Input Frequency Range Output Frequency Range
PLL_HF Same as input 66 MHz–220 MHz 66 MHz–220 MHz
PLL_LF Same as input 25 MHz–66 MHz 25 MHz–66 MHz
PLL_MULT2HF 2x 33 MHz–110 MHz 66 MHz–220 MHz
PLL_MULT2LF 2x 12.5 MHz–33 MHz 25 MHz–66 MHz
PLL_DIV2HF 1/2x 220 MHz–440 MHz 110 MHz–220 MHz
PLL_DIV2LF 1/2x 50 MHz–220 MHz 25 MHz–110 MHz
PLL_MULT4 4x 12.5 MHz–50 MHz 50 MHz–200 MHz
PLL_DIV4 1/4x 100 MHz–440 MHz 25 MHz–110 MHz
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Eclipse II Family Data Sheet Rev. R
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PLL Signals
Table 7 summarizes the key signals in QuickLogic PLLs.
NOTE: Because PLLCLK_IN and PLL_RESET signals have PLL_INPAD, and PLLPAD_OUT has OUTPAD,
you do not need to add additional pads to your design.
I/O Cell Structure
Eclipse II features a variety of distinct I/O pins to maximize performance, functionality, and flexibility with bi-
directional I/O pins and input-only pins. All input and I/O pins are 1.8 V, 2.5 V, and 3.3 V tolerant and comply
with the specific I/O standard selected. For single ended I/O standards, VCCIO specifies the input tolerance
and the output drive. For voltage referenced I/O standards (e.g SSTL), the voltage supplied to the INREF pins
in each bank specifies the input switch point. For example, the VCCIO pins must be tied to a 3.3 V supply to
provide 3.3 V compliance. Eclipse II can also support the LVDS and LVPECL I/O standards with the use of
external resistors (see Table 8).
As designs become more complex and requirements more stringent, several application-specific I/O standards
have emerged for specific applications. I/O standards for processors, memories, and a variety of bus
applications have become commonplace and a requirement for many systems. In addition, I/O timing has
Table 7: QuickLogic PLL Signals
Signal Name Description
PLLCLK_IN Input clock signal.
PLL_RESET Active High Reset If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset
to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work.
ONn_OFFCHIP This is a reserved signal. It can be connected to VCC or GND.
CLKNET_OUT Out to internal gates This signal bypasses the PLL logic before driving the clock tree. Note that
this signal cannot be used in the same quadrant where the PLL signal is used (PLLCLK_OUT).
PLLCLK_OUT Out from PLL to internal gates This signal can drive the clock tree after going through the PLL.
PLLPAD_OUT
Out to off-chip This outgoing signal is used off-chip. The PLLPAD_OUT is always active, driving
the PLL-derived clock signal out through the pad. The PLLPAD_OUT will not oscillate if
PLL_RESET is asserted, or if the PLL is powered down.
LOCK_DETECT
Active High Lock detection signal
NOTE: For simulation purposes, this signal gets asserted after 10 clock cycles. However, it can take
a maximum of 200 clock cycles to sync with the input clock upon release of the PLL_RESET signal.
Table 8: I/O Standards and Applications
I/O Standard Reference Voltage Output Voltage Application
LVT TL n/a 3.3 V General Purpose
LVC M OS 2 5 n/a 2.5 V General Purpose
LVCMOS18 n/a 1.8 V General Purpose
PCI n/a 3.3 V PCI Bus Applications
GTL+ 1n/a Backplane
SSTL3 1.5 3.3 V SDRAM
SSTL2 1.25 2.5 V SDRAM
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Eclipse II Family Data Sheet Rev. R
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become a greater issue with specific requirements for setup, hold, clock to out, and switching times. Eclipse II
has addressed these new system requirements and now includes a completely new I/O cell which consists of
programmable I/Os as well as a new cell structure consisting of three registers—Input, Output, and OE.
Eclipse II offers banks of programmable I/Os that address many of the bus standards that are popular today.
As shown in Figure 7 each bi-directional I/O pin is associated with an I/O cell which features an input register,
an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one
output multiplexers.
Figure 7: Eclipse II I/O Cell
The bi-directional I/O pin options can be programmed for input, output, or bi-directional operation. As shown
in Figure 7, each bi-directional I/O pin is associated with an I/O cell which features an input register, an input
buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one multiplexers.
The select lines of the two-to-one multiplexers are static and must be connected to either VCC or GND.
For input functions, I/O pins can provide combinatorial, registered data, or both options simultaneously to the
logic array. For combinatorial input operation, data is routed from I/O pins through the input buffer to the
array logic. For registered input operation, I/O pins drive the D input of input cell registers, allowing data to
be captured with fast, predictable set-up times without consuming internal logic cell resources. The comparator
and multiplexer in the input path allows for native support of I/O standards with reference points offset from
traditional ground.
For output functions, I/O pins can receive combinatorial or registered data from the logic array. For
combinatorial output operation, data is routed from the logic array through a multiplexer to the I/O pin. For
registered output operation, the array logic drives the D input of the output cell register which in turn drives
the I/O pin through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be
E
R
Q
D
R
Q
D
E
R
Q
D
+
-
PAD
OUTPUT ENABLE
REGISTER
OUTPUT
REGISTER
INPUT
REGISTER
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Eclipse II Family Data Sheet Rev. R
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driven to the I/O pin. The addition of an output register will also decrease the Tco. Since the output register
does not need to drive the routing the length of the output path is also reduced, and static timing analysis
becomes very predictable.
The three-state output buffer controls the flow of data from the array logic to the I/O pin and allows the I/O
pin to act as an input and/or output. The buffer's output enable can be individually controlled by the logic cell
array or any pin (through the regular routing resources), or it can be bank-controlled through one of the global
networks. The signal can also be either combinatorial or registered. This is identical to that of the flow for the
output cell. For combinatorial control operation, data is routed from the logic array through a multiplexer to
the three-state control. The IOCTRL pins can directly drive the OE and CLK signals for all I/O cells within the
same bank.
For registered control operation, the array logic drives the D input of the OE cell register which in turn drives
the three-state control through a multiplexer. The multiplexer allows either a combinatorial or a registered
signal to be driven to the three-state control.
When I/O pins are unused, the OE controls can be permanently disabled, allowing the output cell register to
be used for registered feedback into the logic array.
I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular
routing resources, from one of the global networks, or from two IOCTRL input pins per bank of I/O's. The
CLK and RESET signals share common lines, while the clock enables for each register can be independently
controlled. I/O interface support is programmable on a per bank basis.
The two larger Eclipse II devices contain eight I/O banks. Figure 8 illustrates the I/O bank configurations for
QL8325 and QL8250. The three smaller Eclipse II devices contain two I/O banks per device. Figure 9
illustrates the I/O bank configurations for QL8150, QL8050, and QL8025.
Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and INREF supply
inputs. A mixture of different I/O standards can be used on the device; however, there is a limitation as to
which I/O standards can be supported within a given bank. Only standards that share a common VCCIO and
INREF can be shared within the same bank (e.g., PCI and LVTTL). In the case of the QL8150, QL8050 and
QL8025, only one voltage-referenced standard can be used. The two I/O banks, A and B, share the INREF
pin.
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Eclipse II Family Data Sheet Rev. R
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Figure 8: Multiple I/O Banks on QL8325 and QL8250
Figure 9: Multiple I/O Banks on QL8150, QL8050, and QL8025
Embedded RAM BlocksPLL PLL
Fabric
Embeded Computational Units
Embedded RAM BlocksPLL PLL
VCCIO(F) INREF(F) VCCIO(E) INREF(E)
VCCIO(D)
INREF(D)
VCCIO(C)
INREF (C)
INREF(B)VCCIO(B)
INREF(A)
VCCIO(A)
INREF(H)
VCCIO(H)
INREF(G)
VCCIO(G)
Embedded RAM Blocks
Fabric
Embedded RAM Blocks
VCCIO(B)
INREF
VCCIO(A)
VDED
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Eclipse II Family Data Sheet Rev. R
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Programmable Slew Rate
Each I/O has programmable slew rate capability—the slew rate can be either fast or slow. The slower rate can
be used to reduce the switching times of each I/O.
Programmable Weak Pull-Down
A programmable Weak Pull-Down resistor is available on each I/O. The I/O Weak Pull-Down eliminates the
need for external pull down resistors for used I/Os as shown in Figure 10. The spec for pull-down current is
maximum of 150 μA under worst case condition.
Figure 10: Programmable I/O Weak Pull-Down
I/O Output Logic PA D
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Eclipse II Family Data Sheet Rev. R
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Clock Networks
Global Clocks
There are eight global clock networks in each QL8325 and QL8250 device, and five global clock networks in
each QL8150, QL8050 and QL8025 device. Global clocks can drive logic cells and I/O registers, ECUs, and
RAM blocks in the device. All global clocks have access to a Quad Net (local clock network) connection with
a programmable connection to the logic cell’s register clock input.
Figure 11: Global Clock Architecture
Quad-Net Network
There are five Quad-Net local clock networks in each quadrant for a total of 20 in a device. Each Quad-Net is
local to a quadrant. Before driving the column clock buffers, the quad-net is driven by the output of a mux
which selects between the CLK pin input and an internally generated clock source (see Figure 12).
Figure 12: Global Clock Structure
Quad Net
CLK Pin
Global Clock Net
Internally generated clock, or
clock from general routing network
Global Clock
(CLK) Input
Quad-Net Clock Network
FF
Global Clock Buffer
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Eclipse II Family Data Sheet Rev. R
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Dedicated Clock
There is one dedicated clock in the two larger devices of the Eclipse II Family (QL8325 and QL8250). This
clock connects to the clock input of the Logic Cell and I/O registers, and RAM blocks through a hardwired
connection and is multiplexed with the programmable clock input. The dedicated clock provides a fast global
network with low skew. Users have the ability to select either the dedicated clock or the programmable clock
(Figure 13).
Figure 13: Dedicated Clock Circuitry within Logic Cell
NOTE: For more information on the clocking capabilities of Eclipse II FPGAs, see QuickLogic Application
Note 68 at http://www.quicklogic.com/images/appnote68.pdf.
I/O Control and Local Hi-Drives
Each bank of I/Os has two input-only pins that can be programmed to drive the RST, CLK, and EN inputs of
I/Os in that bank. These input-only pins also serve as high drive inputs to a quadrant. These buffers can be
driven by the internal logic both as an I/O control or high drive. For I/O constrained designs, these pins can
be used for general purpose inputs. To provide more general purpose I/Os in the 208 PQFP package, the I/O
controls pins are not bonded out. The performance of these resources is presented in Table 9.
Table 9: I/O Control Network/Local High-Drive
Destination
TT, 25 C, 2.5 V From Pad From Array
I/O (far) 1.00 ns 1.14 ns
I/O (near) 0.63 ns 0.78 ns
Skew 0.37 ns 0.36 ns
Programmable Clock or
General Routing
Dedicated Clock CLK
Logic Cell
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Eclipse II Family Data Sheet Rev. R
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Table 10 shows the total number of I/O control pins per device/package combination. These pins are not
bonded out in the smaller devices and packages. This increases the number of bi-directional user I/Os available.
Programmable Logic Routing
Eclipse II devices are engineered with six types of routing resources as follows: short (sometimes called
segmented) wires, dual wires, quad wires, express wires, distributed networks, and default wires. Short wires
span the length of one logic cell, always in the vertical direction. Dual wires run horizontally and span the
length of two logic cells. Short and dual wires are predominantly used for local connections. Default wires
supply VCC and GND (Logic ‘1’ and Logic ‘0’) to each column of logic cells.
Quad wires have passive link interconnect elements every fourth logic cell. As a result, these wires are typically
used to implement intermediate length or medium fan-out nets.
Express lines run the length of the device, uninterrupted. Each of these lines has a higher capacitance than a
quad, dual, or short wire, but less capacitance than shorter wires connected to run the length of the device.
The resistance will also be lower because the express wires don't require the use of pass links. Express wires
provide higher performance for long routes or high fan-out nets.
Distributed networks are described in Clock Networks on page 14. These wires span the programmable logic
and are driven by quad-net buffers.
Global Power-On Reset (POR)
The Eclipse II family of devices features a global power-on reset. This reset is hardwired to all registers and
resets them to Logic ‘0’ upon power-up of the device. In QuickLogic devices, the asynchronous Reset input
to flip-flops has priority over the Set input; therefore, the Global POR will reset all flip-flops during power-up.
If you want to set the flip-flops to Logic ‘1’, you must assert the “Set” signal after the Global POR signal has
been deasserted.
Table 10: I/O Control Pins per Device/Package Combination
Device 100 VQFP 101
CTBGA 144 TQFP 196 TFBGA
(0.8 mm)
196 TFBGA
(0.5 mm) 208 PQFP 280 LFBGA 484 BGA
QL8025 -NA - - NAa
a. Not available.
NA NA NA
QL8050 - - - - NA NA NA NA
QL8150 NA NA - - - - NA NA
QL8250 NA NA NA NA NA -16 16
QL8325 NA NA NA NA NA -16 16
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Figure 14: Power-On Reset
Low Power Mode
Quiescent power consumption of all Eclipse II devices can be reduced significantly by de-activating the charge
pumps inside the architecture. By applying 3.3 V to the VPUMP pin, the internal charge pump is de-
activated—this effectively reduces the static and dynamic power consumption of the device. The Eclipse II
device is fully functional and operational in the Low Power mode. Users who have a 3.3 V supply available in
their system should take advantage of this low power feature by tying the VPUMP pin to 3.3 V. Otherwise, if
a 3.3 V supply is not available, this pin should be tied to ground.
VCC
Power-on
Reset
QXXXXXXX 0
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Joint Test Access Group (JTAG) Information
Figure 15: JTAG Block Diagram
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, one
problem being the accessibility of test points. JTAG formed in response to this challenge, resulting in IEEE
standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture.
The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of
a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with
the Instruction Register (IR), which allow users to run three required tests along with several user-defined tests.
JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests
for fuller verification of higher level system elements.
The 1149.1 standard requires the following three tests:
• Extest Instruction. The Extest Instruction performs a printed circuit board (PCB) interconnect test. This
test places a device into an external boundary test mode, selecting the boundary scan register to be
connected between the TAP Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are
preloaded with test patterns (through the Sample/Preload Instruction), and input boundary cells capture
the input data for analysis.
TCK
TMS
TRSTB
RDI TDO
Instruction Decode
&
Control Logic
Tap Controller
State Machine
(16 States)
Instruction Register
Boundary-Scan Register
(Data Register)
Mux
Bypass
Register
Mux
Internal
Register I/O Registers
User Defined Data Register
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• Sample/Preload Instruction. The Sample/Preload Instruction allows a device to remain in its functional
mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this
test, the boundary scan register can be accessed through a data scan operation, allowing users to sample
the functional data entering and leaving the device.
• Bypass Instruction. The Bypass Instruction allows data to skip a device boundary scan entirely, so the
data passes through the bypass register. The Bypass instruction allows users to test a device without passing
through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial
data to be transferred through a device without affecting the operation of the device.
JTAG BSDL Support
• BSDL-Boundary Scan Description Language
• Machine-readable data for test equipment to generate testing vectors and software
• BSDL files available for all device/package combinations from QuickLogic
• Extensive industry support available and ATVG (Automatic Test Vector Generation)
Security Links
There are several security links to disable reading logic from the array, and to disable JTAG access to the
device. Programming these optional links completely disables access to the device from the outside world and
provides an extra level of design security not possible in SRAM-based FPGAs. The option to program these
links is selectable through QuickWorks in the Tools/Options/Device Programming window in SpDE.
Power-Up Loading Link
The flexibility link enables Power-Up Loading of the Embedded RAM blocks. If the link is programmed, the
Power-Up Loading state machine is activated during power-up of the device. The state machine communicates
with an external EPROM via the JTAG pins to download memory contents into the on-chip RAM. If the link
is not programmed, Power-Up Loading is not enabled and the JTAG pins function as they normally would.
The option to program this link is selectable through QuickWorks in the Tools/Options/Device Programming
window in SpDE. For more information on Power-Up Loading, see QuickLogic Application Note 55 at
http://www.quicklogic.com/images/appnote55.pdf. See the Power-Up Loading power-up sequencing
requirement for proper functionality in Figure 16.
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Figure 16: Required Power-Up Sequence When Using Power-Up Loading
To use the power-up loading function in Eclipse II, designers must ensure that VCC begins to ramp within a
maximum of 2 ms of VCCIO, VDED, VDED2, and VPUMP
.
Voltage
VCCIO
VDED
VDED2
VPUMP
VCC
Time
< 2 ms
VCC
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Electrical Specifications
DC Characteristics
The DC Specifications are provided in Table 11 through Table 14.
Table 11: Absolute Maximum Ratings
Parameter Value Parameter Value
VCC Voltage -0.5 V to 2.0 V Latch-up Immunity ±100 mA
VCCIO Voltage -0.5 V to 4.0 V DC Input Current ±20 mA
INREF Voltage 0.5 V to VCCIO Leaded Package
Storage Temperature -65° C to + 150° C
Input Voltage -0.5 V to VCCIO + 0.5 V Laminate Package (BGA)
Storage Temperature -55° C to + 125° C
Table 12: Recommended Operating Range
Symbol Parameter Military Industrial Commercial Unit
Min Max Min Max Min Max
VCC Supply Voltage 1.71 1.89 1.71 1.89 1.71 1.89 V
VCCIO I/O Input Tolerance Voltage 1.71 3.60 1.71 3.60 1.71 3.60 V
TJ Junction Temperature -55 125 -40 100 085 °C
KDelay Factor
-6 Speed Grade 0.49 1.57 0.50 1.51 0.54 1.47 n/a
-7 Speed Grade 0.48 1.40 0.50 1.34 0.53 1.31 n/a
-8 Speed Grade 0.45 1.32 0.47 1.26 0.50 1.23 n/a
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Table 13: DC Characteristics
Symbol Parameter Conditions Min Max Units
IlI or I/O Input Leakage Current VI = VCCIO or GND -1 1µA
IOZ 3-State Output Leakage Current VI = VCCIO or GND - 1 µA
CII/O Input Capacitance - - 8 pF
CCLOCK Clock Input Capacitance - - 8 pF
IOS Output Short Circuit Currenta
a. The data provided in Table 13 represents the JEDEC and PCI specifications. Duration should not exceed
30 seconds.
VO = GND
VO = VCC
-15
40
-180
210
mA
mA
IREF Quiescent Current on INREF --10 10 µA
IPD Current on programmable pull-down VCC = 1.8 V -50 µA
IPUMP Quiescent Current on VPUMP VPUMP= 3.3 V -10 µA
IPLL Quiescent Current on each VCCPLL 2.5 V
3.3 V - 3 mA
IVCCIO Quiescent Current on VCCIO
VCCIO = 3.3 V
VCCIO = 2.5 V
VCCIO = 1.8 V
-
20
10
10
µA
Table 14: DC Input and Output Levelsa
a. The data provided in Table 14 represents the JEDEC and PCI specification. QuickLogic devices either meet or
exceed these requirements. For data specific to QuickLogic I/Os, see preceding Table 19 through Table 27,
Figure 7 through Figure 10, and Figure 39 through Figure 42.
NOTE: All CLK, IOCTRL, and PLLIN pins are clamped to the VDED rail. Therefore, these pins can be driven
up to VDED. All JTAG inputs are clamped to the VDED2 rail. These JTAG input pins can only be
driven up to VDED2.
Symbol INREF VIL VIH VOL VOH IOL IOH
VMIN VMAX VMIN VMAX VMIN VMAX VMAX VMIN mA mA
LVT TL n/a n/a -0.3 0.8 2.2 VCCIO + 0.3 0.4 2.4 2.0 -2.0
LVC M OS 2 n/a n/a -0.3 0.7 1.7 VCCIO + 0.3 0.7 1.7 2.0 -2.0
LV C M O S 18 n/a n/a -0.3 0.63 1.2 VCCIO + 0.3 0.7 1.7 2.0 -2.0
GTL+ 0.88 1.12 -0.3 INREF - 0.2 INREF + 0.2 VCCIO + 0.3 0.6 n/a 40 n/a
PCI n/a n/a -0.3 0.3 x VCCIO 0.6 x VCCIO VCCIO + 0.5 0.1 x VCCIO 0.9 x VCCIO 1.5 -0.5
SSTL2 1.15 1.35 -0.3 INREF - 0.18 INREF + 0.18 VCCIO + 0.3 0.74 1.76 7.6 -7.6
SSTL3 1.3 1.7 -0.3 INREF - 0.2 INREF + 0.2 VCCIO + 0.3 1.10 1.90 8-8
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Figure 17 through Figure 20 show the VIL and VIH characteristics for I/O and clock pins.
Figure 17: VIL Maximum for I/O
Figure 18: VIH Minimum for I/O
VILmax for IO
0
0.5
1
1.5
2
2.5
-55C -40C 0C 25C 70C 90C 110C 125C
Junc tion Temperature
Voltage (V)
1.71 V
1.8 V
1.89 V
2.5 V
3.3 V
3.6 V
VIHmin for IO
0
0.5
1
1.5
2
2.5
-55C -40C 0C 25C 70C 90C 110C 125C
Junction Temperature
Voltage
1. 71 V
1. 8 V
1. 89 V
2. 5 V
3. 3 V
3. 6 V
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Figure 19: VIL Maximum for CLOCK Pins
Figure 20: VIH Minimum for CLOCK Pins
VILm ax for CLOCK pins
0
0.5
1
1.5
2
-55C -40C 0C 25C 70C 90C 110C 125C
Junction Temperature
Voltage (V)
1.71V
1.8 V
1.89 V
2.5 V
3.3 V
3.6 V
VI Hm i n f or CLOCK pi ns
0
0.5
1
1.5
2
2.5
-55C -40C 0C 25C 70C 90C 110C 125C
Junction Tem perature
Voltage (V)
1.71 V
1.8 V
1.89 V
2.5 V
3.3 V
3.6 V
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Figure 21 through Figure 25 show the output drive characteristics for the I/Os across various voltages and
temperatures.
Figure 21: Drive Current at VCCIO = 1.71 V
Figure 22: Drive Current at VCCIO = 1.8 V
Drive Current @ Vccio = 1.71 V
0
5
10
15
20
25
30
35
00.20.4
0.60.811.2
1.41.6
1.71
O utpu t V ol tage (V )
Drive Current (mA)
IOH: -55C
IOL: -55C
IOH: 25C
IOL: 25C
IOH: 125C
IOL: 125C
Drive Current @ Vccio = 1.8 V
0
5
10
15
20
25
30
35
40
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Output V ol t age (V )
Drive Current (mA)
IOH: -55C
IOL: -55C
IOH: 25C
IOL: 25C
IOH: 125C
IOL: 125C
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Figure 23: Drive Current at VCCIO = 2.5 V
Figure 24: Drive Current at VCCIO = 3.3 V
Drive Current @ Vccio = 2.5V
0
10
20
30
40
50
60
70
80
0 0.5 1 1.5 2 2.5
Output Voltage (V)
Drive Current (mA)
IOH: -55C
IOL: - 5 5C
IOH: 25C
IOL: 25 C
IOH: 125C
IOL: 125C
Drive Current @ Vccio = 3.3V
0
20
40
60
80
100
120
0 0.5 1 1.5 2 2.5 3 3.3
Output Voltage (V)
Drive Current (mA)
IOH: -55C
IOL: -55C
IOH: 25C
IOL: 25C
IOH: 125C
IOL: 125C
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Figure 26 through Figure 30 show the quiescent current for the Eclipse II family of devices for each of the
voltage supplies, across voltage and temperature. Quiescent current on VCC is a function of device utilization.
The numbers in the following graphs were taken from 100% utilized devices, filled with 32-bit counters. For
conditions other than those described, measured quiescent current levels may be higher than the values in
Figure 26 through Figure 30. Use the Power Calculator Tool for more accurate estimates.
Figure 26: Quiescent Current on VCC for QL8025
Table 15: Quiescent Current on VCC for QL8025 (Over All Temperatures – Over 1.71 V to 3.6 V)
Parameter Current
IVDED 2.5 µA
ICCIO 1.0 µA
Q u i escent Current o n VCC for Q L 8025
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
-55C -40C 0C 25C 70C 90C 125C
Ambient Temperature
uA
VCC=1.71V
VCC=1.8V
VCC=1.89V
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Figure 27: Quiescent Current on VCC for QL8050
Table 16: Quiescent Current on VCC for QL8050 (Over All Temperatures – Over 1.71 V to 3.6 V)
Parameter Current
IVDED 2.6 µA
ICCIO 2.0 µA
Q uei scen t Current on V CC for Q L8050
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
160.0
180.0
200.0
-55C -40C 0C 25C 70C 90C 125C
Ambient Temperature
uA
VCC=1.71V
VCC=1.8V
VCC=1.89V
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Figure 28: Quiescent Current on VCC for QL8150
Table 17: Quiescent Current on VCC for QL8150 (Over All Temperatures – Over 1.71 V to 3.6 V)
Parameter Current
IVDED 18.4 µA
ICCIO 7.7 µA
Q ui escen t Current on V CC for Q L8150
0.0
200.0
400.0
600.0
800.0
1000.0
1200.0
-55C -40C 0C 25C 70C 90C 125C
Ambient Temperature
uA
VCC=1.71V
VCC=1.8V
VCC=1.89V
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Figure 29: Quiescent Current on VCC for QL8250
Table 18: Quiescent Current on VCC for QL8250 (Over All Temperatures – Over 1.71 V to 3.6 V)
Parameter Current
IVDED 16.9 µA
ICCIO 5.5 µA
Q uiescent Cur r ent on VCC f or QL8250
0.0
100.0
200.0
300.0
400.0
500.0
600.0
700.0
800.0
900.0
1000.0
-55C -40C 0C 25C 70C 90C 125C
Ambient Temperature
uA
VCC=1.71V
VCC=1.8V
VCC=1.89V
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Figure 30: Quiescent Current on VCC for QL8325
Table 19: Quiescent Current on VCC for QL8325 (Over All Temperatures – Over 1.71 V to 3.6 V)
Parameter Current
IVDED 16.9 µA
ICCIO 5.1 µA
Q uiescent Cur r ent on VCC f or QL8325
0.0
200.0
400.0
600.0
800.0
1000.0
1200.0
1400.0
1600.0
-55C -40C 0C 25C 70C 90C 125C
Ambient Temperature
uA
VCC=1.71V
VCC=1.8V
VCC=1.89V
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AC Characteristics
The AC Specifications (at VCC = 1.8 V, TJ = 25° C, Worst Case Corner, Speed Grade = -8 (K = 1.03)) are
provided from Table 20 through Table 29. Logic Cell diagrams and waveforms are provided from Figure 31
through Figure 42.
Figure 31: Eclipse II Logic Cell
Table 20: Logic Cell Delays
Symbol Parameter Value
Min Max
tPD
Combinatorial Delay of the longest path: time taken by the combinatorial circuit
to output 0.28 ns 0.98 ns
tSU
Setup time: time the synchronous input of the flip-flop must be stable before the
active clock edge 0.10 ns 0.25 ns
tHL
Hold time: time the synchronous input of the flip-flop must be stable after the
active clock edge 0 ns 0 ns
tCO
Clock-to-out delay: the amount of time taken by the flip-flop to output after the
active clock edge. 0.22 ns 0.52 ns
tCWHI Clock High Time: required minimum time the clock stays high 0.46 ns 0.46 ns
tCWLO Clock Low Time: required minimum time that the clock stays low 0.46 ns 0.46 ns
tSET
Set Delay: time between when the flip-flop is ”set” (high) and when the output is
consequently “set” (high) 0.69 ns 0.69 ns
tRESET
Reset Delay: time between when the flip-flop is ”reset” (low) and when the
output is consequently “reset” (low) 1.09 ns 1.09 ns
tSW Set Width: time that the SET signal must remain high/low 0.3 ns 0.3 ns
tRW Reset Width: time that the RESET signal must remain high/low 0.3 ns 0.3 ns
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Figure 32: Logic Cell Flip-Flop
Figure 33: Logic Cell Flip-Flop Timings—First Waveform
Figure 34: Logic Cell Flip-Flop Timings—Second Waveform
SET
D
CLK
RESET
Q
SET
RESET
Q
CLK
tCWHI (min) tCWLO (min)
tRESET
tRW
tSET tSW
CLK
D
Q
tSU tHL
tCO
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NOTE: When using a PLL, tPGCK and tBGCK are effectively zero due to delay adjustment by Phase Locked
Loop feedback path.
Figure 35: Global Clock Structure Timing Elements
Figure 36: Dual-Port SRAM Cell
Table 21: Eclipse II Tree Clock Delay
Clock Segment Parameter Value
Min Max
tPGCK Global clock pin delay to quad net -1.92 ns
tBGCK Global clock tree delay (quad net to flip-flop) -0.28 ns
tDPD Dedicated clock pad -1.7 ns
tGSKEW Global delay clock skew -0.1 ns
tDSKEW Dedicated clock skew -0.05 ns
Internally generated clock, or
clock from general routing network
Global Clock
(CLK) Input
Quad-Net Clock Network
FF
Global Clock Buffer
WA
WD
WE
WCLK
RE
RCLK
RA
RD
RAM Module
[7:0]
[17:0]
[7:0]
[17:0]
ASYNCRD
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Figure 37: RAM Cell Synchronous Write Timing
Table 22: RAM Cell Synchronous Write Timing
Symbol Parameter Value
Min Max
RAM Cell Synchronous Write Timing
tSWA
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the
active edge of the WRITE CLOCK 0.47 ns -
tHWA
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the
active edge of the WRITE CLOCK 0 ns -
tSWD
WD setup time to WCLK: time the WRITE DATA must be stable before the active
edge of the WRITE CLOCK 0.48 ns -
tHWD
WD hold time to WCLK: time the WRITE DATA must be stable after the active
edge of the WRITE CLOCK 0 ns -
tSWE
WE setup time to WCLK: time the WRITE ENABLE must be stable before the
active edge of the WRITE CLOCK 0 ns -
tHWE
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active
edge of the WRITE CLOCK 0 ns -
tWCRD
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the
time when the data is available at RD -3.79 ns
tSWA
tSWD
tSWE
tHWA
tHWD
tHWE
tWCRD
old data new data
WCLK
WA
WD
WE
RD
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Table 23: RAM Cell Synchronous and Asynchronous Read Timing
Symbol Parameter Value
Min Max
RAM Cell Synchronous Read Timing
tSRA
RA setup time to RCLK: time the READ ADDRESS must be stable before the
active edge of the READ CLOCK 0.43 ns -
tHRA
RA hold time to RCLK: time the READ ADDRESS must be stable after the active
edge of the READ CLOCK 0 ns -
tSRE
RE setup time to WCLK: time the READ ENABLE must be stable before the active
edge of the READ CLOCK 0.21 ns -
tHRE
RE hold time to WCLK: time the READ ENABLE must be stable after the active
edge of the READ CLOCK 0 ns -
tRCRD
RCLK to RD: time between the active READ CLOCK edge and the time when the
data is available at RD -2.25 ns
RAM Cell Asynchronous Read Timing
rPDRD
RA to RD: time between when the READ ADDRESS is input and when the DATA
is output -1.99 ns
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Figure 40: Eclipse II I/O Cell Output Enable Timing
Table 24: Eclipse II I/O Cell Output Timing
Symbol Parameter Value (ns)
Output Register Cell Only Slow Slew Max Fast Slew Max
tOUTLH Output Delay low to high (90% of H) 4.0 2.95
tOUTHL Output Delay high to low (10% of L) 3.5 2.49
tPZH Output Delay tri-state to high (90% of H) 4.96 2.93
tPZL Output Delay tri-state to low (10% of L) 4.87 2.84
tPHZ Output Delay high to tri-state 5.8 3.62
tPLZ Output Delay low to tri-state 5.58 3.4
tCOP Clock-to-out delay (does not include clock tree delays) 5.49 3.3
Table 25: Output Slew Rates @ VCCIO = 3.3 V, T = 25° C
Fast Slew Slow Slew
Rising Edge 2.8 V/ns 1.0 V/ns
Falling Edge 2.86 V/ns 1.0 V/ns
Table 26: Output Slew Rates @ VCCIO = 2.5 V, T = 25° C
Fast Slew Slow Slew
Rising Edge 1.7 V/ns 0.6 V/ns
Falling Edge 1.9 V/ns 0.6 V/ns
Table 27: Output Slew Rates @ VCCIO = 1.8 V, T = 25° C
Fast Slew Slow Slew
Rising Edge TBD TBD
Falling Edge TBD TBD
L
H
L
H
tOUTLH
tOUTHL
L
H
Z
tPZH L
H
Z
tPZL
L
H
Z
tPLZ
L
H
Z
tPHZ
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Table 28: I/O Input Register Cell Timing
Symbol Parameter Value
Min Max
tISU
Input register setup time: time the synchronous input of the flip-flop must be stable
before the active clock edge 2.15 ns -
tIHL
Input register hold time: time the synchronous input of the flip-flop must be stable after
the active clock edge 0 ns -
tICO Input register clock-to-out: time taken by the flip-flop to output after the active clock edge -0.3 ns
tIRST
Input register reset delay: time between when the flip-flop is “reset”(low) and when the
output is consequently “reset” (low) -0.82 ns
tIESU
Input register clock enable setup time: time “enable” must be stable before the active
clock edge 0.4 ns -
tIEH
Input register clock enable hold time: time “enable” must be stable after the active clock
edge 0 ns -
Table 29: I/O Input Buffer Delays
Symbol Parameter Value
To get the total input delay add this delay to tISU Min Max
tSID (LVTTL) LVTTL input delay: Low Voltage TTL for 3.3 V applications -0.82 ns
tSID (LVCMOS2) LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower
applications -0.82 ns
tSID (LVCMOS18) LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications - -
tSID (GTL+) GTL+ input delay: Gunning Transceiver Logic -0.94 ns
tSID (SSTL3) SSTL3 input delay: Stub Series Terminated Logic for 3.3 V -0.94 ns
tSID (SSTL2) SSTL2 input delay: Stub Series Terminated Logic for 2.5 V -0.94 ns
tSID (PCI) PCI input delay: Peripheral Component Interconnect for 3.3 V -0.82 ns
www.quicklogic.com
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Eclipse II Family Data Sheet Rev. R
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Package Thermal Characteristics
Thermal Resistance Equations:
θJC = (TJ - TC)/P
θJA = (TJ - TA)/P
PMAX = (TJMAX - TAMAX)/θJA
Parameter Description:
θJC: Junction-to-case thermal resistance
θJA: Junction-to-ambient thermal resistance
TJ: Junction temperature
TA: Ambient temperature
P: Power dissipated by the device while operating
PMAX: The maximum power dissipation for the device
TJMAX: Maximum junction temperature
TAMAX: Maximum ambient temperature
NOTE: Maximum junction temperature (TJMAX) is 125°C. To calculate the maximum power dissipation for
a device package look up θJA from Table 30, pick an appropriate TAMAX and use:
PMAX = (125°C - TAMAX)/ θJA.
Table 30: Package Thermal Characteristics
Device Package Description θJA (º C/W)
Package Code Package Type Pin Count 0 LFM 200 LFM 400 LFM
QL8325
QL6325E
PS PBGA 484 26.6 24.1 21.8
PT LFBGA 280 34 31.6 29.9
PQ PQFP 208 32 28 26.5
QL8250
QL6250E
PS PBGA 484 26.6 24.1 21.8
PT LFBGA 280 34 31.6 29.9
PQ PQFP 208 32 28 26.5
QL8150
PT LFBGA 280 34 31.6 29.9
PQ PQFP 208 43.6 41 39
PT TFBGA 196 40 38 35.2
PU TFBGA 196 40 34 33
PF TQFP 144 37 36 34
QL8050
PT TFBGA 196 54 51.8 48
PF TQFP 144 41 39 37
PU CTBGA 101 59 52 50
PV VQFP 100 43 41.3 38.8
QL8025
PT TFBGA 196 54 51.8 48
PF TQFP 144 41 39 37
PV VQFP 100 43 41.3 38.8
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
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Power vs. Operating Frequency
The basic power equation which best models power consumption is given below:
PTOTAL = 0.350 + f[0.0031 ηLC + 0.0948 ηCKBF + 0.01 ηCLBF + 0.0263 ηCKLD +
0.543 ηRAM + 0.20 ηPLL + 0.0035 ηINP + 0.0257 ηOUTP] (mW)
Where:
ηLC is the total number of logic cells in the design
ηCKBF = # of clock buffers
ηCLBF = # of column clock buffers
ηCKLD = # of loads connected to the column clock buffers
ηRAM = # of RAM blocks
ηPLL = # of PLLs
ηINP is the number of input pins
ηOUTP is the number of output pins
NOTE: To learn more about power consumption, see QuickLogic Application Note 60 at
http://www.quicklogic.com/images/appnote60.pdf.
Power-up Sequencing
Figure 43: Power-Up Sequencing
When powering up a device, the VCC/VCCIO/VDED/VDED2 rails must take 400 µs or longer to reach the
maximum value (refer to Figure 43).
NOTE: Ramping VCC, VCCIO, VPUMP
, VDED, or VDED2 faster than 400 µs can cause the device to behave
improperly.
For users with a limited power budget, ensure VCCIO, VDED, VDED2, and VPUMP are within 500 mV of VCC when
ramping up the power supplies.
Voltage
VCCIO
VDED
VDED2
VPUMP
VCC
|VCCIO , VDED , VDED2 , VPUMP - VCC|MAX
Time
400 us
VCC
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Eclipse II Family Data Sheet Rev. R
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Pin Descriptions
Table 31: Pin Descriptions
Pin Direction Function Description
JTAG Pin Descriptions
TDI/RSI ITest Data In for JTAG/RAM init.
Serial Data In
Hold HIGH during normal operation. Connects to serial
PROM data in for RAM initialization. Connect to VDED2 if
unused
TRSTB/RRO I/0 Active low Reset for JTAG/RAM
init. reset out
Hold LOW during normal operation. Connects to serial
PROM reset for RAM initialization. Connect to GND if unused
TMS ITest Mode Select for JTAG Hold HIGH during normal operation. Connect to VDED2 if not
used for JTAG
TCK ITest Clock for JTAG Hold HIGH or LOW during normal operation. Connect to
VDED2 or GND if not used for JTAG
TDO/RCO OTest data out for JTAG/RAM init.
clock out
Connect to serial PROM clock for RAM initialization. Must be
left unconnected if not used for JTAG or RAM initialization.
The output voltage drive is specified by VDED.
Dedicated Pin Descriptions
CLK IGlobal clock network pin
Low skew global clock. This pin provides access to a
dedicated, distributed network capable of driving the CLOCK,
SET, RESET, F1, and A2 inputs to the Logic Cell, READ, and
WRITE CLOCKS, Read and Write Enables of the Embedded
RAM Blocks, CLOCK of the ECUs, and Output Enables of the
I/Os. The voltage tolerance of this pin is specified by VDED.
The voltage tolerance of the CLK pins in the PU101
package are specified by VCCIO(B).
I/O(A) I/O Input/Output pin
The I/O pin is a bi-directional pin, configurable to either an
input-only, output-only, or bi-directional pin. The A inside the
parenthesis means that the I/O is located in Bank A. If an I/O
is not used, SpDE (QuickWorks Tool) provides the option of
tying that pin to GND, VCC, or TriState.
VCC IPower supply pin Connect to 1.8 V supply.
VCCIO(A) IInput voltage tolerance pin
This pin provides the flexibility to interface the device with
either a 3.3 V, 2.5 V, or 1.8 V device. The A inside the
parenthesis means that VCCIO is located in BANK A. Every
I/O pin in Bank A will be tolerant of VCCIO input signals and
will drive VCCIO level output signals. This pin must be
connected to either 3.3 V, 2.5 V, or 1.8 V. VCCIO powers the
the PLLOUT pins.
GND I Ground pin Connect to ground.
PLLIN IPLL clock input Clock input for PLL. The voltage tolerance of this pin is
specified by VDED.
DEDCLK IDedicated clock pin
Very low skew global clock. This pin provides access to a
dedicated, distributed clock network capable of driving the
CLOCK inputs of all sequential elements of the device (e.g.,
RAM, Flip Flops). The voltage tolerance of this pin is
specified by VDED.
GNDPLL IGround pin for PLL Connect to GND.
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Eclipse II Family Data Sheet Rev. R
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INREF(A) IDifferential reference voltage
The INREF is the reference voltage pin for GTL+, SSTL2, and
STTL3 standards. Follow the recommendations provided in
Table 14 for the appropriate standard. The A inside the
parenthesis means that INREF is located in BANK A. This pin
should be tied to GND if voltage referenced standards are not
used.
PLLOUT OPLL output pin
Dedicated PLL output pin. Must be left unconnected if PLL is
powered up and not held in reset, since PLLOUT will be
driving the PLL-derived clock. May be left unconnected if PLL
is held in reset or not powered up. PLLOUT pin is driven by
VCCIO. For a list of each PLLOUT pin and the VCCIO pin that
powers it see Table 32.
IOCTRL(A) IHighdrive input
This pin provides fast RESET, SET, CLOCK, and ENABLE
access to the I/O cell flip-flops, providing fast clock-to-out and
fast I/O response times. This pin can also double as a high-
drive pin to the internal logic cells. The A inside the
parenthesis means that IOCTRL is located in Bank A. There
is an internal pulldown resistor to GND on this pin. This pin
should be tied to GND if it is not used. For backwards
compatibility with Eclipse and EclipsePlus, it can be tied to
VDED or GND. If tied to VDED, it will draw no more than
20 µA per IOCTRL pin due to current through the pulldown
resistor. The voltage tolerance of this pin is specified by
VDED. Note that the 208 PQFP package has no I/O control
pins.
VPUMP ICharge Pump Disable
This pin disables the internal charge pump for lower static
power consumption. To disable the charge pump, connect
VPUMP to 3.3 V. If the Disable Charge Pump feature is not
used, connect VPUMP to GND. For backwards compatibility
with Eclipse and EclipsePlus devices, connect VPUMP to
GND.
VDED IVoltage tolerance for clocks,
TDO JTAG output, and IOCTRL
This pin specifies the input voltage tolerance for CLK,
DEDCLK, PLLIN, and IOCTRL dedicated input pins, as well
as the output voltage drive TDO JTAG pins. If the PLLs are
used, VDED must be the same as VCCPLL. The legal range
for VDED is between 1.71 V and 3.6 V. For backwards
compatibility with Eclipse and EclipsePlus devices, connect
VDED to 2.5 V.
Table 31: Pin Descriptions (Continued)
Pin Direction Function Description
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Eclipse II Family Data Sheet Rev. R
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VDED2 IVoltage tolerance for JTAG pins
(TDI, TMS, TCK, and TRSTB)
These pins specify the input voltage tolerance for the JTAG
input pins. The legal range for VDED2 is between 1.71 V and
3.6 V. These do not specify output voltage of the JTAG output,
TDO. Refer to the VDED pin section for specifying the JTAG
output voltage.
VCCPLL IPower Supply pin for PLL
Connect to 2.5 V or 3.3 V supply. For backwards compatibility
with Eclipse and EclipsePlus devices, connect to 2.5 V. To
minimize static power consumption when designs do not
utilize the PLLs, you may connect VCCPLL to GND. If
VCCPLL is grounded, the PLL is disabled.
PLL_RESET IPLL reset pin
If PLL_RESET is asserted, then CLKNET_OUT and
PLLPAD_OUT are reset to 0. This signal must be asserted
and then released in order for the LOCK_DETECT to work.
If a PLL module is not used, then the associated PLLRST<x>
must be connected to VDED.
Table 32: PLLOUT Pin Supply Voltage
PLLOUT VCCIO
PLLOUT(0) VCCIO(E)
PLLOUT(1) VCCIO(B)
PLLOUT(2) VCCIO(A)
PLLOUT(3) VCCIO(F)
Table 31: Pin Descriptions (Continued)
Pin Direction Function Description
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
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Figure 44: QL8325 and QL8250 I/O Banks with Relevant Pins
Figure 45: QL8150, QL8050, and QL8025 I/O Banks with Relevant Pins
IO BANK A IO BANK B
VCCIO(A)
INREF(A)
IOCTRL(A)
IO(A)
VCCIO (B)
INREF(B)
IOCTRL(B)
IO(B)
IO BANK C IO BANK D
VCCIO (C)
INREF(C)
IOCTRL(C)
IO(C)
VCCIO(D)
INREF(D)
IOCTRL(D)
IO(D)
IO BANK F IO BANK E
VCCIO (F)
INREF(F)
IOCTRL(F)
IO(F)
VCCIO(E)
INREF(E)
IOCTRL(E)
IO(E)
IO BANK HIO BANK G
(H)
INREF(H)
IOCTRL(H)
IO(H)
VCCIO
VCCIO
(G)
INREF(G)
IOCTRL(G)
IO(G)
VCCIO (B
IO(B)
(A)
IO(A)
VCCIO
INREF
IO BANK A
IO BANK B
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Eclipse II Family Data Sheet Rev. R
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Recommended Unused Pin Terminations for Eclipse II Devices
All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally using the
Configuration Editor. This option is given in the bottom-right corner of the placement window. To use the
Placement Editor, choose Constraint > Fix Placement in the Option pull-down menu of SpDE.
The rest of the pins should be terminated at the board level in the manner presented in Table 33.
Table 33: Recommended Unused Pin Terminations
Signal Name Recommended Termination
PLLOUT<x>a
a. x represents a number.
In earlier versions, the recommendation for unused PLLOUT pins was that they be connected to
VCC or GND. This was acceptable for Rev. D (and earlier) silicon, including all 0.25 µm devices.
For Rev. G (and later) silicon this is not correct. Unused PLLOUT pins should be left unconnected.
Used PLLOUT pins will normally be connected to inputs, but can also be left unconnected. For the
truth table of PLLOUT connections, refer to Table 34.
IOCTRL<y>b
b. y represents an alphabetical character.
There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is not
used. For backwards compatibility with Eclipse, it can be tied to VDED or GND. If tied to VDED, it
will draw no more than 20 µA per IOCTRL pin due to current through the pulldown resistor.
CLK/PLLIN<x> Any unused clock pins should be connected to VDED or GND.
PLLRST<x>
If a PLL module is not used, then the associated PLLRST<x> must be connected to VDED or GND.
If VCCPLL is grounded, then PLLRST must be grounded also. If VCCPLL is driven by 2.5 V or
3.3 V, PLLRST must be driven by the same voltage.
INREF<y> If an I/O bank does not require the use of the INREF signal the pin should be connected to GND.
Table 34: Recommended PLLOUT Terminations Truth Table
PLL_RESET Recommended PLLOUT Termination
0Must be left unconnected.
1May be left unconnected, or connected to GND. Must not be connected to VCC.
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
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QL8025 - 100 VQFP Pinout Diagram
QL8025 - 100 VQFP Pinout Table
Table 35: QL8025 - 100 VQFP Pinout Table
Pin Function Pin Function Pin Function Pin Function Pin Function
1GND 21 I/O(A) 41 VCC 61 I/O(B) 81 I/O(B)
2GND 22 I/O(A) 42 I/O(A) 62 I/O(B) 82 I/O(B)
3I/O(A) 23 I/O(A) 43 I/O(A) 63 CLK(2) 83 I/O(B)
4I/O(A) 24 I/O(A) 44 I/O(A) 64 CLK(3) 84 VCC
5I/O(A) 25 TDO 45 I/O(A) 65 VCC 85 I/O(B)
6VCC 26 I/O(A) 46 I/O(A) 66 CLK(4) 86 I/O(B)
7I/O(A) 27 GND 47 VCCIO(A) 67 TMS 87 VCC
8I/O(A) 28 I/O(A) 48 I/O(A) 68 I/O(B) 88 TCK
9VCCIO(A) 29 VCCIO(A) 49 VPUMP 69 GND 89 VDED2
10 I/O(A) 30 I/O(A) 50 I/O(A) 70 I/O(B) 90 I/O(B)
11 TDI 31 I/O(A) 51 GND 71 I/O(B) 91 GND
12 CLK(0) 32 I/O(A) 52 I/O(B) 72 I/O(B) 92 I/O(B)
13 CLK(1) 33 I/O(A) 53 I/O(B) 73 I/O(B) 93 I/O(B)
14 VCC 34 I/O(A) 54 I/O(B) 74 I/O(B) 94 I/O(B)
15 I/O(A) 35 VCC 55 VCC 75 I/O(B) 95 I/O(B)
16 VDED 36 TRSTB 56 I/O(B) 76 GND 96 I/O(B)
17 I/O(A) 37 VDED2 57 INREF 77 I/O(B) 97 I/O(B)
18 GND 38 I/O(A) 58 I/O(B) 78 VCCIO(B) 98 VCCIO(B)
19 I/O(A) 39 I/O(A) 59 I/O(B) 79 I/O(B) 99 I/O(B)
20 I/O(A) 40 GND 60 VCCIO(B) 80 I/O(B) 100 I/O(B)
Pin 1
Pin 26 Pin 51
Pin 76
Eclipse II
QL8025-7PV100C
© 2007 QuickLogic Corporation
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QL8025 - 144 TQFP Pinout Table
Table 36: QL8025 - 144 TQFP Pinout Table
Pin Function Pin Function Pin Function Pin Function
1GND 37 IO(A) 73 IO(A) 109 GND
2GND 38 GND 74 IO(B) 110 IO(B)
3IO(A) 39 IO(A) 75 GND 111 VCCIO(B)
4IO(A) 40 VCCIO(A) 76 IO(B) 112 IO(B)
5IO(A) 41 IO(A) 77 IO(B) 113 IO(B)
6IO(A) 42 IO(A) 78 IO(B) 114 IO(B)
7VCC 43 IO(A) 79 VCC 115 IO(B)
8IO(A) 44 IO(A) 80 IO(B) 116 IO(B)
9IO(A) 45 IO(A) 81 IO(B) 117 NC
10 IO(A) 46 IO(A) 82 INREF 118 IO(B)
11 NC 47 IO(A) 83 IO(B) 119 IO(B)
12 IO(A) 48 IO(A) 84 IO(B) 120 VCC
13 VCCIO(A) 49 VCCIO(A) 85 IO(B) 121 IO(B)
14 IO(A) 50 IO(A) 86 VCCIO(B) 122 VCCIO(B)
15 TDI 51 NC 87 IO(B) 123 IO(B)
16 CLK(0) 52 VCC 88 NC 124 IO(B)
17 CLK(1) 53 TRSTB 89 IO(B) 125 VCC
18 VCC 54 VDED2 90 CLK(2) 126 TCK
19 IO(A) 55 IO(A) 91 CLK(3) 127 VDED2
20 VDED 56 IO(A) 92 VCC 128 IO(B)
21 IO(A) 57 IO(A) 93 CLK(4) 129 IO(B)
22 IO(A) 58 GND 94 TMS 130 GND
23 GND 59 IO(A) 95 IO(B) 131 IO(B)
24 VCCIO(A) 60 VCC 96 GND 132 IO(B)
25 IO(A) 61 IO(A) 97 VCCIO(B) 133 IO(B)
26 IO(A) 62 IO(A) 98 IO(B) 134 IO(B)
27 NC 63 IO(A) 99 IO(B) 135 IO(B)
28 IO(A) 64 IO(A) 100 IO(B) 136 IO(B)
29 IO(A) 65 NC 101 IO(B) 137 NC
30 IO(A) 66 IO(A) 102 NC 138 IO(B)
31 IO(A) 67 IO(A) 103 IO(B) 139 IO(B)
32 IO(A) 68 IO(A) 104 IO(B) 140 IO(B)
33 IO(A) 69 VCCIO(A) 105 IO(B) 141 VCCIO(B)
34 TDO 70 IO(A) 106 IO(B) 142 IO(B)
35 GND 71 VPUMP 107 GND 143 IO(B)
36 IO(A) 72 IO(A) 108 IO(B) 144 IO(B)
© 2007 QuickLogic Corporation
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QL8025 - 196 TFBGA Pinout Table
Table 37: QL8025 - 196 TFBGA Pinout Table
Ball Function Ball Function Ball Function Ball Function Ball Function
A1 IO(B) C13 NC F11 IO(A) J9 GND M7 VCC
A2 IO(B) C14 NC F12 NC J10 GND M8 IO(A)
A3 NC D1 IO(B) F13 IO(A) J11 IO(A) M9 IO(A)
A4 IO(B) D2 NC F14 IO(A) J12 IO(A) M10 IO(A)
A5 IO(B) D3 NC G1 IO(B) J13 NC M11 IO(A)
A6 NC D4 IO(B) G2 TCK J14 NC M12 IO(A)
A7 CLK(4) D5 IO(B) G3 NC K1 NC M13 NC
A8 CLK(2) D6 VCCIO(B) G4 VCC K2 NC M14 IO(A)
A9 NC D7 VCCIO(B) G5 GND K3 IO(B) N1 NC
A10 IO(B) D8 VDED G6 GND K4 IO(B) N2 IO(B)
A11 INREF D9 VCCIO(B) G7 GND K5 VCCIO(B) N3 IO(A)
A12 IO(B) D10 IO(B) G8 GND K6 VCCIO(A) N4 IO(A)
A13 IO(B) D11 NC G9 GND K7 GND N5 IO(A)
A14 IO(B) D12 VPUMP G10 GND K8 GND N6 NC
B1 NC D13 IO(A) G11 IO(A) K9 VCCIO(A) N7 IO(A)
B2 IO(B) D14 IO(A) G12 VCC K10 VCCIO(A) N8 IO(A)
B3 IO(B) E1 IO(B) G13 IO(A) K11 NC N9 IO(A)
B4 NC E2 IO(B) G14 IO(A) K12 IO(A) N10 NC
B5 IO(B) E3 IO(B) H1 NC K13 IO(A) N11 NC
B6 TMS E4 IO(B) H2 IO(B) K14 IO(A) N12 TDO
B7 VCC E5 VCCIO(B) H3 VDED2 L1 IO(B) N13 IO(A)
B8 IO(B) E6 GND H4 VCCIO(B) L2 IO(B) N14 NC
B9 NC E7 GND H5 GND L3 IO(B) P1 IO(A)
B10 IO(B) E8 GND H6 GND L4 IO(B) P2 IO(A)
B11 IO(B) E9 GND H7 GND L5 NC P3 IO(A)
B12 IO(B) E10 IO(A) H8 GND L6 NC P4 NC
B13 IO(A) E11 VCCIO(A) H9 GND L7 VCCIO(A) P5 IO(A)
B14 IO(A) E12 IO(A) H10 GND L8 VDED P6 CLK(0)
C1 IO(B) E13 NC H11 VCCIO(A) L9 VDED P7 CLK(1)
C2 IO(B) E14 VCC H12 TRSTB L10 VCCIO(A) P8 IO(A)
C3 IO(B) F1 IO(B) H13 VDED2 L11 VCC P9 IO(A)
C4 VCC F2 VCC H14 VCC L12 IO(A) P10 IO(A)
C5 IO(B) F3 NC J1 IO(B) L13 IO(A) P11 NC
C6 VCC F4 IO(B) J2 IO(B) L14 IO(A) P12 IO(A)
C7 IO(B) F5 VCCIO(B) J3 IO(B) M1 NC P13 IO(A)
C8 CLK(3) F6 GND J4 VCC M2 IO(B) P14 IO(A)
C9 IO(B) F7 GND J5 IO(B) M3 IO(A)
C10 VCC F8 GND J6 GND M4 GND
C11 IO(B) F9 GND J7 GND M5 VCC
C12 IO(A) F10 IO(A) J8 GND M6 TDI
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QL8050 - 100 VQFP Pinout Diagram
QL8050 - 100 VQFP Pinout Table
Table 38: QL8050 - 100 VQFP Pinout Table
Pin Function Pin Function Pin Function Pin Function Pin Function
1GND 21 I/O(A) 41 VCC 61 I/O(B) 81 I/O(B)
2GND 22 I/O(A) 42 I/O(A) 62 I/O(B) 82 I/O(B)
3I/O(A) 23 I/O(A) 43 I/O(A) 63 CLK(2) 83 I/O(B)
4I/O(A) 24 I/O(A) 44 I/O(A) 64 CLK(3) 84 VCC
5I/O(A) 25 TDO 45 I/O(A) 65 VCC 85 I/O(B)
6VCC 26 I/O(A) 46 I/O(A) 66 CLK(4) 86 I/O(B)
7I/O(A) 27 GND 47 VCCIO(A) 67 TMS 87 VCC
8I/O(A) 28 I/O(A) 48 I/O(A) 68 I/O(B) 88 TCK
9VCCIO(A) 29 VCCIO(A) 49 VPUMP 69 GND 89 VDED2
10 I/O(A) 30 I/O(A) 50 I/O(A) 70 I/O(B) 90 I/O(B)
11 TDI 31 I/O(A) 51 GND 71 I/O(B) 91 GND
12 CLK(0) 32 I/O(A) 52 I/O(B) 72 I/O(B) 92 I/O(B)
13 CLK(1) 33 I/O(A) 53 I/O(B) 73 I/O(B) 93 I/O(B)
14 VCC 34 I/O(A) 54 I/O(B) 74 I/O(B) 94 I/O(B)
15 I/O(A) 35 VCC 55 VCC 75 I/O(B) 95 I/O(B)
16 VDED 36 TRSTB 56 I/O(B) 76 GND 96 I/O(B)
17 I/O(A) 37 VDED2 57 INREF 77 I/O(B) 97 I/O(B)
18 GND 38 I/O(A) 58 I/O(B) 78 VCCIO(B) 98 VCCIO(B)
19 I/O(A) 39 I/O(A) 59 I/O(B) 79 I/O(B) 99 I/O(B)
20 I/O(A) 40 GND 60 VCCIO(B) 80 I/O(B) 100 I/O(B)
Pin 1
Pin 26 Pin 51
Pin 76
Eclipse II
QL8050-7PV100C
www.quicklogic.com
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QL8050 - 101 CTBGA Pinout Table
NOTE: The voltage tolerance of the CLK pins in the PU101 package are specified by VCCIO(B).
Table 39: QL8050 - 101 CTBGA Pinout Table
Pin Function Pin Function Pin Function Pin Function Pin Function
A1 I/O(B) B11 I/O(B) E4 I/O(B) H2 I/O(B) K6 I/O(A)
A2 I/O(B) C1 I/O(B) E8 VCC H3 VCC K7 I/O(A)
A3 I/O(B) C2 I/O(B) E9 I/O(A) H5 GND K8 I/O(A)
A4 I/O(B) C4 I/O(B) E10 VCCIO(B) H7 VCC K9 GND
A5 CLK(4) C5 I/O(B) E11 I/O(A) H9 I/O(A) K10 I/O(A)
A6 CLK(3) C6 I/O(B) F1 I/O(B) H10 I/O(A) K11 I/O(A)
A7 CLK(2) C7 VCC F2 I/O(B) H11 I/O(A) L1 I/O(B)
A8 VCCIO(B) C8 I/O(B) F3 VCC J1 I/O(B) L2 I/O(B)
A9 I/O(B) C10 I/O(A) F8 I/O(A) J2 I/O(B) L3 I/O(A)
A10 I/O(B) C11 VCC F9 VCCIO(A) J4 I/O(A) L4 CLK(0)
A11 I/O(B) D1 I/O(B) F10 I/O(A) J5 VCCIO(A) L5 CLK(1)
B1 I/O(B) D2 I/O(B) F11 GND J6 I/O(A) L6 I/O(A)
B2 I/O(B) D3 I/O(B) G1 I/O(B) J7 I/O(A) L7 I/O(A)
B3 GND D5 I/O(B) G2 GND J8 I/O(A) L8 I/O(A)
B4 I/O(B) D7 I/O(B) G3 GND J10 I/O(A) L9 I/O(A)
B5 I/O(B) D9 VCCIO(B) G4 VCCIO(B) J11 I/O(A) L10 I/O(A)
B6 VCCIO(B) D10 I/O(B) G8 VCCIO(A) K1 I/O(B) L11 I/O(A)
B7 I/O(B) D11 I/O(A) G9 I/O(A) K2 I/O(B)
B8 I/O(B) E1 I/O(B) G10 I/O(A) K3 GND
B9 GND E2 I/O(B) G11 I/O(A) K4 I/O(A)
B10 VPUMP E3 I/O(B) H1 I/O(B) K5 VCCIO(B)
www.quicklogic.com
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
58
QL8050 - 144 TQFP Pinout Table
Table 40: QL8050 - 144 TQFP Pinout Table
Pin Function Pin Function Pin Function Pin Function
1GND 37 IO(A) 73 IO(A) 109 GND
2GND 38 GND 74 IO(B) 110 IO(B)
3IO(A) 39 IO(A) 75 GND 111 VCCIO(B)
4IO(A) 40 VCCIO(A) 76 IO(B) 112 IO(B)
5IO(A) 41 IO(A) 77 IO(B) 113 IO(B)
6IO(A) 42 IO(A) 78 IO(B) 114 IO(B)
7VCC 43 IO(A) 79 VCC 115 IO(B)
8IO(A) 44 IO(A) 80 IO(B) 116 IO(B)
9IO(A) 45 IO(A) 81 IO(B) 117 IO(B)
10 IO(A) 46 IO(A) 82 INREF 118 IO(B)
11 IO(A) 47 IO(A) 83 IO(B) 119 IO(B)
12 IO(A) 48 IO(A) 84 IO(B) 120 VCC
13 VCCIO(A) 49 VCCIO(A) 85 IO(B) 121 IO(B)
14 IO(A) 50 IO(A) 86 VCCIO(B) 122 VCCIO(B)
15 TDI 51 IO(A) 87 IO(B) 123 IO(B)
16 CLK(0) 52 VCC 88 IO(B) 124 IO(B)
17 CLK(1) 53 TRSTB 89 IO(B) 125 VCC
18 VCC 54 VDED2 90 CLK(2) 126 TCK
19 IO(A) 55 IO(A) 91 CLK(3) 127 VDED2
20 VDED 56 IO(A) 92 VCC 128 IO(B)
21 IO(A) 57 IO(A) 93 CLK(4) 129 IO(B)
22 IO(A) 58 GND 94 TMS 130 GND
23 GND 59 IO(A) 95 IO(B) 131 IO(B)
24 VCCIO(A) 60 VCC 96 GND 132 IO(B)
25 IO(A) 61 IO(A) 97 VCCIO(B) 133 IO(B)
26 IO(A) 62 IO(A) 98 IO(B) 134 IO(B)
27 IO(A) 63 IO(A) 99 IO(B) 135 IO(B)
28 IO(A) 64 IO(A) 100 IO(B) 136 IO(B)
29 IO(A) 65 IO(A) 101 IO(B) 137 IO(B)
30 IO(A) 66 IO(A) 102 IO(B) 138 IO(B)
31 IO(A) 67 IO(A) 103 IO(B) 139 IO(B)
32 IO(A) 68 IO(A) 104 IO(B) 140 IO(B)
33 IO(A) 69 VCCIO(A) 105 IO(B) 141 VCCIO(B)
34 TDO 70 IO(A) 106 IO(B) 142 IO(B)
35 GND 71 VPUMP 107 GND 143 IO(B)
36 IO(A) 72 IO(A) 108 IO(B) 144 IO(B)
www.quicklogic.com
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
60
QL8050 - 196 TFBGA Pinout Table
Table 41: QL8050 - 196 TFBGA Pinout Table
Ball Function Ball Function Ball Function Ball Function Ball Function
A1 IO(B) C13 IO(A) F11 IO(A) J9 GND M7 VCC
A2 IO(B) C14 IO(A) F12 IO(A) J10 GND M8 IO(A)
A3 IO(B) D1 IO(B) F13 IO(A) J11 IO(A) M9 IO(A)
A4 IO(B) D2 IO(B) F14 IO(A) J12 IO(A) M10 IO(A)
A5 IO(B) D3 IO(B) G1 IO(B) J13 IO(A) M11 IO(A)
A6 IO(B) D4 IO(B) G2 TCK J14 IO(A) M12 IO(A)
A7 CLK(4) D5 IO(B) G3 IO(B) K1 IO(B) M13 IO(A)
A8 CLK(2) D6 VCCIO(B) G4 VCC K2 IO(B) M14 IO(A)
A9 IO(B) D7 VCCIO(B) G5 GND K3 IO(B) N1 IO(B)
A10 IO(B) D8 VDED G6 GND K4 IO(B) N2 IO(B)
A11 INREF D9 VCCIO(B) G7 GND K5 VCCIO(B) N3 IO(A)
A12 IO(B) D10 IO(B) G8 GND K6 VCCIO(A) N4 IO(A)
A13 IO(B) D11 IO(B) G9 GND K7 GND N5 IO(A)
A14 IO(B) D12 VPUMP G10 GND K8 GND N6 IO(A)
B1 IO(B) D13 IO(A) G11 IO(A) K9 VCCIO(A) N7 IO(A)
B2 IO(B) D14 IO(A) G12 VCC K10 VCCIO(A) N8 IO(A)
B3 IO(B) E1 IO(B) G13 IO(A) K11 IO(A) N9 IO(A)
B4 IO(B) E2 IO(B) G14 IO(A) K12 IO(A) N10 IO(A)
B5 IO(B) E3 IO(B) H1 IO(B) K13 IO(A) N11 IO(A)
B6 TMS E4 IO(B) H2 IO(B) K14 IO(A) N12 TDO
B7 VCC E5 VCCIO(B) H3 VDED2 L1 IO(B) N13 IO(A)
B8 IO(B) E6 GND H4 VCCIO(B) L2 IO(B) N14 IO(A)
B9 IO(B) E7 GND H5 GND L3 IO(B) P1 IO(A)
B10 IO(B) E8 GND H6 GND L4 IO(B) P2 IO(A)
B11 IO(B) E9 GND H7 GND L5 IO(A) P3 IO(A)
B12 IO(B) E10 IO(A) H8 GND L6 IO(A) P4 IO(A)
B13 IO(A) E11 VCCIO(A) H9 GND L7 VCCIO(A) P5 IO(A)
B14 IO(A) E12 IO(A) H10 GND L8 VDED P6 CLK(0)
C1 IO(B) E13 IO(A) H11 VCCIO(A) L9 VDED P7 CLK(1)
C2 IO(B) E14 VCC H12 TRSTB L10 VCCIO(A) P8 IO(A)
C3 IO(B) F1 IO(B) H13 VDED2 L11 VCC P9 IO(A)
C4 VCC F2 VCC H14 VCC L12 IO(A) P10 IO(A)
C5 IO(B) F3 IO(B) J1 IO(B) L13 IO(A) P11 IO(A)
C6 VCC F4 IO(B) J2 IO(B) L14 IO(A) P12 IO(A)
C7 IO(B) F5 VCCIO(B) J3 IO(B) M1 IO(B) P13 IO(A)
C8 CLK(3) F6 GND J4 VCC M2 IO(B) P14 IO(A)
C9 IO(B) F7 GND J5 IO(B) M3 IO(A)
C10 VCC F8 GND J6 GND M4 GND
C11 IO(B) F9 GND J7 GND M5 VCC
C12 IO(A) F10 IO(A) J8 GND M6 TDI
www.quicklogic.com
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
62
QL8150 - 144 TQFP Pinout Table
Table 42: QL8150 - 144 TQFP Pinout Table
Pin Function Pin Function Pin Function Pin Function
1GND 37 IO(A) 73 IO(A) 109 GND
2GND 38 GND 74 IO(B) 110 IO(B)
3IO(A) 39 IO(A) 75 GND 111 VCCIO(B)
4IO(A) 40 VCCIO(A) 76 IO(B) 112 IO(B)
5IO(A) 41 IO(A) 77 IO(B) 113 IO(B)
6IO(A) 42 IO(A) 78 IO(B) 114 IO(B)
7VCC 43 IO(A) 79 VCC 115 IO(B)
8IO(A) 44 IO(A) 80 IO(B) 116 IO(B)
9IO(A) 45 IO(A) 81 IO(B) 117 IO(B)
10 IO(A) 46 IO(A) 82 INREF 118 IO(B)
11 IO(A) 47 IO(A) 83 IO(B) 119 IO(B)
12 IO(A) 48 IO(A) 84 IO(B) 120 VCC
13 VCCIO(A) 49 VCCIO(A) 85 IO(B) 121 IO(B)
14 IO(A) 50 IO(A) 86 VCCIO(B) 122 VCCIO(B)
15 TDI 51 IO(A) 87 IO(B) 123 IO(B)
16 CLK(0) 52 VCC 88 IO(B) 124 IO(B)
17 CLK(1) 53 TRSTB 89 IO(B) 125 VCC
18 VCC 54 VDED2 90 CLK(2) 126 TCK
19 IO(A) 55 IO(A) 91 CLK(3) 127 VDED2
20 VDED 56 IO(A) 92 VCC 128 IO(B)
21 IO(A) 57 IO(A) 93 CLK(4) 129 IO(B)
22 IO(A) 58 GND 94 TMS 130 GND
23 GND 59 IO(A) 95 IO(B) 131 IO(B)
24 VCCIO(A) 60 VCC 96 GND 132 IO(B)
25 IO(A) 61 IO(A) 97 VCCIO(B) 133 IO(B)
26 IO(A) 62 IO(A) 98 IO(B) 134 IO(B)
27 IO(A) 63 IO(A) 99 IO(B) 135 IO(B)
28 IO(A) 64 IO(A) 100 IO(B) 136 IO(B)
29 IO(A) 65 IO(A) 101 IO(B) 137 IO(B)
30 IO(A) 66 IO(A) 102 IO(B) 138 IO(B)
31 IO(A) 67 IO(A) 103 IO(B) 139 IO(B)
32 IO(A) 68 IO(A) 104 IO(B) 140 IO(B)
33 IO(A) 69 VCCIO(A) 105 IO(B) 141 VCCIO(B)
34 TDO 70 IO(A) 106 IO(B) 142 IO(B)
35 GND 71 VPUMP 107 GND 143 IO(B)
36 IO(A) 72 IO(A) 108 IO(B) 144 IO(B)
www.quicklogic.com
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
64
QL8150 - 196 TFBGA (8 mm x 8 mm Package) Pinout Table
Table 43: QL8150 - 196 TFBGA Pinout Table
Ball Function Ball Function Ball Function Ball Function Ball Function
A1 GND C13 IO(A) F11 IO(A) J9 VCCIO(A) M7 TDI
A2 IO(B) C14 IO(A) F12 IO(A) J10 IO(A) M8 VDED
A3 IO(B) D1 IO(B) F13 IO(A) J11 IO(A) M9 IO(A)
A4 IO(B) D2 VCCIO(B) F14 VCCIO(A) J12 IO(A) M10 IO(A)
A5 VCCIO(B) D3 IO(B) G1 GND J13 IO(A) M11 TDO
A6 VCC D4 IO(B) G2 IO(B) J14 VCCIO(A) M12 IO(A)
A7 GND D5 IO(B) G3 VDED2 K1 IO(B) M13 VDED
A8 VCC D6 IO(B) G4 TCK K2 IO(B) M14 IO(A)
A9 VCCIO(B) D7 TMS G5 IO(A) K3 IO(B) N1 IO(A)
A10 IO(B) D8 CLK(4) G6 IO(A) K4 IO(B) N2 IO(B)
A11 IO(B) D9 INREF G7 IO(A) K5 IO(A) N3 IO(A)
A12 IO(B) D10 IO(B) G8 IO(A) K6 IO(A) N4 IO(A)
A13 IO(B) D11 IO(B) G9 IO(A) K7 IO(A) N5 IO(A)
A14 GND D12 IO(A) G10 IO(A) K8 IO(A) N6 IO(A)
B1 IO(B) D13 VPUMP G11 VDED2 K9 GND N7 IO(A)
B2 IO(B) D14 IO(A) G12 IO(A) K10 IO(A) N8 IO(A)
B3 IO(B) E1 VCCIO(B) G13 IO(A) K11 VCCIO(A) N9 IO(A)
B4 IO(B) E2 IO(B) G14 GND K12 IO(A) N10 IO(A)
B5 IO(B) E3 IO(B) H1 VCC K13 IO(A) N11 IO(A)
B6 IO(B) E4 IO(B) H2 IO(B) K14 IO(A) N12 IO(A)
B7 IO(B) E5 IO(B) H3 IO(B) L1 IO(B) N13 IO(A)
B8 IO(B) E6 IO(B) H4 IO(B) L2 IO(B) N14 IO(A)
B9 VDED E7 IO(A) H5 IO(B) L3 IO(B) P1 GND
B10 IO(B) E8 IO(B) H6 IO(A) L4 IO(A) P2 IO(A)
B11 IO(B) E9 IO(B) H7 GND L5 IO(A) P3 IO(A)
B12 IO(B) E10 IO(B) H8 GND L6 IO(A) P4 IO(A)
B13 IO(B) E11 IO(B) H9 IO(A) L7 CLK(0) P5 IO(A)
B14 IO(A) E12 IO(A) H10 IO(A) L8 CLK(1) P6 VCCIO(A)
C1 IO(B) E13 IO(A) H11 IO(A) L9 IO(A) P7 GND
C2 IO(B) E14 VCC H12 TRSTB L10 IO(A) P8 VCC
C3 IO(B) F1 VCC H13 IO(A) L11 IO(A) P9 VCCIO(A)
C4 IO(B) F2 IO(B) H14 VCC L12 IO(A) P10 VCC
C5 IO(B) F3 IO(B) J1 VCCIO(B) L13 IO(A) P11 IO(A)
C6 IO(B) F4 IO(B) J2 IO(B) L14 IO(A) P12 IO(A)
C7 CLK(3) F5 IO(B) J3 IO(B) M1 IO(B) P13 IO(A)
C8 CLK(2) F6 IO(B) J4 IO(B) M2 IO(B) P14 GND
C9 IO(B) F7 IO(A) J5 IO(A) M3 IO(B)
C10 IO(B) F8 IO(A) J6 IO(A) M4 GND
C11 IO(B) F9 IO(A) J7 VCCIO(B) M5 IO(A)
C12 IO(B) F10 IO(A) J8 GND M6 IO(A)
www.quicklogic.com
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
66
QL8150 - 196 TFBGA (12 mm x 12 mm Package) Pinout Table
Table 44: QL8150 - 196 TFBGA Pinout Table
Ball Function Ball Function Ball Function Ball Function Ball Function
A1 IO(B) C13 IO(A) F11 IO(A) J9 GND M7 VCC
A2 IO(B) C14 IO(A) F12 IO(A) J10 GND M8 IO(A)
A3 IO(B) D1 IO(B) F13 IO(A) J11 IO(A) M9 IO(A)
A4 IO(B) D2 IO(B) F14 IO(A) J12 IO(A) M10 IO(A)
A5 IO(B) D3 IO(B) G1 IO(B) J13 IO(A) M11 IO(A)
A6 IO(B) D4 IO(B) G2 TCK J14 IO(A) M12 IO(A)
A7 CLK(4) D5 IO(B) G3 IO(B) K1 IO(B) M13 IO(A)
A8 CLK(2) D6 VCCIO(B) G4 VCC K2 IO(B) M14 IO(A)
A9 IO(B) D7 VCCIO(B) G5 GND K3 IO(B) N1 IO(A)
A10 IO(B) D8 VDED G6 GND K4 IO(A) N2 IO(A)
A11 INREF D9 VCCIO(B) G7 GND K5 VCCIO(B) N3 IO(A)
A12 IO(B) D10 IO(B) G8 GND K6 VCCIO(A) N4 IO(A)
A13 IO(B) D11 IO(A) G9 GND K7 GND N5 IO(A)
A14 IO(B) D12 VPUMP G10 GND K8 GND N6 IO(A)
B1 IO(B) D13 IO(A) G11 IO(A) K9 VCCIO(A) N7 IO(A)
B2 IO(B) D14 IO(A) G12 VCC K10 VCCIO(A) N8 IO(A)
B3 IO(B) E1 IO(B) G13 IO(A) K11 IO(A) N9 IO(A)
B4 IO(B) E2 IO(B) G14 IO(A) K12 IO(A) N10 IO(A)
B5 IO(B) E3 IO(B) H1 IO(B) K13 IO(A) N11 IO(A)
B6 TMS E4 IO(B) H2 IO(B) K14 IO(A) N12 TDO
B7 VCC E5 VCCIO(B) H3 VDED2 L1 IO(B) N13 IO(A)
B8 IO(B) E6 GND H4 VCCIO(B) L2 IO(B) N14 IO(A)
B9 IO(B) E7 GND H5 GND L3 IO(B) P1 IO(A)
B10 IO(B) E8 GND H6 GND L4 IO(B) P2 IO(A)
B11 IO(B) E9 GND H7 GND L5 IO(A) P3 IO(A)
B12 IO(B) E10 IO(B) H8 GND L6 IO(A) P4 IO(A)
B13 IO(B) E11 VCCIO(A) H9 GND L7 VCCIO(A) P5 IO(A)
B14 IO(B) E12 IO(A) H10 GND L8 VDED P6 CLK(0)
C1 IO(B) E13 IO(A) H11 VCCIO(A) L9 VDED P7 CLK(1)
C2 IO(B) E14 VCC H12 TRSTB L10 VCCIO(A) P8 IO(A)
C3 IO(B) F1 IO(B) H13 VDED2 L11 VCC P9 IO(A)
C4 VCC F2 VCC H14 VCC L12 IO(A) P10 IO(A)
C5 IO(B) F3 IO(B) J1 IO(B) L13 IO(A) P11 IO(A)
C6 VCC F4 IO(B) J2 IO(B) L14 IO(A) P12 IO(A)
C7 IO(B) F5 VCCIO(B) J3 IO(B) M1 IO(B) P13 IO(A)
C8 CLK(3) F6 GND J4 VCC M2 IO(B) P14 IO(A)
C9 IO(B) F7 GND J5 IO(B) M3 IO(B)
C10 VCC F8 GND J6 GND M4 GND
C11 IO(B) F9 GND J7 GND M5 VCC
C12 IO(A) F10 IO(A) J8 GND M6 TDI
www.quicklogic.com
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
68
QL8150 - 208 PQFP Pinout Table
Table 45: QL8150 - 208 PQFP Pinout Table
Pin Function Pin Function Pin Function Pin Function Pin Function
1I/O(A) 43 I/O(A) 85 I/O(A) 127 I/O(B) 169 I/O(B)
2I/O(A) 44 VCCIO(A) 86 VCC 128 CLK(2) 170 I/O(B)
3GND 45 I/O(A) 87 I/O(A) 129 VDED 171 I/O(B)
4GND 46 VCC 88 I/O(A) 130 CLK(3) 172 I/O(B)
5I/O(A) 47 I/O(A) 89 VCC 131 VCC 173 I/O(B)
6I/O(A) 48 I/O(A) 90 I/O(A) 132 CLK(4) 174 I/O(B)
7I/O(A) 49 GND 91 I/O(A) 133 TMS 175 VCC
8VCCIO(A) 50 TDO 92 I/O(A) 134 I/O(B) 176 I/O(B)
9I/O(A) 51 I/O(A) 93 I/O(A) 135 I/O(B) 177 VCCIO(B)
10 I/O(A) 52 GND 94 I/O(A) 136 I/O(B) 178 GND
11 I/O(A) 53 I/O(A) 95 I/O(A) 137 GND 179 I/O(B)
12 VCC 54 I/O(A) 96 I/O(A) 138 VCCIO(B) 180 I/O(B)
13 I/O(A) 55 I/O(A) 97 I/O(A) 139 I/O(B) 181 I/O(B)
14 I/O(A) 56 VDED 98 VCCIO(A) 140 I/O(B) 182 VCC
15 I/O(A) 57 I/O(A) 99 I/O(A) 141 I/O(B) 183 TCK
16 I/O(A) 58 GND 100 I/O(A) 142 I/O(B) 184 VDED2
17 I/O(A) 59 I/O(A) 101 VPUMP 143 I/O(B) 185 I/O(B)
18 I/O(A) 60 VCCIO(A) 102 I/O(A) 144 I/O(B) 186 I/O(B)
19 VCCIO(A) 61 I/O(A) 103 I/O(A) 145 I/O(B) 187 I/O(B)
20 I/O(A) 62 I/O(A) 104 GND 146 VCC 188 GND
21 GND 63 I/O(A) 105 I/O(B) 147 I/O(B) 189 VCCIO(B)
22 I/O(A) 64 I/O(A) 106 I/O(B) 148 I/O(B) 190 I/O(B)
23 TDI 65 I/O(A) 107 I/O(B) 149 I/O(B) 191 I/O(B)
24 CLK(0) 66 I/O(A) 108 GND 150 VCCIO(B) 192 I/O(B)
25 CLK(1) 67 I/O(A) 109 I/O(B) 151 I/O(B) 193 I/O(B)
26 VCC 68 I/O(A) 110 I/O(B) 152 I/O(B) 194 I/O(B)
27 I/O(A) 69 I/O(A) 111 VCCIO(B) 153 GND 195 VCC
28 I/O(A) 70 I/O(A) 112 I/O(B) 154 I/O(B) 196 I/O(B)
29 VDED 71 I/O(A) 113 VCC 155 I/O(B) 197 I/O(B)
30 I/O(A) 72 VCCIO(A) 114 I/O(B) 156 GND 198 I/O(B)
31 I/O(A) 73 I/O(A) 115 I/O(B) 157 I/O(B) 199 I/O(B)
32 I/O(A) 74 I/O(A) 116 I/O(B) 158 I/O(B) 200 I/O(B)
33 GND 75 GND 117 I/O(B) 159 I/O(B) 201 I/O(B)
34 VCCIO(A) 76 VCC 118 INREF 160 GND 202 I/O(B)
35 I/O(A) 77 I/O(A) 119 I/O(B) 161 I/O(B) 203 VCCIO(B)
36 I/O(A) 78 TRSTB 120 I/O(B) 162 VCCIO(B) 204 GND
37 I/O(A) 79 VDED2 121 I/O(B) 163 I/O(B) 205 I/O(B)
38 I/O(A) 80 I/O(A) 122 VCCIO(B) 164 I/O(B) 206 I/O(B)
39 I/O(A) 81 I/O(A) 123 GND 165 VCC 207 I/O(B)
40 I/O(A) 82 I/O(A) 124 I/O(B) 166 I/O(B) 208 I/O(B)
41 I/O(A) 83 GND 125 I/O(B) 167 I/O(B)
42 I/O(A) 84 VCCIO(A) 126 I/O(B) 168 I/O(B)
www.quicklogic.com
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
70
QL8150 - 280 LFBGA Pinout Table
Table 46: QL8150 - 280 LFBGA Pinout Table
Ball Function Ball Function Ball Function Ball Function Ball Function Ball Function
A1 NC C10 I/O(B) E19 NC K16 I/O(A) R4 I/O(B) U13 I/O(A)
A2 GND C11 VCCIO(B) F1 NC K17 I/O(A) R5 GND U14 NC
A3 I/O(B) C12 I/O(B) F2 NC K18 I/O(A) R6 GND U15 VCCIO(A)
A4 I/O(B) C13 I/O(B) F3 I/O(B) K19 TRSTB R7 VCC U16 I/O(A)
A5 I/O(B) C14 I/O(B) F4 I/O(B) L1 I/O(B) R8 VCC U17 TDO
A6 NC C15 VCCIO(B) F5 GND L2 I/O(B) R9 GND U18 NC
A7 I/O(B) C16 I/O(B) F15 VCC L3 VCCIO(B) R10 GND U19 I/O(A)
A8 I/O(B) C17 I/O(B) F16 NC L4 I/O(B) R11 VCC V1 NC
A9 I/O(B) C18 I/O(B) F17 I/O(A) L5 VCC R12 VCC V2 GND
A10 CLK(3) C19 I/O(B) F18 I/O(A) L15 GND R13 VCC V3 GND
A11 I/O(B) D1 I/O(B) F19 I/O(A) L16 I/O(A) R14 VDED V4 I/O(A)
A12 I/O(B) D2 I/O(B) G1 I/O(B) L17 VCCIO(A) R15 GND V5 I/O(A)
A13 I/O(B) D3 I/O(B) G2 I/O(B) L18 I/O(A) R16 I/O(A) V6 NC
A14 NC D4 I/O(B) G3 NC L19 I/O(A) R17 VCCIO(A) V7 I/O(A)
A15 I/O(B) D5 I/O(B) G4 I/O(B) M1 I/O(B) R18 I/O(A) V8 I/O(A)
A16 I/O(B) D6 I/O(B) G5 VCC M2 I/O(B) R19 I/O(A) V9 I/O(A)
A17 I/O(B) D7 I/O(B) G15 VCC M3 I/O(B) T1 I/O(B) V10 CLK(1)
A18 NC D8 I/O(B) G16 I/O(A) M4 I/O(B) T2 I/O(B) V11 NC
A19 NC D9 CLK(4) G17 I/O(A) M5 VCC T3 I/O(A) V12 I/O(A)
B1 NC D10 I/O(B) G18 I/O(A) M15 VDED T4 I/O(A) V13 I/O(A)
B2 NC D11 I/O(B) G19 I/O(A) M16 NC T5 I/O(A) V14 NC
B3 I/O(B) D12 I/O(B) H1 I/O(B) M17 I/O(A) T6 NC V15 I/O(A)
B4 I/O(B) D13 INREF H2 I/O(B) M18 I/O(A) T7 I/O(A) V16 I/O(A)
B5 I/O(B) D14 I/O(B) H3 I/O(B) M19 I/O(A) T8 I/O(A) V17 I/O(A)
B6 NC D15 I/O(B) H4 I/O(B) N1 NC T9 I/O(A) V18 GND
B7 I/O(B) D16 I/O(A) H5 VCC N2 I/O(B) T10 I/O(A) V19 NC
B8 I/O(B) D17 I/O(A) H15 VCC N3 I/O(B) T11 NC W1 NC
B9 TMS D18 I/O(A) H16 VDED2 N4 I/O(B) T12 I/O(A) W2 NC
B10 CLK(2) D19 I/O(A) H17 I/O(A) N5 VCC T13 I/O(A) W3 I/O(A)
B11 I/O(B) E1 I/O(B) H18 I/O(A) N15 VCC T14 I/O(A) W4 I/O(A)
B12 I/O(B) E2 I/O(B) H19 I/O(A) N16 I/O(A) T15 I/O(A) W5 I/O(A)
B13 NC E3 VCCIO(B) J1 I/O(B) N17 I/O(A) T16 I/O(A) W6 I/O(A)
B14 I/O(B) E4 I/O(B) J2 I/O(B) N18 NC T17 NC W7 I/O(A)
B15 I/O(B) E5 GND J3 VCCIO(B) N19 NC T18 I/O(A) W8 I/O(A)
B16 I/O(B) E6 VCC J4 I/O(B) P1 I/O(B) T19 I/O(A) W9 TDI
B17 NC E7 VCC J5 GND P2 I/O(B) U1 I/O(A) W10 I/O(A)
B18 GND E8 VDED J15 VCC P3 NC U2 I/O(A) W11 I/O(A)
B19 NC E9 VCC J16 I/O(A) P4 NC U3 NC W12 I/O(A)
C1 I/O(B) E10 GND J17 VCCIO(A) P5 VCC U4 I/O(A) W13 I/O(A)
C2 NC E11 GND J18 I/O(A) P15 GND U5 VCCIO(A) W14 NC
C3 I/O(B) E12 VCC J19 I/O(A) P16 I/O(A) U6 NC W15 I/O(A)
C4 I/O(B) E13 VCC K1 VDED2 P17 I/O(A) U7 I/O(A) W16 I/O(A)
C5 VCCIO(B) E14 GND K2 TCK P18 I/O(A) U8 I/O(A) W17 I/O(A)
C6 NC E15 VPUMP K3 I/O(B) P19 I/O(A) U9 VCCIO(A) W18 I/O(A)
C7 I/O(B) E16 I/O(A) K4 I/O(B) R1 I/O(B) U10 CLK(0) W19 NC
C8 I/O(B) E17 VCCIO(A) K5 GND R2 I/O(B) U11 VCCIO(A)
C9 VCCIO(B) E18 NC K15 GND R3 VCCIO(B) U12 I/O(A)
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© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
72
QL8250 - 208 PQFP Pinout Table
Table 47: QL8250 - 208 PQFP Pinout Table
Pin Function Pin Function Pin Function Pin Function Pin Function
1PLLRST(3) 43 I/O(B) 85 I/O(D) 127 CLK(5),PLLIN(3) 169 I/O(G)
2VCCPLL(3) 44 VCCIO(B) 86 VCC 128 CLK(6) 170 INREF(G)
3GND 45 I/O(B) 87 I/O(D) 129 VDED 171 I/O(G)
4GND 46 VCC 88 I/O(D) 130 CLK(7) 172 I/O(G)
5I/O(A) 47 I/O(B) 89 VCC 131 VCC 173 I/O(G)
6I/O(A) 48 I/O(B) 90 I/O(D) 132 CLK(8) 174 I/O(G)
7I/O(A) 49 GND 91 I/O(D) 133 TMS 175 VCC
8VCCIO(A) 50 TDO 92 I/O(D) 134 I/O(F) 176 I/O(G)
9I/O(A) 51 PLLOUT(1) 93 INREF(D) 135 I/O(F) 177 VCCIO(G)
10 I/O(A) 52 GNDPLL(2) 94 I/O(D) 136 I/O(F) 178 GND
11 I/O(A) 53 GND 95 I/O(D) 137 GND 179 I/O(G)
12 VCC 54 VCCPLL(2) 96 I/O(D) 138 VCCIO(F) 180 I/O(G)
13 INREF(A) 55 PLLRST(2) 97 I/O(D) 139 I/O(F) 181 I/O(G)
14 I/O(A) 56 VDED 98 VCCIO(D) 140 I/O(F) 182 VCC
15 I/O(A) 57 I/O(C) 99 I/O(D) 141 I/O(F) 183 TCK
16 I/O(A) 58 GND 100 I/O(D) 142 I/O(F) 184 VDED2
17 I/O(A) 59 I/O(C) 101 VPUMP 143 I/O(F) 185 I/O(H)
18 I/O(A) 60 VCCIO(C) 102 PLLOUT(0) 144 I/O(F) 186 I/O(H)
19 VCCIO(A) 61 I/O(C) 103 GND 145 INREF(F) 187 I/O(H)
20 I/O(A) 62 I/O(C) 104 GNDPLL(1) 146 VCC 188 GND
21 GND 63 I/O(C) 105 PLLRST(1) 147 I/O(F) 189 VCCIO(H)
22 I/O(A) 64 I/O(C) 106 VCCPLL(1) 148 I/O(F) 190 I/O(H)
23 TDI 65 I/O(C) 107 I/O(E) 149 I/O(F) 191 I/O(H)
24 CLK(0) 66 I/O(C) 108 GND 150 VCCIO(F) 192 I/O(H)
25 CLK(1) 67 I/O(C) 109 I/O(E) 151 I/O(F) 193 I/O(H)
26 VCC 68 INREF(C) 110 I/O(E) 152 I/O(F) 194 INREF(H)
27 CLK(2),PLLIN(2) 69 I/O(C) 111 VCCIO(E) 153 GND 195 VCC
28 CLK(3),PLLIN(1) 70 I/O(C) 112 I/O(E) 154 I/O(F) 196 I/O(H)
29 VDED 71 I/O(C) 113 VCC 155 PLLOUT(3) 197 I/O(H)
30 CLK(4),DEDCLK,
PLLIN(0) 72 VCCIO(C) 114 I/O(E) 156 GNDPLL(0) 198 I/O(H)
31 I/O(B) 73 I/O(C) 115 I/O(E) 157 GND 199 I/O(H)
32 I/O(B) 74 I/O(C) 116 I/O(E) 158 VCCPLL(0) 200 I/O(H)
33 GND 75 GND 117 I/O(E) 159 PLLRST(0) 201 I/O(H)
34 VCCIO(B) 76 VCC 118 INREF(E) 160 GND 202 I/O(H)
35 I/O(B) 77 I/O(C) 119 I/O(E) 161 I/O(G) 203 VCCIO(H)
36 I/O(B) 78 TRSTB 120 I/O(E) 162 VCCIO(G) 204 GND
37 I/O(B) 79 VDED2 121 I/O(E) 163 I/O(G) 205 I/O(H)
38 I/O(B) 80 I/O(D) 122 VCCIO(E) 164 I/O(G) 206 PLLOUT(2)
39 I/O(B) 81 I/O(D) 123 GND 165 VCC 207 GND
40 INREF(B) 82 I/O(D) 124 I/O(E) 166 I/O(G) 208 GNDPLL(3)
41 I/O(B) 83 GND 125 I/O(E) 167 I/O(G)
42 I/O(B) 84 VCCIO(D) 126 I/O(E) 168 I/O(G)
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© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
74
QL8250 - 280 LFBGA Pinout Table
Table 48: QL8250 - 280 LFBGA Pinout Table
Ball Function Ball Function Ball Function Ball Function Ball Function Ball Function
A1 PLLOUT(3) C10 CLK(5)
/PLLIN(3) E19 IOCTRL(D) K16 I/O(C) R4 I/O(H) U13 I/O(B)
A2 GNDPLL(0) C11 VCCIO(E) F1 INREF(G) K17 I/O(D) R5 GND U14 IOCTRL(B)
A3 I/O(F) C12 I/O(E) F2 IOCTRL(G) K18 I/O(C) R6 GND U15 VCCIO(B)
A4 I/O(F) C13 I/O(E) F3 I/O(G) K19 TRSTB R7 VCC U16 I/O(B)
A5 I/O(F) C14 I/O(E) F4 I/O(G) L1 I/O(H) R8 VCC U17 TDO
A6 IOCTRL(F) C15 VCCIO(E) F5 GND L2 I/O(H) R9 GND U18 PLLRST(2)
A7 I/O(F) C16 I/O(E) F15 VCC L3 VCCIO(H) R10 GND U19 I/O(B)
A8 I/O(F) C17 I/O(E) F16 IOCTRL(D) L4 I/O(H) R11 VCC V1 PLLOUT(2)
A9 I/O(F) C18 I/O(E) F17 I/O(D) L5 VCC R12 VCC V2 GNDPLL(3)
A10 CLK(7) C19 I/O(E) F18 I/O(D) L15 GND R13 VCC V3 GND
A11 I/O(E) D1 I/O(G) F19 I/O(D) L16 I/O(C) R14 VDED V4 I/O(A)
A12 I/O(E) D2 I/O(G) G1 I/O(G) L17 VCCIO(C) R15 GND V5 I/O(A)
A13 I/O(E) D3 I/O(F) G2 I/O(G) L18 I/O(C) R16 I/O(C) V6 IOCTRL(A)
A14 IOCTRL(E) D4 I/O(F) G3 IOCTRL(G) L19 I/O(C) R17 VCCIO(C) V7 I/O(A)
A15 I/O(E) D5 I/O(F) G4 I/O(G) M1 I/O(H) R18 I/O(C) V8 I/O(A)
A16 I/O(E) D6 I/O(F) G5 VCC M2 I/O(H) R19 I/O(C) V9 I/O(A)
A17 I/O(E) D7 I/O(F) G15 VCC M3 I/O(H) T1 I/O(H) V10 CLK(1)
A18 PLLRST(1) D8 I/O(F) G16 I/O(D) M4 I/O(H) T2 I/O(H) V11
CLK(4)
DEDCLK/
PLLIN(0)
A19 GND D9 CLK(8) G17 I/O(D) M5 VCC T3 I/O(A) V12 I/O(B)
B1 PLLRST(0) D10 I/O(E) G18 I/O(D) M15 VDED T4 I/O(A) V13 I/O(B)
B2 GND D11 I/O(E) G19 I/O(D) M16 INREF(C) T5 I/O(A) V14 INREF(B)
B3 I/O(F) D12 I/O(E) H1 I/O(G) M17 I/O(C) T6 IOCTRL(A) V15 I/O(B)
B4 I/O(F) D13 INREF(E) H2 I/O(G) M18 I/O(C) T7 I/O(A) V16 I/O(B)
B5 I/O(F) D14 I/O(E) H3 I/O(G) M19 I/O(C) T8 I/O(A) V17 I/O(B)
B6 INREF(F) D15 I/O(E) H4 I/O(G) N1 IOCTRL(H) T9 I/O(A) V18 GNDPLL(2)
B7 I/O(F) D16 I/O(D) H5 VCC N2 I/O(H) T10 I/O(A) V19 GND
B8 I/O(F) D17 I/O(D) H15 VCC N3 I/O(H) T11 CLK(3)
/PLLIN(1) W1 GND
B9 TMS D18 I/O(D) H16 VDED2 N4 I/O(H) T12 I/O(B) W2 PLLRST(3)
B10 CLK(6) D19 I/O(D) H17 I/O(D) N5 VCC T13 I/O(B) W3 I/O(A)
B11 I/O(E) E1 I/O(G) H18 I/O(D) N15 VCC T14 I/O(B) W4 I/O(A)
B12 I/O(E) E2 I/O(G) H19 I/O(D) N16 I/O(C) T15 I/O(B) W5 I/O(A)
B13 IOCTRL(E) E3 VCCIO(G) J1 I/O(G) N17 I/O(C) T16 I/O(B) W6 I/O(A)
B14 I/O(E) E4 I/O(F) J2 I/O(G) N18 IOCTRL(C) T17 VCCPLL(2) W7 I/O(A)
B15 I/O(E) E5 GND J3 VCCIO(G) N19 IOCTRL(C) T18 I/O(B) W8 I/O(A)
B16 I/O(E) E6 VCC J4 I/O(G) P1 I/O(H) T19 I/O(B) W9 TDI
B17 VCCPLL(1) E7 VCC J5 GND P2 I/O(H) U1 I/O(A) W10 CLK(2)/
PLLIN(2)
B18 GNDPLL(1) E8 VDED J15 VCC P3 IOCTRL(H) U2 I/O(A) W11 I/O(B)
B19 PLLOUT(0) E9 VCC J16 I/O(C) P4 INREF(H) U3 VCCPLL(3) W12 I/O(B)
C1 I/O(F) E10 GND J17 VCCIO(D) P5 VCC U4 I/O(A) W13 I/O(B)
C2 VCCPLL(0) E11 GND J18 I/O(D) P15 GND U5 VCCIO(A) W14 IOCTRL(B)
C3 I/O(F) E12 VCC J19 I/O(D) P16 I/O(C) U6 INREF(A) W15 I/O(B)
C4 I/O(F) E13 VCC K1 VDED2 P17 I/O(C) U7 I/O(A) W16 I/O(B)
C5 VCCIO(F) E14 GND K2 TCK P18 I/O(C) U8 I/O(A) W17 I/O(B)
C6 IOCTRL(F) E15 VPUMP K3 I/O(G) P19 I/O(C) U9 VCCIO(A) W18 I/O(B)
C7 I/O(F) E16 I/O(D) K4 I/O(G) R1 I/O(H) U10 CLK(0) W19 PLLOUT(1)
C8 I/O(F) E17 VCCIO(D) K5 GND R2 I/O(H) U11 VCCIO(B)
C9 VCCIO(F) E18 INREF(D) K15 GND R3 VCCIO(H) U12 I/O(B)
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© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
76
QL8250 - 484 PBGA Pinout Table
Table 49: QL8250 - 484 PBGA Pinout Table
Ball Function Ball Function Ball Function Ball Function Ball Function Ball Function
A1 NC C1 NC E1 IOCTRL(A) G1 NC J1 I/O(A) L1
CLK(4),
DEDCLK,
PLLIN(0)
A2 PLLRST(3) C2 I/O(A) E2 I/O(A) G2 NC J2 I/O(A) L2 CLK(0)
A3 I/O(A) C3 VCCPLL(3) E3 I/O(A) G3 I/O(A) J3 I/O(A) L3 CLK(2),PLLIN(2)
A4 I/O(A) C4 PLLOUT(2) E4 I/O(A) G4 I/O(A) J4 I/O(A) L4 I/O(A)
A5 I/O(A) C5 I/O(A) E5 NC G5 I/O(A) J5 I/O(A) L5 I/O(A)
A6 NC C6 NC E6 I/O(H) G6 I/O(A) J6 I/O(A) L6 I/O(A)
A7 I/O(H) C7 I/O(H) E7 NC G7 GND J7 I/O(A) L7 GND
A8 IOCTRL(H) C8 NC E8 I/O(H) G8 I/O(H) J8 VCC L8 GND
A9 I/O(H) C9 IOCTRL(H) E9 I/O(H) G9 I/O(H) J9 GND L9 GND
A10 NC C10 NC E10 I/O(H) G10 NC J10 VCC L10 GND
A11 NC C11 I/O(H) E11 VDED2 G11 I/O(G) J11 VCC L11 GND
A12 TCK C12 NC E12 I/O(G) G12 GND J12 GND L12 GND
A13 I/O(G) C13 I/O(G) E13 I/O(G) G13 NC J13 VCC L13 GND
A14 I/O(G) C14 NC E14 NC G14 NC J14 GND L14 VCC
A15 I/O(G) C15 I/O(G) E15 IOCTRL(G) G15 I/O(G) J15 VCC L15 VCC
A16 NC C16 I/O(G) E16 I/O(G) G16 VPUMP J16 I/O(F) L16 CLK(6)
A17 I/O(G) C17 NC E17 INREF(G) G17 VCCIO(F) J17 VCCIO(F) L17 VCCIO(F)
A18 I/O(G) C18 I/O(G) E18 NC G18 I/O(F) J18 I/O(F) L18 I/O(F)
A19 I/O(F) C19 I/O(F) E19 I/O(F) G19 I/O(F) J19 I/O(F) L19 CLK(8)
A20 GND C20 GNDPLL(0) E20 I/O(F) G20 I/O(F) J20 I/O(F) L20 I/O(F)
A21 PLLOUT(3) C21 I/O(F) E21 NC G21 INREF(F) J21 I/O(F) L21 NC
A22 I/O(F) C22 I/O(F) E22 I/O(F) G22 I/O(F) J22 I/O(F) L22 I/O(F)
B1 I/O(A) D1 I/O(A) F1 I/O(A) H1 I/O(A) K1 TDI M1 I/O(B)
B2 GND D2 I/O(A) F2 INREF(A) H2 I/O(A) K2 I/O(A) M2 I/O(B)
B3 GNDPLL(3) D3 I/O(A) F3 NC H3 I/O(A) K3 I/O(A) M3 I/O(B)
B4 GND D4 I/O(A) F4 I/O(A) H4 I/O(A) K4 I/O(A) M4 CLK(3),PLLIN(1)
B5 I/O(A) D5 I/O(A) F5 I/O(A) H5 IOCTRL(A) K5 I/O(A) M5 NC
B6 I/O(H) D6 I/O(H) F6 VCCIO(A) H6 VCCIO(A) K6 VCCIO(A) M6 VCCIO(B)
B7 I/O(H) D7 NC F7 VCCIO(H) H7 I/O(H) K7 NC M7 CLK(1)
B8 INREF(H) D8 I/O(H) F8 I/O(H) H8 GND K8 VCC M8 VCC
B9 I/O(H) D9 NC F9 VCCIO(H) H9 VCC K9 VCC M9 VCC
B10 I/O(H) D10 I/O(H) F10 I/O(H) H10 VCC K10 GND M10 GND
B11 I/O(H) D11 I/O(H) F11 VCCIO(H) H11 VDED K11 GND M11 GND
B12 NC D12 I/O(G) F12 VCCIO(G) H12 GND K12 GND M12 GND
B13 NC D13 I/O(G) F13 I/O(G) H13 VCC K13 GND M13 GND
B14 NC D14 I/O(G) F14 VCCIO(G) H14 VCC K14 VCC M14 GND
B15 NC D15 IOCTRL(G) F15 NC H15 GND K15 VCC M15 GND
B16 I/O(G) D16 I/O(G) F16 VCCIO(G) H16 I/O(F) K16 NC M16 GND
B17 I/O(G) D17 I/O(G) F17 NC H17 I/O(F) K17 I/O(F) M17 I/O(E)
B18 I/O(G) D18 I/O(F) F18 I/O(F) H18 NC K18 I/O(F) M18 I/O(E)
B19 PLLRST(0) D19 VCCPLL(0) F19 I/O(F) H19 I/O(F) K19 NC M19 I/O(E)
B20 I/O(F) D20 I/O(F) F20 IOCTRL(F) H20 I/O(F) K20 I/O(F) M20 CLK(7)
B21 I/O(F) D21 I/O(F) F21 I/O(F) H21 I/O(F) K21 I/O(F) M21 CLK(5),PLLIN(3)
B22 I/O(F) D22 I/O(F) F22 IOCTRL(F) H22 NC K22 NC M22 TMS
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
77
N1 NC P16 I/O(E) T9 NC V2 I/O(B) W17 NC AA10 I/O(C)
N2 I/O(B) P17 NC T10 TRSTB V3 I/O(B) W18 I/O(E) AA11 I/O(C)
N3 I/O(B) P18 I/O(E) T11 GND V4 I/O(B) W19 NC AA12 I/O(D)
N4 NC P19 NC T12 NC V5 I/O(B) W20 I/O(E) AA13 I/O(D)
N5 I/O(B) P20 I/O(E) T13 I/O(D) V6 NC W21 NC AA14 I/O(D)
N6 NC P21 I/O(E) T14 NC V7 I/O(C) W22 I/O(E) AA15 I/O(D)
N7 NC P22 I/O(E) T15 I/O(D) V8 I/O(C) Y1 I/O(B) AA16 NC
N8 VCC R1 I/O(B) T16 GND V9 NC Y2 I/O(B) AA17 NC
N9 VCC R2 INREF(B) T17 I/O(E) V10 I/O(C) Y3 VCCPLL(2) AA18 I/O(D)
N10 GND R3 I/O(B) T18 I/O(E) V11 NC Y4 I/O(C) AA19 I/O(E)
N11 GND R4 I/O(B) T19 NC V12 VDED2 Y5 I/O(C) AA20 GNDPLL(1)
N12 GND R5 I/O(B) T20 NC V13 NC Y6 I/O(C) AA21 I/O(E)
N13 GND R6 NC T21 IOCTRL(E) V14 I/O(D) Y7 I/O(C) AA22 I/O(E)
N14 VCC R7 I/O(B) T22 I/O(E) V15 I/O(D) Y8 IOCTRL(C) AB1 I/O(B)
N15 VCC R8 GND U1 IOCTRL(B) V16 INREF(D) Y9 I/O(C) AB2 GNDPLL(2)
N16 I/O(E) R9 VCC U2 I/O(B) V17 I/O(D) Y10 I/O(C) AB3 PLLRST(2)
N17 VCCIO(E) R10 VCC U3 IOCTRL(B) V18 I/O(E) Y11 I/O(D) AB4 I/O(B)
N18 I/O(E) R11 GND U4 I/O(B) V19 I/O(E) Y12 NC AB5 I/O(B)
N19 I/O(E) R12 VDED U5 I/O(B) V20 I/O(E) Y13 NC AB6 I/O(C)
N20 I/O(E) R13 VCC U6 I/O(C) V21 I/O(E) Y14 I/O(D) AB7 I/O(C)
N21 I/O(E) R14 VCC U7 VCCIO(C) V22 I/O(E) Y15 IOCTRL(D) AB8 IOCTRL(C)
N22 I/O(E) R15 GND U8 NC W1 I/O(B) Y16 I/O(D) AB9 I/O(C)
P1 NC R16 I/O(D) U9 VCCIO(C) W2 I/O(B) Y17 I/O(D) AB10 I/O(C)
P2 I/O(B) R17 VCCIO(E) U10 I/O(C) W3 I/O(B) Y18 I/O(E) AB11 NC
P3 I/O(B) R18 I/O(E) U11 VCCIO(C) W4 I/O(B) Y19 PLLOUT(0) AB12 I/O(D)
P4 I/O(B) R19 I/O(E) U12 VCCIO(D) W5 I/O(B) Y20 PLLRST(1) AB13 I/O(D)
P5 I/O(B) R20 I/O(E) U13 I/O(D) W6 I/O(C) Y21 I/O(E) AB14 NC
P6 VCCIO(B) R21 I/O(E) U14 VCCIO(D) W7 NC Y22 I/O(E) AB15 I/O(D)
P7 I/O(B) R22 I/O(E) U15 NC W8 NC AA1 TDO AB16 IOCTRL(D)
P8 VCC T1 I/O(B) U16 VCCIO(D) W9 NC AA2 PLLOUT(1) AB17 I/O(D)
P9 GND T2 I/O(B) U17 VCCIO(E) W10 NC AA3 GND AB18 I/O(D)
P10 VCC T3 I/O(B) U18 I/O(E) W11 I/O(C) AA4 I/O(B) AB19 I/O(E)
P11 GND T4 I/O(B) U19 I/O(E) W12 NC AA5 I/O(C) AB20 GND
P12 VCC T5 I/O(B) U20 IOCTRL(E) W13 I/O(D) AA6 I/O(C) AB21 VCCPLL(1)
P13 VCC T6 VCCIO(B) U21 NC W14 NC AA7 NC AB22 I/O(E)
P14 GND T7 GND U22 INREF(E) W15 I/O(D) AA8 INREF(C)
P15 VDED T8 I/O(C) V1 I/O(B) W16 NC AA9 NC
Table 49: QL8250 - 484 PBGA Pinout Table (Continued)
Ball Function Ball Function Ball Function Ball Function Ball Function Ball Function
© 2007 QuickLogic Corporation
www.quicklogic.com
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Eclipse II Family Data Sheet Rev. R
79
QL8325 - 208 PQFP Pinout Table
Table 50: QL8325 - 208 PQFP Pinout Table
Pin Function Pin Function Pin Function Pin Function Pin Function
1PLLRST(3) 43 I/O(B) 85 I/O(D) 127 CLK(5),PLLIN(3) 169 I/O(G)
2VCCPLL(3) 44 VCCIO(B) 86 VCC 128 CLK(6) 170 INREF(G)
3GND 45 I/O(B) 87 I/O(D) 129 VDED 171 I/O(G)
4GND 46 VCC 88 I/O(D) 130 CLK(7) 172 I/O(G)
5I/O(A) 47 I/O(B) 89 VCC 131 VCC 173 I/O(G)
6I/O(A) 48 I/O(B) 90 I/O(D) 132 CLK(8) 174 I/O(G)
7I/O(A) 49 GND 91 I/O(D) 133 TMS 175 VCC
8VCCIO(A) 50 TDO 92 I/O(D) 134 I/O(F) 176 I/O(G)
9I/O(A) 51 PLLOUT(1) 93 INREF(D) 135 I/O(F) 177 VCCIO(G)
10 I/O(A) 52 GNDPLL(2) 94 I/O(D) 136 I/O(F) 178 GND
11 I/O(A) 53 GND 95 I/O(D) 137 GND 179 I/O(G)
12 VCC 54 VCCPLL(2) 96 I/O(D) 138 VCCIO(F) 180 I/O(G)
13 INREF(A) 55 PLLRST(2) 97 I/O(D) 139 I/O(F) 181 I/O(G)
14 I/O(A) 56 VDED 98 VCCIO(D) 140 I/O(F) 182 VCC
15 I/O(A) 57 I/O(C) 99 I/O(D) 141 I/O(F) 183 TCK
16 I/O(A) 58 GND 100 I/O(D) 142 I/O(F) 184 VDED2
17 I/O(A) 59 I/O(C) 101 VPUMP 143 I/O(F) 185 I/O(H)
18 I/O(A) 60 VCCIO(C) 102 PLLOUT(0) 144 I/O(F) 186 I/O(H)
19 VCCIO(A) 61 I/O(C) 103 GND 145 INREF(F) 187 I/O(H)
20 I/O(A) 62 I/O(C) 104 GNDPLL(1) 146 VCC 188 GND
21 GND 63 I/O(C) 105 PLLRST(1) 147 I/O(F) 189 VCCIO(H)
22 I/O(A) 64 I/O(C) 106 VCCPLL(1) 148 I/O(F) 190 I/O(H)
23 TDI 65 I/O(C) 107 I/O(E) 149 I/O(F) 191 I/O(H)
24 CLK(0) 66 I/O(C) 108 GND 150 VCCIO(F) 192 I/O(H)
25 CLK(1) 67 I/O(C) 109 I/O(E) 151 I/O(F) 193 I/O(H)
26 VCC 68 INREF(C) 110 I/O(E) 152 I/O(F) 194 INREF(H)
27 CLK(2),PLLIN(2) 69 I/O(C) 111 VCCIO(E) 153 GND 195 VCC
28 CLK(3),PLLIN(1) 70 I/O(C) 112 I/O(E) 154 I/O(F) 196 I/O(H)
29 VDED 71 I/O(C) 113 VCC 155 PLLOUT(3) 197 I/O(H)
30 CLK(4),DEDCLK,
PLLIN(0) 72 VCCIO(C) 114 I/O(E) 156 GNDPLL(0) 198 I/O(H)
31 I/O(B) 73 I/O(C) 115 I/O(E) 157 GND 199 I/O(H)
32 I/O(B) 74 I/O(C) 116 I/O(E) 158 VCCPLL(0) 200 I/O(H)
33 GND 75 GND 117 I/O(E) 159 PLLRST(0) 201 I/O(H)
34 VCCIO(B) 76 VCC 118 INREF(E) 160 GND 202 I/O(H)
35 I/O(B) 77 I/O(C) 119 I/O(E) 161 I/O(G) 203 VCCIO(H)
36 I/O(B) 78 TRSTB 120 I/O(E) 162 VCCIO(G) 204 GND
37 I/O(B) 79 VDED2 121 I/O(E) 163 I/O(G) 205 I/O(H)
38 I/O(B) 80 I/O(D) 122 VCCIO(E) 164 I/O(G) 206 PLLOUT(2)
39 I/O(B) 81 I/O(D) 123 GND 165 VCC 207 GND
40 INREF(B) 82 I/O(D) 124 I/O(E) 166 I/O(G) 208 GNDPLL(3)
41 I/O(B) 83 GND 125 I/O(E) 167 I/O(G)
42 I/O(B) 84 VCCIO(D) 126 I/O(E) 168 I/O(G)
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
81
QL8325 - 280 LFBGA Pinout Table
Table 51: QL8325 - 280 LFBGA Pinout Table
Ball Function Ball Function Ball Function Ball Function Ball Function Ball Function
A1 PLLOUT(3) C10 CLK(5)/
PLLIN(3) E19 IOCTRL(D) K16 I/O(C) R4 I/O(H) U13 I/O(B)
A2 GNDPLL(0) C11 VCCIO(E) F1 INREF(G) K17 I/O(D) R5 GND U14 IOCTRL(B)
A3 I/O(F) C12 I/O(E) F2 IOCTRL(G) K18 I/O(C) R6 GND U15 VCCIO(B)
A4 I/O(F) C13 I/O(E) F3 I/O(G) K19 TRSTB R7 VCC U16 I/O(B)
A5 I/O(F) C14 I/O(E) F4 I/O(G) L1 I/O(H) R8 VCC U17 TDO
A6 IOCTRL(F) C15 VCCIO(E) F5 GND L2 I/O(H) R9 GND U18 PLLRST(2)
A7 I/O(F) C16 I/O(E) F15 VCC L3 VCCIO(H) R10 GND U19 I/O(B)
A8 I/O(F) C17 I/O(E) F16 IOCTRL(D) L4 I/O(H) R11 VCC V1 PLLOUT(2)
A9 I/O(F) C18 I/O(E) F17 I/O(D) L5 VCC R12 VCC V2 GNDPLL(3)
A10 CLK(7) C19 I/O(E) F18 I/O(D) L15 GND R13 VCC V3 GND
A11 I/O(E) D1 I/O(G) F19 I/O(D) L16 I/O(C) R14 VDED V4 I/O(A)
A12 I/O(E) D2 I/O(G) G1 I/O(G) L17 VCCIO(C) R15 GND V5 I/O(A)
A13 I/O(E) D3 I/O(F) G2 I/O(G) L18 I/O(C) R16 I/O(C) V6 IOCTRL(A)
A14 IOCTRL(E) D4 I/O(F) G3 IOCTRL(G) L19 I/O(C) R17 VCCIO(C) V7 I/O(A)
A15 I/O(E) D5 I/O(F) G4 I/O(G) M1 I/O(H) R18 I/O(C) V8 I/O(A)
A16 I/O(E) D6 I/O(F) G5 VCC M2 I/O(H) R19 I/O(C) V9 I/O(A)
A17 I/O(E) D7 I/O(F) G15 VCC M3 I/O(H) T1 I/O(H) V10 CLK(1)
A18 PLLRST(1) D8 I/O(F) G16 I/O(D) M4 I/O(H) T2 I/O(H) V11
CLK(4)
DEDCLK/
PLLIN(0)
A19 GND D9 CLK(8) G17 I/O(D) M5 VCC T3 I/O(A) V12 I/O(B)
B1 PLLRST(0) D10 I/O(E) G18 I/O(D) M15 VDED T4 I/O(A) V13 I/O(B)
B2 GND D11 I/O(E) G19 I/O(D) M16 INREF(C) T5 I/O(A) V14 INREF(B)
B3 I/O(F) D12 I/O(E) H1 I/O(G) M17 I/O(C) T6 IOCTRL(A) V15 I/O(B)
B4 I/O(F) D13 INREF(E) H2 I/O(G) M18 I/O(C) T7 I/O(A) V16 I/O(B)
B5 I/O(F) D14 I/O(E) H3 I/O(G) M19 I/O(C) T8 I/O(A) V17 I/O(B)
B6 INREF(F) D15 I/O(E) H4 I/O(G) N1 IOCTRL(H) T9 I/O(A) V18 GNDPLL(2)
B7 I/O(F) D16 I/O(D) H5 VCC N2 I/O(H) T10 I/O(A) V19 GND
B8 I/O(F) D17 I/O(D) H15 VCC N3 I/O(H) T11 CLK(3)
/PLLIN(1) W1 GND
B9 TMS D18 I/O(D) H16 VDED2 N4 I/O(H) T12 I/O(B) W2 PLLRST(3)
B10 CLK(6) D19 I/O(D) H17 I/O(D) N5 VCC T13 I/O(B) W3 I/O(A)
B11 I/O(E) E1 I/O(G) H18 I/O(D) N15 VCC T14 I/O(B) W4 I/O(A)
B12 I/O(E) E2 I/O(G) H19 I/O(D) N16 I/O(C) T15 I/O(B) W5 I/O(A)
B13 IOCTRL(E) E3 VCCIO(G) J1 I/O(G) N17 I/O(C) T16 I/O(B) W6 I/O(A)
B14 I/O(E) E4 I/O(F) J2 I/O(G) N18 IOCTRL(C) T17 VCCPLL(2) W7 I/O(A)
B15 I/O(E) E5 GND J3 VCCIO(G) N19 IOCTRL(C) T18 I/O(B) W8 I/O(A)
B16 I/O(E) E6 VCC J4 I/O(G) P1 I/O(H) T19 I/O(B) W9 TDI
B17 VCCPLL(1) E7 VCC J5 GND P2 I/O(H) U1 I/O(A) W10 CLK(2)/
PLLIN(2)
B18 GNDPLL(1) E8 VDED J15 VCC P3 IOCTRL(H) U2 I/O(A) W11 I/O(B)
B19 PLLOUT(0) E9 VCC J16 I/O(C) P4 INREF(H) U3 VCCPLL(3) W12 I/O(B)
C1 I/O(F) E10 GND J17 VCCIO(D) P5 VCC U4 I/O(A) W13 I/O(B)
C2 VCCPLL(0) E11 GND J18 I/O(D) P15 GND U5 VCCIO(A) W14 IOCTRL(B)
C3 I/O(F) E12 VCC J19 I/O(D) P16 I/O(C) U6 INREF(A) W15 I/O(B)
C4 I/O(F) E13 VCC K1 VDED2 P17 I/O(C) U7 I/O(A) W16 I/O(B)
C5 VCCIO(F) E14 GND K2 TCK P18 I/O(C) U8 I/O(A) W17 I/O(B)
C6 IOCTRL(F) E15 VPUMP K3 I/O(G) P19 I/O(C) U9 VCCIO(A) W18 I/O(B)
C7 I/O(F) E16 I/O(D) K4 I/O(G) R1 I/O(H) U10 CLK(0) W19 PLLOUT(1)
C8 I/O(F) E17 VCCIO(D) K5 GND R2 I/O(H) U11 VCCIO(B)
C9 VCCIO(F) E18 INREF(D) K15 GND R3 VCCIO(H) U12 I/O(B)
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
83
QL8325 - 484 PBGA Pinout Table
Table 52: QL8325 - 484 PBGA Pinout Table
Ball Function Ball Function Ball Function Ball Function Ball Function Ball Function
A1 I/O(A) C1 I/O(A) E1 IOCTRL(A) G1 I/O(A) J1 I/O(A) L1
CLK(4)
DEDCLK/
PLLIN(0)
A2 PLLRST(3) C2 I/O(A) E2 I/O(A) G2 I/O(A) J2 I/O(A) L2 CLK(0)
A3 I/O(A) C3 VCCPLL(3) E3 I/O(A) G3 I/O(A) J3 I/O(A) L3 CLK(2)/
PLLIN(2)
A4 I/O(A) C4 PLLOUT(2) E4 I/O(A) G4 I/O(A) J4 I/O(A) L4 I/O(A)
A5 I/O(A) C5 I/O(A) E5 I/O(A) G5 I/O(A) J5 I/O(A) L5 I/O(A)
A6 I/O(H) C6 I/O(H) E6 I/O(H) G6 I/O(A) J6 I/O(A) L6 I/O(A)
A7 I/O(H) C7 I/O(H) E7 N/C G7 GND J7 I/O(A) L7 GND
A8 IOCTRL(H) C8 I/O(H) E8 I/O(H) G8 I/O(H) J8 VCC L8 GND
A9 I/O(H) C9 IOCTRL(H) E9 I/O(H) G9 I/O(H) J9 GND L9 GND
A10 N/C C10 I/O(H) E10 I/O(H) G10 I/O(H) J10 VCC L10 GND
A11 N/C C11 I/O(H) E11 VDED2 G11 I/O(G) J11 VCC L11 GND
A12 TCK C12 I/O(H) E12 I/O(G) G12 GND J12 GND L12 GND
A13 I/O(G) C13 I/O(G) E13 I/O(G) G13 I/O(G) J13 VCC L13 GND
A14 I/O(G) C14 I/O(G) E14 I/O(G) G14 I/O(G) J14 GND L14 VCC
A15 I/O(G) C15 I/O(G) E15 IOCTRL(G) G15 I/O(G) J15 VCC L15 VCC
A16 I/O(G) C16 I/O(G) E16 I/O(G) G16 VPUMP J16 I/O(F) L16 CLK(6)
A17 I/O(G) C17 I/O(G) E17 INREF(G) G17 VCCIO(F) J17 VCCIO(F) L17 VCCIO(F)
A18 I/O(G) C18 I/O(G) E18 I/O(G) G18 I/O(F) J18 I/O(F) L18 I/O(F)
A19 I/O(F) C19 I/O(F) E19 I/O(F) G19 I/O(F) J19 I/O(F) L19 CLK(8)
A20 GND C20 GNDPLL(0) E20 I/O(F) G20 I/O(F) J20 I/O(F) L20 I/O(F)
A21 PLLOUT(3) C21 I/O(F) E21 I/O(F) G21 INREF(F) J21 I/O(F) L21 I/O(F)
A22 I/O(F) C22 I/O(F) E22 I/O(F) G22 I/O(F) J22 I/O(F) L22 I/O(F)
B1 I/O(A) D1 I/O(A) F1 I/O(A) H1 I/O(A) K1 TDI M1 I/O(B)
B2 GND D2 I/O(A) F2 INREF(A) H2 I/O(A) K2 I/O(A) M2 I/O(B)
B3 GNDPLL(3) D3 I/O(A) F3 I/O(A) H3 I/O(A) K3 I/O(A) M3 I/O(B)
B4 GND D4 I/O(A) F4 I/O(A) H4 I/O(A) K4 I/O(A) M4 CLK(3)/
PLLIN(1)
B5 I/O(A) D5 I/O(A) F5 I/O(A) H5 IOCTRL(A) K5 I/O(A) M5 I/O(B)
B6 I/O(H) D6 I/O(H) F6 VCCIO(A) H6 VCCIO(A) K6 VCCIO(A) M6 VCCIO(B)
B7 I/O(H) D7 I/O(H) F7 VCCIO(H) H7 I/O(H) K7 I/O(A) M7 CLK(1)
B8 INREF(H) D8 I/O(H) F8 I/O(H) H8 GND K8 VCC M8 VCC
B9 I/O(H) D9 I/O(H) F9 VCCIO(H) H9 VCC K9 VCC M9 VCC
B10 I/O(H) D10 I/O(H) F10 I/O(H) H10 VCC K10 GND M10 GND
B11 I/O(H) D11 I/O(H) F11 VCCIO(H) H11 VDED K11 GND M11 GND
B12 N/C D12 I/O(G) F12 VCCIO(G) H12 GND K12 GND M12 GND
B13 N/C D13 I/O(G) F13 I/O(G) H13 VCC K13 GND M13 GND
B14 N/C D14 I/O(G) F14 VCCIO(G) H14 VCC K14 VCC M14 GND
B15 I/O(G) D15 IOCTRL(G) F15 N/C H15 GND K15 VCC M15 GND
B16 I/O(G) D16 I/O(G) F16 VCCIO(G) H16 I/O(F) K16 I/O(F) M16 GND
B17 I/O(G) D17 I/O(G) F17 N/C H17 I/O(F) K17 I/O(F) M17 I/O(E)
B18 I/O(G) D18 I/O(F) F18 I/O(F) H18 I/O(F) K18 I/O(F) M18 I/O(E)
B19 PLLRST(0) D19 VCCPLL(0) F19 I/O(F) H19 I/O(F) K19 I/O(F) M19 I/O(E)
B20 I/O(F) D20 I/O(F) F20 IOCTRL(F) H20 I/O(F) K20 I/O(F) M20 CLK(7)
B21 I/O(F) D21 I/O(F) F21 I/O(F) H21 I/O(F) K21 I/O(F) M21 CLK(5)/
PLLIN(3)
B22 I/O(F) D22 I/O(F) F22 IOCTRL(F) H22 I/O(F) K22 I/O(F) M22 TMS
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© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
84
N1 I/O(B) P16 I/O(E) T9 N/C V2 I/O(B) W17 I/O(D) AA10 I/O(C)
N2 I/O(B) P17 I/O(E) T10 TRSTB V3 I/O(B) W18 I/O(E) AA11 I/O(C)
N3 I/O(B) P18 I/O(E) T11 GND V4 I/O(B) W19 I/O(E) AA12 I/O(D)
N4 I/O(B) P19 I/O(E) T12 N/C V5 I/O(B) W20 I/O(E) AA13 I/O(D)
N5 I/O(B) P20 I/O(E) T13 I/O(D) V6 I/O(C) W21 I/O(E) AA14 I/O(D)
N6 I/O(B) P21 I/O(E) T14 N/C V7 I/O(C) W22 I/O(E) AA15 I/O(D)
N7 I/O(B) P22 I/O(E) T15 I/O(D) V8 I/O(C) Y1 I/O(B) AA16 I/O(D)
N8 VCC R1 I/O(B) T16 GND V9 N/C Y2 I/O(B) AA17 I/O(D)
N9 VCC R2 INREF(B) T17 I/O(E) V10 I/O(C) Y3 VCCPLL(2) AA18 I/O(D)
N10 GND R3 I/O(B) T18 I/O(E) V11 I/O(C) Y4 I/O(C) AA19 I/O(E)
N11 GND R4 I/O(B) T19 I/O(E) V12 VDED2 Y5 I/O(C) AA20 GNDPLL(1)
N12 GND R5 I/O(B) T20 I/O(E) V13 N/C Y6 I/O(C) AA21 I/O(E)
N13 GND R6 I/O(B) T21 IOCTRL(E) V14 I/O(D) Y7 I/O(C) AA22 I/O(E)
N14 VCC R7 I/O(B) T22 I/O(E) V15 I/O(D) Y8 IOCTRL(C) AB1 I/O(B)
N15 VCC R8 GND U1 IOCTRL(B) V16 INREF(D) Y9 I/O(C) AB2 GNDPLL(2)
N16 I/O(E) R9 VCC U2 I/O(B) V17 I/O(D) Y10 I/O(C) AB3 PLLRST(2)
N17 VCCIO(E) R10 VCC U3 IOCTRL(B) V18 I/O(E) Y11 I/O(D) AB4 I/O(B)
N18 I/O(E) R11 GND U4 I/O(B) V19 I/O(E) Y12 I/O(D) AB5 I/O(B)
N19 I/O(E) R12 VDED U5 I/O(B) V20 I/O(E) Y13 I/O(D) AB6 I/O(C)
N20 I/O(E) R13 VCC U6 I/O(C) V21 I/O(E) Y14 I/O(D) AB7 I/O(C)
N21 I/O(E) R14 VCC U7 VCCIO(C) V22 I/O(E) Y15 IOCTRL(D) AB8 IOCTRL(C)
N22 I/O(E) R15 GND U8 N/C W1 I/O(B) Y16 I/O(D) AB9 I/O(C)
P1 I/O(B) R16 I/O(D) U9 VCCIO(C) W2 I/O(B) Y17 I/O(D) AB10 I/O(C)
P2 I/O(B) R17 VCCIO(E) U10 I/O(C) W3 I/O(B) Y18 I/O(E) AB11 I/O(C)
P3 I/O(B) R18 I/O(E) U11 VCCIO(C) W4 I/O(B) Y19 PLLOUT(0) AB12 I/O(D)
P4 I/O(B) R19 I/O(E) U12 VCCIO(D) W5 I/O(B) Y20 PLLRST(1) AB13 I/O(D)
P5 I/O(B) R20 I/O(E) U13 I/O(D) W6 I/O(C) Y21 I/O(E) AB14 I/O(D)
P6 VCCIO(B) R21 I/O(E) U14 VCCIO(D) W7 N/C Y22 I/O(E) AB15 I/O(D)
P7 I/O(B) R22 I/O(E) U15 N/C W8 I/O(C) AA1 TDO AB16 IOCTRL(D)
P8 VCC T1 I/O(B) U16 VCCIO(D) W9 I/O(C) AA2 PLLOUT(1) AB17 I/O(D)
P9 GND T2 I/O(B) U17 VCCIO(E) W10 I/O(C) AA3 GND AB18 I/O(D)
P10 VCC T3 I/O(B) U18 I/O(E) W11 I/O(C) AA4 I/O(B) AB19 I/O(E)
P11 GND T4 I/O(B) U19 I/O(E) W12 I/O(D) AA5 I/O(C) AB20 GND
P12 VCC T5 I/O(B) U20 IOCTRL(E) W13 I/O(D) AA6 I/O(C) AB21 VCCPLL(1)
P13 VCC T6 VCCIO(B) U21 I/O(E) W14 I/O(D) AA7 I/O(C) AB22 I/O(E)
P14 GND T7 GND U22 INREF(E) W15 I/O(D) AA8 INREF(C)
P15 VDED T8 I/O(C) V1 I/O(B) W16 N/C AA9 I/O(C)
Table 52: QL8325 - 484 PBGA Pinout Table (Continued)
Ball Function Ball Function Ball Function Ball Function Ball Function Ball Function
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Eclipse II Family Data Sheet Rev. R
94
Packaging Information
The Eclipse II product family packaging information is presented in Table 53.
Ordering Information
Table 53: Packaging Options
Device
Information
Device
QL8325/QL8250 QL8150 QL8050 QL8025
Pin Pb Pb-
Free Pin Pb Pb-
Free Pin Pb Pb-
Free Pin Pb Pb-
Free
Package
Definitionsa
a. BGA = Ball Grid Array
CTBGA = ChipArray® Thin Ball Grid Array
LFBGA = Low Profile Fine Pitch Ball Grid Array
PQFP = Plastic Quad Flat Pack
TFBGA = Thin Fine Pitch Ball Grid Array
TQFP = Thin Quad Flat Pack
VQFP = Very Thin Quad Flat Pack
208 PQFP
(28 mm x 28 mm)
Pitch - 0.50 mm
X X
144 TQFP
(20 mm x 20 mm)
Pitch - 0.50 mm
X X
100 VQFP
(14 mm x 14 mm)
Pitch - 0.50 mm
X X
100 VQFP
(14 mm x 14 mm)
Pitch - 0.50 mm
X X
280 LFBGA
(17 mm x 17 mm)
Pitch - 0.80 mm
X X
196 TFBGA
(12 mm x 12 mm)
Pitch - 0.80 mm
X X
101 CTBGA
(6 mm x 6 mm)
Pitch - 0.50 mm
X
144 TQFP
(20 mm x 20 mm)
Pitch - 0.50 mm
X X
484 BGA
(23 mm x 23 mm)
Pitch - 1.0 mm
X X
196 TFBG
(8 mm x 8 mm)
Pitch - 0.50 mmA
X
144 TQFP
(20 mm x 20 mm)
Pitch - 0.50 mm
X X
196 TFBGA
(12 mm x 12 mm)
Pitch - 0.80 mm
X X
208 PQFP
(28 mm x 28 mm)
Pitch - 0.50 mm
X X
196 TFBGA
(12 mm x 12 mm)
Pitch - 0.80 mm
X X
280 LFBGA
(17 mm x 17 mm)
Pitch - 0.80 mm
X X
QL 8025 -6 PV100 C
Operating Range:
C = Commercial
I = Industrial
M = Military
Package Lead Count:
PV100 (PVN100)* = 100-pin VQFP
PUN101*** = 101-ball CTBGA (0.5 mm)
PF144 (PFN144)* = 144-pin TQFP
PQ208 (PQN208)* = 208-pin PQFP
PT196 (PTN196)* = 196-ball TFBGA (0.8 mm)
PUN196** = 196-ball TFBGA (0.5 mm)
PT280 (PTN280)* = 280-ball LFBGA (0.8 mm)
PS484 (PSN484)* = 484-ball PBGA (1.0 mm)
8150,
Part Number:
8050,
8250,8325
QuickLogic Device
Speed Grade:
6 - Fast
7 - Faster
8 - Fastest
8025,
* Lead-free packaging is available, contact QuickLogic regarding availability
(see Contact Information).
** 196 TFBGA (8 mm x 8 mm, 0.5 mm pitch) is offered in lead-free packaging only.
*** 101 CTBGA (6 mm x 6 mm, 0.5 mm pitch) is offered in lead-free packaging only.
© 2007 QuickLogic Corporation
www.quicklogic.com
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Eclipse II Family Data Sheet Rev. R
95
Contact Information
Phone: (408) 990-4000 (US)
(905) 940-4149 (Canada)
+(44) 1932 57 9011 (Europe)
+(86) 21 6867 0273 (Asia – except Japan)
+(81) 45 470 5525 (Japan)
E-mail: info@quicklogic.com
Sales: www.quicklogic.com/sales
Support: www.quicklogic.com/support
Internet: www.quicklogic.com
Revision History
Revision Date Comments
A Preliminary August 2002 Brian Faith, Judd Heape, and Andreea Rotaru
Rev. A December 2002 Brian Faith and Andreea Rotaru
Rev. B January 2003 Brian Faith and Andreea Rotaru
Rev. C May 2003 Brian Faith and Kathleen Murchek
Rev. D December 2003 Brian Faith, Mehul Kochar, and Kathleen Murchek
Rev. E January 2004 Brian Faith and Kathleen Murchek
Rev. F May 2004 Brian Faith, Mehul Kochar, and Kathleen Murchek
Rev. G January 2005 Brian Faith, Mehul Kochar, and Kathleen Murchek
Rev. H March 2005
Brian Faith, Mehul Kochar, and Kathleen Murchek
Added QL8150 - 280 device.
Updated PLL information.
Added lead-free packaging information.
Rev. I July 2005
Mehul Kochar and Kathleen Murchek
Changed Max I/O from 163 to 165 in
Table 1 and Table 2 for QL8150 - 280 device.
Rev. J November 2005 Itsu Wang and Kathleen Murchek
Added QL8150 - 196 device (8 mm x 8 mm).
Rev. K February 2006 Mehul Kochar and Kathleen Murchek
Added 484 PBGA lead-free packaging to the ordering information.
Rev. L April 2006
Mehul Kochar and Kathleen Murchek
DC Characteristics table, for symbol I VCCIO
changed VCCIO = 3.6 V to VCCIO = 3.3 V.
Rev. M April 2006
Itsu Wang and Kathleen Murchek
Updated QL8150 - 196 TFBGA pinout table.
Changed Max I/Os for QL8150 - 196 TFBGA (0.5 mm) from 148 to 146.
Rev. N May 2006 Kathleen Murchek
Replaced pages 1 and 2 of 144-pin package drawing.
Rev. O December 2006 Jason Lew and Kathleen Murchek
Added QL8150 - 101 device and related information.
www.quicklogic.com
© 2007 QuickLogic Corporation
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Eclipse II Family Data Sheet Rev. R
96
Copyright and Trademark Information
Copyright © 2002-2007 QuickLogic Corporation. All Rights Reserved.
The information contained in this document is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic
Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying,
duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of
QuickLogic is prohibited.
QuickLogic and the QuickLogic logo, ViaLink, and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse II and
SpDE are trademarks of QuickLogic Corporation.
Rev. P January 2007 Jason Lew and Kathleen Murchek
Updated QL8150 - 101 pinout table.
Rev. Q April 2007
Jason Lew and Kathleen Murchek
Updated 101-pin mechanical drawing.
Updated thermal data for the PU101 package.
Updated QL8150 - 196 device max I/Os from 146 to 148.
Rev. R July 2007
Mehul Kochar and Kathleen Murchek
Updated packing options table to specify
lead-free and standard package options.
Revision Date Comments
