Order Now Product Folder Support & Community Tools & Software Technical Documents LMZ14203 SNVS632S - DECEMBER 2009 - REVISED JULY 2017 LMZ14203 SIMPLE SWITCHER(R) 6-V to 42-V, 3-A Power Module in Leaded SMT-TO Package 1 Features 2 Applications * * 1 * * * * * * * * * * * Integrated Shielded Inductor & Simple PCB Layout Flexible Start-Up Sequencing Using External SoftStart and Precision Enable Protection Against Inrush Currents and Faults Such as Input UVLO and Output Short Circuit -40C to 125C Junction Temperature Range Single Exposed Pad and Standard Pinout for Easy Mounting and Manufacturing Fast Transient Response for Powering FPGAs and ASICs Low Output Voltage Ripple Pin-to-Pin Compatible Family: - LMZ1420x (42 V Maximum 3 A, 2 A, 1 A) - LMZ1200x (20 V Maximum 3 A, 2 A, 1 A) Fully Enabled for WEBENCH(R) Power Designer Electrical Specifications - 18-W Maximum Total Output Power - Up to 3-A Output Current - Input Voltage Range 6 V to 42 V - Output Voltage Range 0.8 V to 6 V - Efficiency up to 90% Performance Benefits - Operates at High Ambient Temperature With No Thermal Derating - High Efficiency Reduces System Heat Generation - Low Radiated Emissions (Electromagnetic Interference [EMI]) Tested With EN55022 Class B Standard - Passes 10-V/m Radiated Immunity EMI Test Standard EN61000 4-3 Create a Custom Design Using the LMZ14203 With the WEBENCH(R) Power Designer Simplified Application Schematic * * Point of Load Conversions From 12-V and 24-V Input Rail Space Constrained and High Thermal Requirement Applications Negative Output Voltage Applications (See AN-2027 SNVA425) 3 Description The LMZ14203 SIMPLE SWITCHER power module is an easy-to-use step-down DC-DC solution that can drive up to 3-A load with exceptional power conversion efficiency, line and load regulation, and output accuracy. The LMZ14203 is available in an innovative package that enhances thermal performance and allows for hand or machine soldering. The LMZ14203 can accept an input voltage rail between 6 V and 42 V and deliver an adjustable and highly accurate output voltage as low as 0.8 V. The LMZ14203 only requires three external resistors and four external capacitors to complete the power solution. The LMZ14203 is a reliable and robust design with the following protection features: thermal shutdown, input UVLO, output overvoltage protection, short-circuit protection, output current limit, and allows start-up into a prebiased output. A single resistor adjusts the switching frequency up to 1 MHz. Device Information(1)(2) PART NUMBER 10.16 mm x 9.85 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Peak reflow temperature equals 245C. See SNAA214 for more details. Efficiency 12-V Input at 25C 100 95 VOUT 90 EFFICIENCY (%) FB SS EN GND VIN RON BODY SIZE (NOM) TO-PMOD (7) LMZ14203 VIN PACKAGE LMZ14203 VOUT CFF RON RFBT Enable 5.0 3.3 2.5 85 80 1.8 1.5 1.2 75 70 0.8 65 60 CIN CSS RFBB COUT 55 25C 50 0 0.5 1 1.5 2 2.5 3 OUTPUT CURRENT (A) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMZ14203 SNVS632S - DECEMBER 2009 - REVISED JULY 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 3 4 4 4 4 6 Detailed Description ............................................ 10 7.1 7.2 7.3 7.4 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics ............................................. Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 10 11 Application and Implementation ........................ 12 8.1 Application Information............................................ 12 8.2 Typical Application .................................................. 12 9 Power Supply Recommendations...................... 18 10 Layout................................................................... 18 10.1 Layout Guidelines ................................................. 10.2 Layout Example .................................................... 10.3 Power Dissipation and Board Thermal Requirements........................................................... 10.4 Power Module SMT Guidelines ............................ 18 19 20 20 11 Device and Documentation Support ................. 22 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Custom Design With WEBENCH(R) Tools ............. Device Support...................................................... Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 23 23 23 12 Mechanical, Packaging, and Orderable Information ........................................................... 23 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision R (October 2015) to Revision S Page * Changed equation 9 to put a bracket around fsw*delta VIN ................................................................................................ 15 * Changed equation 10 to put a bracket around VIN and RON2 ............................................................................................... 16 Changes from Revision Q (August 2015) to Revision R * Added this new bullet to the Power Module SMT Guidelines .............................................................................................. 20 Changes from Revision P (May 2015) to Revision Q * Page Page Changed the title of the document ......................................................................................................................................... 1 Changes from Revision O (October 2013) to Revision P Page * Added ESD Rating table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1 * Removed Easy-to-Use Pin Package image ........................................................................................................................... 1 Changes from Revision N (March 2013) to Revision O Page * Changed 12 mils................................................................................................................................................................... 18 * Changed 12 mils................................................................................................................................................................... 20 * Added Power Module SMT Guidelines................................................................................................................................. 20 2 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 LMZ14203 www.ti.com SNVS632S - DECEMBER 2009 - REVISED JULY 2017 5 Pin Configuration and Functions NDW Package 7-Pin TO-PMOD Top View Exposed Pad Connect to GND 7 6 5 4 3 2 1 VOUT FB SS GND EN RON VIN Pin Functions PIN NAME NO. TYPE DESCRIPTION EN 3 Analog Enable. Input to the precision enable comparator. Rising threshold is 1.18 V nominal; 90 mV hysteresis nominal. Maximum recommended input level is 6.5 V. FB 6 Analog Feedback. Internally connected to the regulation, overvoltage, and short-circuit comparators. The regulation reference point is 0.8 V at this input pin. Connected the feedback resistor divider between the output and ground to set the output voltage. GND 4 Ground Ground. Reference point for all stated voltages. Must be externally connected to exposed thermal pad. RON 2 Analog ON-time resistor. An external resistor between this pin and the VIN pin sets the ON-time of the application. Typical values range from 25 k to 124 k. SS 5 Analog Soft-start. An internal 8-A current source charges an external capacitor to produce the soft-start function. This node is discharged at 200 A during disable, overcurrent, thermal shutdown and internal UVLO conditions. VIN 1 Power Supply input. Nominal operating range is 6 V to 42 V . A small amount of internal capacitance is contained within the package assembly. Additional external input capacitance is required between this pin and exposed pad. VOUT 7 Power Output voltage. Output from the internal inductor. Connect the output capacitor between this pin and exposed pad. Thermal Pad -- Ground Exposed thermal pad. Internally connected to pin 4. Used to dissipate heat from the package during operation. Must be electrically connected to pin 4 external to the package. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT VIN, RON to GND -0.3 43.5 V EN, FB, SS to GND -0.3 7 V Junction Temperature 150 C Peak Reflow Case Temperature (30 sec) 245 C 150 C Storage Temperature (1) (2) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For soldering specifications, refer to the following document: Absolute Maximum Ratings for Soldering (SNOA549). Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 3 LMZ14203 SNVS632S - DECEMBER 2009 - REVISED JULY 2017 www.ti.com 6.2 ESD Ratings V(ESD) (1) VALUE UNIT 2000 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Electrostatic discharge JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN MAX VIN 6 42 V EN 0 6.5 V -40 125 C Operation Junction Temperature (1) UNIT Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics. 6.4 Thermal Information LMZ14203 THERMAL METRIC (1) NDW (TO-PMOD) UNIT 7 PINS RJA Junction-to-ambient thermal resistance RJC(top) Junction-to-case (top) thermal resistance (1) 4-layer JEDEC Printed Circuit Board, No air flow 19.3 2-layer JEDEC Printed Circuit Board, No air flow 21.5 No air flow 1.9 C/W C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics TJ = 25C unless otherwise noted. Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 24 V, Vout = 3.3 V PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT SYSTEM PARAMETERS Enable Control (3) VEN EN threshold trip point VEN-HYS VEN rising TJ = 25C over the junction temperature (TJ) range of -40C to +125C EN threshold hysteresis VEN falling SS source current VSS = 0V 1.18 1.1 1.25 90 V mV Soft Start ISS TJ = 25C over the junction temperature (TJ) range of -40C to +125C ISS-DIS 8 5 SS discharge current 11 -200 A A Current Limit ICL (1) (2) (3) 4 Current limit threshold DC average VIN= 12 V to 24 V TJ = 25C over the junction temperature (TJ) range of -40C to +125C 4.2 3.2 5.25 A Minimum and maximum limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Typical numbers are at 25C and represent the most likely parametric norm. EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See AN-2024 and layout for information on device under test. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 LMZ14203 www.ti.com SNVS632S - DECEMBER 2009 - REVISED JULY 2017 Electrical Characteristics (continued) TJ = 25C unless otherwise noted. Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 24 V, Vout = 3.3 V PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT ON/OFF Timer tON-MIN ON timer minimum pulse width 150 ns tOFF OFF timer pulse width 260 ns Regulation and Overvoltage Comparator VFB In-regulation feedback voltage VSS > 0.8 V TJ = 25C TJ = -40C to 125C over the junction temperature (TJ) IO = 3 A range of -40C to +125C VSS > 0.8 V TJ = 25C IO = 10 mA VFB-OV 0.804 0.784 0.786 0.825 0.802 0.818 V V Feedback overvoltage protection threshold 0.92 V IFB Feedback input bias current 5 nA IQ Nonswitching Input Current VFB= 0.86 V 1 mA ISD Shut Down Quiescent Current VEN= 0 V 25 A 165 C 15 C Thermal Characteristics TSD Thermal Shutdown Rising TSD-HYST Thermal shutdown hysteresis Falling PERFORMANCE PARAMETERS VO Output Voltage Ripple 8 VO/VIN Line Regulation VIN = 12 V to 42 V, IO= 3 A VO/IOUT Load Regulation VIN = 24 V Efficiency VIN = 24 V VO = 3.3 V IO = 1 A 92% Efficiency VIN = 24 V VO = 3.3 V IO = 3 A 85% Submit Documentation Feedback Product Folder Links: LMZ14203 PP 0.01% 1.5 Copyright (c) 2009-2017, Texas Instruments Incorporated mV mV/A 5 LMZ14203 SNVS632S - DECEMBER 2009 - REVISED JULY 2017 www.ti.com 6.6 Typical Characteristics Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10-F X7R Ceramic; CO = 100-F X7R Ceramic; TA = 25C for efficiency curves and waveforms. 2.5 100 95 2 3.3 2.5 1.8 1.5 1.2 80 75 DISSIPATION (W) EFFICIENCY (%) 90 85 70 0.8 65 60 3.3 2.5 1.8 1.5 1 1.5 1.2 0.8 0.5 25C 55 25C 50 0 0.5 1 1.5 2 2.5 0 3 0 0.5 1 1.5 2 2.5 3 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 1. Efficiency 6-V Input at 25C Figure 2. Dissipation 6-V Input at 25C 100 2.5 95 2 5.0 3.3 2.5 85 80 DISSIPATION (W) EFFICIENCY (%) 90 1.8 1.5 1.2 75 70 0.8 65 5.0 3.3 2.5 1.5 1.8 1 1.5 1.2 0.8 0.5 60 25 C 55 25C 50 0 0 0.5 1 1.5 2 2.5 0 3 0.5 1 1.5 2 2.5 3 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 3. Efficiency 12-V Input at 25C Figure 4. Dissipation 12-V Input at 25C 100 2.5 95 5.0 2 5.0 85 80 3.3 2.5 75 1.8 3.3 DISSIPATION (W) EFFICIENCY (%) 90 70 65 1.5 2.5 1 1.8 0.5 60 25C 55 25C 50 0 6 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 OUTPUT CURRENT(A) OUTPUT CURRENT (A) Figure 5. Efficiency 24-V Input at 25C Figure 6. Dissipation 24-V Input at 25C Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 LMZ14203 www.ti.com SNVS632S - DECEMBER 2009 - REVISED JULY 2017 Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10-F X7R Ceramic; CO = 100-F X7R Ceramic; TA = 25C for efficiency curves and waveforms. 2.5 100 5.0 95 2 3.3 5.0 85 DISSIPATION (W) EFFICIENCY (%) 90 3.3 80 75 70 65 1.5 1 0.5 60 25C 55 25C 50 0 0 0.5 1 1.5 2 2.5 0 3 0.5 1 1.5 2 2.5 3 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 7. Efficiency 36-V Input at 25C Figure 8. Dissipation 36-V Input at 25C 100 3 95 2.5 85 DISSIPATION (W) EFFICIENCY (%) 90 3.3 2.5 80 75 1.8 1.5 1.2 70 65 60 1.5 1.5 1.2 1 0.8 85C 85C 0 50 0.5 0 1.8 0.5 0.8 55 3.3 2.5 2 1 1.5 2 0 3 2.5 0.5 1 1.5 2.5 3 Figure 10. Dissipation 6-V Input at 85C Figure 9. Efficiency 6-V Input at 85C 100 3 95 5.0 2.5 85 5.0 80 3.3 2.5 75 DISSIPATION (W) 90 EFFICIENCY (%) 2 OUTPUT CURRENT (A) OUTPUT CURRENT (A) 1.8 1.5 70 1.2 65 60 0.8 3.3 2.5 2 1.8 1.5 1.5 1.2 1 0.8 0.5 85C 55 85C 50 0 0.5 0 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 11. Efficiency 8-V Input at 85C Figure 12. Dissipation 8-V Input at 85C Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 7 LMZ14203 SNVS632S - DECEMBER 2009 - REVISED JULY 2017 www.ti.com Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10-F X7R Ceramic; CO = 100-F X7R Ceramic; TA = 25C for efficiency curves and waveforms. 3 100 95 2.5 90 DISSIPATION (W) 85 EFFICIENCY (%) 5.0 3.3 5.0 3.3 80 2.5 1.8 1.5 75 70 1.2 65 2 2.5 1.8 1.5 1.5 1.2 1 0.8 0.8 60 0.5 85C 55 85C 50 0 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 3 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 14. Dissipation 12-V Input at 85C Figure 13. Efficiency 12-V Input at 85C 3 100 95 5.0 2.5 90 3.3 5.0 85 DISSIPATION (W) EFFICIENCY (%) 2.5 3.3 80 2.5 75 1.8 70 65 60 2 1.5 2.5 1.8 1 0.5 85C 55 85C 50 0 0.5 0 1 1.5 2 2.5 0 3 0.5 1 1.5 2 2.5 3 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 15. Efficiency 24-V Input at 85C Figure 16. Dissipation 24-V Input at 85C 100 3 5.0 95 2.5 85 5.0 80 3.3 DISSIPATION (W) EFFICIENCY (%) 90 75 70 65 60 1.5 1 0.5 55 85C 0 0.5 85C 0 50 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 17. Efficiency 36-V Input at 85C 8 3.3 2 Submit Documentation Feedback Figure 18. Dissipation 36-V Input at 85C Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 LMZ14203 www.ti.com SNVS632S - DECEMBER 2009 - REVISED JULY 2017 Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10-F X7R Ceramic; CO = 100-F X7R Ceramic; TA = 25C for efficiency curves and waveforms. 3.36 OUTPUT VOLTAGE (V) 3.34 3.32 20 3.3 12 15 3.28 42 36 8 6 25C 3.26 0 0.5 1 1.5 2 2.5 3 OUTPUT CURRENT (A) Figure 20. Output Ripple 24 VIN 3.3 VO 3 A, BW = 200 MHz Figure 19. Line and Load Regulation at 25C 3.5 12Vin OUTPUT CURRENT (A) 3 2.5 36VIN 6Vin 2 24Vin 6Vin 1.5 1 12Vin JA = 19.6C/W 0.5 VOUT = 3.3V 0 50 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (C) Figure 21. Transient Response 24 VIN 3.3 VO 0.6-A to 3-A Step Figure 22. Thermal Derating VOUT = 3.3 V Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 9 LMZ14203 SNVS632S - DECEMBER 2009 - REVISED JULY 2017 www.ti.com 7 Detailed Description 7.1 Overview The LMZ14203 power module is an easy-to-use step-down DC-DC solution that can drive up to 3-A load with exceptional power conversion efficiency, line and load regulation, and output accuracy. 7.2 Functional Block Diagram Vin VIN 1 Linear reg Cvcc 5 CIN SS Css CBST 3 EN RON 2 VOUT 7 RON Timer CFF 6 6.8 eH VO Co FB RFBT RFBB 0.47 eF Regulator IC Internal Passives GND 4 7.3 Feature Description 7.3.1 COT Control Circuit Overview Constant ON-Time control is based on a comparator and an ON-time one shot, with the output voltage feedback compared with an internal 0.8-V reference. If the feedback voltage is below the reference, the main MOSFET is turned on for a fixed ON-time determined by a programming resistor RON. RON is connected to VIN such that ONtime is reduced with increasing input supply voltage. Following this ON-time, the main MOSFET remains off for a minimum of 260 ns. If the voltage on the feedback pin falls below the reference level again the ON-time cycle is repeated. Regulation is achieved in this manner. 7.3.2 Output Overvoltage Comparator The voltage at FB is compared to a 0.92-V internal reference. If FB rises above 0.92 V the ON-time is immediately terminated. This condition is known as overvoltage protection (OVP). It can occur if the input voltage is increased very suddenly or if the output load is decreased very suddenly. Once OVP is activated, the top MOSFET ON-times will be inhibited until the condition clears. Additionally, the synchronous MOSFET will remain on until inductor current falls to zero. 7.3.3 Current Limit Current limit detection is carried out during the OFF-time by monitoring the current in the synchronous MOSFET. Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 4.2 A (typical) the current limit comparator disables the start of the next ON-time period. The next switching cycle will occur only if the FB input is less than 0.8 V and the inductor current has decreased below 4.2 A. Inductor current is monitored during the period of time the synchronous MOSFET is conducting. So long as inductor current exceeds 4.2 A, further ON-time intervals for the top MOSFET will not occur. Switching frequency is lower during current limit due to the longer OFF-time. NOTE Current limit is dependent on both duty cycle and temperature. 10 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 LMZ14203 www.ti.com SNVS632S - DECEMBER 2009 - REVISED JULY 2017 Feature Description (continued) 7.3.4 Thermal Protection The junction temperature of the LMZ14203 should not be allowed to exceed its maximum ratings. Thermal protection is implemented by an internal Thermal Shutdown circuit which activates at 165 C (typical) causing the device to enter a low power standby state. In this state the main MOSFET remains off causing VO to fall, and additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for accidental device overheating. When the junction temperature falls back below 145C (typical hysteresis = 20 C) the SS pin is released, VO rises smoothly, and normal operation resumes. Applications requiring maximum output current especially those at high input voltage may require application derating at elevated temperatures. 7.3.5 Zero Coil Current Detection The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which inhibits the synchronous MOSFET when its current reaches zero until the next ON-time. This circuit enables the DCM operating mode, which improves efficiency at light loads. 7.3.6 Prebiased Start-Up The LMZ14203 will properly start up into a prebiased output. This start-up situation is common in multiple rail logic applications where current paths may exist between different power rails during the start-up sequence. Figure 23 is a scope capture that shows proper behavior during this event. Figure 23. Prebiased Start-Up 7.4 Device Functional Modes 7.4.1 Discontinuous Conduction and Continuous Conduction Modes At light-load, the regulator operates in discontinuous conduction mode (DCM). With load currents above the critical conduction point, it operates in continuous conduction mode (CCM). When operating in DCM the switching cycle begins at zero amps inductor current; increases up to a peak value, and then recedes back to zero before the end of the OFF-time. During the period of time that inductor current is zero, all load current is supplied by the output capacitor. The next ON-time period starts when the voltage on the FB pin falls below the internal reference. The switching frequency is lower in DCM and varies more with load current as compared to CCM. Conversion efficiency in DCM is maintained because conduction and switching losses are reduced with the smaller load and lower switching frequency. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 11 LMZ14203 SNVS632S - DECEMBER 2009 - REVISED JULY 2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LMZ14203 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 3 A. The following design procedure can be used to select components for the LMZ14203. Alternately, the WEBENCH software may be used to generate complete designs. When generating a design, the WEBENCH software uses iterative design procedure and accesses comprehensive databases of components. For more details, see www.ti.com. 8.2 Typical Application U1 EP Enable VIN VOUT FB SS GND EN 3.3VO @ 3A 7 6 5 4 VIN 2 1 3 RON LMZ14203TZ 8V to 42V RENT 68.1k CFF 0.022 PF RFBT 3.32k RON 61.9k RENB 11.8k CIN1 1 PF CIN2 10 PF CSS 0.022 PF RFBB 1.07k CO1 1 PF CO2 100 PF Figure 24. Evaluation Board Schematic Diagram 8.2.1 Design Requirements For this example the following application parameters exist. * VIN Range = Up to 42 V * VOUT = 0.8 V to 5 V * IOUT = 3 A Please refer to Table 1 for more information. 12 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 LMZ14203 www.ti.com SNVS632S - DECEMBER 2009 - REVISED JULY 2017 Table 1. Component Value Combinations VOUT (V) RFBT (k) VIN (V) RFBB (k) RDS(on) (k) 1.07 61.9 42 47.5 30 100 MIN MAX 7.5 42 5 5.62 3.3 3.32 2.5 2.26 1.8 1.87 1.5 1.5 1 1.13 28 1.2 4.22 8.45 22.6 19 0.8 0 39.2 24.9 18 32.4 25 6 21 Table 2. List of Materials Ref Des Description Case Size Manufacturer U1 SIMPLE SWITCHER PFM-7 Texas Instruments Manufacturer P/N LMZ14203TZ CIN1 1 F, 50 V, X7R 1206 Taiyo Yuden UMK316B7105KL-T CIN2 10 F, 50 V, X7R 1210 Taiyo Yuden UMK325BJ106MM-T CO1 1 F, 50 V, X7R 1206 Taiyo Yuden UMK316B7105KL-T CO2 100 F, 6.3 V, X7R 1210 Taiyo Yuden JMK325BJ107MM-T RFBT 3.32 k 0603 Vishay Dale CRCW06033K32FKEA RFBB 1.07 k 0603 Vishay Dale CRCW06031K07FKEA RON 61.9 k 0603 Vishay Dale CRCW060361k9FKEA RENT 68.1 k 0603 Vishay Dale CRCW060368k1FKEA RENB 11.8 k 0603 Vishay Dale CRCW060311k8FKEA CFF 22 nF, 10%, X7R, 16 V 0603 TDK C1608X7R1H223K CSS 22 nF, 10%, X7R, 16 V 0603 TDK C1608X7R1H223K 8.2.2 Detailed Design Procedure 8.2.2.1 Custom Design With WEBENCH(R) Tools Click here to create a custom design using the LMZ14203 device with the WEBENCH(R) Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: * Run electrical simulations to see important waveforms and circuit performance * Run thermal simulations to understand board thermal performance * Export customized schematic and layout into popular CAD formats * Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 8.2.2.2 Design Steps for the LMZ14203 Application The LMZ14203 is fully supported by WEBENCH and offers the following: Component selection, electrical and thermal simulations as well as the build-it board for a reduction in design time. The following list of steps can be used to manually design the LMZ14203 application. 1. Select minimum operating VIN with enable divider resistors 2. Program VO with divider resistor selection 3. Program turnon time with soft-start capacitor selection Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 13 LMZ14203 SNVS632S - DECEMBER 2009 - REVISED JULY 2017 4. 5. 6. 7. 8. www.ti.com Select CO Select CIN Set operating frequency with RON Determine module dissipation Lay out PCB for required thermal performance 8.2.2.2.1 Enable Divider, RENT and RENB Selection The enable input provides a precise 1.18-V band-gap rising threshold to allow direct logic drive or connection to a voltage divider from a higher enable voltage such as VIN. The enable input also incorporates 90 mV (typical) of hysteresis resulting in a falling threshold of 1.09 V. The maximum recommended voltage into the EN pin is 6.5 V. For applications where the midpoint of the enable divider exceeds 6.5 V, a small Zener diode can be added to limit this voltage. The function of this resistive divider is to allow the designer to choose an input voltage below which the circuit will be disabled. This implements the feature of programmable under voltage lockout. This is often used in battery powered systems to prevent deep discharge of the system battery. It is also useful in system designs for sequencing of output rails or to prevent early turnon of the supply as the main input voltage rail rises at powerup. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems such as 24-V AC/DC systems where a lower boundary of operation should be established. In the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the LMZ14203 output rail. The two resistors should be chosen based on the following ratio: RENT / RENB = (VIN UVLO / 1.18 V) - 1 (1) The LMZ14203 demonstration and evaluation boards use 11.8 k for RENB and 68.1 k for RENT resulting in a rising UVLO of 8 V. This divider presents 6.25 V to the EN input when the divider input is raised to 42 V. The EN pin is internally pulled up to VIN and can be left floating for always-on operation. 8.2.2.2.2 Output Voltage Selection Output voltage is determined by a divider of two resistors connected between VO and ground. The midpoint of the divider is connected to the FB input. The voltage at FB is compared to a 0.8V internal reference. In normal operation an ON-time cycle is initiated when the voltage on the FB pin falls below 0.8 V. The main MOSFET ONtime cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8 V. As long as the voltage at FB is above 0.8 V, ON-time cycles will not occur. The regulated output voltage determined by the external divider resistors RFBT and RFBB is: VO = 0.8 V x (1 + RFBT / RFBB) (2) Rearranging terms; the ratio of the feedback resistors for a desired output voltage is: RFBT / RFBB = (VO / 0.8 V) - 1 (3) These resistors should be chosen from values in the range of 1 k to 10 k. For VO = 0.8 V the FB pin can be connected to the output directly so long as an output preload resistor remains that draws more than 20 uA. Converter operation requires this minimum load to create a small inductor ripple current and maintain proper regulation when no load is present. A feed-forward capacitor is placed in parallel with RFBT to improve load step transient response. Its value is usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for best transient response and minimum output ripple. A table of values for RFBT , RFBB , CFF and RON is included in the applications schematic. 8.2.2.2.3 Soft-Start Capacitor Selection Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to prevent overshoot. Upon turnon, after all UVLO conditions have been passed, an internal 8-uA current source begins charging the external soft-start capacitor. The soft-start time duration to reach steady-state operation is given by the formula: tSS = VREF x CSS / Iss = 0.8 V x CSS / 8 uA 14 (4) Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 LMZ14203 www.ti.com SNVS632S - DECEMBER 2009 - REVISED JULY 2017 This equation can be rearranged as follows: CSS = tSS x 8 A / 0.8 V (5) Use of a 0.022-F capacitor results in 2.2 ms soft-start duration. This is recommended as a minimum value. As the soft-start input exceeds 0.8 V the output of the power stage will be in regulation. The soft-start capacitor continues charging until it reaches approximately 3.8 V on the SS pin. Voltage levels between 0.8 V and 3.8 V have no effect on other circuit operation. Note the following conditions will reset the soft-start capacitor by discharging the SS input to ground with an internal 200-A current sink. * * * * The enable input being pulled low Thermal shutdown condition Overcurrent fault Internal VCC UVLO (Approx 4-V input to VIN) 8.2.2.2.4 CO Selection None of the required CO output capacitance is contained within the module. At a minimum, the output capacitor must meet the worst case minimum ripple current rating of 0.5 x ILR P-P, as calculated in Equation 12 below. Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10 F is generally required. Experimentation will be required if attempting to operate with a minimum value. Ceramic capacitors or other low ESR types are recommended. See AN-2024 SNVA422 for more detail. The following equation provides a good first pass approximation of CO for load transient requirements: CO ISTEP x VFB x L x VIN / (4 x VO x (VIN - VO) x VOUT-TRAN) (6) Solving: CO 3 A x 0.8 V x 6.8 H x 24 V / (4 x 3.3 V x ( 24 V - 3.3 V) x 33 mV) 43 F (7) The LMZ14203 demonstration and evaluation boards are populated with a 100-uF 6.3-V X5R output capacitor. Locations for extra output capacitors are provided. 8.2.2.2.5 CIN Selection The LMZ14203 module contains an internal 0.47-F input ceramic capacitor. Additional input capacitance is required external to the module to handle the input ripple current of the application. This input capacitance should be very close to the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. Worst-case input ripple current rating is dictated by the equation: I(CIN(RMS)) 1 /2 x IO x (D / 1 - D) where * D VO / VIN (8) (As a point of reference, the worst case ripple current will occur when the module is presented with full load current and when VIN = 2 x VO). Recommended minimum input capacitance is 10uF X7R ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. TI also recommends to pay attention to the voltage and temperature deratings of the capacitor selected. Note ripple current rating of ceramic capacitors may be missing from the capacitor data sheet and you may need to contact the capacitor manufacturer for this rating. If the system design requires a certain minimum value of input ripple voltage VIN be maintained then the following equation may be used. CIN IO x D x (1-D) / ( fSW-CCM x VIN) (9) If VIN is 1% of VIN for a 24-V input to 3.3-V output application this equals 240 mV and fSW = 400 kHz. CIN 3 A x 3.3 V / 24 V x (1- 3.3 V / 24 V) / (400000 x 0.240 V) 3.7 F Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 15 LMZ14203 SNVS632S - DECEMBER 2009 - REVISED JULY 2017 www.ti.com 8.2.2.2.6 Discontinuous Conduction and Continuous Conduction Mode Selection Operating frequency in DCM can be calculated as follows: fSW(DCM) VO x (VIN-1) x 6.8 H x 1.18 x 1020 x IO/ ((VIN-VO) x RON2) (10) In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the OFF-time. The switching frequency remains relatively constant with load current and line voltage variations. The CCM operating frequency can be calculated using Equation 7 above. Following is a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes. Figure 25. CCM and DCM Operating Modes VIN = 24 V, VO = 3.3 V, IO = 3 A/0.4 A 2 s/div The approximate formula for determining the DCM/CCM boundary is as follows: IDCB VO x (VIN- VO) / (2 x 6.8 H x fSW(CCM) x VIN) (11) Following is a typical waveform showing the boundary condition. Figure 26. Transition Mode Operation VIN = 24 V, VO = 3.3 V, IO = 0.5 A 2 s/div The inductor internal to the module is 6.8 H. This value was chosen as a good balance between low and high input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple current (ILR). ILR can be calculated with: ILR P-P = VO x (VIN- VO) / (6.8H x fSW x VIN) where * VIN is the maximum input voltage and fSW is determined from Equation 13. (12) If the output current IO is determined by assuming that IO = IL, the higher and lower peak of ILR can be determined. Be aware that the lower peak of ILR must be positive if CCM operation is required. 8.2.2.2.7 RON Resistor Selection Many designs will begin with a desired switching frequency in mind. For that purpose the following equation can be used. fSW(CCM) VO / (1.3 x 10-10 x RON) (13) This can be rearranged as 16 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 LMZ14203 www.ti.com SNVS632S - DECEMBER 2009 - REVISED JULY 2017 RON VO / (1.3 x 10 -10 x fSW(CCM)) (14) The selection of RON and fSW(CCM) must be confined by limitations in the ON-time and OFF-time for the COT Control Circuit Overview section. The ON-time of the LMZ14203 timer is determined by the resistor RON and the input voltage VIN. It is calculated as follows: tON = (1.3 x 10-10 x RON) / VIN (15) The inverse relationship of tON and VIN gives a nearly constant switching frequency as VIN is varied. RON should be selected such that the ON-time at maximum VIN is greater than 150 ns. The ON-timer has a limiter to ensure a minimum of 150 ns for tON. This limits the maximum operating frequency, which is governed by the following equation: fSW(MAX) = VO / (VIN(MAX) x 150 ns) (16) This equation can be used to select RON if a certain operating frequency is desired so long as the minimum ONtime of 150 ns is observed. The limit for RON can be calculated as follows: RON VIN(MAX) x 150 ns / (1.3 x 10 -10) (17) If RON calculated in Equation 14 is less than the minimum value determined in Equation 17 a lower frequency should be selected. Alternatively, VIN(MAX) can also be limited to keep the frequency unchanged. NOTE The minimum OFF-time of 260 ns limits the maximum duty ratio. Larger RON (lower FSW) should be selected in any application requiring large duty ratio. 8.2.3 Application Curves 100 3.5 95 3 OUTPUT CURRENT (A) EFFICIENCY (%) 90 85 80 75 70 65 2.5 2 1.5 1 60 0.5 55 25C 50 0 0.5 1 1.5 2 2.5 3 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (C) OUTPUT CURRENT(A) Figure 27. Efficiency VIN = 24 V VOUT = 5.0 V Figure 28. Thermal Derating Curve VIN = 24 V, VOUT = 5.0 V Figure 29. Radiated Emissions (EN 55022 Class B) From Evaluation Board Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 17 LMZ14203 SNVS632S - DECEMBER 2009 - REVISED JULY 2017 www.ti.com 9 Power Supply Recommendations The LMZ14203 device is designed to operate from an input voltage supply range between 4.5 V and 42 V. This input supply should be well regulated and able to withstand maximum input current and maintain a stable voltage. The resistance of the input supply rail should be low enough that an input current transient does not cause a high enough drop at the LMZ14203 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is located more than a few inches from the LMZ14203, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-F or 100-F electrolytic capacitor is a typical choice. 10 Layout 10.1 Layout Guidelines PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1. Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PCB layout. The high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on the output pin if the input capacitor (Cin1) is placed at a distance away from the LMZ14203. Therefore place CIN1 as close as possible to the LMZ14203 VIN and GND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor should consist of a localized top side plane that connects to the GND exposed pad (EP). 2. Have a single point ground. The ground connections for the feedback, soft-start, and enable components should be routed to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP. 3. Minimize trace length to the FB pin. Both feedback resistors, RFBT and RFBB, and the feed forward capacitor CFF, should be close to the FB pin. Since the FB node is high impedance, maintain the copper area as small as possible. The trace are from RFBT, RFBB, and CFF should be routed away from the body of the LMZ14203 to minimize noise. 4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and provide optimum output accuracy. 5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 x 6 via array with minimum via diameter of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125C. 18 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 LMZ14203 www.ti.com SNVS632S - DECEMBER 2009 - REVISED JULY 2017 10.2 Layout Example VIN VO LMZ14203 VOUT VIN High di/dt Cin1 CO1 GND Loop 2 Loop 1 Figure 30. Minimize Area of Current Loops in Buck Module Top View Thermal Vias GND GND EPAD 1 2 3 4 5 6 7 VIN EN RON SS GND VOUT FB CIN VIN COUT VOUT RON RENT RFBT CSS RENB CFF RFBB GND Plane Figure 31. PCB Layout Guide Figure 32. EVM Board Layout - Top View Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 19 LMZ14203 SNVS632S - DECEMBER 2009 - REVISED JULY 2017 www.ti.com Layout Example (continued) Figure 33. EVM Board Layout - Bottom View 10.3 Power Dissipation and Board Thermal Requirements For the design case of VIN = 24 V, VO = 3.3 V, IO = 3 A, TAMB(MAX) = 85C , and TJUNCTION = 125C, the device must see a thermal resistance from case to ambient of: RCA< (TJ-MAX - TAMB(MAX)) / PIC-LOSS - RJC (18) Given the typical thermal resistance from junction to case to be 1.9C/W. Use the 85C power dissipation curves in the Typical Characteristics section to estimate the PIC-LOSS for the application being designed. In this application it is 2.25 W. RCA < (125 - 85) / 2.25 W - 1.9 = 15.8 To reach RCA = 15.8, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a good estimate of the required board area covered by 1 oz. copper on both the top and bottom metal layers is: Board Area_cm2 > 500C x cm2/W / RCA (19) As a result, approximately 31.5 square cm of 1 oz copper on top and bottom layers is required for the PCB design. The PCB copper heat sink must be connected to the exposed pad. Approximately thirty six, 8-mil thermal vias spaced 59 mils (1.5 mm) apart must connect the top copper to the bottom copper. For an example of a high thermal performance PCB layout, refer to the Evaluation Board application note AN-2024 SNVA422. 10.4 Power Module SMT Guidelines The recommendations below are for a standard module surface mount assembly * Land Pattern - Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads * Stencil Aperture - For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land pattern - For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation * Solder Paste - Use a standard SAC Alloy such as SAC 305, type 3 or higher * Stencil Thickness - 0.125 mm to 0.15 mm * Reflow - Refer to solder paste supplier recommendation and optimized per board size and density * Refer to AN SNAA214 for Reflow information. * Maximum number of reflows allowed is one 20 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 LMZ14203 www.ti.com SNVS632S - DECEMBER 2009 - REVISED JULY 2017 Power Module SMT Guidelines (continued) Figure 34. Sample Reflow Profile Table 3. Sample Reflow Profile Table Probe Max Temp (C) Reached Max Temp Time Above 235C Reached 235C Time Above 245C Reached 245C Time Above 260C Reached 260C #1 242.5 6.58 0.49 6.39 #2 242.5 7.10 0.55 6.31 0.00 - 0.00 - 0.00 7.10 0.00 - #3 241.0 7.09 0.42 6.44 0.00 - 0.00 - Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 21 LMZ14203 SNVS632S - DECEMBER 2009 - REVISED JULY 2017 www.ti.com 11 Device and Documentation Support 11.1 Custom Design With WEBENCH(R) Tools Click here to create a custom design using the LMZ14203 device with the WEBENCH(R) Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: * Run electrical simulations to see important waveforms and circuit performance * Run thermal simulations to understand board thermal performance * Export customized schematic and layout into popular CAD formats * Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 11.2 Device Support 11.2.1 Development Support WEBENCH software uses an iterative design procedure and accesses comprehensive databases of components. For more details, go to www.ti.com/webench. 11.2.2 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.3 Documentation Support 11.3.1 Related Documentation This section contains additional document support. * Design Summary LMZ1 and LMZ2 Power Modules, SNAA214 * Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module, SNVA425 * Evaluation Board Application Note AN-2024, SNVA422 * Absolute Maximum Ratings for Soldering, SNOA549 11.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and 22 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 LMZ14203 www.ti.com SNVS632S - DECEMBER 2009 - REVISED JULY 2017 Community Resources (continued) contact information for technical support. 11.6 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.7 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.8 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LMZ14203 23 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMZ14203TZ-ADJ/NOPB ACTIVE TO-PMOD NDW 7 250 RoHS & Green SN Level-3-245C-168 HR -40 to 125 LMZ14203 TZ-ADJ LMZ14203TZE-ADJ/NOPB ACTIVE TO-PMOD NDW 7 45 RoHS & Green SN Level-3-245C-168 HR -40 to 125 LMZ14203 TZ-ADJ LMZ14203TZX-ADJ/NOPB ACTIVE TO-PMOD NDW 7 500 RoHS & Green SN Level-3-245C-168 HR -40 to 125 LMZ14203 TZ-ADJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 27-May-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device LMZ14203TZ-ADJ/NOPB LMZ14203TZX-ADJ/NOP B Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TOPMOD NDW 7 250 330.0 24.4 10.6 14.22 5.0 16.0 24.0 Q2 TOPMOD NDW 7 500 330.0 24.4 10.6 14.22 5.0 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-May-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMZ14203TZ-ADJ/NOPB TO-PMOD NDW 7 250 367.0 367.0 45.0 LMZ14203TZX-ADJ/NOPB TO-PMOD NDW 7 500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA NDW0007A BOTTOM SIDE OF PACKAGE TOP SIDE OF PACKAGE TZA07A (Rev D) www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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