(R) Technology SiI 1178 Dual Link PanelLink Transmitter Data Sheet Document # SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet Silicon Image, Inc. SiI-DS-0127-A September 2005 Application Information To obtain the most updated Application Notes and other useful information for your design, contact your local Silicon Image sales office. Please also visit the Silicon Image web site at www.siliconimage.com. Copyright Notice This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc. Trademark Acknowledgment Silicon Image, the Silicon Image logo, PanelLink(R) and the PanelLink(R) Digital logo are registered trademarks of Silicon Image, Inc. TMDSTM is a trademark of Silicon Image, Inc. VESA(R) is a registered trademark of the Video Electronics Standards Association. All other trademarks are the property of their respective holders. Disclaimer This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Revision History Revision Date Comment A 09/20/05 Data Sheet (c) 2005 Silicon Image ii SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet TABLE OF CONTENTS Functional Description .................................................................................................................................... 2 Data Capture Logic ..................................................................................................................................... 2 PanelLink TMDS Core ................................................................................................................................ 2 I2C Slave Machine, Registers, and Configuration Logic............................................................................. 3 Hot Plug Logic............................................................................................................................................. 3 Electrical Specifications .................................................................................................................................. 4 Absolute Maximum Conditions ................................................................................................................... 4 Normal Operating Conditions ..................................................................................................................... 4 DC Specifications........................................................................................................................................ 5 AC Specifications ........................................................................................................................................ 6 Timing Diagrams ......................................................................................................................................... 7 Input Timing Diagrams ................................................................................................................................ 7 Pin Descriptions.............................................................................................................................................. 9 Input Pins .................................................................................................................................................... 9 Status Pin .................................................................................................................................................. 10 Configuration/Programming Pins.............................................................................................................. 10 Input Voltage Reference Pin ..................................................................................................................... 10 Output and Differential Signal Data Pins .................................................................................................. 11 Dual Link Configuration and Control Pin................................................................................................... 11 Power and Ground Pins............................................................................................................................ 11 Feature Information ...................................................................................................................................... 12 I2C Interface .............................................................................................................................................. 12 I2C Register Mapping ................................................................................................................................ 13 RESET Description ................................................................................................................................... 15 Dual Zone PLL .......................................................................................................................................... 15 Manual Zone Control............................................................................................................................. 15 Automatic Zone Control......................................................................................................................... 16 Input Signal Swing and Clocking Selection .............................................................................................. 16 EDGE Selection ........................................................................................................................................ 17 Data De-skew DK[1:0] Feature ................................................................................................................. 18 Dual Link Applications............................................................................................................................... 19 Master Configuration ............................................................................................................................. 20 Slave Configuration ............................................................................................................................... 20 Master-Slave Skew Control ...................................................................................................................... 20 Data Mapping Modes for Dual Link .............................................................................................................. 21 Dual Link I2C Programming Sequence Example ...................................................................................... 23 Timing Diagrams ....................................................................................................................................... 23 Enabling Hot Plug Detection Mode........................................................................................................... 24 Design Recommendations ........................................................................................................................... 25 Overview of Pin Differences...................................................................................................................... 25 1.5V to 3.3V I2C Bus Level-Shifting .......................................................................................................... 25 ESD Protection on TMDS Output Pins ..................................................................................................... 26 Voltage Ripple Regulation......................................................................................................................... 27 PCB Ground Planes.................................................................................................................................. 27 Decoupling Capacitors.............................................................................................................................. 27 Source Termination Resistors on Differential Outputs .............................................................................. 28 Transmitter Layout .................................................................................................................................... 30 Recommended Circuits............................................................................................................................. 32 Packaging ..................................................................................................................................................... 33 E-pad Enhancement ................................................................................................................................. 33 Determining Heat Dissipation Requirements ........................................................................................ 33 Designing with E-pad Landing Area ...................................................................................................... 34 48-pin TSSOP Package ............................................................................................................................ 35 Ordering Information ................................................................................................................................. 35 SiI-DS-0127-A iii SiI 1178 PanelLink Transmitter Data Sheet LIST OF TABLES Table 1. General I2C Register Definitions ..................................................................................................... 14 Table 2. Dual Link I2C Register Definitions................................................................................................... 15 Table 3. Dual Zone PLL I2C Control Register Bits ........................................................................................ 16 Table 4. DK[1:0] Increments and Effect on Setup and Hold times .............................................................. 18 Table 5. Dual Link Data Mapping - High Resolution Application ................................................................. 21 Table 6. Dual Link Data Mapping - 10-bit Deep Color Application .............................................................. 22 Table 7. Dual Link Programming Sequence and Flowchart ......................................................................... 23 Table 8. Recommended Components for 1-2MHz Noise Suppression........................................................ 28 Table 9. DVI Connector to SiI 1178 Tx for Dual Link Pin Connection .......................................................... 31 Table 10. Allowed Power Consumption vs. E-Pad Solder State................................................................... 34 LIST OF FIGURES Figure 1. SiI 1178 Tx Pin Diagram.................................................................................................................. 1 Figure 2. Functional Block Diagram ............................................................................................................... 2 Figure 3. Clock Cycle/High/Low Times in High Swing Mode ......................................................................... 7 Figure 4. Differential Transition Times ............................................................................................................ 7 Figure 5. VSYNC, HSYNC Delay Times to DE .................................................................................................... 7 Figure 6. DE High/Low Times......................................................................................................................... 7 Figure 7. Low Swing Control and Data Setup/Hold Times to IDCK Differential Clock ................................. 8 Figure 8. High Swing Control and Data Setup/Hold Times to IDCK+ ............................................................ 8 Figure 9. I2C Data Valid Delay (driving Read Cycle data) .............................................................................. 8 Figure 10. RST# Minimum Timing .................................................................................................................. 8 Figure 11. I2C Byte Read .............................................................................................................................. 12 Figure 12. I2C Byte Write .............................................................................................................................. 12 Figure 13. Logical Interface Options for 12-bit Mode ................................................................................... 17 Figure 14. De-skewing Feature Timing ........................................................................................................ 18 Figure 15. Dual Link Configuration............................................................................................................... 19 Figure 16. Single/Dual Link Timing Diagram ................................................................................................ 24 Figure 17. I2C Bus Voltage Level-Shifting using Fairchild NDC7002N ........................................................ 25 Figure 18. I2C Bus Voltage Level Shifting using Philips GTL 2010 .............................................................. 26 Figure 19. ESD Protection Circuit ................................................................................................................ 26 Figure 20. Voltage Regulation using LM317EMP......................................................................................... 27 Figure 21. Decoupling and Bypass Capacitor Placement............................................................................ 27 Figure 22. Decoupling and Bypass Schematic............................................................................................. 28 Figure 23. Differential Output Source Terminations ..................................................................................... 28 Figure 24. Source Termination Layout Illustration ........................................................................................ 29 Figure 25. Transmitter to DVI Connector Layout.......................................................................................... 30 Figure 26. Recommended Hot Plug Connection.......................................................................................... 32 Figure 27. E-pad Diagram ............................................................................................................................ 33 Figure 28. Package Diagram........................................................................................................................ 35 iv SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet September 2005 Features * SDA RST# 26 25 23 24 GND CTL3/A1 PVCC1 22 VCC SCL 21 VSYNC 27 20 28 19 DE HSYNC 32 TXC- 18 D0 31 17 D1 33 16 D2 34 15 D3 35 36 TX014 TX0+ 13 D4 AGND D5 38 TX1- 12 37 11 IDCK- 39 TX1+ IDCK+ AVCC 40 10 TX241 9 TX2+ 42 D6 AGND 43 D7 HTPLG 44 8 PGND 45 7 PVCC2 46 D8 SYNCO/SYNCI 47 * D9 MSEN 48 * * EXT_SWING * PanelLink Digital technology simplifies PC design by resolving many of the system level issues associated with high-speed mixed signal design, providing the system designer with a digital interface solution that is quicker to market and lower in cost. PGND Used in pairs, SiI 1178 transmitters support dual link mode and allow dynamic switching between single link and dual link operation by way of their I2C interfaces. 29 * * * 30 * AGND The SiI 1178 Tx is pin-compatible with the SiI 1178 Tx, supporting 12-bit mode (1/2 pixel per clock edge at double data rates) for true color (16.7 million) support.. Input jitter tolerance is greatly enhanced over the SiI 1178 Tx, enabling spread spectrum applications. Single-clock/dual-edge clocking is supported in both high swing and low swing modes. Scaleable bandwidth: Single link operation from 25 - 165 Megapixels per second (VGA to UXGA) Dual link operation up to 330 Mega-pixels per second 12-bit (1/2 pixel) DDR input with flexible input clocking: Single-clock/dual-edge or dualclock/single-edge Full support for low swing DVO 2.0 mode I2C slave programming interface Selectable input level voltage swing: Low voltage interface: 1.0 to 1.9V High swing interface: 3.3V Monitor detection supported through Hot Plug and receiver sense Cable distance support: Over 10m Compliant with DVI 1.0 Space saving and environmentally safe 48-pin TSSOP Pb-free package TXC+ The SiI 1178 transmitter uses PanelLink Digital technology to support displays ranging from single link resolutions of VGA to UXGA resolution (25 - 165Mpps) and dual link resolutions of up to QUXGA (330Mpps). AVCC General Description SiI 1178 Tx 48-Pin TSSOP 1 2 3 4 5 6 GND VREF VCC GND D11 D10 (Top View) Figure 1. SiI 1178 Tx Pin Diagram SiI-DS-0127-A 1 SiI 1178 PanelLink Transmitter Data Sheet Functional Description Hot Plug Logic Registers & Configuration Logic TX2+ TX1+ PanelLink TMDS Digital core Data Capture Logic A1 SCL SDA I2C Slave Machine Rx Sense TX0+ TXC+ HTPLG MSEN The SiI 1178 Tx is a DVI 1.0 compliant digital-output transmitter with Dual Link capability. Figure 2 shows the functional blocks of the chip. EXT_SWING SYNCI/ SYNCO VREF IDCK- IDCK+ VS HS DE D[11:0] ISEL/RST# CTL3/A1 SCL SDA CTL3 Figure 2. Functional Block Diagram Data Capture Logic The Data Capture Logic Block receives video data sent by the host over a 12-bit bus, with 1/2 pixel arriving at each sampled clock edge. Programming over the I2C interface selects the edges of the clocks (rising or falling) to be used for first and second phase data sampling. The voltage level on VREF sets the SiI 1178 Tx in high swing or low swing mode. The VREF connection also determines whether one or two input clocks are used. In high swing mode, only a single clock, IDCK+, is used; data is latched on both edges of this clock. IDCK- is ignored in high swing mode and must be tied low. In low swing mode (DVO mode), both IDCK+ and IDCK- clocks are used to sample data. In low swing mode where only IDCK+ is available, IDCK- must be tied to VREF. PanelLink TMDS Core The PanelLink TMDS core encodes video information onto three TMDS differential data pairs and a differential clock pair. In dual link mode, where a pair of chips works together as "Master" and "Slave", both cores are synchronized to each other by way of the SYNCO to SYNCI clock connection. Only the Master transmitter TMDS clock output is connected to the DVI connector. A resistor tied to the EXT_SWING pin is used to control the TMDS swing amplitude. 2 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet I2C Slave Machine, Registers, and Configuration Logic The SiI 1178 Tx uses a slave I2C interface, capable of running up to 50kHz, for communication with the host. For the purposes of configuring the chip, registers are read and written through the slave I2C interface. The SiI 1178 Tx must be programmed via I2C to be operational for correct dual link operation and clock edge selection. The device may be powered down by setting the PD bit. The slave I2C interface is not 5V tolerant. If the switching levels from the host are not 3.3V, then a voltage level shifter must be used. The RST# input resets the internal registers and is asserted after power up and receipt of a stable input pixel clock. Hot Plug Logic Connection of a display to the DVI interface can be detected using the Receiver Sense logic. Either the state of the detection, or an interrupt signal indicating a change of state, may be sent to the MSEN pin. This is useful to the host controller monitoring the SiI 1178 Tx. The HTPLG signal from DVI indicates that a monitor EDID is available for reading by the host via the DDC bus. SiI-DS-0127-A 3 SiI 1178 PanelLink Transmitter Data Sheet Electrical Specifications Absolute Maximum Conditions Symbol VCC1,2 VI1,2 VO1,2 TJ1,2 TSTG1,2 Parameter Supply Voltage 3.3V Input Voltage Output Voltage Junction Temperature (with power applied) Min -0.3 -0.3 -0.3 Storage Temperature -65 Typ Max 4.0 VCC+ 0.3 VCC+ 0.3 125 Units V V V 150 C C Notes 1. Permanent device damage may occur if absolute maximum conditions are exceeded. 2. Functional operation should be restricted to the conditions described under Normal Operating Conditions. Normal Operating Conditions Symbol VCC VCCN TA Parameter Supply Voltage Supply Voltage Noise Ambient Temperature (with power applied1) JA-4LS Thermal Resistance (Junction to Ambient) 2 JA-4LNS Thermal Resistance (Junction to Ambient) 3,6 JA-2LS Thermal Resistance (Junction to Ambient) 4 Thermal Resistance (Junction to Ambient) 5, 6 JA-2LNS Note 1. 2. 3. 4. 5. 6. Min 3.0 Typ 3.3 0 25 Max 3.6 100 70 Units V mVP-P 36 C/W 100 C/W 63 C/W 109 C/W C Airflow at 0 m/s. Multilayer board, E-pad soldered. Multilayer board, E-pad not soldered. Two-layer board, E-pad soldered. Two-layer board, E-pad not soldered. See page 34 for solder down requirements. 4 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet DC Specifications Under normal operating conditions unless otherwise specified. Symbol VCINL VCIPL VREF VIH VIL VSH High swing high-level input voltage High swing low-level input voltage Low swing high-level input voltage Conditions ICL = -18mA ICL = 18mA Low Swing Mode High Swing Mode VREF = VCC VREF = VCC VREF = VDDQ/2 VSL Low swing low-level input voltage VREF = VDDQ/2 Input Leakage Current High Impedance -10 RLOAD= 50 REXT_SWING = 390 510 IIL VOD Parameter Input Clamp Voltage1 Input Clamp Voltage1 Input Reference Voltage 2 IPDQ Differential Voltage Single Ended peak-to-peak Amplitude Differential High Level Output Voltage2 Differential Output Short Circuit Current1 Quiet Power-down Current3 IPD ICCT Power-down Current4 Transmitter Supply Current VDOH IDOS Min Typ 0.50 3.00 2.0 -0.3 VDDQ/2 + 100mV 0.75 3.30 550 Max GND - 0.8 VCC + 0.8 0.95 3.60 VCC + 0.3 0.8 Units V V V VDDQ/2 - 100mV 10 V 590 AVCC V V V A mV V VOUT = 0V 5 A PD bit = 0, VCC=3.6V, 0C ambient 5 mA 5 mA mA 170 mA Typical Pattern5 at IDCK=165MHz, 25C ambient, VCC=3.3V, one pixel per clock mode. REXT_SWING = 390 Worst Case Pattern6 at IDCK=165MHz, 0C ambient, VCC=3.6V, one pixel per clock mode. REXT_SWING = 390 135 Notes 1. Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions for a pulse of greater than 3 ns or for more than one third of the clock cycle, whichever is less. Exceeding the Clamp Current ICL listed can result in permanent damage to the chip. 2. Guaranteed by characterization. 3. Quiet Power-down current measured with no transmitter input pins toggling. 4. Power-down current measured with input data bus and control signals toggling. 5. Typical pattern consists of a gray scale area, a checkerboard area, and a text area. 6. Worst-case pattern consists of a black and white checkerboard pattern, with each square being two pixels wide. 7. VDDQ defines the maximum voltage level of Low Swing input. It is not an actual input voltage. Chip characterization for Low Swing operation is performed at 1.5V only. Voltage level of Low Swing input should never exceed absolute maximum rating. SiI-DS-0127-A 5 SiI 1178 PanelLink Transmitter Data Sheet AC Specifications Under normal operating conditions unless otherwise specified. Symbol TCIP FCIP TCIH TCIL SLHT Parameter IDCK Period IDCK Frequency IDCK High Time IDCK Low Time Differential Swing Low-toHigh Transition Time Conditions one pixel per clock one pixel per clock IDCK = 165MHz IDCK = 165MHz SHLT Differential Swing High-toLow Transition Time TIJIT TSHS Worst Case IDCK Jitter Data, DE, VSYNC, HSYNC Setup Time to IDCK+ falling/rising edge Data, DE, VSYNC, HSYNC Hold Time from IDCK + falling/rising edge Data, DE, VSYNC, HSYNC Setup Time to IDCK+ falling/rising edge Data, DE, VSYNC, HSYNC Hold Time from IDCK+ falling/rising edge DE high time DE low time VSYNC and HSYNC Delay from DE falling edge VSYNC and HSYNC Delay to DE rising edge SDA Data Valid Delay from SCL high to low transition RST# Signal Low Time required for valid reset De-skew step size increment THHS TSLS THLS THDE TLDE TDDF TDDR TI2CDVD TRESET TSTEP Notes: 1. 2. 3. 4. 5. 6. 7. 8. Min 6 25 2.6 2.9 170 Typ Max 40 165 230 Units ns MHz ns ns ps Figure Figure 3 Figure 3 Figure 3 Figure 3 Figure 4 Notes 4 4 4 4 6 200 RLOAD = 50, REXT_SWING = 390 170 200 230 ps Figure 4 6 VREF = 3.3V (High Swing Input) 1 0.6 ns ns Figure 8 2 1,5,7 VREF = 3.3V (High Swing Input) 0.5 ns Figure 8 1,5,7 VREF = 0.75V (Low Swing Input) See note 8 ns Figure 7 1,5 VREF = 0.75V (Low Swing Input) See note 8 ns Figure 7 1,5 Figure 6 Figure 6 Figure 5 1 1,5 1 TCIP TCIP TCIP 1 TCIP Figure 5 3 us Figure 9 s Figure 10 ps Figure 14 RLOAD = 50, REXT_SWING = 390 8191 128 CL = 400pf 50 See page 18 for range 3 Guaranteed by design. Actual jitter tolerance may be higher depending on the frequency of the jitter. 2 I C operation is guaranteed rated at 50kHz and slower speeds. Minimum frequency (maximum IDCK period) defined per DVI 1.0 Specification, section 2.3.1. DE Low time defined as per DVI 1.0 Specification, Section 3.4 Link Timing Requirements. th TMDS rise and fall times per DVI 1.0 Specification, Table 4-4, as 0.4*TBIT maximum, where TBIT = 1/10 of TCIP. Typical VCC is defined at 3.3V. The SiI 1178 Transmitter Low Swing timing mode is designed to meet all Intel DVO operational requirements. The DVO interface is proprietary to Intel Corp. and therefore these timings cannot be disclosed here. Refer to the Intel DVO 2.0 specification for details. 6 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet Timing Diagrams Input Timing Diagrams TCIP TCIH VIH VIH VIH VIL VIL TCIL Figure 3. Clock Cycle/High/Low Times in High Swing Mode SLHT SHLT 80% VOD 20% VOD Figure 4. Differential Transition Times DE DE VIL VIH TDDF TDDR VSYNC, HSYNC VSYNC, HSYNC VIH VIL Figure 5. VSYNC, HSYNC Delay Times to DE THDE DE VIH VIH VIL VIL TLDE Figure 6. DE High/Low Times SiI-DS-0127-A 7 SiI 1178 PanelLink Transmitter Data Sheet IDCK + Differential Clock VREF THLS TSLS D[11:0], DE, VSYNC, HSYNC VREF TSLS THLS Figure 7. Low Swing Control and Data Setup/Hold Times to IDCK Differential Clock Note that VREF is set to VDDQ/2 in Low Swing Mode. IDCK+ VCC/2 THHS TSHS D[11:0], DE, VSYNC, HSYNC VCC/2 TSHS THHS Figure 8. High Swing Control and Data Setup/Hold Times to IDCK+ Note that typical VCC is 3.3V. SDA TI2CDVD SCL Figure 9. I2C Data Valid Delay (driving Read Cycle data) VIH VCC RST# TRESET Figure 10. RST# Minimum Timing Note that VCC must be stable between its limits for Normal Operating Conditions for TRESET before RST# is high. RST# must also be pulled LOW for TRESET before accessing registers. 8 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet Pin Descriptions The SiI 1178 Tx is limited to operation in I2C mode. All required dynamic configuration, including switching between single link and dual link operation, can be achieved via I2C operations to registers Input Pins Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 IDCK+ Pin # 18 17 16 15 14 13 10 9 8 7 6 5 12 Type In Description 12-bit pixel bus input. For single link and high-resolution dual link applications, this bus inputs one-half pixel (12 bits) at every clock sampling point. For deep color dual link applications, this bus takes in either the most significant or least significant bits. Refer to Table 5 and Table 6 for exact mapping details. In IDCK- 11 In DE 19 In HSYNC VSYNC CTL3 + A1 20 21 24 In In In Input Data Clock +. In high swing mode, this pin alone is used for data latching on both edges. In low swing mode, the input clock is sensed differentially (IDCK+ minus IDCK-). Input Data Clock -. This clock is only used in low swing mode; the input clock is sensed differentially as noted above. In high swing mode, this pin should be tied to GND. However, in the case of low swing mode where only IDCK+ is supplied, tie IDCK- to the same voltage level as the VREF pin. Data enable. This signal is high when input pixel data is valid to the transmitter and low otherwise. It is critical that this signal have the same setup/hold timing as the data bus. Horizontal Sync input control signal. Vertical Sync input control signal. Control 3 Input + I2C Address Select. The use of this multi-function input depends on RST#. A1 - The bus device address to which the I2C interface will respond is determined by the state of the A1 pin during the rising edge of RST#. A1 is used to set the second bit of the I2C device address; it also determines whether the part will be Master or Slave when used in dual link applications. A1 = HIGH at reset: I2C Address 0x72; preconfigured for Slave A1 = LOW at reset: I2C Address 0x70; preconfigured for Master The device is only fully configured for dual link after the DLNKEN bit is set via I2C registers. CTL3 - After RST# goes high and the A1 setting has been latched, this pin functions as the CTL3 input unless the CTL23en bit is used to disable it. See page 12 for information. SiI-DS-0127-A 9 SiI 1178 PanelLink Transmitter Data Sheet Status Pin Pin Name MSEN Pin # 48 Type Description Out Monitor Sense. This output is programmable through the I2C interface either to indicate the Receiver Sense status (available only on DC-coupled systems) or the Hot Plug status, or to generate an interrupt that one of these has changed state. This is an open-collector pin. Therefore, an external pull-up resistor to the host input interface voltage (5K recommended) is required on this pin whenever the pin output function is used. This pin must be connected from the Master to Graphics Host for display detection. However this pin can be no connect for Slave Tx. Configuration/Programming Pins Pin Name Pin # Type Description RST# 25 In SCL 27 In SDA 26 In HTPLG 44 In EXT_SWING 30 Analog Reset / I2C Interface Address Select. This pin acts as an asynchronous reset to the I2C interface controller. It must be set HIGH for normal operation after the Graphics Host has satisfied the minimum TRESET assertion time. Also, a low-to-high edge on this pin latches the state on the CTL3/A1 pin to set the I2C device access address bit A1. I2C Clock. This pin is the I2C Clock input. The incoming clock may be run up to 50kHz. This pin is not 5V-tolerant and will only support 3.3V signaling. When sharing with lower voltage or higher voltage I2C clocks, a level shifter will be required. See Figure 17 for a circuit example on 1.5V to 3.3V level shifting. This is an open-collector pin. Therefore, a pull-up resistor to 3.3V (2.2K to 4.7K recommended) must be used. I2C Data. 2 This pin is the I C Data input and output. The incoming data may be run up to 50kHz. This pin is not 5V-tolerant and will only support 3.3V signaling. When sharing with lower voltage or higher voltage I2C clocks, a level shifter will be required. See Figure 17 for a circuit example on 1.5V to 3.3V level shifting. This is an open-collector pin. Therefore, a pull-up resistor to 3.3V (2.2K to 4.7K recommended) must be used. Hot Plug input. This pin is used to monitor the "Hot Plug" detect signal from the DVI Connector. This pin is not 5V-tolerant and a 5V to 3.3V level shifting circuit must be used as shown in Figure 26. Voltage Swing Adjust. This resistor sets the amplitude of the voltage swing. Each Master and Slave must have a separate 390 + 5% resistor on this pin pulled up to AVCC. A smaller resistor value sets a larger voltage swing and vice versa. Input Voltage Reference Pin Pin Name VREF Pin # 2 Type Analog Description Input Reference Voltage. Selects the swing range of the digital parallel data inputs (D [11:0], DE, VSYNC, HSYNC and IDCK+). To enable high swing mode, VREF should be set to 3.3V. When VREF is between 0.5V and 0.95V, the digital parallel data inputs are low swing inputs. In low swing mode, VREF must be set to 1/2 the value of the maximum low swing input voltage. For DVO mode, VREF should be set to 0.75V. CTL3 is always assumed to be a high swing signal and therefore is not affected by VREF. 10 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet Output and Differential Signal Data Pins Pin Name TX0+ TX0TX1+ TX1TX2+ TX2TXC+ TXC- Pin # 36 35 39 38 42 41 33 32 Type Analog Analog Analog Analog Analog Analog Analog Analog Description TMDS Low Voltage Differential Signal output data pairs. TMDS Low Voltage Differential Signal output clock pair. Dual Link Configuration and Control Pin Pin Name Pin # Type Description SYNCO/ SYNCI 47 In/Out Sync Out / Sync In. This pin can be switched between 2 functions during Dual Link mode. This pin is always configured in High Swing mode. SYNCO (A1 = LOW, DLNKEN bit = 1) This pin is an Clock output signal from the dual link Master. This pin should be connected to the Slave SYNCI pin for core clock synchronization with the Slave. SYNCI (A1 = HIGH, DLNKEN bit = 1) This pin is an input to the dual link Slave. This pin should be connected to the Master SYNCO pin for core clock synchronization with the Master. The SYNCO to SYNCI trace should be as short as possible. Power and Ground Pins Pin Name VCC GND AVCC AGND PVCC1 PVCC2 PGND SiI-DS-0127-A Pin # 3,22 1,4,23 34,40 31,37,43 28 46 29,45 Type Power Ground Power Ground Power Power Ground Description Digital VCC must be set to 3.3V nominal. Digital GND. Analog VCC must be set to 3.3V nominal. Analog GND. PLL Driver Analog VCC must be set to 3.3V nominal. Filter PLL Analog VCC, must be set to 3.3V nominal. PLL Analog GND. 11 SiI 1178 PanelLink Transmitter Data Sheet Feature Information I2C Interface The SiI 1178 Tx slave state machine operates from an internal clock derived from the incoming SCL signal. No video clock and input is required to read and write to the I2C registers from address 0x00 to 0x0F. These accesses can also take place using only the SCL clock in power down mode. The SiI 1178 Tx responds to the seven-bit binary I2C address of 0x70 in Master Mode and 0x72 in Slave Mode. A read or write transaction is determined by bit 0 of the I2C address. Setting this bit to 1 will enable a write transaction and setting this bit to 0 will enable a read transaction. SDA S A 1 Register Address Stop Slave Address Start Bus Activity : Master Start The I2C read operation is shown in Figure 11, and the write operation in Figure 12. Slave Address S P A C K A C K A C K Data No A C K Slave Address SDA S A 1 Register Address Stop Bus Activity : Master Start Figure 11. I2C Byte Read Data P A C K A C K A C K Figure 12. I2C Byte Write 12 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet I2C Register Mapping Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0x0 VND_IDL 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 VND_IDH DEV_IDL DEV_IDH DEV_REV 0x9 0xA RSVD write to 00 VLOW RSVD write to 1 VEN 0xB 0xC RSVD write to 1 0xD 0xE MSTR_ SLV DCTL[2:0] RSVD write to 00 0xF Bit 1 RSVD write to 01 TSEL RSEN CTL23_ EN RSVD EDGE PD HTPLG MDI 010 3, 5 10010001 4, 5 4 1001001 5 01100000 4, 5 RSVD write to 001001 EZONE ZONEF ZONEO RSVD Initialization Notes Value 0x01 0x19 0xA5 00110100 CTL[3:0] DLKEN Bit 0 0x00 0x06 0x00 0x00 RSVD FRQ_LOW FRQ_HIGH HEN MSEL[2:0] DK[1:0] Bit 2 RSVD write to 0000 RSVD write to 001 4 3, 5 00000001 0x0C 4 Notes: 1. Legend: Symbol indicates either an indeterminate value or a value set dynamically based on pin input level. Hexadecimal values use a prefix of `0x'. All values use bit 7 as most significant, bit 0 as least significant. 2. Read-only or read/write capabilities are noted on the next page. 3. On any RST# assertion event, all registers that have default values lose their previously programmed value and are set back to the default values listed on the next page. 4. Registers listed as RSVD and shaded gray are reserved for factory use and should not be accessed. 5. Write the initialization values indicated. SiI-DS-0127-A 13 SiI 1178 PanelLink Transmitter Data Sheet Table 1. General I2C Register Definitions Register Name VND_IDL VND_IDH DEV_IDL DEV_IDH Access RO RO RO RO DEV_REV FRQ_LOW FRQ_HIGH HEN RO RO RO RW VEN RW EDGE RW PD RW VLOW RO MSEL[2:0] RW TSEL RW RSEN RO HTPLG MDI RO RW DK[1:0] CTL[3:0] RW RW CTL23_EN RW Description Vendor ID Low byte (0x01) Vendor ID High byte (0x00) Device ID Low byte (0x06) Device ID High byte (0x00) Device Revision (0x00) IDCK. Low frequency limit is 25MHz. (0x19) IDCK High frequency limit is 165MHz. (0xA5) Horizontal Sync Enable 0 - HSYNC input is transmitted as fixed LOW 1 - HSYNC input is transmitted as input. Default Vertical Sync Enable 0 - VSYNC input is transmitted as fixed LOW 1 - VSYNC input is transmitted as input. Default Edge Select 0 - Falling edge latched first in dual edge mode Default 1 - Rising edge latched first in dual edge mode Power Down mode 0 - Power Down. Default after RESET 1 - Normal operation Voltage Swing Mode 0 - VREF signal indicates low swing inputs 1 - VREF indicates high swing inputs Select source of the MSEN output pin 000 - Tri-state MSEN output (will go high due to pullup) 001 - Outputs the MDI bit (interrupt) 010 - Outputs the RSEN bit (receiver detect). Default 011 - Outputs the HTPLG bit (hot plug detect) 100 to 111 - Do not use Interrupt Generation Method 0 - Interrupt bit (MDI) is generated by monitoring RSEN 1 - Interrupt bit (MDI) is generated by monitoring HTPLG Receiver Sense. This bit is HIGH if a powered on receiver is connected to the transmitter outputs, LOW otherwise. This function is only available for use in DC-coupled systems. Hot Plug Detect input. The state of HTPLG pin can be read from this bit. Monitor Detect Interrupt. Uses signal specified by TSEL to generate an interrupt. Write `1' to this bit to clear the interrupt status. 0 - Detection signal has changed logic level 1 - Detection signal has not changed state De-Skewing Setting. See page 18 for full control detail. Control 3-0. General Purpose bits to transmit CTL0, CTL1, CTL2, CTL3 when DE is LOW. 0 - Transmit specific CTL as LOW 1 - Transmit specific CTL as HIGH Note that when CTL23_EN bit is set, only CTL 1:0 can be set with these bits. Control 2-3 Enable. This bit determines the source of CTL3 to be sent out over TMDS. 0 - Disable CTL3 input function, send CTL2-3 as defined by bit in CTL[3:0]. 1 - Enable CTL3 input as source for CTL3 over TMDS, CTL2=0. Default Notes: 1. RO = Read Only Registers 2. RW = Read/Write Registers 3. `Default' indicates value set after a reset event. Not all bits default to a defined state after reset. 14 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet Table 2. Dual Link I2C Register Definitions Register Name DLNKEN Access RW MSTR_SLV RO DCTL[2:0] RW Description Dual Link enable bit. 0 - Disable Dual Link mode. Default Value. 1 - Enable Dual Link mode. Master/Slave Status. This bit is only valid when DLNKEN bit is 1. 0 - Slave in Dual Link mode. 1 - Master in Dual Link mode. Skew control between master and slave in DUAL link mode (see the dual link section for more information). Increment 260psec. 000 : 1 step minimum setup / maximum hold 001 : 2 step 010 : 3 step 011 : 4 step Default 100 : 5 step 101 : 6 step 110 : 7 stepmaximum setup / minimum hold 111 : Not available. Notes: 1. RO = Read Only Registers 2. RW = Read/Write Registers 3. Default indicates value set after Reset event. RESET Description The input pin RST# serves as an asynchronous (active LOW) reset signal for the I2C slave controller. The following lists the behavior of the chip during and after Reset: * * * RST# must be driven low for at least 50s for proper I2C logic reset. During reset, the chip I2C registers and logic cannot be accessed. Dual link mode cannot be selected during this period. After reset, the chip TMDS outputs will be turned OFF and all registers that are listed with default initialization values will be set to those values. The SiI 1178 Tx can be accessed and enabled via I2C beginning from this event. Dual Zone PLL The SiI 1178 Tx offers a dual-zone PLL that changes its operational parameters depending on the frequency zone selected. In the low zone, operation is ideal in the low frequency range, from 20MHz to around 120MHz. High zone operation is optimized in the high frequency range, above 100MHz. In the overlapping range, either low zone or high zone operation can be used. Operating zone optimization contributes to robust operation over long cables. For example, optimized PLL characteristics account for the ability of the transmitter to send video at UXGA over 20m cables. PLL zone selection is controlled either manually or automatically. Manual zone control is the preferred mode of operation. Manual Zone Control Whenever the application allows it, PLL zone selection should be made manually. The I2C register bits ZONEF and EZONE allow the host graphics controller to set the optimal zone for the current video resolution being transmitted. For frequencies over 100MHz, the controller should select high zone PLL operation. Table 3 describes the relevant register bits. SiI-DS-0127-A 15 SiI 1178 PanelLink Transmitter Data Sheet Automatic Zone Control For applications that are not able to program the I2C registers, the chip incorporates an automatic zone control circuit. This circuit determines whether the input pixel clock is operating in the low frequency range or the high frequency range, and sets the PLL zone selection accordingly. The chip defaults to the automatic mode of zone selection after reset. The zone determination depends primarily on input frequency, but is also affected by operating voltage and chip temperature. Therefore, it is possible for an automatic zone switch to occur while video input is stable, causing momentary (~1s) unevenness in the video output clock and data streams. This could occur, for example, while the chip is still warming up to its normal operating temperature. However, the automatic selection circuit provides wide hysteresis to ensure that there will not be any oscillation around the zone switch point. Table 3. Dual Zone PLL I2C Control Register Bits Register Name ZONEF Access RW EZONE RW ZONEO RO Description Zone Force. Enable external selection of main PLL operating zone. When ZONEF=1, the main PLL zone is selected by EZONE. 0 - Automatic zone selection - EZONE bit disabled (default) 1 - Manual zone selection - EZONE bit enabled External Zone Select. Selects operating zone of main PLL, but only when ZONEF=1 (disabled by default). 0 - Low zone (recommended for 20-120MHz) 1 - High zone (recommended for > 100MHz) Zone Output - indicates current operating zone. When ZONEF=0 (automatic), ZONEO indicates that PLL is operating in zone optimized for: 0 = Lower frequencies 1 = Higher frequencies. When ZONEF=1 (manual), ZONEO indicates the zone that automatic selection would have chosen. 0 - Low frequency operation is sensed 1 - High frequency operation is sensed Input Signal Swing and Clocking Selection The SiI 1178 Tx offers two modes of data input signal sampling. Within those modes the input clocking method can also be selected. High swing input is defined for signal swings associated with the chip digital VCC voltage, nominally 3.3V. Internal sampling is centered at the VCC/2 point. To select high swing operation, tie VREF to VCC. o High swing input automatically selects only a single input clock IDCK+. Tie IDCK- to GND. Low swing input is defined for signal swings that are lower than VCC. VREF selects the center point for the sampling, plus or minus 100mV. To select low swing input tie VREF to the max signal swing, divided by two. 1.5V DVO operation, for example, requires VREF to be tied to a 0.75V reference. o Two input clocks are used by default with low swing input mode. Connect both IDCK+ and IDCK- to the appropriate source clocks. o If only a single input clock is used with low swing input mode, tie the IDCK- pin to VREF. Note that use of VREF for low swing sample point selection is valid only up to 1.9V. For high swing sample point selection, VREF can fall only in the nominal VCC range (3.0-3.6V). Other values for VREF are undefined. 16 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet EDGE Selection The SiI 1178 Tx provides flexible edge selection. In high swing mode, the device supports a single clock input on IDCK+. The EDGE bit selects whether to latch the first data on the rising or the falling edge. In high swing mode, IDCK- must be grounded for proper operation. In low swing mode, the device supports dual clock inputs on IDCK+ and IDCK-. The EDGE bit selects whether to latch the data on the rising or the falling edges of the input clocks. If using only IDCK+ in low swing mode, IDCK- must be tied to VREF for proper operation. Figure 13 details the behavior of the edge selection bit in both high swing and low swing modes . DE D[11:0] P 0L P OH P 1L P 1H P N-1 H PNL P NH L = Low half pixel H = High half pixel HIGH/ LOW SWING MODE IDCK+ EDGE = 0 IDCK+ LOW SWING MODE IDCK- HIGH/ LOW SWING MODE IDCK+ EDGE = 1 IDCK+ LOW SWING MODE IDCKFirst Latch Edge Figure 13. Logical Interface Options for 12-bit Mode SiI-DS-0127-A 17 SiI 1178 PanelLink Transmitter Data Sheet Data De-skew DK[1:0] Feature Input clock to data setup/hold time can be adjusted through the use of the de-skew feature. It should be noted that it is the clock that is being adjusted internally. The configuration pins DK[1:0] or applicable I2C registers can be used to vary the input setup/hold time by TCD. The DK[1:0] bits in the configuration registers can be used to control the TCD value. Table 4 lists the De-skew time increment range and the effect on Setup and Hold. The de-skew feature should not be used in dual link applications. The variability of the delay from one chip sample to the next would be compounded if two of the chips were used as they must be for dual link. DE, HSYNC, VSYNC, D[11:0] IDCK+ IDCK- TCD -TCD DK[1:0] 01 00 10 default Figure 14. De-skewing Feature Timing Table 4. DK[1:0] Increments and Effect on Setup and Hold times DK[1:0] De-Skew Time (TCD ) Setup and Hold Time Effect 01 -100ps to -400ps Reduces Setup time, increases Hold time. 00 0 ps No effect. Default and recommended setting. 10 +100ps to +400ps Reduces Hold time, increases Setup time. 11 -300ps to +300ps Not recommended. 18 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet Dual Link Applications The SiI 1178 Tx is designed for use in pairs for dual link applications. The primary link or Master transmitter sends synchronization information to the secondary link or Slave transmitter to maintain the correct inter-pair skew among all six data pairs. The DVI 1.0 specification requires that all pixel clock frequencies above 165MHz be transmitted over dual TMDS links. The specification also allows for extra color depth to be transmitted across the second link. The discussion below refers to the higher pixel rate application, but can also be applied to the extra color depth application as described in the Data Mapping Modes for Dual Link section. The descriptions below differentiate dual link mode and dual link operation as follows. Dual Link Mode: The circuit must be designed to indicate one Master and one Slave device; also the Master-toSlave synchronization must be established. Finally, the chips must be programmed through the I2C registers to recognize the dual link application. Dual Link Operation: Once designed and configured for dual link mode, the chips can operate as either a single link or a dual link interface. The host graphics controller selects between single link and dual link operation through an I2C register bit depending on pixel rate. LOW Data must not be supplied to the Master or Slave until both devices have been fully programmed to Dual Link mode. SDA SCL ODD DATA D[23:12] Tx[2:0] A1 SYNCO TxC To Single Link or Dual Link Rx Slave D[11:0] IDCK SiI 1178 Tx[2:0] TxC HIGH A1 HSYNC VSYNC DE SYNCI DE TxC SCL From Multimedia Controller SiI 1178 Tx[2:0] SCL IDCK HSYNC VSYNC D[11:0] IDCK HSYNC VSYNC DE SDA D[11:0] Master SDA EVEN DATA Figure 15. Dual Link Configuration SiI-DS-0127-A 19 Tx[5:3] SiI 1178 PanelLink Transmitter Data Sheet Master Configuration The Master transmitter is partially configured for Master mode in a Dual Link operation by setting the A1/CTL3 pin to low before reset, as shown in Figure 15. The primary 12-bit data from the host graphics controller is connected to the Master transmitter. This bus provides both EVEN and ODD pixels for pixel rates at or below 165MHz, and the EVEN pixel for pixels rates greater than 165MHz. The Control Signals HSYNC, VSYNC and DE are connected to both the Master and Slave transmitters. Both transmitters require the DE signal (they cannot generate this signal internally). The input clock(s) are connected to both the Master and Slave transmitters. The SYNCO pin of the Master transmitter is connected to the SYNCI pin of the Slave transmitter. This signal is used to synchronize the two transmitters. This signal has a skew control mechanism to control the skew between the Master and Slave transmitters, which is done through the I2C register bits DCTL[2:0]. To fully enable the SiI 1178 Tx as Master in dual link mode, the DLNKEN bit must be set to 1. A detailed programming sequence is provided on page 23. Slave Configuration The Slave transmitter is partially configured for Slave mode in a Dual Link operation by setting the A1/CTL3 pin to high before reset as shown in Figure 15. The secondary 12-bit data from the host graphics controller is connected to the Slave transmitter. This bus provides the ODD pixels for pixel rates greater than 165MHz. For rates at or below 165MHz, the host sends no data to the Slave transmitter. Instead, the host powers down the Slave by setting the PD bit in the I2C registers. It is important to explicitly power down the Slave transmitter when in single link operation, because the dual link Slave receiver will put the display device into dual link mode if it sees any secondary link activity (even just black video data). The control signals HSYNC, VSYNC and DE along with input clock(s) are shared with the Master transmitter. The SYNCI pin of the Slave transmitter is connected to the SYNCO pin of the Master transmitter as noted above. To fully enable the SiI 1178 Tx as Slave in dual link mode, the DLNKEN bit must be set to 1. A detailed programming sequence is provided on page 23. Master-Slave Skew Control Due to the possibility of individual design constraints or mismatches between ODD and EVEN data synchronization, the SiI 1178 Tx has been designed with a dual link skew control feature. This feature allows the skew between the SiI 1178 Tx Master and Slave to be controlled by setting the DCTL[2:0] register. This register allows four steps for adjusting the output of the Master SiI 1178 Tx either ahead of or behind the outputs of the Slave device. This feature should only be used in to control or adjust excessive inter-pair skew between the DVI outputs of the Master and Slave. DCTL[2:0] will not adjust or compensate for input data setup and hold timing deficiencies. Definition of the steps available for DCTL[2:0] is provided in Table 2 on page 15. 20 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet Data Mapping Modes for Dual Link The DVI 1.0 specification offers two uses for dual link. It can support either higher resolution, or else it can support greater color depth. Table 5 shows how the mapping works for high resolution applications. The input data is divided up into even and odd pixels as shown. Pixels 0, 2, 4, etc. are carried on the Master link. Pixels 1, 3, 5, etc. are carried on the Slave link. Table 5. Dual Link Data Mapping - High Resolution Application Device Master SiI 1178 Tx EVEN Pixel Data Slave SiI 1178 Tx ODD Pixel Data Pin Name D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 1st Clock Edge G0[3] G0[2] G0[1] G0[0] B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0] G1[3] G1[2] G1[1] G1[0] B1[7] B1[6] B1[5] B1[4] B1[3] 2nd Clock Edge R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] G0[7] G0[6] G0[5] G0[4] R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[7] D2 D1 D0 B1[2] B1[1] B1[0] G1[6] G1[5] G1[4] Notes 1. Color Pixel Components: R = RED, G = GREEN, B = BLUE 2. Bit significance within a color: [7:0] = [Msb:Lsb] SiI-DS-0127-A 21 SiI 1178 PanelLink Transmitter Data Sheet Table 6 shows how the mapping works for deep color applications. The input data is divided up into Most Significant bits (MS bits) of the pixel and Least Significant bits (LS bits) as shown. The MS bits are carried on the Master link. The LS bits are carried on the Slave link, and are left-justified as noted in the DVI spec. Using this scheme ensures that connection of a future source with 12-bit or 16-bit color depth will still map the most significant bits correctly to a 10-bit display. Table 6. Dual Link Data Mapping - 10-bit Deep Color Application Device Master SiI 1178 Tx MS bits Pixel Data Slave SiI 1178 Tx LS bits Pixel Data Pin Name D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1st Clock Edge G0[5] G0[4] G0[3] G0[2] B0[9] B0[8] B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] low low low low B1[1] B1[0] low low low low low low 2nd Clock Edge R0[9] R0[8] R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] G0[9] G0[8] G0[7] G0[6] R1[1] R1[0] low low low low low low G1[1] G1[0] low low Notes 1. Color Pixel Components: R = RED, G = GREEN, B = BLUE 2. Bit significance within a color: [7:0] = [Msb:Lsb] 22 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet Dual Link I2C Programming Sequence Example To enable the SiI 1178 Tx Master and Slave, the sequence in Table 7 provides a typical program flow. The example uses falling clock edges for input latching. Table 7. Dual Link Programming Sequence and Flowchart Step Program Sequence 11 Program Sequence 2 Check Configuration Program Sequence 3 Flowchart Details Ensure that both Master and Slave have been configured to follow physical configuration shown on Figure 15 Disable all video and clock output from the host graphics controller. Program Slave (0x72) with the following register values. 0x0F0x44 0x0F0x4C [This register must be set to this value for normal operation after resolution change, exit from power down mode, suspend and hibernation] 0x0E34h if > =100MHz(single Link); 10h if <100Mhz 0x0A0x80 0x090x30 [Set MSEN to output Hotplug pin status] 0x0C0x89 [Initialize reserved register bits] 0x0D0x70 [Enable dual link function and default DCTL] 0x080x32 or 30h [Enable H/V Sync, set correct EDGE, but disable output] Program Master (0x70) with the same sequence as above. Check Master/Slave setting option. Read Master (0x70) 0x0C[6] = 1 Read Slave (0x72) 0x0C[6] = 0 Proceed if both bits are read back with the correct values. Program Master (0x70) with the following register value. 0x080x31(EDGE = Low) or 0x33 (EDGE = High) [Enable output] Program Slave (0x72) with the following register value. 0x080x31(EDGE = Low) or 0x33 (EDGE = High) [Enable output] BEGIN Disable Video and Clock Output from Multimedia Controller Program Sequence 1: Intialize Slave Tx, PD=0 Program Sequence 2: Intialize Master Tx, PD=0 Master/Slave RO bit correct? N Y Enable Video and Clock Output from Multimedia Controller Program Sequence 3: Set Master Tx PD=1 Set Slave Tx PD=1 END Notes 1. Entire programming sequence must be executed after every Reset event, Resolution swtich, Video Clock changes or suspend events. 2. Slave must be programmed before Master during all events listed in note 1. Timing Diagrams Figure 16 is an example of the timing for a dual link application. When the bandwidth is less than or equal to 165Mpps, the host graphics controller does not send any data to the Slave transmitter. The Slave transmitter is powered down by setting bit PD=0 in the I2C registers. The host graphics controller is sending both EVEN and ODD data to the Master transmitter via the primary 12-bit bus in single link mode. SiI-DS-0127-A 23 SiI 1178 PanelLink Transmitter Data Sheet When the bandwidth is greater than 165Mpps, the host graphics controller sends the EVEN data to the Master transmitter via the primary 12-bit bus and the ODD data to the slave transmitter via the secondary 12-bit bus. It also powers up the Slave transmitter by setting bit PD=1 in the I2C registers. The host graphics controller is always driving the data in 12 bits, in both dual-edge/single-clock and singleedge/dual-clock modes. Only in dual link applications are both the Master and Slave transmitters configured to receive data in that mode. Master D[11:0] D[11:0] D[11:0] D[11:0] D[11:0] For frequencies less than or equal to 165MHz, Multimedia Controller is sending both EVEN and ODD data to Master device only. Slave D[11:0] D[11:0] D[11:0] D[11:0] D[11:0] For frequencies greater than 165MHz, the Multimedia Controller is sending only the EVEN data to the Master device. D[23:12] D[23:12] D[23:12] D[23:12] Multimedia Controller is not sending any data to the slave. It is powered down. For frequencies greater than 165MHz, the Multimedia Controller is sending only the ODD data to the Slave device. It takes the Slave out of power down mode. IDCK+ (Dual Edge) OR IDCK+ (Dual Clock) IDCK- Slave PD bit must be set to 1 by this period Slave PD bit Figure 16. Single/Dual Link Timing Diagram Enabling Hot Plug Detection Mode As documented in the VESA Digital Flat Panel Standard, all monitors are required to support Hot Plug Detection but support is optional for the host. The SiI 1178 Tx supports the Hot Plug Detect feature. In I2C mode, use the HTPLG input. It should be noted that the HTPLG pin on the SiI 1178 Tx is only 3.3V tolerant. Therefore, the HTPLG voltage level from the DVI connector should be level shifted or clamped at 3.3V. When the voltage level at the HTPLG pin is 3.3V, the HTPLG bit will be set to 1. To output the HTPLG bit via the MSEN pin, register bits MSEL [2:0] should be programmed to 011. The SiI 1178 Tx can also be programmed to determine Hot Plug detection via the Receiver Sense function. In this mode, input of the HTPLG signal is not required. By programming MSEL[2:0] to 010, the SiI 1178 Tx will output the RSEN bit state though the MSEN pin to indicate whether the SiI 1178 Tx is connected to a powered receiver. 24 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet Design Recommendations The following sections describe recommendations for robust board design with the SiI 1178 Tx. Designers should include provision for these circuits in their design, and adjust the specific passive component values according to the characterization results. Overview of Pin Differences When used in an SiI 1162 Tx application, the SiI 1178 Tx is a drop-in replacement that also offers increased input clock jitter tolerance. However, the SiI 1178 Tx part only supports I2C -controlled mode of operation - it cannot be used in a strap-selected application as the SiI 1162 Tx could. Two pins change function as a result. ISEL/RST# AE RST#: The ISEL function of the SiI 1162 Tx, used to set strap-operated mode, is no longer supported. PD#: The PD# input pin is no longer available. Power down must instead be controlled by the PD bit in the I2C register set. 1.5V to 3.3V I2C Bus Level-Shifting The SiI 1178 Tx I2C SDA and SCL swing level must be 3.3V. Intel motherboards with DVO sources provide an I2C signal with voltage swing of 1.5V. To ensure proper initialization of the SiI 1178 Tx, a bi-directional voltage levelshifting circuit between the SiI 1178 Tx I2C bus and the Intel Graphics Host should be implemented. Two possible choices that have been tested by Silicon Image for this purpose are a dual N-channel transistor (Fairchild Semiconductor NDC7002N) and a high-speed bus switch (Philips GTL2010). Figure 17 is a schematic example using the Fairchild dual N-channel transistor to translate I2C from 1.5V to 3.3V and vice versa. 1.5V 2.9V 1 1K 1.5V 1 2 S 2.2K D 3 2N7002 2.9V 1K 1.5V I2C CLK FROM VGA Q2 G 2 S 1.5V I2C DATA FROM VGA 3.3V 3.3V I2C DATA TO SiI 1178 3.3V Q4 G D 3 2N7002 2.2K 3.3V I2C CLK TO SiI 1178 Figure 17. I2C Bus Voltage Level-Shifting using Fairchild NDC7002N SiI-DS-0127-A 25 SiI 1178 PanelLink Transmitter Data Sheet Figure 18 is a schematic example using the Philips high-speed bus switch to achieve a 1.5V to 3.3V bi-directional level-shift. 1.5V 5V R1 R2 1K 1K 3.3V R3 R4 R5 200K 2.2K 2.2K U1 1.5V I2C DATA FROM VGA 1 2 3 4 5 6 7 8 9 10 11 12 1.5V I2C CLK FROM VGA GND GREF SREF DREF S1 D1 S2 D2 S3 D3 S4 D4 S5 D5 S6 D6 S7 D7 S8 D8 S9 D9 S10 D10 GTL2010 3.3V I2C DATA TO SiI 1178 24 23 22 21 20 19 18 17 16 15 14 13 3.3V I2C CLK TO SiI 1178 Figure 18. I2C Bus Voltage Level Shifting using Philips GTL 2010 ESD Protection on TMDS Output Pins Silicon Image does not advise inserting ESD devices onto the differential lines between the SiI 1178 transmitter and the connector in high-speed applications. Capacitance and inductance on these lines from such discrete devices will adversely affect the high-speed performance as it will change the impedance of the lines. However for applications with throughput of less than 108Mbps, a small signal diode such as the BAV99 and 10 series resistors may be placed on the differential lines. The diodes should be placed closer to the DVI connector while the 10 resistors should be placed closer to the transmitter output. As noted in the section Transmitter Layout (page 30), 100 differential impedance is an important parameter for proper layout. See Figure 19 for an illustration. DVI CONNECTOR 3.3V BAV99 TMDS Trace 10 GND Figure 19. ESD Protection Circuit 26 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet Voltage Ripple Regulation The power supply to VCC pins is very important to the proper operation of the transmitter. An example of a tested regulator circuit is shown in Figure 20. Note that alternative voltage regulator circuits should be considered only if they meet the LM317 standards of line/load regulation. To regulate to 3.3V from a 5V source, choose a voltage regulator capable of 1.7V dropout (such as the LM1117). Decoupling and bypass capacitors are also involved with power supply connections, as described in detail in Decoupling Capacitors on page 27. LM317EMP Vin 12V Vout 3.3V Vin Vout ADJ 240 1% 390 1% Figure 20. Voltage Regulation using LM317EMP PCB Ground Planes All ground pins on the device should be connected to the same, contiguous ground plane in the PCB for dual link applications. This approach helps to avoid ground loops and inductances from one ground plane segment to another. Such low-inductance ground paths are critical for return currents, which affect EMI performance. The entire ground plane surrounding the PanelLink transmitter should be one piece, and include the ground vias for the DVI connector. Decoupling Capacitors Designers should include decoupling and bypass capacitors at each power pin in the layout. These are shown schematically in Figure 22. Place these components as close as possible to the PanelLink device pins, and avoid routing through vias if possible. Figure 21 is representative of the various types of power pins on the transmitter. VCC C1 C2 L1 VCC Ferrite GND C3 Via to GND Figure 21. Decoupling and Bypass Capacitor Placement SiI-DS-0127-A 27 SiI 1178 PanelLink Transmitter Data Sheet VCC L1 VCC Pin C1 C2 C3 Figure 22. Decoupling and Bypass Schematic The values shown in Table 8 are recommendations that should be adjusted according to the noise characteristics of the specific board-level design. Pins in one group (such as VCC) for an individual SiI 1178 Tx may share C2, the ferrite and C3. Master and Slave must not share the same decoupling capacitors for any pin group: each pin should have a separate C1 placed as close to the pin as possible. Table 8. Recommended Components for 1-2MHz Noise Suppression C1 100 - 300 pF C2 0.1 F C3 10 F L1 Ferrite, 200+ @ 100MHz Source Termination Resistors on Differential Outputs Source termination, consisting of a 300 resistor (this value may vary on the physical design and electrical characteristics of the PCB) and a 0.1F non-polar capacitor, should be used on the differential outputs of the Master and Slave SiI 1178 Tx to improve signal swings. See Figure 23 for an illustration. Note that the specific value for the source termination resistor and capacitor will depend on the PCB layout and construction. Different values may be needed to create optimum DVI-compliant output waveforms from the transmitter. TXC+ TXCTX0+ 300 ohm 300 ohm 0.1uF 300 ohm 0.1uF 300 ohm 0.1uF 300 ohm 0.1uF TX0TX1+ TX1TX2+ TX2TX3+ TX3TX4+ 300 ohm 0.1uF TX4TX5+ 300 ohm 0.1uF TX50.1uF Figure 23. Differential Output Source Terminations 28 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet Source termination suppresses signal reflection to prevent non-DVI compliant receivers from mis-sampling the TMDS signals at high frequencies (beyond 135MHz). The impact on DVI compliant receivers is minimal. Therefore, Silicon Image recommends source termination for most applications. Note that the capacitor is required to meet DVI idle mode DC offset requirements and must not be omitted. Note also that the signal suppression requires the REXT_SWING value to be changed. Refer to recommendations on page 11. Power consumption will be slightly higher when using source termination. C R Detail of Source termination (magnified) R and C 0603 components installed. Figure 24. Source Termination Layout Illustration The layout in Figure 24 has been developed to minimize trace stubs on the differential TMDS lines, while providing pads for the source termination components (left-hand magnified view). Source termination components should be placed close to the transmitter pins. The resistor and capacitor are shown installed on the pads provided (right-hand magnified view). SiI-DS-0127-A 29 SiI 1178 PanelLink Transmitter Data Sheet Transmitter Layout The transmitter chip should be placed as close as possible to the output connector which carries the TMDS signals. For a system using the industry-standard DVI connector (see http://www.ddwg.org), the differential lines should be routed as directly as possible from transmitter to connector with minimal trace length difference, intrapair length difference must be within + 0.75 inch to minimize intra-pair skew. PanelLink devices are tolerant of skews between differential pairs, so spiral skew compensation for path length differences is not required. Each differential pair should be routed together, minimizing the number of vias through which the signal lines are routed. An example of a DVI routing is shown in Figure 25. 24 17 9 16 8 1 TxCTxC+ Tx0Tx0+ Tx1Tx1+ Tx2Tx2+ TxCTxC+ Tx0Tx0+ Tx1Tx1+ Tx2Tx2+ Slave Master Figure 25. Transmitter to DVI Connector Layout As defined in the DVI 1.0 Specification, the impedance of the traces between the connector and the transmitter should be 100 differentially, and close to 50 single-ended. The 100 requirement is to best match the differential impedance of the cable and connectors therefore preventing reflections. The common mode currents are very small on the TMDS interface, so differential impedance is more important than single-ended. 30 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet Table 9 lists the pin mapping required on the DVI connector for Master and Slave SiI 1178 Tx. Table 9. DVI Connector to SiI 1178 Tx for Dual Link Pin Connection Pin # DVI Connector Signal Assignment SiI 1178 Tx - Master Pin # Pin Name SiI 1178 Tx - Slave Pin # Pin Name 1 TMDS Data2- 30 2 TMDS Data2+ 31 3 4 TMDS Data2/4 Shield TMDS Data4- 27 5 TMDS Data4+ 28 6 7 8 9 DDC Clock DDC Data Analog VSYNC TMDS Data1- 27 10 TMDS Data1+ 28 11 12 TMDS Data1/3 Shield TMDS Data3- 24 13 TMDS Data3+ 25 14 15 16 17 +5V Power Ground Hot Plug Detect TMDS Data0- 24 18 TMDS Data0+ 25 19 20 TMDS Data0/5 Shield TMDS Data5- 30 21 TMDS Data5+ 31 22 23 TMDS Clock Shield TMDS Clock+ 22 24 TMDS Clock- 23 C1 C2 C3 C4 C5 Analog Red Analog Green Analog Blue Analog HSYNC Analog Ground SiI-DS-0127-A TMDS Low Voltage Signal Tx2- from Master TMDS Low Voltage Signal Tx2+ from Master TMDS Low Voltage Signal Tx1- from Slave TMDS Low Voltage Signal Tx1+ from Slave TMDS Low Voltage Signal Tx1- from Master TMDS Low Voltage Signal Tx1+ from Master TMDS Low Voltage Signal Tx0- from Slave TMDS Low Voltage Signal Tx0+ from Slave TMDS Low Voltage Signal Tx0- from Master TMDS Low Voltage Signal Tx0+ from Master TMDS Low Voltage Signal TxC+ from Master TMDS Low Voltage Signal TxC- from Master 31 TMDS Low Voltage Signal Tx2- from Slave TMDS Low Voltage Signal Tx2+ from Slave SiI 1178 PanelLink Transmitter Data Sheet Recommended Circuits The Hot Plug pin on the DVI connector will supply a voltage up to 5V. A level-shifting circuit is needed to connect to the HTPLG pin on the SiI 1178 Tx, as the input pin of the device is not 5V-tolerant. The DVI Specification also makes this recommendation (Sections 2.2.9.1 and 2.2.9.2). See Figure 26. VCC3 0 ohms SD103A 2N3904 DVI Connector HTPLG Pin 10K ohms SiI 1178 HTPLG Pin 10K ohms Figure 26. Recommended Hot Plug Connection 32 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet Packaging E-pad Enhancement The SiI 1178 Tx is packaged in a 48-pin TSSOP package with E-pad. The E-pad dimensions are shown in Figure 27. E-pad Dimensions typ P1 P P1 E-pad Height E-pad Width max 2.3 5.5 All dimensions are in millimeters. E-pad is centered on the package center lines. P Figure 27. E-pad Diagram The E-pad is designed to allow better heat dissipation, and must be soldered down for adequate heat dissipation for all operating frequencies and environments. Determining Heat Dissipation Requirements Generally, the thermal performance of a package can be represented by the following parameter (JEDEC standard JESD 51-2, 51-6): JA , Thermal resistance from junction to ambient JA = (TJ - TA) / PH Where: TJ is the junction temperature TA is the ambient temperature PH is the power dissipation JA represents the resistance to the heat flow from the chip to ambient air. It is an index of heat dissipation capability. Lower JA means better thermal performance. Implementation of the thermal landing area, combined with complete soldering of the package to the landing area, results in a JA of 36C/W for a multi-layer PCB (4 or more layers). If the SiI 1178 package is assembled to a twolayer PCB without the thermal landing area, the JA increases to 109C/W; if instead it is assembled to a multilayer PCB without the thermal landing area, JA is only 100C/W due to the slightly improved ability of the multilayer PCB to carry away heat. SiI-DS-0127-A 33 SiI 1178 PanelLink Transmitter Data Sheet Table 10 illustrates the power dissipation allowed under different PCB and E-Pad soldered states of SiI 1178. Table 10. Allowed Power Consumption vs. E-Pad Solder State JA E-Pad not soldered to multi-layer PCB E-Pad not soldered to 2 layer PCB E-Pad soldered down to multi-layer PCB E-Pad soldered down to 2 layer PCB 100C/W 109C/W 36C/W 63C/W Allowed 0.55W 0.50W 1.53W PH Max 0.61W 0.61W 0.61W PH Notes: 1. All calculations based on TJ of 125C and TA of 70C. 2. Max PH is based on peak current consumption listed on page 5 and 3.6V at speed of 165MHz. 0.87W 0.61W * In the case of no thermal landing pad on a two-layer PCB (JA = 109C/W), assuming a worst-case scenario with operation at the maximum ambient temperature (70C) and maximum voltage of 3.6V, the maximum allowable peak power dissipation is 0.50W at 1.65MHz. This configuration does not allow any headroom for SiI 1178 typical power consumption of 0.50W. * In the same non-soldered case but on a multi-layer PCB (JA = 100C/W), the maximum allowable peak power dissipation is 0.55W. This configuration is also not recommended since the 0.61W peak power consumption of the SiI 1178 exceeds the allowed power dissipation. * In both 2 layer and Multi-layer soldered states, each allow a power dissipation of 0.87W and 1.53W respectively. This provides sufficient headroom for operation during sustained typical power dissipation of 0.50W or peak power dissipation of 0.61W by SiI 1178. All PCBs must be designed with a thermal landing area for use with the SiI 1178 E-pad. Operating outside of chip specifications is not recommended; contact your Silicon Image representative for analysis of non-standard operational requirements. Designing with E-pad Landing Area When designing the PCB to solder down the E-pad, keep the following in mind. The ground connections from die to lead-frame are down-bonded to the E-pad to minimize ground inductance. Therefore, the E-pad must not be electrically connected to any other voltage level except ground (GND). When providing a thermal landing area for soldering the E-pad, design the PCB with a clearance of at least 0.25mm between the edge of the E-pad and the inner edges of the lead pads to avoid any electrical shorts. The thermal land area on the PCB may use thermal vias to improve heat removal from the package. These thermal vias can double as ground connections, attaching internally in the PCB to the ground plane. An array of vias should be designed into the PCB beneath the package. For optimum thermal performance, it is recommended that the via diameter be 12 to 13 mils (0.30 to 0.33mm) and the via barrel be plated with 1 ounce copper to plug the via. This is desirable to avoid any solder wicking inside the via during the soldering process, which may result in voids in solder between the exposed pad and the thermal land. If the copper plating does not plug the vias, the thermal vias can be `tented' with solder mask on the top surface of the PCB to avoid solder wicking inside the via during assembly. The solder mask diameter should be at least 4 mils (0.1mm) larger than the via diameter. Package stand-off is also a consideration. For a nominal stand-off of 0.1mm (see Figure 28, dimension `A1'), the stencil thickness of 5 to 8 mils should provide a good solder joint between the E-pad and the thermal land. The aperture opening should be subdivided into an array of smaller openings. 34 SiI-DS-0127-A SiI 1178 PanelLink Transmitter Data Sheet 48-pin TSSOP Package 48-pin TSSOP Package Dimensions and Marking Specification JEDEC Package Code MO-153 L1 typ Device # E1 Date Code Revision Lot # Trace Code & Revision E SiIDDDDCSU LLLLLL.LL-L N.N LLLLLLLL YYWW A A1 A2 D1 E1 E L1 b c e Thickness Stand-off Body Thickness Body Size Body Size Footprint Lead Length Lead Width Lead Thickness Lead Pitch 9.70 4.40 max 1.10 0.15 0.95 9.80 4.50 6.40 0.95 0.23 0.20 0.40 Dimensions in millimeters. Overall thickness A=A1+A2. D1 Lead length L1 = (E-E1)/2. A2 A1 e b Ordering Information SiI-DS-0127-A Production Legend DDDD LNNNNN.LLL YY WW N.N LLLLLLL Figure 28. Package Diagram Production Part Number: Device Number SiIDDDD SiI1178CSU 35 SiI1178CSU Description Part Number Lot Number Year of Mfr Week of Mfr Revision Number Country of Packaging SiI 1178 PanelLink Transmitter Data Sheet (c) 2005 Silicon Image. Inc. Tel: Fax: E-mail: Web: Silicon Image, Inc. 1060 E. Arques Avenue Sunnyvale, CA 94085 USA 36 (408) 616-4000 (408) 830-9530 salessupport@siimage.com www.siliconimage.com SiI-DS-0127-A