Philips
Semiconductors
PCA8550
4-bit multiplexed/1-bit latched 5-bit
I2C EEPROM DIP switch
Product data
Supersedes data of 2001 Jan 12 2003 Jun 27
INTEGRATED CIRCUITS
Philips Semiconductors Product data
PCA8550
4-bit multiplexed/1-bit latched 5-bit
I2C EEPROM DIP switch
2
2003 Jun 27
FEATURES
•4-bit 2-to-1 multiplexer, 1-bit latch DIP switch
•5-bit internal non-volatile register
•Override input forces all outputs to logic 0
•Internal non-volatile register write/readable via I2C-bus
•Write-protect pin enables/disables I2C writes to register
•2.5 V multiplexed outputs
•3.3 V non-multiplexed output (latched)
•5 V tolerant inputs
•Useful for ‘jumperless’ configuration of PC motherboards
•Designed for use in Pentium Pro/Pentium II systems
DESCRIPTION
The primary function of the 4-bit 2-to-1 I2C multiplexer is to select
either a 4-bit input or data from a non-volatile register and drive this
value onto the output pins. One additional non-multiplexed register
output is also provided. The non-multiplexed output is latched to
prevent output value changes during I2C writes to the non-volatile
register. A write protect input is provided to enable/disable the ability
to write to the non-volatile register. An “override” input feature forces
all outputs to logic 0.
PIN CONFIGURATION
I2C SCL
I2C SDA
MUX_IN C
VCC
116
215
314
413
512
611
710
89
MUX_IN D
GND
MUX_OUT B
MUX_OUT C
MUX_OUT D
SW00579
OVERRIDE_N
MUX_IN A MUX_SELECT
MUX_OUT A
MUX_IN B
WP
NON_MUXED_OUT
Figure 1. Pin configuration
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER
16-Pin Plastic SO 0 to +70 °C PCA8550D PCA8550 SOT109-1
16-Pin Plastic SSOP 0 to +70 °C PCA8550DB PA8550 SOT338-1
16-Pin Plastic TSSOP 0 to +70 °C PCA8550PW PCA8550 SOT403-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
FUNCTIONAL DESCRIPTION
When the MUX_SELECT signal is logic 0, the multiplexer will select
the data from the non-volatile register to drive on the MUX_OUT
pins. When the MUX_SELECT signal is logic 1, the multiplexer will
select the MUX_IN lines to drive on the MUX_OUT pins. The
MUX_SELECT signal is also used to latch the NON_MUXED_OUT
signal which outputs data from the non-volatile register. The
NON_MUXED_OUT signal latch is transparent when MUX_SELECT
is in a logic 0 state, and will latch data when MUX_SELECT is in a
logic 1 state. When the active-LOW OVERRIDE_N signal is set to
logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will
be driven to logic 0. This information is summarized in Table 1.
The write protect (WP) input is used to control the ability to write the
contents of the 5-bit non-volatile register. If the WP signal is logic 0,
the I2C-bus will be able to write the contents of the non-volatile
register. If the WP signal is logic 1, data will not be allowed to be
written into the non-volatile register.
The factory default for the contents of the non-volatile register are all
logic 0. These stored values can be read or written using the
I2C bus (described in the next section).
The OVERRIDE_N, WP, MUX_IN, and MUX_SELECT signals have
internal pull-up resistors. See the DC and AC Characteristics for
hysteresis and signal spike suppression figures.
Pentium II is a registered trademark of Intel Corporation.
Philips Semiconductors Product data
PCA8550
4-bit multiplexed/1-bit latched 5-bit
I2C EEPROM DIP switch
2003 Jun 27 3
PIN DESCRIPTION
PIN
NUMBER SYMBOL FUNCTION
1 I2C SCL I2C-bus clock
2 I2C SDA Bi-directional I2C-bus data
3 OVERRIDE_N Forces all outputs to logic 0
4MUX_IN A
5MUX_IN B
6MUX_IN C External inputs to multiplexer
7MUX_IN D
8 GND Common ground voltage rail
9MUX_OUT D
10 MUX_OUT C
11 MUX_OUT B 2.5 V multiplexed output
12 MUX_OUT A
13 MUX_SELECT Selects MUX_IN inputs or
register contents for
MUX_OUT outputs
14 NON_MUXED_OUT TTL-level output from
non-volatile memory
15 WP Non-volatile register
write-protect
16 VCC Positive voltage rail
FUNCTION TABLE
Table 1. Function table
OVERRIDE
_N MUX_SELECT MUX_OUT
OUTPUTS NON_MUXED_OUT
OUTPUT
0 0 All 0’sAll 0’s
0 1 MUX_IN
inputs Latched
NON_MUXED_OUT1
1 0 From non-
volatile
register From non-volatile
register
1 1 MUX_IN
inputs From non-volatile
register
NOTE
1. Latched NON_MIXED_OUT state will be the value present on
the NON_MUXED_OUT output at the time of the MUX_SELECT
input transitioned from a logic 0 to a logic 1 state.
I2C INTERFACE
Communicating with this device is initiated by sending a valid
address on the I2C-bus. The address format (see FIgure 2) is a fixed
unique 7-bit value followed by a 1-bit read/write value which
determines the direction of the data transfer.
100
1 1 1 0 R/W
LSB
MSB
Figure 2. I2C Address Byte
Following the address and acknowledge bit are 8 data bits which,
depending on the read/write bit in the address, will read data from or
write data to the non-volatile register. Data will be written to the
register if the read/write bit is logic 0 and the WP input is logic 0.
Data will be read from the register if the bit is logic 1. The three
high-order bits (see FIgure 3) are logic 0. The next bit is data which
is non-multiplexed. The low four bits are the data which will be
multiplexed. A write with any of the first three bits non-zero will be
aborted.
NOTE:
1. To ensure data integrity, the non-volatile register must be
internally write protected when VCC to the I2C-bus is powered
down or VCC to the component is dropped below normal
operating levels.
LSB
MSB
MUX
DATA A
MUX
DATA B
MUX
DATA C
MUX
DATA D
NON-
MUXED
DATA
000
Figure 3. I2C Data Byte
POWER-ON RESET (POR)
When power is applied to VCC, an internal power-on reset holds the
PCA8550 in a reset state until VCC has reached VPOR. At that point,
the reset condition is released and the PCA8550 volatile registers
and I2C state machine will initialize to their default states.
The MUX_OUT and NON_MUXED_OUT pin values depend on:
-the OVERRIDE_N and MUX_SELECT logic levels
-the previously stored values in the EEPROM register/current
MUX_IN pin values as shown in Table 1.
Philips Semiconductors Product data
PCA8550
4-bit multiplexed/1-bit latched 5-bit
I2C EEPROM DIP switch
2003 Jun 27 4
BLOCK DIAGRAM
5-BIT EEPROM
0
SELECT
NON_MUX_OUT
14
I C INTERFACE LOGIC
4-BIT 2-to-1 MULTIPLEXER
1
3.3 V
3.3 V
3.3 V
3.3 V
2.5 V
2.5 V
2.5 V
2.5 V
A20M
MUX_OUT A
/FSBM0
IGNNE
MUX_OUT B
/FSBM1
LINT1/NMI
MUX_OUT C
/FSBM2
LINT0/INTR
MUX_OUT D
/FSBM3
OE
13
3
15
4
5
6
7
CHIP
SET
WRITE
PROTECT
A20M
MUX_IN A
IGNNE
MUX_IN B
LINT1/NMI
MUX_IN C
LINT0/INTR
MUX_IN D
OVERRIDE_N
CRESET
MUX_SELECT
10-30 kΩ
10-30k ΩPENTIUM PRO/
PENTIUM II
PROCESSORS
12
11
10
9
SW00347
10-30 kΩ
NMO
LATCH
2
2 SDA
1 SCL
16 VCC
8 GND
POWER-ON
RESET
INPUT
FILTER
100-150 kΩ
Figure 4. Block diagram
Philips Semiconductors Product data
PCA8550
4-bit multiplexed/1-bit latched 5-bit
I2C EEPROM DIP switch
2003 Jun 27 5
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage -0.5 to +4.6 V
VIDC input voltage Note 3 -1.5 to VCC +1.5 V
VOUT DC output voltage Note 3 -0.5 to VCC +0.5 V
Tstg Storage temperature range -60 to +150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
VCC DC supply voltage 3.0 3.6 V
VPOR Power-on reset voltage No load; VI = VDD or GND —2.6 V
VIL LOW-level input voltage SCL, SDA IOL= 3 mA -0.5 0.9 V
VIH HIGH-level input voltage SCL, SDA IOL= 3 mA 2.7 4.0 V
VOL LOW-level output voltage SCL, SDA IOL= 3 mA —0.4 V
VIL LOW-level input voltage OVERRIDE_N,
MUX_IN,
MUX_SELECT -0.5 0.8 V
VIH HIGH-level input voltage OVERRIDE_N,
MUX_IN,
MUX_SELECT 2.0 4.0 V
IOL LOW-level output current MUX_OUT
NON_MUXED_OUT —2.0 mA
IOH HIGH-level output current MUX_OUT
NON_MUXED_OUT —-2.0 mA
dt/dv Input transition rise or fall time 0 10 ns/V
Tamb Operating ambient temperature 0 70 °C
Philips Semiconductors Product data
PCA8550
4-bit multiplexed/1-bit latched 5-bit
I2C EEPROM DIP switch
2003 Jun 27 6
DC CHARACTERISTICS
Temp = 0 to +70 °C 3.0 V < VCC ≤ 3.6 V
LIMITS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
SCL, SDA
VOL LOW-level output voltage 0 0.6 V
IOL LOW-level output current VOL = 0.4 V 3.0 mA
IOL LOW-level output current VOL = 0.6 V 6.0 mA
IIL1LOW-level input current VIL = 0.4 V -7 -32 µA
IIH HIGH-level input current VIH = 2.4 V -1.5 -12 µA
Vhys Hysteresis voltage 0.19 V
OVERRIDE_N, WP, MUX_SELECT
IIL LOW-level input current -86 -267 µA
IIH HIGH-level input current -20 -100 µA
MUX_IN A ⇒ D
IIL LOW-level input current VIL = 0.4 V -0.72 -2.0 mA
IIH HIGH-level input current VIH = 2.4 V -0.72 -2.0 mA
MUX_OUT
IOL = 100 µA -0.3 0.4
VOL LOW-level output voltage IOL = 2.0 mA -0.3 0.7 V
IOH = -100 µA 2.0 2.625
VOH HIGH-level output voltage IOH = -1.0 mA 1.7 2.625 V
NON_MUXED_OUT
IOL = 100 µA -0.5 0.4
VOL LOW-level output voltage IOL = 2.0 mA -0.5 0.7 V
IOH = -100 µA 2.4 3.6
VOH HIGH-level output voltage IOH = -2.0 mA 2.0 3.6 V
ICC Quiescent supply current VCC = 3.3 V; VI = 0 V to VCC 10 mA
ICC Quiescent supply current VI = VCC 500 µA
CIInput capacitance 10 pF
ESD protection 2.0 KV
Input diode clamp voltage -1.5 V
NOTES:
1. VHYS is the hysteresis of Schmitt-Trigger inputs
2. Human body model
NON-VOLATILE STORAGE SPECIFICATIONS
Parameter Specification
Memory cell data retention 10 years min
Number of memory cell write cycles 100,000 cycles min
Application Note AN250 I2C DIP Switch provides additional information on memory cell data retention and the minimum number of write cycles.
Philips Semiconductors Product data
PCA8550
4-bit multiplexed/1-bit latched 5-bit
I2C EEPROM DIP switch
2003 Jun 27 7
AC CHARACTERISTICS
LIMITS
SYMBOL PARAMETER MIN MAX UNIT
tMPD Mux input to output propagation delay 20.0 ns
tSOV MUX_SELECT to output valid 22 ns
tOVN OVERRIDE_N to NON_MUX output delay 15.0 ns
tOVM OVERRIDE_N to mux output delay 25.0 ns
tROutput rise time 1.0 3.0 ns/V
tFOutput fall time 1.0 3.0 ns/V
CLTest load capacitance on Muxed/Non-Muxed
outputs 15 pF
I2C-bus
fSCL I2C clock frequency 10 400 KHz
tSCH I2C clock HIGH time 600 ns
tSCL I2C clock LOW time 1.3 ns
tDSP I2C data spike time 0 50 ns
tSDS I2C data set-up time 100 ns
tSDH I2C data hold time 0 ns
tICR I2C input rise time (10-400 pF bus) 20 300 ns
tICF I2C input fall time (10-400 pF bus) 20 300 ns
tBUF I2C-bus free time between start and stop 1.3 ns
tSTS I2C repeated start condition set-up 600 ns
tSTH I2C repeated start condition hold 600 ns
tSPS I2C stop condition set-up 600 ns
CBI2C-bus capacitive load 400 pF
TWWrite cycle time1TYPICAL = 15 ms
NOTE:
1. WRITE CYCLE time can only be measured indirectly during write cycle. The device will not acknowledge its I2C address.
Philips Semiconductors Product data
PCA8550
4-bit multiplexed/1-bit latched 5-bit
I2C EEPROM DIP switch
2003 Jun 27 8
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Philips Semiconductors Product data
PCA8550
4-bit multiplexed/1-bit latched 5-bit
I2C EEPROM DIP switch
2003 Jun 27 9
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
Philips Semiconductors Product data
PCA8550
4-bit multiplexed/1-bit latched 5-bit
I2C EEPROM DIP switch
2003 Jun 27 10
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
Philips Semiconductors Product data
PCA8550
4-bit multiplexed/1-bit latched 5-bit
I2C EEPROM DIP switch
2003 Jun 27 11
REVISION HISTORY
Rev Date Description
_6 20030627 Product data (9397 750 11678); ECN 853-2015 29936 dated 19 May 2003.
Supersedes data of 2001 Jan 12 (9397 750 07926).
Modifications:
•Update marketing information.
•Increase number of write cycles from 3K to 100K.
_5 20010112 Product data (9397 750 07926); ECN 853-2015 25405 of 12 Jan 2001.
Philips Semiconductors Product data
PCA8550
4-bit multiplexed/1-bit latched 5-bit
I2C EEPROM DIP switch
2003 Jun 27 12
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right t o make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Koninklijke Philips Electronics N.V. 2003
All rights reserved. Printed in U.S.A.
Date of release: 06-03
Document order number: 9397 750 11678
Philips
Semiconductors
Data sheet status[1]
Objective data
Preliminary data
Product data
Product
status[2] [3]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Level
I
II
III
