OVERVIEW
®
Phone: 949-450-8700
Fax: 949-450-8710
E-mail: info@broadcom.com
Web: www.broadcom.com
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2004 by BROADCOM CORPORATION. All rights reserved.
8152-PB02-R 04/23/04
Broadcom®, the pulse logo, and Connecting everything® are trademarks of Broadcom Corporation and/
or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the
property of their respective owners.
The BCM8152 is a fully integrated MSA-compatible multi-rate
SONET/SDH/10GE/FEC transceiver operating at the OC-192/STM-64
(9.953 Gbps), 10GE (10.3125 Gbps), 10GFC (10.315 Gbps), or one of
three FEC (Forward Error Correction) (10.664/10.709, 11.096, or 11.31
Gbps) data rates with serializer, deserializer, integrated clock
multiplication unit (CMU), 10G clock, bus skew, limiting amplifier, data
recovery circuit (CDR), and enhanced feature set. On-chip clock
synthesis is performed by the high-frequency, low-jitter phase-locked
loop (PLL) on the BCM8152 transceiver chip allowing the use of a low-
frequency reference clock selectable to the line rate divided by either 16
or 64.
Clock recovery is performed on the device by synchronizing its on-chip
voltage-controlled oscillator (VCO) directly to the incoming data stream.
An on-chip phase detector and charge pump plus external VCXO
implements a cleanup PLL. The cleanup PLL can be used to clean up the
CDR recovered clock for loop timing applications or to clean up a noisy
system clock.
The low-jitter LVDS interface guarantees compliance with the bit error
rate requirements of the Telcordia, ANSI, ITU-T, and IEEE 802.3ae
standards.
The BCM8152 is packaged in a 15 x 15 mm, 301-pin BGA.
C
B
FIFO
Control
Write
Pointer
Read
Pointer
16 x 10
FIFO
Output
Retimer
16:1
MUX
TxFIFOERRB
RB_TX
TSDP
TSDN
TSCLKP
TSCLKN
PDTSCLK
POR
TxRESETB
TxPICLKSEL
SKEW1/0
TxPOLSEL
TxLSBSEL
TxDIN[15:0]P
TxDIN[15:0]N
TxPICLKP
TxPICLKN
RB_LVDSIN
Multi-rate CMU
TxPCLKN
TxLOCKERRB
TxMCLKP
TxMCLKP
TxPCLKP
TxRATESEL1/0
IFSEL
VCP/VCN_CMU
TxREFSEL
TxREFCLKN
TxREFCLKP
C
Input
Register 16
B
Parallel
LVDS
Inputs
CML
Serial
Input
TxMCLKSEL
RxMUTEPOCLKB
RxMUTEMCLKB
RxDOUT[15:0]P
RxDOUT[15:0]N
RxPOCLKP
RxPOCLKN
RxMCLKP
RxMCLKN
ALOSB
VCP/VCN_CDR
Register
RDINN
RDINP
TH_ALOSB2/1
Parallel
LVDS
RB_ALOSB
RB_LVDSOUT
RxMUTEDOUTB
ALOS
DETECT
CML
Limiting
1:16
DeMux
Multi-Rate
CDR
Output
RXLSBSEL
RxPOLSEL
Amplifier
A
RxRATESEL1/0
RxREFSEL
RxLCKREFB
LOSIB
RxLOCKERRB
A
A
A
RxMCLKSEL
Outputs
Serial
Input
RxREFCLKP
RxREFCLKN
16
RxREFCKENB
OFFSETP/N
ENEXTOFST
RxPHSADJ[2:0,FINE]