LP3997 www.ti.com SNVS272B - MAY 2004 - REVISED MAY 2013 Micropower 250-mA CMOS LDO Regulator With Error Flag and Power-On-Reset Check for Samples: LP3997 FEATURES DESCRIPTION * * * * * * * * The LP3997 regulator is designed to meet the requirements of portable, battery-powered systems, providing accurate output voltage, low noise, and low quiescent current. The LP3997 provides 3.3V output at up to 250mA load current. The chip architecture is capable of providing output voltages as low as 0.8V. When switched in shutdown mode, the power consumption is virtually zero. 1 2 Low 140-mV Dropout at 250-mA Load Stable With Ceramic Capacitor. Low Noise With Bypass Capacitor Less Than 80 A Typical IQ at 250 mA Virtually Zero IQ (Disabled) Thermal and Short Circuit Protection 3.3-V Output (1) 8-Lead VSSOP Package (2) The LP3997 is designed to be stable with space saving ceramic output capacitor as small as 1F. The LP3997 also includes an out-of-regulation error flag. When the output is more than 5% below its nominal voltage, the error flag sets to low. If a capacitor is connected to device's delay pin, a delayed power-on reset signal will be generated. APPLICATIONS * * * * * (1) (2) Portable Consumer Electronics Cellular Handsets Laptop and Palm Computers PDAs Digital Cameras For other voltage options, contact your TI sales office For other package options, contact your TI sales office. Typical Application Circuit 4 VIN 5 VIN 6 8 Enable VOUT VOUT SENSE SD 470k LP3997 7 2 Error/POR ERROR DELAY 1 GND 2.2 PF 0.1 PF 3 CBYP 0.1 PF 2.2 PF 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2013, Texas Instruments Incorporated LP3997 SNVS272B - MAY 2004 - REVISED MAY 2013 www.ti.com Functional Block Diagram VIN VOUT + SENSE ON OFF SD RFB2 POR 2.2 PA 0.5V ERROR 6 M: RFB1 VREF 1.2V + - GND CBYP DELAY Pin Descriptions Pin No. Name Description 1 CBYP Noise bypass pin. For low noise applications a 0.1F or larger ceramic capacitor should be connected from this pin to ground. This will also improve PSSR. 2 DELAY A capacitor connected from this pin to ground will allow a delayed power-on-reset signal at the ERROR (pin 7) output. See Applications Information. 3 GND Ground pin. Local ground for CBYP ,CIN, COUT and CDELAY. 4 VIN Input supply pin. Connect CIN between this pin and GND. 5 VOUT 6 SENSE Connect this pin to VOUT (pin 5). For best performance the connection should be made as close to the load as possible. 7 ERROR This open drain output is an error flag output which goes low when VOUT drops 5% below its nominal voltage. This pin also provides a power-on-reset signal if a capacitor is connected to the DELAY pin. 8 SD Output voltage, Connect COUT between this pin and ground. Shutdown. Disables the regulator when less than 0.4V is applied. Enables the regulator when greater than 0.9V. The Shutdown pin is pulled down internally by a 6M resistor. Connection Diagram CBYP 1 8 SD DELAY 2 7 ERROR GND 3 6 SENSE VIN 4 5 VOUT 8-Lead VSSOP Package Number DGK 2 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LP3997 LP3997 www.ti.com SNVS272B - MAY 2004 - REVISED MAY 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Input Voltage -0.3 to 6.5V Output Voltage -0.3 to (VIN + 0.3V) with 6.5V (max) SD Input Voltage -0.3 to (VIN + 0.3V) with 6.5V (max) Junction Temperature 150C Lead/Pad Temp. VSSOP 260C Storage Temperature -65 to 150C Internally Limited (4) Continuous Power Dissipation Human Body Model (5) All Pins Except CBYP Machine Model ESD (2) (3) (4) (5) 200V Human Body Model (5) CBYP Pin (1) 2KV 1KV Machine Model 100V Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics tables. All Voltages are with respect to the potential at the GND pin. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Internal thermal shutdown circuitry protects the device from permanent damage. The human body model is 100pF discharged through a 1.5k resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. Operating Ratings (1) Input Voltage 2V to 6V Junction Temperature -40C to 125C Ambient Temperature TA Range (2) (1) (2) -40C to 85C Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics tables. The maximum ambient temperature (TA(max)) is dependant on the maximum operating junction temperature (TJ(max-op) = 125C), the maximum power dissipation of the device in the application (PD(max)), and the junction to ambient thermal resistance of the part/package in the application (JA), as given by the following equation: TA(max) = TJ(max-op) - (JA x PD(max)). Thermal Properties (1) Junction To Ambient Thermal Resistance (2), JA (VSSOP) (1) (2) 210C/W Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics tables. Junction to ambient thermal resistance is dependant on the application and board layout. In applications where high maximum power dissipation is possible, special care must be paid to thermal dissipation issues in board design. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LP3997 3 LP3997 SNVS272B - MAY 2004 - REVISED MAY 2013 www.ti.com Electrical Characteristics Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN = 2.2 F, IOUT = 1 mA, COUT = 2.2 F and CBYP = 0.1 F. Typical values and limits appearing in normal type apply for TJ = 27C. Limits appearing in boldface type apply over the full temperature range for operation, -40 to +125C. (1) Symbol Parameter VIN Input Voltage VOUT Output Voltage Tolerance Test Conditions Typ Over full line and load regulation Line Regulation Error VIN = (VOUT(NOM) + 1.0V) to 6.0V, IOUT = 1mA Limit Unit Min Max 2 6 V -1.5 +1.5 % -3 +3 0.02 0.3 %/V Load Regulation Error IOUT = 1mA to 250mA 20 80 V/mA VDO Dropout Voltage (2) IOUT = 250mA 140 400 mV ILOAD Load Current See IQ Quiescent Current SD = 950mV, IOUT = 0mA 55 100 SD = 950mV, IOUT = 250mA 80 150 0.01 0.5 (3) (4) 0 SD = 0.4V ISC Short Circuit Current Limit IOUT Maximum Output Current PSRR Power Supply Rejection Ratio See (5) 600 A 1000 250 CBYP = 0.1F Without CBYP f = 1kHz, IOUT = 1mA to 150mA 61 f = 10kHz, IOUT = 150mA 55 f = 1kHz, IOUT = 1mA to 150mA 61 f = 10kHz, IOUT = 150mA 39 en Output noise Voltage (4) BW = 10Hz to 100kHz, w/o CBYP VIN = VOUT(nom) +1V CBYP = 0.1F 180 TSHUTDOWN Thermal Shutdown Temperature 150 Hysteresis 10 Maximum Input Current at SD Input SD = 0.0V 0.01 VIL Low Input Threshold VIN = 2V to 6V VIH High Input Threshold VIN = 2V to 6V A mA mA dB VRMS 100 C Shutdown Control Characteristics ISD SD = 6V (6) A 1 0.4 0.95 V V Error Flag Characteristics VTH Power Good Trip Threshold VIN Rising 95 VHYST Hysteresis VIN Rising or Falling 2.5 VOL ErrorError OutputOutput low Voltage ISINK = 2mA 0.1 IOFF Error Output High Leakage ERROR = VOUT(NOM) 10 IDELAY Delay Pin Current Source VOUT > 95% VOUT(NOM) 2.2 (1) (2) (3) (4) (5) (6) 4 91 99 %VOUT %VOUT 0.4 1.2 V 2000 nA 3 A All limits are ensured. All electrical characteristics having room-temperature limits are tested during production at TJ = 25C or correlated using Statistical Quality Control methods. Operation over the temperature specification is ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Dropout voltage is defined as the voltage difference between input and output when the output voltage drops 100mV below its nominal value. The device maintains the regulated output voltage without the load. This electrical specification is ensured by design. Short circuit current is measured on the input supply line at the point when the short circuit condition reduces the output voltage to 5% of its nominal value. SD Pin has 6M typical, resistor connected to GND. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LP3997 LP3997 www.ti.com SNVS272B - MAY 2004 - REVISED MAY 2013 Electrical Characteristics (continued) Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN = 2.2 F, IOUT = 1 mA, COUT = 2.2 F and CBYP = 0.1 F. Typical values and limits appearing in normal type apply for TJ = 27C. Limits appearing in boldface type apply over the full temperature range for operation, -40 to +125C. (1) Symbol Parameter Test Conditions Typ Limit Min Max Unit Timing Characteristics tON Turn On Time Transient Response (7) (7) To 95% Level w/o CBYP Line Transient Response |VOUT| Trise = Tfall = 30s (7) VIN = 600mV Load Transient Response |VOUT| Trise = Tfall = 1s (7) IOUT = 1mA to 150mA 150 250 s CBYP = 0.1F 2 ms w/o CBYP 40 CBYP = 0.1F 4 mV (pk - pk) 70 80 mV This electrical specification is ensured by design. Output Capacitor, Recommended Specifications Symbol Co Parameter Output Capacitor Conditions Capacitance (1) ESR (1) Typ 2.2 Limit Min Max Unit 0.7 5 F 500 m The capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be considered when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor type is X7R. However, dependent on application, X5R, Y5V, and Z5U can also be used. (See capacitor characteristics section in Applications Information). Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LP3997 5 LP3997 SNVS272B - MAY 2004 - REVISED MAY 2013 www.ti.com Typical Performance Characteristics. Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN = 2.2 F, IOUT = 1 mA, COUT = 2.2 F and CBYP = 0.1 F. Typical values and limits appearing in normal type apply for TJ = 27C. Limits appearing in boldface type apply over the full temperature range for operation, -40 to +125C. Output Voltage Change vs Temperature Ground Current vs Load Current 100 3.00 90 GROUND CURRENT (PA) VOUT CHANGE (%) 2.00 1.00 0.00 -1.00 -2.00 TA = 125oC 80 70 TA = -40oC 60 50 TA = 25oC 40 30 20 10 -3.00 -50 0 -25 0 25 50 75 100 0 125 50 TEMPERATURE (oC) 120 110 110 100 100 90 90 80 TA = 25oC 70 60 TA = 85oC 50 40 80 TA = 25oC 70 TA = 85oC 60 40 TA = -40oC TA = -40oC 30 4 4.5 5 5.5 20 3.5 6 Ground Current vs VIN. ILOAD = 250mA 110 DROPOUT VOLTAGE (mV) GND I (PA) 5.5 6 180 TA = 85oC 80 TA = -40oC 50 40 30 160 140 TA = 125oC 120 100 80 TA = -40oC 60 40 TA = 25oC 20 0 4 4.5 5 5.5 6 VIN 6 5 Dropout Voltage vs Load Current TA = 25oC 60 4.5 200 100 70 4 VIN 120 20 3.5 250 Ground Current vs VIN. ILOAD = 1mA VIN 90 200 50 30 20 3.5 150 LOAD CURRENT (mA) Ground Current vs VIN. ILOAD = 0mA GND I (PA) GND I (PA) 120 100 0 50 100 150 200 250 LOAD CURRENT (mA) Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LP3997 LP3997 www.ti.com SNVS272B - MAY 2004 - REVISED MAY 2013 Typical Performance Characteristics. (continued) Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN = 2.2 F, IOUT = 1 mA, COUT = 2.2 F and CBYP = 0.1 F. Typical values and limits appearing in normal type apply for TJ = 27C. Limits appearing in boldface type apply over the full temperature range for operation, -40 to +125C. VIN (V) 4.9 4.3 'VOUT 'VOUT (20 mV/DIV) Line Transient CIN = COUT = 2.2 PF CBYP = 0 IL = 1 to 250 mA 4.9 4.3 (10 mV/DIV) VIN (V) Line Transient CIN = COUT = 2.2 PF CBYP = 0.1 PF IL = 1 to 250 mA TIME (100 Ps/DIV) TIME (100 Ps/DIV) Load Transient (No CBYP) Enable Start-up Time CBYP = 0 CIN = COUT = 2.2 PF VOUT (1V/DIV) VSD 250 (1V/DIV) 'VOUT LOAD CURRENT (mA) (50 mV/DIV) IL = 1 mA 1 TIME (500 Ps/DIV) TIME (100 Ps/DIV) Enable Start-up Time (1V/DIV) VOUT VIN = 4.3V VOUT (1V/DIV) CBYP = 0.1 PF IL = 1 mA Short Circuit Current CURRENT (A) (1V/DIV) VSD 2.0 1.5 1.0 0.5 0 TIME (500 Ps/DIV) TIME (50 Ps/DIV) Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LP3997 7 LP3997 SNVS272B - MAY 2004 - REVISED MAY 2013 www.ti.com Typical Performance Characteristics. (continued) Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN = 2.2 F, IOUT = 1 mA, COUT = 2.2 F and CBYP = 0.1 F. Typical values and limits appearing in normal type apply for TJ = 27C. Limits appearing in boldface type apply over the full temperature range for operation, -40 to +125C. Power Supply Rejection Ratio 0 CBYP = 0.1 PF -10 IOUT = 150 mA -20 CBYP = 0 -30 NOISE (PV/ Hz) RIPPLE REJECTION (dB) Noise Spectrum 10 -40 -50 IOUT = 1 mA -60 1 CBYP = 0.1 PF 0.1 -70 -80 -90 100 1k 10k 100k 1M 0.01 0.1 1 10 FREQUENCY (kHz) FREQUENCY (kHz) Turn-On Sequence Turn-Off Sequence VIN 2V/DIV CDELAY = 0.1 PF CBYP = 0 ILOAD = 250 mA VIN 2V/DIV CDELAY = 0.1 PF CBYP = 0 ILOAD = 250 mA 100 VOUT 2V/DIV VOUT 2V/DIV CDELAY 2V/DIV CDELAY 2V/DIV ERROR 2V/DIV ERROR 2V/DIV TIME (50 Ps/DIV) TIME (20 ms/DIV) 8 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LP3997 LP3997 www.ti.com SNVS272B - MAY 2004 - REVISED MAY 2013 Applications Information External Capacitors In common with most regulators, the LP3997 requires the inclusion of external capacitors. VIN An input capacitor is required for stability. It is recommended that a minimum of 1.0F capacitor is connected between the LP3997 input pin and ground (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: To ensure stable operation it is essential that good PCB design practices are employed to minimize ground impedance and keep input inductance low. If these conditions cannot be met, or if long wire leads are used to connect the battery or other power source to the LP3997, then it is recommended to increase the input capacitor to at least 2.2F. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain 1.0F over the entire operating temperature range. VOUT VOUT is the output voltage of the regulator. Connect capacitance (minimum 1.0F) to ground from this pin. To ensure stability the capacitor must meet the minimum value for capacitance and have an ESR in the range 5m to 500m. Ceramic X7R types are recommended. If an output capacitor larger than 4.7F is fitted then checks on in-rush current, transient performance and stability, should be made. SENSE SENSE is used to sense the output voltage. Connect sense to VOUT SHUTDOWN SD controls the turning on and off of the LP3997. VOUT is ensured to be on when the voltage on the SD pin is greater than 0.95V. VOUT is ensured to be off when the voltage on the SD pin is less than 0.4V. ERROR ERROR is an open drain output which is set low when VOUT is more than 5% below its nominal value. An external pull up resistor is required on this pin. When a capacitor is connected from DELAY to GROUND, the error signal is delayed (see DELAY section). This delayed error signal can be used as the power-on reset signal for the application system. The ERROR pin is disconnected when not used. DELAY A capacitor from DELAY to GROUND sets the time delay for ERROR changing from low to high state. The delay time is set by the following formula. t DELAY VTH(DELAY) X C DELAY = I DELAY VTH(DELAY) is nominally 1.2V. The DELAY pin should be open circuit if not used. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LP3997 9 LP3997 SNVS272B - MAY 2004 - REVISED MAY 2013 www.ti.com CBYP For low noise application, connect a high frequency ceramic capacitor from CBYP to ground, A 0.01F to 0.1F X5R or X7R is recommended. This capacitor is connected directly to high impedance node in the band gap reference circuit. Any significant loading on this node will cause a change in the regulated output voltage. For this reason, DC leakage current from this pin must be kept as low as possible for best output voltage accuracy. CAPACITOR CHARACTERISTICS In common with most regulators, the LP3997 requires external capacitors for regulator stability. The LP3997 is specifically designed for portable applications requiring minimum board space and can use capacitors in the range 1F to 4.7F.These capacitors must be correctly selected for good performance. Ceramic capacitors are the smallest, least expensive and have the lowest ESR values (which makes them best for eliminating high frequency noise). The ESR of a typical 1F ceramic capacitor is in the range of 20 m to 40 m, which easily meets the ESR requirement for stability by the LP3997.These capacitors must be correctly selected to ensure good performance of the LP3997. For both input and output capacitors careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly dependant on the conditions of operation and capacitor type. CAP VALUE (% of Nom. 1 PF) In particular the output capacitor selection should take account of all the capacitor parameters to ensure that the specification is met within the application. Capacitance value can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependant on the particular case size with smaller sizes giving poorer performance figures in general. As an example Figure 1 shows a typical graph showing a comparison of capacitor case sizes in a Capacitance versus DC Bias plot. As shown in the graph, as a result of the DC Bias condition, the capacitance value may drop below the minimum capacitance value given in the recommended capacitor table (0.7F in this case). Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions as some capacitor sizes (e.g. 0402) may not be suitable in the actual application. 0603, 10V, X5R 100% 80% 60% 0402, 6.3V, X5R 40% 20% 0 1.0 2.0 3.0 4.0 5.0 DC BIAS (V) Figure 1. Capacitance versus DC Bias Plot The value of ceramic capacitors can vary with temperature. The capacitor type X7R, which operates over a temperature range of -55C to +125C, will only vary the capacitance to within 15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of -55C to +85C. Most large value ceramic capacitors, larger than 1F are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature goes from 25C to 85C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1F to 4.7F range. 10 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LP3997 LP3997 www.ti.com SNVS272B - MAY 2004 - REVISED MAY 2013 Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly ) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25C down to -40C, so some guard band must be allowed. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LP3997 11 LP3997 SNVS272B - MAY 2004 - REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Revision A (May 2013) to Revision B * 12 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 11 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LP3997 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) LP3997MM-3.3/NOPB ACTIVE Package Type Package Pins Package Drawing Qty VSSOP DGK 8 1000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM Op Temp (C) Device Marking (4/5) -40 to 125 SAKB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LP3997MM-3.3/NOPB Package Package Pins Type Drawing VSSOP DGK 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 178.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3997MM-3.3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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