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March 2010 Rev. 1.0.0
Exar Corporation www.exar.com
48720 Kato Road, Fremont CA 94538, USA Tel. +1 510 668-7000 – Fax. +1 510 668-7001
GENERAL DESCRIPTION
The XRP6142 is a synchronous step down
switching controller for over 15 Amps point-of-
loads converters and optimized to generate
and support DDR I, II and III memory
voltages requirements.
Optimized to operate from standard 3.3V and
5V rails, the XRP6142 supports conversions
down to 0.5V from an input voltage as low as
1V and can reach efficiencies of up to 96%.
Based on a constant on-time control scheme
and operating at a constant switching
frequency over the whole input voltage range,
it provides excellent load transient response
while requiring no external compensation
components. Three selectable on-time options
allow for further switching frequency, solution
footprint and efficiency optimization.
Dedicated support for DDR I, II and II
memories is also provided. The XRP6142
easily generates V
DDQ
(V
DD
) or V
TT
voltages
while an on board buffer provides the buffered
V
TT
reference voltage.
Under-voltage Lock out, short-circuit and
over-current and over-temperature protection
insure safe operations under abnormal
operating conditions.
The XRP6142 is available in a compact RoHS
compliant “green”/halogen free 16-pin QFN
package.
APPLICATIONS
• High-Power Point-of-Loads Converters
• Audio-Video Equipments
• FPGA and DSP Power Supplies
• DDR Memory Based Embedded Systems
FEATURES
• Over 15A Point-of-Load Capable
− Down to 0.5V Output Voltage Conversion
− Up to 96% Efficiency
• Wide 1.0V-5.5V Input Voltage Range
Conversions
− Single Input 3.3V and 5V rails Operations
• Constant On-Time Operations
− Constant Frequency Operations
− No External Compensation
• DDR I, II & III Termination Support
− V
DDQ
/V
DD
or V
TT
Voltages Generation
− Buffered V
TT
Ref. Voltage Generation
• Soft-Start and Enable Functions
• UVLO, Short Circuit and Over Current
Protection
• RoHS Compliant “Green”/Halogen Free
3mm x 3mm 16-Pin QFN Package
TYPICAL APPLICATION DIAGRAM
Figure. 1: XRP6142 as a Step-Down Converter or a DDR Supply
AGND
VIN
VOUT
R1
R2
L1
PGND
VCC
EN
VREF
REFIN
VIN
BST
FB
Thermal
Pad
VTTREF
VDDQ/2
SW
ILIM
GL
CSGND
GH
XRP6142 CFF COUT
QB
QT
CIN
3V-5.5V
SP2996B
VTT
VIN
GND
ACNTL
REF EN
VOUT
VDDQ
VREF
Operation as DDR Supply
R3
R4
RLIM
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© 2010 Exar Corporation Page 2 of 17 Rev. 1.0.0
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only, and functional operation of
the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect
reliability.
V
CC
...................................................................... 7.0V
V
IN
....................................................................... 7.0V
BST .................................................................... 13.5V
SW ............................................................. -1V to 7.0V
BST-SW ...................................................... -0.3V to 6V
All other pins ..................................... -0.3V to V
CC
+0.3V
Storage Temperature .............................. -65°C to 150°C
Power Dissipation ................................ Internally Limited
Lead Temperature (Soldering, 10 sec) ................... 300°C
ESD Rating (HBM - Human Body Model) .................... 2kV
ESD Rating (MM - Machine Model) ........................... 500V
OPERATING RATINGS
Input Voltage Range V
CC
.............................. 3.0V to 5.5V
Input Voltage Range V
IN
............................... 1.0V to 5.5V
Junction Temperature Range .................... -40°C to 125°C
Thermal Resistance θ
JA
................................... 33.3°C/W
ELECTRICAL SPECIFICATIONS
Specifications are for an Operating Junction Temperature of T
J
= 25°C; limits applying over the full Operating Junction
Temperature range are denoted by a “•”. Minimum and Maximum limits are guaranteed through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at T
J
= 25°C, and are provided for reference purposes
only. Unless otherwise indicated, V
CC
= V
IN
= 3.3V.
Parameter Min. Typ. Max. Units Conditions
V
REF
, Reference Voltage 0.495 0.5 0.505 V
0.492 0.5 0.508 V •
V
FB
offset 7 mV
V
REFIN
= V
REF
V
REFIN
, Voltage Range VREF 1.3 V
V
DDQ/2
, Input Impedance 60 MΩ
V
TTREF
, Output Error -1.25 +1.25 %
• V
DDQ/2
= 0.75V, I
VTTR
=0mA
V
TTREF
Current Limit ±20 ±40 ±65 mA
• Sourcing: V
TTREF
=0, V
DDQ/2
=V
REF
Sinking: V
TTREF
=2V
I
Q
, Operating Quiescent Current 400 600 µA Not switching, V
FB
=V
REFIN
+0.1V
I
OFF
, Shutdown current 0.1 µA
EN=0V
T
ON
, Switch On-Time
0.4 0.5 0.6
µs
• XR6142EL0-5-F (T
ON
=500ns)
0.8 1.0 1.2 • XR6142EL1-0-F (T
ON
=1000ns)
1.6 2.0 2.4 • XR6142EL2-0-F (T
ON
=2000ns)
T
OFF_MIN
, Minimum Off-Time 300 400 ns
• All T
ON
options
T
D
, Gate Drive Dead-Time 50 ns
V
IH_EN
, EN Pin Rising Threshold 1.15 1.2 1.25 V •
V
EN_HYS
, EN Pin Hysteresis 50 200 mV
I
FB
, Feedback Pin Bias Current 50 nA
V
FB
=2.0V
V
CCUVLO
, Under-Voltage Lockout 2.8 3.0 V
• V
CC
rising edge
V
CCUVLO_HYS
, Under-Voltage Lock
out Hysteresis 500 mV
V
SC_TH
, Feedback Pin Short
Circuit Latch Threshold 55 65 75 %
• % of VREFIN
ILIM Pin Source Current 42.5 50 57.5 µA
ILIM Current Temperature
Coefficient 0.3 %/C
V
ILIM
Current Limit Trip Level -20 0 +20 mV
•
Current Limit Blanking 130 ns
GL Rising > 1.0V
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© 2010 Exar Corporation Page 3 of 17 Rev. 1.0.0
Parameter Min. Typ. Max. Units Conditions
Hiccup Timeout 110 ms
0.5μs, 1μs and 2μs option, V
OUT
=1V
Soft Start time 3 5 10 ms
R
DS(ON)1
, GH FET driver pull-up
On resistance 2.5 Ω I
GH
=20 mA
R
DS(ON)2
, GH FET driver pull-down
On resistance 2 Ω I
GH
=20 mA
R
DS(ON)3
, GL FET driver pull-up On
resistance 2.5 Ω I
GL
=20 mA
R
DS(ON)4
, GL FET driver pull-down
On resistance 2 Ω I
GL
=20 mA
BLOCK DIAGRAM
Figure. 2: XRP6142 Block Diagram
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© 2010 Exar Corporation Page 4 of 17 Rev. 1.0.0
PIN ASSIGNMENT
Figure. 3: XRP6142 Pin Assignment
PIN DESCRIPTION
Name Pin Number Description
AGND 1 Analog Ground
VTTREF 2 Buffered output of VDDQ/2
V
TT
reference voltage for DDR applications.
VDDQ/2 3 Buffer input voltage.
Voltage used for the input to the V
TTREF
buffer
V
REF
4 Precision reference output
REFIN 5 Reference input to the switching-regulator feedback comparator
FB 6 Feedback input to feedback comparator
CSGND 7 Current-sense ground
ILIM 8
Connect a resistor between this pin and the low-side current-sense element in order to
set the current-limit-trip threshold. See applications section for instructions on how to
set this resistor
PGND 9 Gate driver GND.
GL 10 Low-side N-channel MOSFET driver
SW 11 Switch node for floating-high-side gate drive
GH 12 High-side N-channel MOSFET driver
BST 13 Bootstrap capacitor to drive the high-side gate driver, GH
V
IN
14 Input voltage for the power train
Vcc 15 Input voltage for the XRP6142 internal circuitry and gate drives. V
IN
and V
CC
can be tied
together when V
IN
≥ 3.0V
EN 16 Precision enable pin. Pulling this pin above 1.2V will turn the part on
Thermal pad - Internally connected to AGND
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© 2010 Exar Corporation Page 5 of 17 Rev. 1.0.0
ORDERING INFORMATION
Part Number Temperature
Range Marking Package Packing
Quantity Note 1 Note 2
XRP6142EL0-5-F -40°C≤T
J
≤+125°C
6142E
YYWW05
X
16-pin QFN Bulk RoHS Compliant
Halogen Free 0.5µs on time
XRP6142ELTR0-5-F -40°C≤T
J
≤+125°C
6142E
YYWW05
X
16-pin QFN 3K/Tape & Reel RoHS Compliant
Halogen Free 0.5µs on time
XRP6142EL1-0-F -40°C≤T
J
≤+125°C
6142E
YYWW10
X
16-pin QFN Bulk RoHS Compliant
Halogen Free 1.0µs on time
XRP6142ELTR1-0-F -40°C≤T
J
≤+125°C
6142E
YYWW10
X
16-pin QFN 3K/Tape & Reel RoHS Compliant
Halogen Free 1.0µs on time
XRP6142EL2-0-F -40°C≤T
J
≤+125°C
6142E
YYWW20
X
16-pin QFN Bulk RoHS Compliant
Halogen Free 2.0µs on time
XRP6142ELTR2-0-F -40°C≤T
J
≤+125°C
6142E
YYWW20
X
16-pin QFN 3K/Tape & Reel RoHS Compliant
Halogen Free 2.0µs on time
XRP6142EVB XRP6142 Evaluation Board – XRP6142EL2-0-F based
“YY” = Year – “WW” = Work Week – “X” = Lot Number
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© 2010 Exar Corporation Page 6 of 17 Rev. 1.0.0
TYPICAL PERFORMANCE CHARACTERISTICS
All data taken at V
IN
= 3V to 5.5V, T
J
= T
A
= 25°C, unless otherwise specified - Schematic and BOM from Application
Information section of this datasheet.
Fig. 4: T
ON
versus V
IN
Fig. 5: T
ON
versus V
IN
Fig. 6: Efficiency versus I
OUT
Fig. 7: Load regulation
Fig. 8: Line regulation
Fig. 9: Frequency versus I
OUT
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
123456
VIN (V)
TON (μs)
V
CC
=5V
I
O
=0A
0.2
0.4
0.6
0.8
1.0
1.2
123456
VIN (V)
TON (μs)
V
CC
=5V
I
O
=0A
80
85
90
95
100
0 5 10 15 20
IOUT (A)
Efficiency (%)
V
IN
=V
CC
=5V
V
OUT
=2.5V
2.480
2.490
2.500
2.510
2.520
0 5 10 15 20
I
OUT
(A)
V
OUT
(V)
VIN=VCC=5V
2.450
2.475
2.500
2.525
2.550
3.5 4.0 4.5 5.0 5.5
V
IN
(V)
V
OUT
(V)
Io=0A
Io=10A
VCC=5V
300
350
400
450
500
0 5 10 15 20
I
OUT
(A)
f (kHz)
VIN=VCC=5V
XRP6142EL2.0-F
XRP6142EL2.0-F
XRP6142EL2.0-F
XRP6142EL2.0-F
XRP6142EL2.0-F
XRP6142EL1.0-F
XRP6142EL0.5-F
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© 2010 Exar Corporation Page 7 of 17 Rev. 1.0.0
Fig. 10: Frequency versus V
IN
Fig. 11: IOCP versus RLIM
Fig. 12: Power-up into a 15A load, V
IN
=5V, V
OUT
=2.5V
Fig. 13: Power-down from a 15A load, V
IN
=5V, V
OUT
=2.5V
Fig. 14: Steady state, output ripple is 30mV p-p, V
OUT
=2.5V
Fig. 15: Transient response, 250mV p-p, 15A load step
300
350
400
450
500
3.54.04.55.05.5
V
IN
(V)
f (kHz)
VCC=5V
IOUT=15A
0
5
10
15
20
25
0.8 1.2 1.6 2.0
RLIM (kΩ)
IOCP (A)
tested Iocp
calculated Iocp
XRP6142EL2.0-F
XRP6142EL2.0-F
XRP6142EL2.0-F
XRP6142EL2.0-F
XRP6142EL2.0-F
XRP6142EL2.0-F
VIN
5V/DIV
VOUT
2V/DIV
VSW
5V/DIV
IOUT
2V/DIV
VIN
5V/DIV
VOUT
2V/DIV
VSW
5V/DIV
IOUT
2V/DIV
2ms/DIV
2ms/DIV
2μs/DIV 100μs/DIV
VSW
5V/DIV
VOUT
20mV/DIV
AC coupled
IL
10A/DIV
IOUT
10A/DIV
VOUT
100mV/DIV
AC coupled
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© 2010 Exar Corporation Page 8 of 17 Rev. 1.0.0
THEORY OF OPERATION
The XRP6142 synchronous buck controller
utilizes the constant-on-time principle. The on-
time is internally set and is available in three
different set points to allow for different
frequency options. The XRP6142 automatically
adjusts the on-time during operation inversely
with the input voltage V
IN
, to maintain a
constant frequency. Therefore, the switching
frequency is independent of the inductor and
capacitor size, unlike hysteretic controllers.
At the beginning of the cycle, the XRP6142
turns on the high-side FET for a fixed duration.
The on time is internally set and adjusted by
V
IN
. At the end of the on time, the high-side
FET is turned off, for a predetermined
minimum off time (nominally 300ns). After
T
OFF-MIN
has expired, the high-side FET will stay
off until the feedback comparator trip point of
0.5V has been reached. Then the high-side
FET turns on again and the cycle repeats. The
operation of the low-side FET is
complementary to the high-side FET. A short
dead-time prevents shoot-through from
occurring.
TIMING OPTIONS
Three versions of XRP6142 (Timing Options)
are identified by their on times at V
IN
=3.3V.
For each version, T
ON
is inversely proportional
to V
IN
. The constant of proportionality K, is
shown in the table below. Variation of T
ON
versus V
IN
is shown graphically in figures 4
and 5.
Part Number T
ON
at V
IN
=3.3V K=T
ON
xV
IN
(μs.V)
XRP6142EL0.5-F 0.5μs 1.65
XRP6142EL1.0-F 1.0μs 3.3
XRP6142EL2.0-F 2.0μs 6.6
Note that for a Buck converter the switching
frequency is given by:
ONIN
OUT
TV
V
f×
=
Since for each XRP6142 Timing Option, the
product of V
IN
and T
ON
is a constant, then
frequency is determined by V
OUT
as shown in
the following table.
V
OUT
f(kHz) for each Timing Option
0.5μs 1.0μs 2.0μs
0.8 485 242 121
1.0 606 303 152
1.2 727 364 182
1.5 909 455 227
1.8 1091 545 273
2.5 --- 758
379
3.3 --- ---
500
I
NTERNAL SOFT-START
Soft-start time is internally set at 5ms
(nominal). This removes the need for external
components associated with soft-start
function, and helps save cost and reduce PCB
space.
ENABLE
A precision enable function is provided (1.20V
±0.05V). EN should be tied to V
CC
in
applications that do not require this function.
INTERNAL REFERENCE VOLTAGE
A high-precision 0.5V internal reference is
provided at the V
REF
pin. This is normally tied
to the REFIN pin, thus setting the threshold of
the voltage comparator.
INTERNAL BOOTSTRAP DIODE
XRP6142 includes an internal low-Vf bootstrap
diode. Place a 0.1uF capacitor between BST
and SW pins to provide drive voltage for the
high-side FET.
UNDER-VOLTAGE LOCKOUT
UVLO monitors V
CC
and ensures adequate
voltage exists before starting to switch the
FETs.
SHORT CIRCUIT PROTECTION
An internal short-circuit comparator monitors
the feedback voltage. If feedback voltage falls
below 65% of reference voltage (this is
equivalent to output voltage falling below 65%
of nominal value) the IC will latch off. V
CC
has
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© 2010 Exar Corporation Page 9 of 17 Rev. 1.0.0
to be recycled in order for IC to resume
operation.
OVERCURRENT PROTECTION (OCP)
OCP function is implemented by monitoring
the voltage across the low-side FET when it is
on. OCP is programmed via a resistor RLIM
connected between ILIM and SW pins. An
internal constant-current source ILIM (50uA
nominal) establishes a voltage across RLIM.
This voltage sets the trip point of the OCP
comparator. If the OCP comparator is
triggered for eight consecutive switching
cycles, then a hiccup timeout, as described in
the next section, is initiated. Calculate RLIM
from:
A
mVR
IL
IOCP
RLIM
ONDS
μ
5.42
20
2
)(
+
⎥
⎦
⎤
⎢
⎣
⎡×
⎟
⎠
⎞
⎜
⎝
⎛Δ
+
=
Where:
IOCP is the output current at which
overcurrent protection is activated (usually set
20% above maximum I
OUT
)
∆IL is inductor current ripple nominally set at
30% of I
OUT
R
DS(ON)
is the maximum rated on resistance of
the FET
20mV is the OCP comparator offset spec
42.5μA is the minimum spec of the ILIM
source
The actual IOCP is 50% to 100% higher than
expected IOCP as seen in figure 11. This is
because RLIM in the above equation is
calculated based on worst case parameters.
A temperature coefficient of 0.3%/°C has been
designed into ILIM. This useful feature nulls
out the positive temperature coefficient of the
FET R
DS(ON)
to a first order. Thus IOCP should
be largely independent of operating
temperature.
HICCUP TIMEOUT
When an over current condition is detected,
the internal FET drivers are turned off for
110ms, following which, a soft-start is
attempted. If the OCP condition is still present,
then the timeout and soft-start cycle repeat.
This is referred to as hiccup timeout.
PROGRAMMING VOUT
A pair of output resistors is used to set the
output voltage V
OUT
. Calculate R1 from:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−= 121
REF
OUT
V
V
RR
Where:
R2 is nominally set at 10k (bottom resistor)
V
REF
is reference voltage (0.5V)
Note that V
OUT
must contain some voltage
ripple in order for XRP6142 to regulate the
output. Since XRP6142 regulates the bottom
of the output ripple the average value will be
higher (see figure 16).
Fig. 16: V
OUT
Voltage Ripple
V
OUT
can be programmed more precisely from:
()
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−
×−
=1
,5.0
21
REF
OUTOUT
V
rippleVV
RR
Where:
ESRILrippleVOUT ×Δ=,
ESR is the output capacitor’s Equivalent Series
Resistance.
OUTPUT CAPACITOR
C
OUT
is the most critical component for proper
operation, since the XRP6142 relies on V
OUT
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© 2010 Exar Corporation Page 10 of 17 Rev. 1.0.0
voltage ripple for regulating the output. To
ensure stable operation two constraints must
be met:
First the C
OUT
must have sufficient ESR in
order to get enough voltage ripple at feedback
pin. It is recommended that XRP6142 be
operated with at least 25mV ripple at feedback
pin. Assuming majority of output voltage
ripple is from ESR, we get:
IL
mV
ESR Δ
≥25
…………. (1)
Where ∆IL is inductor current ripple nominally
set at 30% of I
OUT
.
Note that V
OUT
ripple, is attenuated by the
resistor divider R1/R2, and a smaller ripple is
seen at FB pin. For example if V
OUT
ripple is
25mV and R1=R2=10k, then the voltage
ripple at FB is only 12.5mV. One solution to
this problem is to increase the output ripple
accordingly, such that ripple at FB is 25mV. A
more desirable solution is to provide a high-
frequency/low-impedance path for the output
ripple to be transmitted to FB without
attenuation. This can be done by placing a
small feed-forward capacitor CFF in parallel
with R1. As a starting point calculate CFF
from:
fsR
CFF ×××
=12
10
π
Where fs is the switching frequency
In general, a CFF of 1nF should provide
satisfactory feed-forward for most applications
based on the XRP6142.
The second constraint for stability establishes
a relation between ESR and C
OUT
.
OUT
C
Ton
ESR ≥
…………. (2)
Once ESR is calculated from equation (1),
equation (2) can be used to calculate C
OUT
.
The aforementioned are in addition to the
usual requirements for C
OUT
for a buck
converter. The usual constraint in order to
meet load step transient requirement is given
by:
2
2
2
1
2
2
OUT
OUT
VVos
II
C−
−
≥
Where:
I
2
is load step high-level current
I
1
is load step low-level current
V
OUT
is output voltage including transient
(nominally this is set 3% higher than V
OUT
)
In general, the best capacitors are the ones
with known and consistent ESR across
operating temperature range. Examples
include POSCAPs, Tantalums and certain
Aluminum Electrolytics.
OUTPUT INDUCTOR
Select the output inductor for inductance and
current rating. As a rule of thumb the DC
current rating and saturation current should
be at least 50% higher than maximum output
current. Calculate the inductance from:
()
fsIL
DVV
L
OUTIN
×Δ
×−
=
Where:
D is duty cycle
fs is switching frequency
∆IL is inductor current ripple nominally set at
30% of I
OUT
.
INPUT CAPACITOR
Select the input capacitor for capacitance,
voltage rating and RMS current rating. As a
rule of thumb, the voltage rating should be
twice the maximum input voltage of the
converter. RMS current rating can be
approximated from:
()
DDII OUTRMS −×= 1
Calculate C
IN
such that input voltage ripple
does not exceed 2% of V
IN
. Ceramic input
capacitors are recommended. This choice
minimizes input voltage ripple due to ESL and
ESR. Thus a simplified expression for C
IN
can
be written:
X
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© 2010 Exar Corporation Page 11 of 17 Rev. 1.0.0
()
2
,
02.0
ININ
OUTINOUTMAXOUT
IN
VVfs
VVVI
C××
−××
=
SYNCHRONOUS FET (LOW-SIDE FET)
Select the synchronous FET for voltage rating
BV
DSS
, on resistance rating R
DS(ON)
and gate
drive rating V
GS
. As a rule of thumb, voltage
rating should be at least twice the converter
input voltage. FETs with voltage rating of up to
30V should provide satisfactory performance.
Drive voltage of 4.5V is sufficient for
applications with minimum input voltage of
4.5V. For applications with a lower input
voltage a FET with 2.5V gate drive should be
selected. Switching losses of the Synchronous
FET are negligible in comparison to its
conduction losses. R
DS(ON)
is calculated based
on conduction losses from:
()
2
)(
1
OUT
Conduction
ONDS
ID
P
R×−
≤
It is common practice to allocate 50% of the
total FET losses to the synchronous FET. As an
example, consider a 10W buck converter with
a target efficiency of 90%. Therefore, the
target total power loss is 1.1W. Assume that
the only significant non-FET loss is the
inductor loss estimated at 0.1W. Thus the
maximum conduction loss of the synchronous
FET should not exceed 0.5W. By using this
value in the above equation R
DS(ON)
can be
calculated and a suitable FET selected.
SWITCHING FET (HIGH-SIDE FET)
Select the switching FET for voltage rating
BV
DSS
, on-resistance rating R
DS(ON)
, gate drive
rating V
GS
, rise time t
r
and fall time t
f
. BV
DSS
and V
GS
selection guidelines are the same as
Synchronous FET. The switching FET incurs
switching (i.e., transitional) as well as
conduction losses. R
DS(ON)
is calculated based
on conduction losses from:
2
)(
OUT
Conduction
ONDS
ID
P
R×
≤
It is common practice to allocate 50% of the
total high-side FET losses to conduction.
Proceeding with the example from previous
section the total target loss is 0.5W, and thus
target conduction loss equals 0.25W. By using
this value in the above equation R
DS(ON)
can be
calculated. Rise and fall time can be
approximated from:
soutIN
Switching
fr fIV
P
tt ××
=+
Since the allotted switching loss budget is
0.25W, t
r
and t
f
can be calculated from the
above equation.
For a detailed explanation of FET losses and
FET selection procedure refer to EXAR
application note ANP-20.
R-C SNUBBER (OPTIONAL)
An R-C snubber placed across the synchronous
FET eliminates the ringing and reduces the
amplitude of overshoot at SW node. Use
surface-mount components and place them
close to the FET drain-source. Calculate the
value of snubber capacitor Csnb from:
CossCsnb ×= 3
Coss is the output capacitance of the
synchronous FET corresponding to V
IN
.
Calculate the value of the snubber resistor
Rsnb from:
OUT
OUT
I
V
Rsnb ×
=
2
DDR MEMORY POWER APPLICATIONS
XRP6142 can be used to generate the required
V
DDQ
(V
DD
) or V
TT
Reference voltages for DDR I,
II and III memories and provides a 40mA
buffered V
TT
Reference voltage. When used in
conjunction with Exar’s SP2996 DDR Memory
Termination, the XRP6142 provides a complete
DDR power management solution. A cost-
effective DDR2 solution is shown on page 15.
XRP6142 provides the VDDQ and VTTREF
voltages. SP2996 provides the VTT voltage.
Please note that the current output of VDDQ
can be increased up to 10A by using a larger
QT/QB MOSFET and scaling the L1 and C3
accordingly.
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© 2010 Exar Corporation Page 12 of 17 Rev. 1.0.0
PCB LAYOUT GUIDELINES
The following guidelines will help attain stable
operation and reduce jitter:
1- Place all the power components; C
IN
,
QT, QB, L1 and C
OUT
on the same side
of the board if possible.
2- Make the loop between C
IN
, QT and QB
as small as possible and use low-
impedance traces.
3- Make the loop between QB, L1 and
C
OUT
as small as possible and use low-
impedance traces.
4- Place the source of QT, drain of QB and
input connection of L1 as close as
possible and use low-impedance
traces.
5- Use a short trace and connect AGND to
the thermal pad. This forms the signal
ground.
6- Use a short trace and connect PGND to
AGND.
7- Use a low-impedance trace and
connect the PGND pin to the C
OUT
.
8- Place CFF, R1 and R2 close to the IC,
and connect R2 to signal ground. Use a
short trace and connect R1 to C
OUT
.
9- Bypass the V
CC
pin to signal ground
with a ceramic capacitor(s) as close to
the IC as possible. Connect the V
CC
pin
to V
IN
or an independent V
CC
source
through a 10Ω resistor. This will help
filter out noise from V
CC
.
X
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© 2010 Exar Corporation Page 13 of 17 Rev. 1.0.0
DESIGN EXAMPLES
5V STEP-DOWN CONVERTER
Note: The data shown in figures 6 trough 15 was collected using this circuit.
C5
220uF
GND
VIN=4.5V-5.5V
GND
VOUT=2.5V, 0-15A
U1
XRP6142EL2.0-F
AGND
1
VTTREF
2
VDDQ/2
3
VREF
4
REFIN
5
FB
6
CSGND
7
ILIM
8
PGND 9
GL 10
SW 11
GH 12
BST 13
VIN 14
VCC 15
EN 16
T. PAD
QB
Vishay Si4164DY
8
7
6
5
4
1
2
3
L1, Wurth Elektronik
0.82uH, 27A, 0.9 mOhm
1 2
RLIM 2.2k
CVCC1
0.1uF
C1-C3 ceramic, 10V
C5-C6 SANY O
POSCAP
6TPE220MI, 6.3V,
18mOhm
Snubber components
are optional
CFF
1nF
Csnb
3.9nF
Rsnb
0.2 Ohm
RVCC
10 Ohm
QT
Vishay Si4164DY
8
7
6
5
4
1
2
3
C6
220uF
C1
47uF
C2
47uF
C3
47uF
CBST
0.1uF
C4
0.1uF
CVCC
4.7uF
R1
39.2k (1%)
R2
10k (1%)
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© 2010 Exar Corporation Page 14 of 17 Rev. 1.0.0
3.3V STEP-DOWN CONVERTER
Snubber components
are optional
C5
220uF
GND
T POI N T S
GND
T POI N T S
VIN=3V-3.6V
T POI N T S
VOUT=1.2V, 0-10A
T POI N T S
U1
XRP6142EL1.0-F
AGND
1
VTTREF
2
VDDQ/2
3
VREF
4
REFIN
5
FB
6
CSGND
7
ILIM
8
PGND 9
GL 10
SW 11
GH 12
BST 13
VIN 14
VCC 15
EN 16
T. PAD
QB
Fairchild FDS6570
8
7
6
5
4
1
2
3
L1, Wurth Elektronik1
0.72uH, 22A, 1.65 mOhm
1 2
RLIM 3.65k
CVCC1
0.1uF
C5-C6 SANYO
POSCAP
6TPE220MI, 6.3V,
18mOhm
C1-C3 ceramic, 10V
CFF
1nF
Csnb
3.9nF
Rsnb
0.2 Ohm
RVCC
10 Ohm
QT
Fairchild FDS6570
8
7
6
5
4
1
2
3
C6
220uF
C1
47uF
C2
47uF
C3
47uF
CBST
0.1uF
C4
0.1uF
CVCC
4.7uF
R1
14k (1%)
R2
10k (1%)
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© 2010 Exar Corporation Page 15 of 17 Rev. 1.0.0
DDR2 MEMORY SOLUTION
QB
Vishay , Si2312BDS
1
2 3
VREF
C4
47uF, ceramic, 6.3V
R3
10k (1%)
R4
10k (1%)
C5
1uF
C3
150uF
GND
GND
VIN=3.3V or 5V
VDDQ=1.8V, 0-3A
U1
XRP6142EL1.0-F
AGND
1
VTTREF
2
VDDQ/2
3
VREF
4
REFIN
5
FB
6
CSGND
7
ILIM
8
PGND 9
GL 10
SW 11
GH 12
BST 13
VIN 14
VCC 15
EN 16
T. PAD
L1, Vishay IHLP-2525CZ
1.5uH, 9A, 15 mOhm
1 2
RLIM 3.65k
CVCC
1uF
C3 SANY O
POSCAP
4TPE150MAZB,
4V, 35mOhm
CFF
1nF
RVCC
10 Ohm
QT
Vishay , Si2312BDS
1
2 3
C1
47uF, ceramic, 10V
CBST
0.1uF
C2
0.1uF
R1
25.5k (1%)
R2
10k (1%)
Q1
CES7002A
VREF/VTT ENABLE
VTT=0.9V, 1A peak, 0.5ADC
U2 SP2996B
VCNTL 8
VCNTL 7
VOUT
4VCNTL 5
GND
2
REFEN
3
VIN
1
VCNTL 6
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© 2010 Exar Corporation Page 16 of 17 Rev. 1.0.0
PACKAGE SPECIFICATION
16-PIN QFN
X
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P6
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© 2010 Exar Corporation Page 17 of 17 Rev. 1.0.0
REVISION HISTORY
Revision Date Description
1.0.0 03/24/2010 Initial release of datasheet
FOR FURTHER ASSISTANCE
Email: customersupport@exar.com
Exar Technical Documentation: http://www.exar.com/TechDoc/default.aspx?
E
XAR CORPORATION
HEADQUARTERS AND SALES OFFICES
48720 Kato Road
Fremont, CA 94538 – USA
Tel.: +1 (510) 668-7000
Fax: +1 (510) 668-7030
www.exar.com
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein,
conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a
user’s specific application. While the information in this publication has been carefully checked; no responsibility, however,
is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its
safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in
writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all
such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
