Rev. I–23-Aug-01
1
Features
•Full Range of Matrices up to 700k Cells
•0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates
•RAM and DPRAM Compilers
•Library Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATG)
•High Speed Performances:
– 200 ps Typical Gate Delay @5V
– typical 625 MHz Toggle Frequency @5V and 360 MHz @3.3V
•High System Frequency Skew Control:
–250 MHz PLL for Clock Generation
–Clock Tree Synthesis Software
•3 & 5 Volts Operation; Single or Dual Supply Modes
•Low Power Consumption:
–0.6 µW/Gate/MHz @3V
–2.2 µW/Gate/MHz @5V
•Integrated Power on Reset
•Matrices With a max of 582 full programmable Pads
•Standard 3, 6, 12 and 24mA I/Os
•Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator
•CMOS/TTL/PCI Interface
•ESD (2 kV) and Latch-up Protected I/O
•High Noise & EMC Immunity:
–I/O with Slew Rate Control
–Internal Decoupling
–Signal Filtering between Periphery & Core
–Application Dependent Supply Routing & Several independant supply sources
•Wide Range of Packages Including PGA, CQFP, PLCC PQFP, BGA, SSOP ...
•Delivery in Die Form
•Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout,
Power Management
•Cadence, Mentor, Vital & Synopsys Reference Platforms
•EDIF & VHDL Reference Formats
•A va ilable In Commercia l, Industria l and Mi litary Quality Grades: for space a ppplicati on
see MG2RT and MG 2R T P specific atio ns.
•QML Q with SMD 5962-00B02.
Description
The MG2 series is a 0.5 micron, array based, CMOS product family. Several arrays up
to 700k c ells co ver all system inte gration ne eds. The MG2 is man ufactured usi ng a
0.5 micron drawn, 3 metal layers CMOS process.
The MG2 serie s base cell arc hitec tur e prov i des hig h ro uta bility of l ogi c wi th extr eme ly
dense compi led memori es: RAM a nd DPRA M. RO M c an be gene rated usin g synth e-
sis tools . Fo r ins tan ce , the larges t arra y is ca pab le of i nteg ra tin g 128 K bi ts of DP RA M
with 128K bits of ROM and over 300,000 random gates.
Accurate control of clock distribution can be achieved by PLL hardware and CTS
(Cloc k Tre e Synthe sis) so ftware . New noise pr evention techni ques are ap plied in th e
array and in the periphery: Three or more independent supplies, internal decoupling,
custo misation dependen t supply routi ng, noise fil tering, skew c ontrolled I/Os, low
swing differential I/Os, all contribute to improve the noise immunity and reduce the
emission level.
500K used gates
0.5 Micron CMOS
Sea of Gate s
MG2
2
MG2
Rev. I–23-Aug-01
The MG2 is supported by an advanced s oftware environment based on industry stan-
dards li nking prop rietary and commerci al tools. Cad ence, Mento r, Synopsy s and VHDL
are the reference front end tools. Floor planning associated with timing driven layout
provides a short back end cycle. The MG2 family continues the Atmel offering in array
based commercial, industrial and military circuits.
A netlist based on this library can be simulated as either MG2, or MG2RT or MG2RTP.
Table 1. Description of Matrices
Note: * The max. number of usable gates is application dependent
**call factory
Type Total cells Max. usable
cells* Total pads Maximum programmable I/Os
MG2044 44616 35693 171 148
MG2091 91464 73171 235 212
MG2140 140322 112258 285 262
MG2194 193800 155040 331 308
MG2265 264375 211500 384 362
MG2360 361680 289344 435 412
MG2480 481143 384914 507 484
MG2700** 698523 558818 605 582
3MG2 Rev. I–23-Aug-01
Libraries
The MG2 cell library has been designed to take full advantage of the features offered by
both logic and test synthesis tools.
Design testability is assured by the full support of SCAN, JTAG (IEEE 1149) and BIST
methodologies.
More complex macro functions are available in VHDL, as example: I2C, UART,
Timer, ...
Block Generators Block generators are used to create a customer specific simulation model and metallisa-
tion patt ern for reg ular func tions like RA M, DPRAM & FI FO. The bas ic cell ar chitectu re
allows one bit per cell for RAM and DPRAM. T he main charac teristics of these genera-
tors are summarised below.
Table 2. Block Generators Capability
Function Maximum
Size (bits) bits/word Typical characteristics (16k bits) @5V
access time (ns) Used cells
RAM 36 k 1-36 820 k
DPRAM 36 k 1-36 8.6 23 k
4
MG2
Rev. I–23-Aug-01
I/O Buffe r Inte rf ac ing
I/O Fexibility All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A
level translator is located close to each buffer.
Inputs Input buff ers with CMOS o r TTL thr esholds are non i nverti ng and fe ature ve rsion s with
and without hysteresis. The CMOS and TTL input buffers may incorporate pull-up or pull
down term inato rs. For spec ial purpo se s, a buffer allo wing direct inp ut to the matri x core
is available.
Outputs Several kinds of CMOS and TTL output drivers are offered: fast buffers with 3, 6, 12 and
24 mA drive at 5V, low noise buffers with 12 mA drive at 5V.
Clock generation &
PLL
Clock generation Atmel Wireless & Microcontrollers offers 7 different types of oscillators: 5 high frequency
crystal oscillator and 2 RC oscillators. For all devices, the mark-space ratio is better than
40/60 and the start-up time less than 10 ms.
PLL (on request) Contact factory.
Frequency (MHz) Typical consumption (mA)
Max 5V Max 3V 5V 3V
Xtal 7M 12 71.2 0.4
Xtal 20M 28 17 2.5 0.8
Xtal 50M 70 40 7 2
Xtal 100M 130 75 16 5
Xtal 32K 32 3 4
RC 10M 10 2 1
RC 32M 32 31.5
5MG2 Rev. I–23-Aug-01
Power supply & noise protection
The s peed a nd den sity of th e SCM OS3/2RT tech nology ca uses la rge switc hing cu rre nt
spikes for example when:
•16 high cur rent output buffers switch simultaneou sly,
•or 10% of the 700 000 gates are switching within a window of 1ns.
Sharp edges and high currents cause some FG_Leftsitic elements in the packaging to
become significant. In this frequency range, the package inductance and series resis-
tance should be taken into account. It is known that an inductor slows down the settling
time of the current a nd causes v oltage drops on the po wer supply lines. These drops
can affect the behaviou r of the c ircuit itself or di sturb the external appli cation (groun d
bounce).
In ord er to impr ov e the no is e immu nit y of t he MG co re ma tri x, sever al me chan ism s have
been implemented inside the MG arrays. Two kinds of protection have been added: one
to limi t th e I/O b uffer swi tc hi ng noise and the oth er to prot ec t th e I/O bu ffer s a gai ns t th e
switching noise coming from the matrix.
I/O Buffers switching
protection Three features are implemented to limit the noise generated by the switching current:
•The power supplies of the input and output buffers are seFG_Leftted.
•The rise and fall times of the output buffers can be controlled by an internal
regulator.
•A design rule concerning the number of buffers connected on the same power
supply line has been imposed.
Matrix switching current
protection This noise disturbance is caused by a large number of gates switching simultaneously.
To allow this without impacting the functionality of the circuit, three new features have
been added:
•Decoupling capacitors are integrated directly on the silicon to reduce the power
supply dr op.
•A power supply network has been implemented in the matrix. This solution reduces
the number of FG_Leftsitic elements such as inductance and resistance and
constitutes an artificial VDD and Ground plane. One mesh of the network supplies
approximately 150 cells.
•A low pass filter has been added between the matrix and the input to the output
buffer. This limits the transmission of the noise coming from the ground or the VDD
supply of the matrix to the external world via the output buffers.
Note: For addit ion al inf orm atio n, see ’MG2 / Phase Locked Loop” Rev 1.0, 15 Oct. 96.
6
MG2
Rev. I–23-Aug-01
Powe r cons umption
The power consumption of an MG2 array is due to three factors: leakage (P1), core (P2)
and I/O (P3) consumption.
P = P1 + P2 + P3
Leakage (Standby)
Power Consumption The consumption due to leakage currents is defind as:
P1 = (VDD - VSS) * ICCSB * NCELL
Where ICCSB is the leakage current through a polarised basic gate and NCELL is the num-
ber of used cells.
Core Power
Consumption The power cons umpti on due to the swit ching of cel ls in the core of the matrix is define d
as:
P2 = NCELL * PGATE * CACTIVITY * F
Where NCELL is the number of used cells , F the data togg ling freq uency, whic h is equal
to hal f the clock frequenc y for rand om data an d PGATE is the power consumption per
cell.
PGATE = PCA + PCO
ACTIVITY is the fraction of the total number of cells toggling per cycle.
Capacitance Power PCA = C * (VDD - VSS)2/2
C is the tota l ou tput cap ac ita nc e and may be express ed as the sum of the dr ain ca pac i-
tance of the driver, the wiring capacitance and the gate capacitance of the inputs.
Worst case value: PCA # 1.8 µW/gate/MHz @ 5 V
Commutation Power PCO = (VD D - VSS) * Idsohm
Where Idsohm is the current flowing into the driver between supply and ground during the
commutation. Idsohm is about 15 % of the Pmos saturation currrent.
Worst case value: Pco # 0.7 µW/gate/MHz @ 5 V
I/O Power Consumption The power consumption due to the I/Os is:
P3 = Ni * CO * (VDD - VSS)2 * Fi/2
With Ni equals to the number of buffers running at Fi and CO is the output capacitance.
Note: If a signal is a clock, Fi = F, if it is a data with random values, Fi = F/4.
7MG2 Rev. I–23-Aug-01
Table 3. Power Consumption Example @ 5V
Matrix MG2265
Used gates (70 %) 185 k
Frequency 40 MHz
Standby Power
Iccsb (125°C) 1 nA
P1 = (VDD - VSS) * ICCSB * NCELL 1 mW
Core Power
Power Consumption per Cell 1.96 µW/Gate/MHz
Cactivity 20 %
P2 = NCELL * PGATE * Cactivity * F 1449 mW
I/O Pow er
Total Number of Buffers 364
Number of Outputs and I/O Buffers 100
Output Capacitance 50 pF
P3 = Ni * CO * (VDD - VSS)2 * Fi/2 625 mW
Total Power
P = P1 + P2 + P3 2.07 W
8
MG2
Rev. I–23-Aug-01
Packaging Atmel offers a wide range of packaging options which are listed below:
Table 4. Packaging Options
Note: * Contac t Atmel Loca l D es ign Cente r s to che ck the ava ila bil ity of th e us ed m atri x a nd th e
plan package.
** To get the linear values in milimeters, multiply by 25.4
***Ceramic Land Grid Array: contact factory.
Package Type Pins
min/max* Lead spacing
(inch**)
MQFP 100
352 0.0256
0.020
CQPF 44
196 0.050
MPGA 176
391 0.10
100
PBGA 121
676 100
0.10
CLGA 349
564 0.05
9MG2 Rev. I–23-Aug-01
Design flows & tools
Design Flows and modes A generic design flow for an MG2 array is illustrated below.
A top down design methodology is proposed which starts with high level system
description and is refined in successive design steps. At each step, structural verifica-
tion is performed which includes the following tasks:
•Gate level logic simulation and comparison with high level simulation results.
•Design and test rule check.
•Power consumption analysis.
•Timing analysis (only after floor plan).
The main design stages are:
•System specification, p referably in VHD L form.
•Functional description at RTL level.
•Logic synthesis.
•Floor planning and bonding diagram generation.
•Test/Scan insertion, ATG and/or fault simulation.
•Physical cell placement, JTAG insertion and clock tree synthesis.
•Routing
To meet the various requirements of designers, several interface levels between the
customer and Atmel are possible.
For each of the possible desig n modes a review mee ting is requir ed for data transfer
from the user to Atmel. In all cases the final routing and verifications are performed by
Atmel.
The design ac ceptan ce is forma lise d by a design rev iew which au thori ses Atmel to pr o-
ceed with sample manufacturing.
10
MG2
Rev. I–23-Aug-01
Figure 1. MG2 Design Flow
Design tool and design
kits (DK) The basic content of a design kit is described in the table below.
The interface formats to and from Atmel rely on IEEE or industry standard:
•VHDL for functional descriptions
•VHDL or EDIF for netlists
•Tabular, log or .CAP for simulation results
•SDF (VITAL format) and SPF for backannotation
•LEF and DEF for physical floor plan information
The design kit supported for several commercial tools is outlined in the table below.
Table 5. De si gn Ki t Suppo rt
System
Specifications
RTL
Simulation
Logic
synthesis
Floor Plan
Bonding diagram
Scan insertion
ATG & Fault Simulation
Placement
JTAG insertion
Clock Tree Synthesis
Routing
Samples
Manufacturing
and Test
Design Kit Support VHDL Gate
Cadence * *
Mentor * *
Synopsys * *
Vital * *
11 MG2 Rev. I–23-Aug-01
Table 6. De si gn ki t Descripti on
Design Tool or library
Atmel
Software
Name
Third
Party
Tools
Design manual & libraries *
VHDL library for blocks *
Synthesis library *
Gate level simulation library *
Design rules analyser STAR
Power consumption analyser COMET
Floor plan library *
Timing analyser library *
Package & bonding software PIM
Scan path & JTAG insertion MISS
ATG & fault simulation library *
* refer to “Des ign kits cross reference tables” AT D-TS- W F-R0181
12
MG2
Rev. I–23-Aug-01
Operating character istics
Absolute Maximum Ratings
DC Characteristic s Table 7. DC Char acte rsti cs
Specified at VDD = +5 V +/- 10%
Ambient temperature under bias (TA)
Military -55°C to +125°C
Junction temperature TJ < TA + 20°C
Storage temperature -65°C to +150°C
TLL/CMOS:
Supply voltage VDD -0.5 V to +6
I/O v o lt a g e -0.5 V to VD D + 0.5 V
Stresses above those listed may cause permanent damage to the device. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Symbol Definition Parameter Min Typ Max Unit Conditions
VIL Input LOW voltage CMOS input
TTL input 0
01.5
0.8 V
VIH Input HIGH voltage CMOS input
TTL input 3.5
2.2 VDD
VDD V
VOL Output low voltage TTL 0.4 V IOL = -12, 6, 3 mA*
VOH Output high voltage CMOS
TTL 3.9
2.4 VIOH = -12, 6, 3 mA*
VT+ Schmitt trigger positive threshold CMOS input
TTL input 3.6
1.6 V
VT- Schmitt trigger negative
threshold CMOS input
TTL input 1.2
1.0 V
Delta V CMOS hysteresis 25oC/5V
TTL hysteresis 25oC/5V 1.9
0.6 V
IL Input leakage No pull up/down
Pull up
Pull down -55
79
+/-1
-69
125
+/-5
-120
330
µA
µA
µA
IOZ 3-State Output Leakage current +/-1 +/-5 µA
IOS Output Short circuit current IOSN
IOSP 48
36 mA
mA
BOUT12
VOUT = 4.5V
VOUT = VSS
ICCSB Leakage current per cell 1.0 10.0 nA
ICCOP Operating current per cell 0.39 0.53 µA/MHz
Note: * According buffer: Bout12, Bout6, Bout3.
13 MG2 Rev. I–23-Aug-01
Table 8. DC Char acte ri st ic s
Specified at VDD = +3V - 10%
Note: *According buffer: Bout12, Bout6, Bout3
Symbol Parameter Min Typ Max Unit Conditions
VIL Input LOW voltage
LVCMOS input
LVTTL input 0
00.3VDD
0.8 V
VIH Input HIGH voltage
LVCMOS input
LVTTL input 0.7VDD
2.0 VDD
VDD V
VOL Output LOW voltage
TTL 0.4 VIOL = -6, 3, 1.5 mA*
VOH Output HIGH voltage
TTL 2.4 VIOH = -4, 2, 1 mA*
VT+ Schmitt trigger positive threshold
LVCMOS input
LVTTL input 2.2
1.2 V
VT- Schmitt trigger negative threshold
LVCMOS input
LVTTL input 0.9
0.8 V
Delta V CMOS hysteresis 25oC/5V
TTL hysteresis 25oC/5V 0.8
0.2 V
IL
Input leakage
No pull up/down
Pull up
Pull down
-20
32 24
42
+/-1
-60
150
µA
µA
µA
IOZ 3-State Outp ut Leakage current +/-1 µA
IOS Output Shor t circuit current
IOSN
IOSP 24
12 mΑ
mA
BOUT12
VOUT = V DD
VOUT = VSS
ICCSB Leakage current per cell 0.6 5nA
ICCOP Operating current per cell 0.2 0.3 µA/MHz
14
MG2
Rev. I–23-Aug-01
Table 9. AC Charac teristics
TJ = 25°C, Process typical (all values in ns)
Buffer Description Load Transition VDD
5V 3V
BOUT12 Output buffer with 12 mA drive 60pf T plh 3.18 4.67
Tphl 2.35 3.33
Cell Description Load Transition VDD
5V 3V
BINCMOS CMOS input buffer 15 fan Tplh 0.75 1.12
Tphl 0.7 0.98
BINTTL TTL input buffer 16 fan Tplh 0.88 1.29
Tphl 0.65 1.03
INV Inverter 12 fan Tplh 0.54 0.85
Tphl 0.39 0.49
NAND2 2 - input NAND 12 fan Tplh 0.57 0.89
Tphl 0.49 0.67
FDFF D flip-flop, Clk to Q 8 fan Tplh 0.86 1.30
Tphl 0.73 1.08
Ts 0.44 1.06
Th 0.00 0.00
© Atmel Nantes SA, 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Co nditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document , reserves the right to change devices or specifications detailed herein at any time w ithout notice, and does
not make any commitment to update t he information contained herein. No licenses to patents or other intellectual property of At mel are granted
by the Company in conn ection with the sale of At mel produc ts, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
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