Features * * * * * * * * * * * * * * * * * * * * * * Full Range of Matrices up to 700k Cells 0.5 m Drawn CMOS, 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATG) High Speed Performances: - 200 ps Typical Gate Delay @5V - typical 625 MHz Toggle Frequency @5V and 360 MHz @3.3V High System Frequency Skew Control: - 250 MHz PLL for Clock Generation - Clock Tree Synthesis Software 3 & 5 Volts Operation; Single or Dual Supply Modes Low Power Consumption: - 0.6 W/Gate/MHz @3V - 2.2 W/Gate/MHz @5V Integrated Power on Reset Matrices With a max of 582 full programmable Pads Standard 3, 6, 12 and 24mA I/Os Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator CMOS/TTL/PCI Interface ESD (2 kV) and Latch-up Protected I/O High Noise & EMC Immunity: - I/O with Slew Rate Control - Internal Decoupling - Signal Filtering between Periphery & Core - Application Dependent Supply Routing & Several independant supply sources Wide Range of Packages Including PGA, CQFP, PLCC PQFP, BGA, SSOP ... Delivery in Die Form Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management Cadence, Mentor, Vital & Synopsys Reference Platforms EDIF & VHDL Reference Formats Available In Commercial, Industrial and Military Quality Grades: for space appplication see MG2RT and MG2RTP specifications. QML Q with SMD 5962-00B02. 500K used gates 0.5 Micron CMOS Sea of Gates MG2 Description The MG2 series is a 0.5 micron, array based, CMOS product family. Several arrays up to 700k cells cover all system integration needs. The MG2 is manufactured using a 0.5 micron drawn, 3 metal layers CMOS process. The MG2 series base cell architecture provides high routability of logic with extremely dense compiled memories: RAM and DPRAM. ROM can be generated using synthesis tools. For instance, the largest array is capable of integrating 128K bits of DPRAM with 128K bits of ROM and over 300,000 random gates. Accurate control of clock distribution can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques are applied in the array and in the periphery: Three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level. Rev. I-23-Aug-01 1 MG2 The MG2 is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Cadence, Mentor, Synopsys and VHDL are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle. The MG2 family continues the Atmel offering in array based commercial, industrial and military circuits. A netlist based on this library can be simulated as either MG2, or MG2RT or MG2RTP. Table 1. Description of Matrices Type Total cells Max. usable cells* Total pads Maximum programmable I/Os MG2044 44616 35693 171 148 MG2091 91464 73171 235 212 MG2140 140322 112258 285 262 MG2194 193800 155040 331 308 MG2265 264375 211500 384 362 MG2360 361680 289344 435 412 MG2480 481143 384914 507 484 MG2700** 698523 558818 605 582 Note: * The max. number of usable gates is application dependent **call factory 2 Rev. I-23-Aug-01 Libraries The MG2 cell library has been designed to take full advantage of the features offered by both logic and test synthesis tools. Design testability is assured by the full support of SCAN, JTAG (IEEE 1149) and BIST methodologies. More complex macro functions are available in VHDL, as example: I2C, UART, Timer, ... Block Generators Block generators are used to create a customer specific simulation model and metallisation pattern for regular functions like RAM, DPRAM & FIFO. The basic cell architecture allows one bit per cell for RAM and DPRAM. The main characteristics of these generators are summarised below. Table 2. Block Generators Capability Function 3 Maximum Size (bits) bits/word Typical characteristics (16k bits) @5V access time (ns) Used cells RAM 36 k 1-36 8 20 k DPRAM 36 k 1-36 8.6 23 k MG2 Rev. I-23-Aug-01 MG2 I/O Buffer Interfacing I/O Fexibility All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level translator is located close to each buffer. Inputs Input buffers with CMOS or TTL thresholds are non inverting and feature versions with and without hysteresis. The CMOS and TTL input buffers may incorporate pull-up or pull down terminators. For special purposes, a buffer allowing direct input to the matrix core is available. Outputs Several kinds of CMOS and TTL output drivers are offered: fast buffers with 3, 6, 12 and 24 mA drive at 5V, low noise buffers with 12 mA drive at 5V. Clock generation & PLL Clock generation Atmel Wireless & Microcontrollers offers 7 different types of oscillators: 5 high frequency crystal oscillator and 2 RC oscillators. For all devices, the mark-space ratio is better than 40/60 and the start-up time less than 10 ms. Frequency (MHz) PLL (on request) Typical consumption (mA) Max 5V Max 3V 5V 3V Xtal 7M 12 7 1.2 0.4 Xtal 20M 28 17 2.5 0.8 Xtal 50M 70 40 7 2 Xtal 100M 130 75 16 5 Xtal 32K 32 3 4 RC 10M 10 2 1 RC 32M 32 3 1.5 Contact factory. 4 Rev. I-23-Aug-01 Power supply & noise protection The speed and density of the SCMOS3/2RT technology causes large switching current spikes for example when: * 16 high current output buffers switch simultaneously, * or 10% of the 700 000 gates are switching within a window of 1ns. Sharp edges and high currents cause some FG_Leftsitic elements in the packaging to become significant. In this frequency range, the package inductance and series resistance should be taken into account. It is known that an inductor slows down the settling time of the current and causes voltage drops on the power supply lines. These drops can affect the behaviour of the circuit itself or disturb the external application (ground bounce). In order to improve the noise immunity of the MG core matrix, several mechanisms have been implemented inside the MG arrays. Two kinds of protection have been added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the matrix. I/O Buffers switching protection Matrix switching current protection Three features are implemented to limit the noise generated by the switching current: * The power supplies of the input and output buffers are seFG_Leftted. * The rise and fall times of the output buffers can be controlled by an internal regulator. * A design rule concerning the number of buffers connected on the same power supply line has been imposed. This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added: * Decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. * A power supply network has been implemented in the matrix. This solution reduces the number of FG_Leftsitic elements such as inductance and resistance and constitutes an artificial VDD and Ground plane. One mesh of the network supplies approximately 150 cells. * A low pass filter has been added between the matrix and the input to the output buffer. This limits the transmission of the noise coming from the ground or the VDD supply of the matrix to the external world via the output buffers. Note: 5 For additional information, see 'MG2 / Phase Locked Loop" Rev 1.0, 15 Oct. 96. MG2 Rev. I-23-Aug-01 MG2 Power consumption The power consumption of an MG2 array is due to three factors: leakage (P1), core (P2) and I/O (P3) consumption. P = P1 + P2 + P3 Leakage (Standby) Power Consumption The consumption due to leakage currents is defind as: P1 = (VDD - VSS) * ICCSB * NCELL Where ICCSB is the leakage current through a polarised basic gate and NCELL is the number of used cells. Core Power Consumption The power consumption due to the switching of cells in the core of the matrix is defined as: P2 = NCELL * PGATE * CACTIVITY * F Where NCELL is the number of used cells, F the data toggling frequency, which is equal to half the clock frequency for random data and PGATE is the power consumption per cell. PGATE = PCA + PCO ACTIVITY is the fraction of the total number of cells toggling per cycle. Capacitance Power PCA = C * (VDD - VSS)2/2 C is the total output capacitance and may be expressed as the sum of the drain capacitance of the driver, the wiring capacitance and the gate capacitance of the inputs. Worst case value: PCA # 1.8 W/gate/MHz @ 5 V Commutation Power PCO = (VDD - VSS) * Idsohm Where Idsohm is the current flowing into the driver between supply and ground during the commutation. Idsohm is about 15 % of the Pmos saturation currrent. Worst case value: Pco # 0.7 W/gate/MHz @ 5 V I/O Power Consumption The power consumption due to the I/Os is: P3 = Ni * CO * (VDD - VSS)2 * Fi/2 With Ni equals to the number of buffers running at Fi and CO is the output capacitance. Note: If a signal is a clock, Fi = F, if it is a data with random values, Fi = F/4. 6 Rev. I-23-Aug-01 Table 3. Power Consumption Example @ 5V Matrix MG2265 Used gates (70 %) 185 k Frequency 40 MHz Standby Power Iccsb (125C) 1 nA P1 = (VDD - VSS) * ICCSB * NCELL 1 mW Core Power Power Consumption per Cell Cactivity 1.96 W/Gate/MHz 20 % P2 = NCELL * PGATE * Cactivity * F 1449 mW I/O Power Total Number of Buffers 364 Number of Outputs and I/O Buffers 100 Output Capacitance 50 pF 2 P3 = Ni * CO * (VDD - VSS) * Fi/2 625 mW Total Power P = P1 + P2 + P3 7 2.07 W MG2 Rev. I-23-Aug-01 MG2 Packaging Atmel offers a wide range of packaging options which are listed below: Table 4. Packaging Options Package Type MQFP CQPF MPGA PBGA CLGA Note: Pins Lead spacing min/max* (inch**) 100 352 0.0256 0.020 44 196 176 391 0.050 0.10 100 121 100 676 0.10 349 564 0.05 * Contact Atmel Local Design Centers to check the availability of the used matrix and the plan package. ** To get the linear values in milimeters, multiply by 25.4 ***Ceramic Land Grid Array: contact factory. 8 Rev. I-23-Aug-01 Design flows & tools Design Flows and modes A generic design flow for an MG2 array is illustrated below. A top down design methodology is proposed which starts with high level system description and is refined in successive design steps. At each step, structural verification is performed which includes the following tasks: * Gate level logic simulation and comparison with high level simulation results. * Design and test rule check. * Power consumption analysis. * Timing analysis (only after floor plan). The main design stages are: * System specification, preferably in VHDL form. * Functional description at RTL level. * Logic synthesis. * Floor planning and bonding diagram generation. * Test/Scan insertion, ATG and/or fault simulation. * Physical cell placement, JTAG insertion and clock tree synthesis. * Routing To meet the various requirements of designers, several interface levels between the customer and Atmel are possible. For each of the possible design modes a review meeting is required for data transfer from the user to Atmel. In all cases the final routing and verifications are performed by Atmel. The design acceptance is formalised by a design review which authorises Atmel to proceed with sample manufacturing. 9 MG2 Rev. I-23-Aug-01 MG2 Figure 1. MG2 Design Flow System Specifications RTL Simulation Logic synthesis Floor Plan Bonding diagram Scan insertion ATG & Fault Simulation Placement JTAG insertion Clock Tree Synthesis Routing Samples Manufacturing and Test Design tool and design kits (DK) The basic content of a design kit is described in the table below. The interface formats to and from Atmel rely on IEEE or industry standard: * VHDL for functional descriptions * VHDL or EDIF for netlists * Tabular, log or .CAP for simulation results * SDF (VITAL format) and SPF for backannotation * LEF and DEF for physical floor plan information The design kit supported for several commercial tools is outlined in the table below. Table 5. Design Kit Support Design Kit Support VHDL Gate Cadence * * Mentor * * Synopsys * * Vital * * 10 Rev. I-23-Aug-01 Table 6. Design kit Description Design Tool or library Atmel Software Name Third Party Tools Design manual & libraries * VHDL library for blocks * Synthesis library * Gate level simulation library * Design rules analyser Power consumption analyser STAR COMET Floor plan library * Timing analyser library * Package & bonding software PIM Scan path & JTAG insertion MISS ATG & fault simulation library * * refer to "Design kits cross reference tables" ATD-TS-WF-R0181 11 MG2 Rev. I-23-Aug-01 MG2 Operating characteristics Absolute Maximum Ratings Ambient temperature under bias (TA) Military -55C to +125C Junction temperature TJ < TA + 20C Storage temperature -65C to +150C TLL/CMOS: Supply voltage VDD -0.5 V to +6 I/O voltage -0.5 V to VDD + 0.5 V Stresses above those listed may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics Table 7. DC Characterstics Specified at VDD = +5 V +/- 10% Symbol Definition Parameter Min VIL Input LOW voltage CMOS input TTL input VIH Input HIGH voltage VOL Output low voltage TTL VOH Output high voltage CMOS TTL VT+ Schmitt trigger positive threshold CMOS input TTL input VT- Schmitt trigger negative threshold CMOS input TTL input Max Unit 0 0 1.5 0.8 V CMOS input 3.5 VDD TTL input 2.2 VDD 0.4 3.9 2.4 1.2 1.0 IL No pull up/down Pull up Pull down Input leakage IOZ 3-State Output Leakage current IOS -55 79 IOH = -12, 6, 3 mA* V +/-5 -120 330 A A A +/-1 +/-5 A 48 36 mA mA ICCSB Leakage current per cell 1.0 10.0 nA ICCOP Operating current per cell 0.39 0.53 A/MHz Note: IOL = -12, 6, 3 mA* V +/-1 -69 125 IOSN IOSP Output Short circuit current V V 1.9 0.6 TTL hysteresis 25oC/5V Conditions V V 3.6 1.6 CMOS hysteresis 25oC/5V Delta V Typ BOUT12 VOUT = 4.5V VOUT = VSS * According buffer: Bout12, Bout6, Bout3. 12 Rev. I-23-Aug-01 Table 8. DC Characteristics Specified at VDD = +3V - 10% Symbol Parameter VIL Input LOW voltage LVCMOS input VIH VOL VOH VT+ VT- Typ Max 0 0 0.3VDD LVTTL input Input HIGH voltage LVCMOS input 0.7VDD VDD LVTTL input 2.0 VDD 0.8 Unit TTL 0.4 Output HIGH voltage TTL 2.4 V 2.2 LVTTL input 1.2 Schmitt trigger negative threshold LVCMOS input 0.8 0.2 TTL hysteresis 25oC/5V IOL = -6, 3, 1.5 mA* IOH = -4, 2, 1 mA* V V 0.9 0.8 CMOS hysteresis 25oC/5V V V Schmitt trigger positive threshold LVCMOS input Conditions V Output LOW voltage LVTTL input Delta V Min V Input leakage IL IOZ 150 A A A +/-1 A IOSN 24 IOSP 12 m mA No pull up/down +/-1 Pull up -20 Pull down 32 24 42 3-State Output Leakage current -60 Output Short circuit current IOS ICCSB Leakage current per cell 0.6 5 nA ICCOP Operating current per cell 0.2 0.3 A/MHz Note: 13 BOUT12 VOUT = VDD VOUT = VSS *According buffer: Bout12, Bout6, Bout3 MG2 Rev. I-23-Aug-01 MG2 Table 9. AC Characteristics TJ = 25C, Process typical (all values in ns) Buffer BOUT12 Cell BINCMOS BINTTL INV NAND2 FDFF Description Output buffer with 12 mA drive Description CMOS input buffer TTL input buffer Inverter 2 - input NAND D flip-flop, Clk to Q Load 60pf Load 15 fan 16 fan 12 fan 12 fan 8 fan Transition VDD 5V 3V Tplh 3.18 4.67 Tphl 2.35 3.33 Transition VDD 5V 3V Tplh 0.75 1.12 Tphl 0.7 0.98 Tplh 0.88 1.29 Tphl 0.65 1.03 Tplh 0.54 0.85 Tphl 0.39 0.49 Tplh 0.57 0.89 Tphl 0.49 0.67 Tplh 0.86 1.30 Tphl 0.73 1.08 Ts 0.44 1.06 Th 0.00 0.00 14 Rev. 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