__~ Fast Logic Programmable Pulse : PPG-33F Generator Bit) TTL Interfaced Features: m Precise pulse widths m@ 3-BIT address 1 ns to 50 ns incrmental steps m@ Trigger inherent delay Too = 3.5ns t2ns Too = 5.0ns+2ns m Inherent pulse width PW, = 9 ns + 2 ns PW, =6nst2ns @ Rising-edge triggered mu 14 pins DIP package m@ Low profile Specifications: @ Input pulse width: 6 ns min. = Programmed pulse-width tolerance: + 8% or 1 ns whichever is greater. = Supply voltage (Vcc): 5 Vdc + 5%. & Operating temperature: 0 C to 70 C. = Temperature coefficient: 100 PPM/* C. = Supply current: Icct: 41 ma. IccH: 20 ma. w DC parameters: See TTL-Fast Schottky Logic Table on Page 6. | t- 195 ADDRE . +.010 440 ao $3.35 MAX. . QO + 10: coo 290 -010 com re 4 H .830 MAX. > KAAX | |- -030 vec d4,x . + 005 : : : OUT : TRIG. 1! | PULSE FORMING ns er GENERATOR | 13 5 out . 020 GRpo4iWx i Equal Spaces Ln ae @ .100 = .600 Incremental: Pulse Total Pulse TRUTH TABLE Width Per Step Width Change - Part Number (ns). (ns) Enable Address (Bit No.) | Pulse Width " RES 3 2 1 Out PPG-33F-.5 S+8 35 1 = High PPG-33F-1 14:4 7 8 8 9 t5 0 = Low PPG-33F-2 2 +4 14 o 8 e i r = Don't care PPG-33F-3 3 + 45 2t 0 0 1 t T; To = Reference PPG-33F-5 5 + 6 35 or inwerent PPG-33F-10 0 240 70 0 1 0 0 Ts pulse width. PPG-33F-15 6 +13 105 0 1 0 1 Ts T, to T; = Multipiier of 0 1 1 0 qT, pulse width. PPG-33F-20 20 + 145 140 0 1 1 1 Tt; PPG-33F-40 40 + 2.0 280 1 9 o 0 0 PPG-33F-50 50 + 2.5 350 Contact us for specific requirements. We customize. 3 Mt. Prospect Avenue, Clifton, New Jersey 07013 = (201) 773-2299 m FAX (201) 773-9672 57