DS001-1 (v2.3) No vember 1, 2001 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778
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Introduction
The Spartan™-II 2.5V Field-Programmable Gate Arra y fa m-
ily giv es users high performance, ab undant logic resources,
and a rich feature set, all at an exceptionally low price. The
six-member family offers densities ranging from 15,000 to
200,000 system gates, as shown in Table 1. System perfor-
mance is supported up to 200 MHz.
Spartan-II devices deliver more gates, I/Os, and features
per dollar than other FPGAs by combining advanced pro-
cess technology with a streamlined Virtex-based architec-
ture. Features include block RAM (to 56K bits), distributed
RAM (to 75,264 bits ), 16 selectable I/O standards, and four
DLLs. F ast, predictable interconnect means that successiv e
design iterations continue to meet timing requirements.
The Spartan-II family is a superior alternative to
mask-programmed ASICs. The FPGA av oids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no ha rdware replaceme nt
necessary (impossible with ASICs).
Features
• Second generation ASIC replacement technology
- Dens ities as high as 5,292 logic cells with u p to
200,000 system gates
- Streamlined features based on Virt ex archit ecture
- Unlimited reprogramm ability
- Very low cost
• S y stem level features
- SelectRAM+™ hierarchical memory:
·16 bits/LUT distributed RAM
·Configurable 4K bit block RAM
·Fast interfaces to exter nal RAM
- Fu lly P C I co mplia nt
- Low-power segmented routing architecture
- Full readback ability fo r verification/observabilit y
- Dedicated carr y logi c for high-speed arithm et ic
- Dedicated multiplier support
- Cascade chain for wide-input functions
- Ab undant registers/latches with enable , set, reset
- Four dedicated DLLs for advanced clock control
- Four primary low-skew global clock distribution nets
- I EEE 1149. 1 comp ati ble boundar y scan logic
•Vers atile I/O and packaging
- Low cost packages available in all densities
- Family footprint compatibility in common packages
- 16 high-performance interface standards
- Hot swap Compact PCI friend ly
- Z ero hold time simplifies system timing
•Fully s upported by powerful Xilinx development syst em
- Foundation ISE Series: Fully integrated software
- A lliance Serie s: For use with third -par t y tools
- F ully autom atic mapping , placem ent, and routing
0Spartan-II 2.5V FPGA Family:
Introduction and Ordering
Information
DS001-1 (v2.3) November 1, 2001 00Preliminary Product Speci fication
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Table 1: Sp artan-II F PGA Fa mily Me mbe r s
Device Logic
Cells System Gate s
(Logic and RAM)
CLB
Array
(R x C) Total
CLBs
Maximum
Available
User I/O(1)
Total
Distributed RAM
Bits
Total
Block RAM
Bits
XC2S 15 432 15,00 0 8 x 12 96 86 6,144 16K
XC2S30 972 30,000 12 x 18 216 132 13,824 24K
XC2S50 1,728 50,000 16 x 24 384 176 24,576 32K
XC2S100 2,700 100,000 20 x 30 600 196 38,400 40K
XC2S150 3,888 150,000 24 x 36 864 260 55,296 48K
XC2S200 5,292 200,000 28 x 42 1,176 284 75,264 56K
Notes:
1. All use r I/ O counts do not incl ude the four global clock/user input pin s. See details in Tabl e 3, page 3.
S pa rta n- II 2. 5 V FPG A Fam ily : Introdu c t io n an d O rd e ring Infor ma t ion
2www.xilinx.com DS001-1 (v 2.3) November 1, 2001
1-800-255-7778 Preliminary Product Specification
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General Overview
The Spartan-II family of FPGAs hav e a regular , fle xible , pro-
grammable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corn er of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and t he IOB col um ns. These funct iona l elemen ts are
interconnected by a powerful hierarchy of versatile routing
channels (see Figure 1).
Spar tan-II FPGAs are customized by loading configu ration
data into internal static memory cells. Unlimited reprogram-
ming cycles are pos sible with this approac h. St ored values
in these cells determine logic functions and interconnec-
tions implem ented in the FP GA. Configuration dat a can be
read from an external serial PROM (master serial mode), or
written into the FPGA in slave serial, slave parallel, or
Boundar y S can modes.
Spartan-II FPGAs are typically used in high-volume applica-
tions where the versatility of a fast programmable solution
adds benefits. Spartan-II FPGAs are ideal for shortening
product development cycles while offering a cost-effective
solution for high volume production.
Spartan-II FPGAs achieve high-performance, low-cost
operation through advanced architecture and semiconduc-
tor technology. Spartan-II devices provide system clock
rates up to 200 MHz. Spartan-II FPGAs offer the most
cost-effective solution while maintaining leading edge per-
formance. In addition to the conventional benefits of
high-volume programmable logic solutions, Spartan-II
FPGAs also offer on-chip synchronous single-port and
dual-port RAM (block and distr ibuted for m ), DLL c lock driv-
ers, programmable set and reset on all flip-flops, fast carry
logic, and many other features .
The Xilinx XC17S00A PROM family is recommended for
serial configuration of Spartan-II FPGAs. The In-System
Programmable (ISP) XC18V00 PROM family is recom-
mended for parallel or serial configuration.
Figure 1: Basic Spartan-II Family FPGA Block Diagram
XC2S15
DLL DLL
DLL
DLL
BLOCK RAM BLOCK RAM
BLOCK RAMBLOCK RAM
I/O LOGIC
CLBs CLBs
CLBs CLBs
DS001_01_091800
Sparta n - II 2.5V FP GA Fa m ily: Int roduct i on a nd Orderin g In forma tion
DS001-1 (v2.3) No vember 1, 2001 www.xilinx.com 3
Preliminary Product Specification 1-800-255-7778
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Spartan-II Product Availabili ty
Table 2 shows the pa ckage and spee d grades available for
Spartan-II family devices. Table 3 shows the m a xi mum user
I/Os available on the device and the number of user I/Os
available for each device/package combination. The four
global clock pins are usable as additional user I/Os when
not u se d as a global c lock pin. These pins are not includ ed
in user I/O counts.
Table 2: Spartan-II P ackag e and Speed Grade Av ail ability
Device
Pins 100 144 144 208 256 456
Type Plastic
VQFP Plastic
TQFP Chip Scale
BGA Plastic
PQFP Fine P itc h
BGA Fine P itch
BGA
Code VQ100 TQ144 CS144 PQ208 FG256 FG456
XC2S15 -5 C, I C, I C, I - - -
-6CCC- - -
XC2S30-5 C, IC, IC, IC, I - -
-6CCCC- -
XC2S50 -5 - C, I - C, I C, I -
-6-C-CC-
XC2S100 -5 - C, I - C, I C, I C, I
-6-C-CCC
XC2S150 -5 - - - C, I C, I C, I
-6---CCC
XC2S200 -5 - - - C, I C, I C, I
-6---CCC
Notes:
1. C = Commercial, TJ = 0° to +85 °C; I = Indus trial, TJ = –40°C to +1 0 0 °C.
Table 3: Sp artan-II Us e r I/O C h art(1)
Device Maximum
User I/O
Available User I/O According to Package Typ e
VQ100 TQ144 CS144 PQ208 FG256 FG456
XC2S15 86 60 86 86 - - -
XC2S30 132 60 92 92 132 - -
XC2S50 176 - 92 - 140 176 -
XC2S100 196 - 92 - 140 176 196
XC2S150 260 - - - 140 176 260
XC2S200 284 - - - 140 176 284
Notes:
1. All use r I/ O counts do not incl ude the four global clock/user input pin s.
S pa rta n- II 2. 5 V FPG A Fam ily : Introdu c t io n an d O rd e ring Infor ma t ion
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1-800-255-7778 Preliminary Product Specification
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Ordering Information
Revision History
The Spartan-II Family Data Sheet
DS001-1, Spartan-II 2.5V FPGA Family: Introduction and Ordering Information (Module 1)
DS001-2, Spa r t a n-I I 2.5V FPGA Fami ly: Functional Description (M odule 2)
DS001-3, Spa r t a n-I I 2.5V FPGA Fami ly: DC and Switching Characteristics (Module 3)
DS001-4, Spa r t a n-I I 2.5V FPGA Fami ly: Pinout Tables (Module 4)
XC2S50 -6 PQ 208 C
Example: Temperature Range
Numbe r of Pins
Package Type
De vi ce Type
Speed Grade
Device O rdering Options
Device Speed Grade Number of Pins / Pac kage Type Temperature Range (TJ)
XC2S15 -5 Standard Perfor mance VQ100 100-pin Plastic Ver y Thin QFP C = Commercial 0°C to +85 °C
XC2S30 -6 Higher Performance CS144 144-ball Chip-Scale BGA I = Indust ria l –40°C to +100°C
XC2S50 TQ144 144-pin Plastic Thin QFP
XC2S100 PQ208 208-pin Plastic QFP
XC2S150 FG256 256-ball Fine Pitch BGA
XC2S200 FG456 456-ball Fine Pitch BGA
Version No. Date Description
2.0 09/18/00 Sectioned the Spartan-II F amily data sheet into four modules. Added industrial temperature
range informat ion.
2.1 10/31/00 Removed Power down f eature.
2.2 03/05/01 Added statement on PROMs.
2.3 11/01 /01 Upda te Product Availability ch art. Minor text edits.
PN 01 1311
