FEDL610Q178FULL-01
Issue Date: May 18, 2012
ML610Q178
The low power micro controller corresponding to 5v for household appliances
I
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GENERAL DESCRIPTION
Equipped with a 8-bit CPU nX-U8/100, the ML610Q178 is a high-performance 8-bit CMOS microcontroller
that integrates a wide variety of peripherals such as 10-bit A/D converter, timer, PWM, synchronous serial port,
UART, I2C bus interface (master), Battery level detect circuit, LCD driver. The nX-U8/100 CPU is capable of
executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the
3-stage pipelined architecture.
In addition, it has an on-chip debugging function, which allows software debugging/rewriting with the LSI
mounted on the board.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system:16-bit instructions
− Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
− On-Chip debug function
− Minimum instruction execution time
Approx 30.5 μs (at 32.768kHz system clock)
Approx 0.122 μs (at 8.192MHz system clock)＠VDD = 2.2 to 5.5V
• Internal memory
− Has 128-Kbyte flash ROM(64K × 16-bit) built in. (1K byte of test domain that it cannot be used is
included)
− Has 4-Kbyte RAM (4096 × 8 bits) built in.
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 23 maskable interrupt sources (Internal source: 19, External source: 4)
• Time base counter
− Low-speed time base counter × 1 channel
− High-speed time base counter × 1 channel
• Watchdog timer
− Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 6ch (16-bit configuration available)
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• PWM
− Resolution 16 bits × 2 channel(IGBT control)
• Synchronous serial port
− 2ch
− Master/slave selectable
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
• UART
− Half-duplex
− TXD/RXD × 2 channels
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
− Positive logic/negative logic selectable
− Built-in baud rate generator
• I2C bus interface
− Master function only
− Fast mode (400kbit/s@4MHz), Standard mode (100kbit/s@4MHz)
• Successive approximation type A/D converter
− 10-bit A/D converter
− Input: 16ch （Maximum）
− Conversion time: 12.75μs per channel
• General-purpose ports ×74（Maximum）
− Non-maskable interrupt input port × 1ch
− Input-only port × 6ch
− Output-only port × 8ch (including secondary functions)
− Input/output × 27ch (including secondary functions)
− Input/output × 32ch (including LCD driver functions)
• LCD driver
− 160 dots max. (40 seg × 4 com), 1/1 to 1/4 duty
− Frame frequency selecable (approx. 64Hz, 73Hz, 85Hz, 102Hz, 32Hz, 128Hz, 171Hz, and 256Hz)
− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
• Power supply voltage detect function
− Judgment voltages: One of 4 levels
− Judgment accuracy: ±2% (Typ.)
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• Reset
− Reset through the RESET_N pin
− Reset by the watchdog timer (WDT) overflow
• Clock
− Low-speed clock (This LSI can not guarantee the operation withoug low-speed clock)
Crystal oscillation (32.768 kHz) or Built-in RC oscillation (32.7kHz)
− High-speed clock
Built-in oscillation (8.192MHz), Crystal/Ceramic oscillation (8MHz), external clock
• Power management
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral
circuits are stopped.)
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the
oscillation clock)
− Block control function: Operation of an intact functional block circuit is powerd down. (register reset and clock
stop)
• Shipment
− 100-pin QFP (QFP100-P-1420-0.65-BK)
− ML610Q178-xxxGA (blank product: ML610Q178-NNNGA)
xxx: ROM code number
• Guaranteed operating range
− Operating temperature: −40°C to 85°C
− Operating voltage: VDD = 2.2V to 5.5V, VREF = 4.5V to 5.5V
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BLOCK DIAGRAM
Figure 1-1 is a block diagram of the ML610Q178.
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding port.
Program
Memory
（Flash）
128Kbyte
RAM
4096byte
Interrupt
Controller
CPU (nX-U8/100) Large Model
Timing
Controller
EA
SP
Instruction
Decoder
BUS
Controller
Instruction
Register
TBC
INT
4
INT
68bit Timer
×6
GPIO
NMI
P20 to P23
INT
5
P50 to P53
Data-bus
TEST0
RESET_N
OSC
POWER
VDDL
RESET &
TEST
ALU
EPSW1～3
PSW
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
0～15
V
PP
VDD
VSS
OUTCLK*
UART RXD0*
1
,
RXD1*
1
TXD0*
1
, TXD1*
1
INT
2
LSCLK*
P40 to P43
On-Chip
ICE
P00 to P03
SSIO SCK0*
1
,
SCK1*
1
SIN0*
1
,
SIN1*
1
SOUT0*
1
,
SOUT1*
1
INT
2
WDT
INT
10bit-ADC
AIN0 to AIN15
*3
VREF
VDD
VSS
OSC0*
1
INT
I2C
INT
1SDA*
1
SCL*
1
PWM
INT
2PWM4*
1
PWM5*
1
LCD
Driver
COM0 to COM3
SEG0 to SEG7
LCD
Drive Voltage VL1, VL2, VL3
XT0
XT1
P60 to P67
*
3
P90 to P93
BLD
PW45EV0*
1
P30 to P33
*3
INT
1
P10 to P11
P34 to P36
OSC1*
TEST1_N
P44 to P47
*3
SEG8 to SEG39
*2
PW45EV1*
1
PC0 to PC7
*
2
PD0 to PD7
*
2
PE0 to PE7
*
2
PF0 to PF7
*
2
*
1
Secondary or tertiary function
*2 Select I/O port or LCD driver
*3 Select I/O port or A/D converter input
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PIN CONFIGURATION
ML610Q178 QFP package product
NC: No Connection
PE1/SEG25
NMI
P03/INT3
P02/INT2
P01/INT1
P00/INT0
RESET
_
N
TEST0
PE7/SEG31
PE6/SEG30
PE5/SEG29
PE4/SEG28
PE3/SEG27
PE2/SEG26
PE0
/
SEG24
PD7/SEG23
PD6/SEG22
PD5/SEG21
PD4/SEG20
PF7/SEG39
PF6/SEG38
PF5/SEG37
PC5/SEG13
PC4/SEG12
PC3/SEG11
PC2/SEG10
PC1/SEG9
PC0/SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
P90/LED4
P91/LED5
P92/LED6
P
93/
LED7
P67/AIN15
P66/AIN14
P65/AIN13
P64/AIN12
VSS
P33/AIN3
P32/AIN2
P31/AIN1
P30/AIN0
VREF
P10/OSC0
P50/SIN1
P51/SCK1
P52/SOUT1
P53/TXD1
P34/PWM4
P35/PWM5
P36/LSCLK
P40/SDA
P41/SCL
P42/RXD0
P43/TXD0
VDD
VPP
TEST1_N
VDDL
XT1
XT0
VL1
VL2
VL3
P23/LED3
P22/LED2
P21/LED1
P20/LED0
P63/AIN11
P62/AIN10
P61/AIN9
P60/AIN8
P47/AIN7
P46/AIN6
P45/AIN5
PF4/SEG36
P44/AIN4
VSS
PC7/SEG15
PC6/SEG14
1pin
100pin
30pin
31pin
50pin
51pin
81pin
80pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
61
60
59
58
57
55
54
53
52
51
71
70
69
68
67
66
65
64
63
62
80
79
78
77
76
75
74
73
72
56
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
COM3
COM2
COM1
COM0
PD2/SEG18
PD1/SEG17
PD0/SEG16
PD3/SEG19
PF3/SEG35
PF2/SEG34
PF1/SEG33
PF0/SEG32
P11/OSC1
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LIST OF PINS
Primary function Secondary function Tertiary function
Pin
No. Pin
name I/O Description Pin
name I/O Description Pin
name I/O Description
18,85 Vss ⎯ Negative power supply pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
19 VDD ⎯ Positive power supply pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
20 VDDL ⎯ Power supply for internal logic
(internally generated) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
23 VPP ⎯ Power supply pin for Flash ROM ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
24 VL1 ⎯ Power supply pin for LCD bias ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
25 VL2 ⎯ Power supply pin for LCD bias ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
26 VL3 ⎯ Power supply pin for LCD bias ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
14 TEST0 I/O
Input/output pin for testing ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
15 TEST1_N I/O
Input/output pin for testing ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
71 RESET_N I Reset input pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
21 XT0 I
Low-speed clock oscillation pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
22 XT1 O
Low-speed clock oscillation pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6 VREF I
Reference power supply pin of
Successive-approximation type
ADC
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
80 NMI I
Input port,
non-maskable interrupt ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
76 P00/EXI0/
PW45EV0 I
Input port /
External interrupt /
PW45EV0 input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
77 P01/EXI1 I
Input port /
External interrupt ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
78 P02/EXI2/
RXD0 I
Input port /
External interrupt
UART0 data input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
79 P03/EXI3/
RXD1 I
Input port /
External interrupt /
UART1 data input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
16 P10 I Input port OSC0 I
High-speed clock
oscillation pin ⎯ ⎯ ⎯
17 P11 I Input port OSC1 O High-speed clock
oscillation pin ⎯ ⎯ ⎯
81 P20/
LED0 O Output port / LED drive LSCLK O Low-speed clock
output ⎯ ⎯ ⎯
82 P21/
LED1 O Output port / LED drive OUTCLK O Low-speed clock
output ⎯ ⎯ ⎯
83 P22/
LED2 O Output port / LED drive ⎯ ⎯ ⎯ TM9OUT O Timer9 output
84 P23/
LED3 O Output port / LED drive ⎯ ⎯ ⎯ TMBOUT O TimerB output
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Primary function Secondary function Tertiary function Fourthly function
Pin
No. Pin
name I/O Description Pin
name I/O Description Pin
name I/O Description Pin
name I/O Description
5
P30/
PW45EV1
/AIN0
I/O
Input/output port
/
PW45EV1 input
/
Successive
approximation
type ADC input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4 P31/AIN1 I/O
Input/output port
/
Successive
approximation
type ADC input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
3 P32/AIN2 I/O
Input/output port
/
Successive
approximation
type ADC input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2 P33/AIN3 I/O
Input/output port
/
Successive
approximation
type ADC input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
11 P34 I/O Input/output port
⎯ ⎯ ⎯ PWM4 O PWM4
output ⎯ ⎯ ⎯
12 P35 I/O Input/output port
⎯ ⎯ ⎯ PWM5 O PWM5
output ⎯ ⎯ ⎯
13 P36 I/O Input/output port
LSCLK O
Low-speed
clock
output
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
72 P40 I/O Input/output port SDA I/O I2C data
input/output SIN0 I
SSIO0 data
input ⎯ ⎯ ⎯
73 P41 I/O Input/output port SCL I/O I2C clock
input/output SCK0 I/O
SSIO0
synchronous
clock
input/output
⎯ ⎯ ⎯
74 P42 I/O Input/output port RXD0 I UART0
data input SOUT0 O SSIO0 data
output ⎯ ⎯ ⎯
75 P43 I/O Input/output port TXD0 O UART0
data output PWM4 O PWM4
output TXD1 O UAR1
data output
1
P44/
T0P4CK/
AIN4
I/O
Input port /
Timer0 /
PWM4 external
clock input/
Successive
approximation
type ADC input
SIN0 I
SSIO0 data
input ⎯ ⎯ ⎯
100
P45/
T1P5CK/
AIN5
I/O
Input port /
Timer1 /
PWM5 external
clock input/
Successive
approximation
type ADC input
SCK0 I/O
SSIO0
synchronous
clock
input/output
⎯ ⎯ ⎯
99
P46/
T8ACK/
AIN6
I
Input port /
Timer8 /
TimerA external
clock input /
Successive
approximation
type ADC input
SOUT0 O SSIO0 data
output ⎯ ⎯ ⎯
98
P47/
T9BCK/
AIN7
I
Input port /
Timer9 /
TimerB external
clock input /
Successive
approximation
type ADC input
PWM5 O PWM5
output ⎯ ⎯ ⎯
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Primary function Secondary function Tertiary function Fourthly function
Pin
No. Pin
name I/O Description Pin
name I/O Description Pin
name I/O Description Pin
name I/O Description
7 P50 I/O Input/output port
⎯ ⎯ ⎯ SIN1 I
SSIO1 data
input ⎯ ⎯ ⎯
8 P51 I/O Input/output port
⎯ ⎯ ⎯ SCK1 I/O
SSIO1
synchronous
clock
input/output
⎯ ⎯ ⎯
9 P52 I/O Input/output port RXD1 I
UART1
data input SOUT1 O SSIO1 data
output ⎯ ⎯ ⎯
10 P53 I/O Input/output port TXD1 O UART1
data input ⎯ ⎯ ⎯ TXD0 O UAR0
data output
97 P60/
AIN8 I/O
Input/output
port/
Successive
approximation
type ADC input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
96 P61/
AIN9 I/O
Input/output
port/
Successive
approximation
type ADC input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
95 P62/
AIN10 I/O
Input/output
port/
Successive
approximation
type ADC input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
94 P63/
AIN11 I/O
Input/output
port/
Successive
approximation
type ADC input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
93 P64/
AIN12 I/O
Input/output
port/
Successive
approximation
type ADC input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
92 P65/
AIN13 I/O
Input/output
port/
Successive
approximation
type ADC input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
91 P66/
AIN14 I/O
Input/output
port/
Successive
approximation
type ADC input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
90 P67/
AIN15 I/O
Input/output
port/
Successive
approximation
type ADC input
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
86 P90/
LED4 O Output port /
LED drive ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
87 P91/
LED5 O Output port /
LED drive ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
88 P92/
LED6 O Output port /
LED drive ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
89 P93/
LED7 O Output port /
LED drive ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
30 COM0 O
LCD common
pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
29 COM1 O
LCD common
pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
28 COM2 O
LCD common
pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
27 COM3 O
LCD common
pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
31 SEG0 O
LCD segment
pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
32 SEG1 O
LCD segment
pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
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Primary function Secondary function Tertiary function Fourthly function
Pin
No. Pin
name I/O Description Pin
name I/O Description Pin
name I/O Description Pin
name I/O Description
33 SEG2 O
LCD segment
pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
34 SEG3 O
LCD segment
pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
35 SEG4 O
LCD segment
pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
36 SEG5 O
LCD segment
pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
37 SEG6 O
LCD segment
pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
38 SEG7 O
LCD segment
pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
39 PC0 I/O Input/output port SEG8 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
40 PC1 I/O Input/output port SEG9 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
41 PC2 I/O Input/output port SEG10 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
42 PC3 I/O Input/output port SEG11 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
43 PC4 I/O Input/output port SEG12 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
44 PC5 I/O Input/output port SEG13 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
45 PC6 I/O Input/output port SEG14 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
46 PC7 I/O Input/output port SEG15 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
47 PD0 I/O Input/output port SEG16 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
48 PD1 I/O Input/output port SEG17 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
49 PD2 I/O Input/output port SEG18 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
50 PD3 I/O Input/output port SEG19 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
51 PD4 I/O Input/output port SEG20 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
52 PD5 I/O Input/output port SEG21 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
53 PD6 I/O Input/output port SEG22 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
54 PD7 I/O Input/output port SEG23 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
55 PE0 I/O Input/output port SEG24 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
56 PE1 I/O Input/output port SEG25 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
57 PE2 I/O Input/output port SEG26 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
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Primary function Secondary function Tertiary function Fourthly function
Pin
No. Pin
name I/O Description Pin
name I/O Description Pin
name I/O Description Pin
name I/O Description
58 PE3 I/O Input/output port SEG27 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
59 PE4 I/O Input/output port SEG28 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
60 PE5 I/O Input/output port SEG29 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
61 PE6 I/O Input/output port SEG30 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
62 PE7 I/O Input/output port SEG31 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
63 PF0 I/O Input/output port SEG32 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
64 PF1 I/O Input/output port SEG33 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
65 PF2 I/O Input/output port SEG34 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
66 PF3 I/O Input/output port SEG35 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
67 PF4 I/O Input/output port SEG36 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
68 PF5 I/O Input/output port SEG37 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
69 PF6 I/O Input/output port SEG38 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
70 PF7 I/O Input/output port SEG39 O
LCD
segment
pin
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
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PIN DESCRIPTION
Pin name I/O Description Primary/
Secondary Logic
Power supply
VSS —
Negative power supply pin — —
VDD —
Positive power supply pin — —
VDDL —
Positive power supply pin for internal logic (internally generated). Connect
capacitors (CL) (see Measuring Circuit 1) between this pin and VSS . — —
VPP —
Power supply pin for programming Flash ROM. — —
VL1 —
Power supply pins for LCD bias (external input) — —
VL2 —
Power supply pins for LCD bias (external input) — —
VL3 —
Power supply pins for LCD bias (external input) — —
Test
TEST0 I/O Input/output pin for testing. Has a pull-down resistor built in. — Positive
TEST1_N I/O Input/output pin for testing. Has a pull-up resistor built in. — Negative
System
RESET_N I
Reset input pin. When this pin is set to a “L” level, the device is placed in
system reset mode and the internal circuit is initialized. If after that this pin
is set to a “H” level, program execution starts. This pin has a pull-up
resistor built in.
— Negative
XT0 I — —
XT1 O
Crystal connection pin for low-speed clock. A 32.768 kHz crystal oscillator
(see measuring circuit 1) is connected to this pin. Capacitors CDL and CGL
are connected across this pin and VSS as required. — —
OSC0 I Secondary —
OSC1 O
External input pin for high-speed clock. This function is allocated to the
secondary function of the P10 pin. Secondary —
LSCLK O
Low-speed clock output. This function is allocated to the secondary function
of the P20/P36 pin. Secondary —
OUTCLK O
High-speed clock output. This function is allocated to the secondary
function of the P21 pin. Secondary —
General-purpose input port
P00 to P03 I
P10 to P11 I
General-purpose input ports. Provided with a secondary function for each
port. Cannot be used as ports if their secondary functions are used. Primary Positive
General-output input port
P20 to P23 O General-purpose output ports.Provided with a secondary function for each
port. Cannot be used as ports if their secondary functions are used. Primary Positive
P90 to P93 O General-purpose output ports.Provided with a secondary function for each
port. Cannot be used as ports if their secondary functions are used. Primary Positive
General-purpose input/output port
P30 to P36
P40 to P47
P50 to P53
General-purpose input/output ports.Provided with a secondary function for
each port. Cannot be used as ports if their secondary functions are used.
PC0 to PC7
PD0 to PD7
PE0 to PE7
PF0 to PF7
I/O
General-purpose input/output ports.Provided with a LCD segment for each
port. Cannot be used as ports if LCD segment are used.
Primary Positive
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Pin name I/O Description Primary/
Secondary Logic
UART
TXD0 O
UART0 data output pin. Allocated to the secondary function of the P43 pin
and the fourthly function of the P53 pin.
Secondary
Fourthly Positive
RXD0 I
UART0 data input pin. Allocated to the primary function of the P02 pin and
the secondary function of the P42 pin. Secondary Positive
TXD1 O
UART1 data output pin. Allocated to the secondary function of the P53 pin
and the fourthly function of the P43 pin.
Secondary
Fourthly Positive
RXD1 I
UART1 data input pin. Allocated to the primary function of the P03 pin and
the secondary function of the P52 pin. Secondary Positive
I2C bus interface
SDA I/O
I2C data input/output pin. This pin is used as the secondary function of the
P40 pin. This pin has an NMOS open drain output. When using this pin as
a function of the I2C, externally connect a pull-up resistor.
Secondary Positive
SCL I/O
I2C clock output pin. This pin is used as the secondary function of the P41
pin. This pin has an NMOS open drain output. When using this pin as a
function of the I2C, externally connect a pull-up resistor.
Secondary Positive
Synchronous serial (SSIO)
SIN0 I
Synchronous serial data input pin. Allocated to the tertiary function of the
P40 pin and P44 pin. Tertiary Positive
SCK0 I/O
Synchronous serial clock input/output pin. Allocated to the tertiary function
of the P41 pin and P45 pin. Tertiary —
SOUT0 O
Synchronous serial data output pin. Allocated to the tertiary function of the
P42 pin and P46 pin. Tertiary Positive
SIN1 I
Synchronous serial data input pin. Allocated to the tertiary function of the
P50 pin . Tertiary Positive
SCK1 I/O
Synchronous serial clock input/output pin. Allocated to the tertiary function
of the P51 pin. Tertiary —
SOUT1 O
Synchronous serial data output pin. Allocated to the tertiary function of the
P52 pin. Tertiary Positive
PWM
PWM4 O
PWM4 output pin. Allocated to the tertiary function of the P34 and P43 pins. Tertiary Positive
PWM5 O
PWM5 output pin. Allocated to the tertiary function of the P35and P47 pins. Tertiary Positive
T0P4CK I
External clock input pin for timer 0 and PWM4. Allocated to the primary
function of the P44 pin. Primary —
T1P5CK I
External clock input pin for timer 1 and PWM5. Allocated to the primary
function of the P45 pin. Primary —
PW45EV0
PW45EV1 I Control start /stop pin for PWM4 and PWM5. Allocated to the primary
function of the P00 pin and P30 pin. Primary —
External interrupt
NMI I
External non-maskable interrupt input pin. The interrupt occurs on both the
rising and falling edges. Primary Positive/
Negative
EXI0–EXI3 I
External maskable interrupt input pins. It is possible, for each bit, to specify
whether the interrupt is enabled and select the interrupt edge by software.
Allocated to the primary function of the P00–P03 pins.
Primary Positive/
Negative
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Pin name I/O Description Primary/
Secondary Logic
Timer
T0P4CK I
External clock input pin for timer 0 and PWM4. Allocated to the primary
function of the P44 pin. Primary —
T1P5CK I
External clock input pin for timer 1 and PWM5. Allocated to the primary
function of the P45 pin. Primary —
T8ACK I
External clock input pin for timer 8 and timer A. Allocated to the primary
function of the P46 pin. Primary —
T9BCK I
External clock input pin for timer 9 and timer B. Allocated to the primary
function of the P47 pin. Primary —
TM9OUT O
Timer9 overflow output pin. Allocated to the secondary function of the P22
pin. Tertiary Positive
TMBOUT O
TimerB overflow output pin. Allocated to the secondary function of the P23
pin. Tertiary Positive
LED drive
LED0-LED7 O
Pins for LED driving. Allocated to the primary function of the P20–P23 pins
and P90–P93 pins. Primary Positive/
Negative
Successive-approximation type A/D converter
VREF I
Reference power supply pin for successive approximation type A/D
converter. — —
AIN0–AIN15 I
Analog inputs to Ch0–Ch15 of the successive-approximation type A/D
converter. Allocated to the secondary function of the P30 to P33 and P44 to
P47 and P60 to P67 pins.
Primary —
LCD driver
COM0 to
COM3 O LCD common output pins. Primary —
SEG0 to
SEG7 O LCD segment output pins. Primary —
SEG8 to
SEG39 O LCD segment output pins. Allocated to the secondary function of the PC0
to PC7 and PD0 to PD7 and PE0 to PE7 and PF0 to PF7 pins. Secondary —
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TERMINATION OF UNUSED PINS
How to Terminate Unused Pins
Pin Recommended pin termination
VPP open
RESET_N open
TEST0 open
TEST1_N open
VREF Connect to VDD
P00 to P03 Connect VDD or VSS
P10 to P11 Connect VDD or VSS
P20 to P23 open
P30 to P33 (AIN0 to AIN3) open
P34 to P36 open
P40 to P43 open
P44 to P47 (AIN4 to AIN7) open
P50 to P53 open
P60 to P67 (AIN8 to AIN15) open
P90 to P93 open
COM0 to COM3 open
SEG0 to SEG7 open
PC0 to PC7 （SEG8 to15） open
PD0 to PD7 （SEG16 to 23） open
PE0 to PE7 （SEG24 to 31） open
PF0 to PF7 （SEG32 to 39） open
Note:
For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance inputs
and left open, the supply current may become excessively large. Therefore, it is recommended to configure those pins as
either inputs with a pull-down resistor/pull-up resistor or outputs.
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ELECTRICAL CHARACTERISTICS
Ab solute Maximum Rat ings
(VSS = 0V)
Parameter Symbol Condition Rating Unit
Power supply voltage 1 VDD Ta = 25°C −0.3 to +7.0 V
Power supply voltage 2 VDDL Ta = 25°C −0.3 to +3.6 V
Power supply voltage 3 VPP Ta = 25°C −0.3 to +9.5 V
Power supply voltage 4 VL1 Ta = 25°C −0.3 to +2.33 V
Power supply voltage 5 VL2 Ta = 25°C −0.3 to +4.66 V
Power supply voltage 6 VL3 Ta = 25°C −0.3 to +7.0 V
Reference voltage VREF Ta = 25°C −0.3 to VDD+0.3 V
Analog input voltage VAI Ta = 25°C −0.3 to VDD+0.3 V
Input voltage VIN Ta = 25°C −0.3 to VDD+0.3 V
Output voltage VOUT Ta = 25°C −0.3 to VDD+0.3 V
Output current 1 IOUT1 Port3,4,5,6,C,D,E,F
Ta = 25°C −12 to +11 mA
Output current 2 IOUT2 Port2,9 Ta = 25°C −12 to +20 mA
Power dissipation PD Ta = 25°C 1 W
Storage temperature TSTG ― −55 to +150 °C
Recommended Operating Conditions
(VSS = 0V)
Parameter Symbol Condition Range Unit
Operating temperature TOP ― −40 to +85 °C
Operating voltage VDD ― 2.2 to 5.5 V
Reference voltage VREF ― 4.5 to VDD V
Analog input voltage VAI ― V
SS to VREF
Operating frequency (CPU) fOP ― 30k to 8.4M Hz
Low-speed crystal oscillation frequency fXTL ― 32.768k Hz
Capacitor externally connected to VDD pin CV ― 10±30% μF
Capacitor externally connected to VPP pin C1 ― 1±30% μF
Capacitor externally connected to Vref pin CAV ― 1±30% μF
CDL 12 to 25
Low-speed crystal oscillation
external capacitor CGL
Use 32.768KHz Crystal
Oscillator DT-26
(DAISHINKU CORP.) 12 to 25
pF
High-speed crystal/ceramic oscillation
frequency fXTH ― 8M/8.192M Hz
CDH ― 47±30%
High-speed crystal oscillation
external capacitor* CGH ― 47±30% pF
Capacitor externally connected to VDDL pin CL ― 10±30% μF
* CGH and CDH are built into, external capacity is unnecessary for CSTLS8M00G56 (made by Murata Mfg.).
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Flash Me mory Operating Conditions
(VSS = 0V)
Parameter Symbol Condition Range Unit
Operating temperature TOP At write/erase 0 to +40 °C
VDD At write/erase 2.7 to 5.5
VDDL At write/erase*1 2.5 to 2.75
Operating voltage
VPP At write/erase1 7.7 to 8.3
V
Maximum rewrite count CEP ― 80 times
Data retention period YDR ― 10 years
*1: At the writing of a flash ROM, it is necessary to supply voltage to VDDL pin within the limits of the above-mentioned
regulation. Pulldown resistance is built in the VPP pin.
DC Characteristics (1 of 5)
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
Measuring
circuit
High-speed crystal oscillation
start time TXTH ― ― 2 20 ms
Low-speed crystal oscillation
start time*2 TXTL ― ― 0.6 2 s
Low-speed RC oscillator
frequency fLCR Ta= -10 to 60°C Typ
-5% 32.7k Typ
+5% Hz
PLL oscillation frequency fPLL LSCLK=32.768kHz
100 clock average
Typ
-1% 8.192 Typ
+1% MHz
Reset pulse width PRST ― 100 ― ―
Reset noise rejection pulse
width PNRST ― ― ― 0.4
μs
1
*1: Use 32.768KHz Crystal Oscillator DT-26 (Daishinku) with capacitance CGL/CDL＝12pF.
Reset
RESET_N
Reset by RESET_N pin
PRST
VIL1VIL1
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DC Characteristics (2 of 5)
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
Meas
uring
circuit
LD3 to 0 = 0H 2.35
LD3 to 0 = 3H 2.80
LD3 to 0 = 9H 3.70
BLD threshold
voltage VBLD Ta = 25°C
LD3 to 0 = FH
Typ.
-2%
4.60
Typ.
+2% V 1
DC Characteristics (3 of 5)
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
Meas
uring
circuit
-40 to +35℃ ― 0.7 6
Supply current 1 IDD1
CPU: In STOP state
Low-speed/high-speed
oscillation: Stopped
VDD=3.0V -40 to +85℃ ― 0.7 22
-40 to +35℃ ― 2.0 7
Supply current 2 IDD2
CPU: In HALT state
(LTBC,WBC: Operating*2)
High-speed oscillation: Stopped
VDD=3.0V -40 to +85℃ ― 2.0 24
-40 to +35℃ ― 13 20
Supply current 3 IDD3
CPU: Running at 32kHz*1
High-speed oscillation: Stopped
VDD=3.0V
-40 to +85℃ ― 13 42
μA
Supply current 4 IDD4
CPU: Running at 8.192MHz
Crystal/ceramic oscillating mode*2
VDD = SPVDD = 5.0V
― 5 8 mA
1
*1: Case when the CPU operating rate is 100% (with no HALT state)
*2 : Significant bits of BLKCON0 to BLKCON4 registers are all “1”.
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DC Characteristics (4 of 5)
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
Measuring
circuit
VOH1 IOH1 = −0.5mA VDD
−0.5 ― ―
Output voltage 1
(P20 to P23)
(P30 to P36)
(P40 to P47)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
(PE0 to PE7)
(PF0 to PF7)
VOL1 IOL1 = +0.5mA ― ― 0.5
Output voltage 2
(P20–P23)
(P90-P93)
VOL2 When LED drive
mode is selected
IOL2 = +10mA
VDD ≥ 4.5V ― ― 0.5
Output voltage 3
(P40–P41) VOL3 When I2C mode is
selected IOL3 = +3mA ― ― 0.4
V 2
IOOH VOH = VDD
(in high-impedance state) ― ― 1
Output leakage
current
(P20 to P23)
(P30 to P36)
(P40 to P47)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
(PE0 to PE7)
(PF0 to PF7)
IOOL VOL = VSS
(in high-impedance state) −1 ― ―
μA 3
VL3=3V、VOL=0.3V 15 40 ―
IOL1 VL3=5V、VOL=0.5V 100 200 ―
VL3=3V、VOH=2.7V ― -30 -15
Output current 1
COM0 to COM3
IOH1 VL3=5V、VOH=4.5V ― -90 -45
VL3=3V、VOL=0.3V 15 30 ―
IOL2 VL3=5V、VOL=0.5V 70 150 ―
VL3=3V、VOH=2.7V ― -13 -6
Output current 2
SEG0 to SEG39
IOH2 VL3=5V、VOH=4.5V ― -40 -20
μA 3
IIH1 VIH1 = VDD 0 ― 1
Input current 1
(RESET_N)
(TEST1_N) IIL1 VIL1 = VSS −1500 −300 −20
IIH2 VIH2 = VDD (when pulled down) 2 30 250
IIL2 VIL2 = VSS (when pulled up) −250 −30 −2
IIH2Z VIH2 = VDD
(in high-impedance state) ― ― 1
Input current 2
(NMI)
(P00 to P03)
(P10 to P11)
(P30 to P36)
(P40 to P47)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
(PE0 to PE7)
(PF0 to PF7)
IIL2Z VIL2 = VSS
(in high-impedance state) -1 ― ―
IIH3 VIH3 = VDD 20 300 1500
Input current 3
(TEST0) IIL3 VIL3 = VSS -1 ― ―
μA 4
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DC Characteristics (5 of 5)
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
Measuring
circuit
VIH1 ― 0.7×
VDD ― V
DD
Input voltage 1
(RESET_N)
(TEST0)
(TEST1_N)
(NMI)
(P00 to P03)
(P10 to P11)
(P30 to P36)
(P40 to P43)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
(PE0 to PE7)
(PF0 to PF7)
VIL1 ― 0 ― 0.3×
VDD
V 5
Input pin capacitance
(RESET_N)
(TEST0)
(TEST1_N)
(NMI)
(P00 to P03)
(P10 to P11)
(P30 to P36)
(P40 to P43)
(P50 to P53)
(PC0 to PC7)
(PD0 to PD7)
(PE0 to PE7)
(PF0 to PF7)
CIN
f = 10kHz
Vrms = 50mV
Ta = 25°C
― ― 10 pF ―
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Measuring Circuits
Measuring circuit 1
Measuring circuit 2
Input pins
V
VIH
VIL
Output pins
(*2)
(*1)
VDD V
REF VDDL VSS
VL1 VL2 VL3
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
A
VDD V
REF VDDL
CL
CV
V
VCc
Cb
Ca
32.768kHz
crystal
CGL
CDL
XT0
XT1
8MHz
crystal
CGH
CDH
OSC0
OSC1
VSS
V
CV ：10μF
CL ：10μF
CGL ：12pF
CDL ：12pF
CGH ：47pF
CDH ：47pF
CL1,C L2,C L3：0.22μF
32.768kHz Crystal oscillator
(DMX-26 DAISHINKU Corp.)
8MHz Crystal oscillator
CSTLS8M00G56（MURATA Corp.）
it has built-in CGH, and CDH
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Measuring circuit 3
Measuring circuit 4
Measuring circuit 5
VIH
VIL
*1: Input logic circuit to determine the specified measuring conditions.
VDD VREF VDDL VSS
Waveform monitoring
Output pins
Input pins
(*1)
A
*3: Measured at the specified input pins.
(注3)
VDD V
REF VDDL VSS
Output pins
Input pins
Input pins
A
VIH
VIL
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
(*2)
(*1)
VDD VREF
VDDL VSS
Output pins
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AC Characteristics (External Interrupt)
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
External interrupt disable
period TNUL Interrupt: Enabled (MIE = 1),
CPU: NOP operation
2.5×
sysclk ― 3.5×
sysclk μs
tNUL
P00–P03
(Rising-edge interrupt)
P00–P03
(Falling-edge interrupt)
NMI, P00–P03
(Both-edge interrupt) tNUL
tNUL
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AC Characteristics (Synchronous Serial Port)
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
High-speed oscillation stopped 10 ― ― μs
SCK input cycle
(slave mode) tSCYC During high-speed oscillation 500 ― ― ns
SCK output cycle
(master mode) tSCYC ― ― SCK(*1) ― sec
High-speed oscillation stopped 4 ― ― μs
SCK input pulse width
(slave mode) tSW During high-speed oscillation 200 ― ― ns
SCK output pulse width
(master mode) tSW ― SCK(*1)
×0.4
SCK(*1)
×0.5
SCK(*1)
×0.6 sec
SOUT output delay time
(slave mode) tSD ― ― ― 180 ns
SOUT output delay time
(master mode) tSD ― ― ― 80 ns
SIN input setup time
(slave mode) tSS ― 50 ― ― ns
SIN input hold time tSH ― 50 ― ― ns
*1: Clock period selected by SnCK3–0 of the serial port n mode register (SIOnMOD1)
tSD
SCKn*
SINn*
SOUTn
*: Indicates the secondary function of the corresponding port.
tSD
tSS tSH
tSW tSW
tSCYC
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AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kHz)
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Rating
Parameter Symbol Condition
Min. Typ. Max.
Unit
SCL clock frequency fSCL ⎯ 0 ⎯ 100 kHz
SCL hold time
(start/restart condition) tHD:STA ⎯ 4.0 ⎯ ⎯ μs
SCL ”L” level time tLOW ⎯ 4.7 ⎯ ⎯ μs
SCL ”H” level time tHIGH ⎯ 4.0 ⎯ ⎯ μs
SCL setup time
(restart condition) tSU:STA ⎯ 4.7 ⎯ ⎯ μs
SDA hold time tHD:DAT ⎯ 0 ⎯ ⎯ μs
SDA setup time tSU:DAT ⎯ 0.25 ⎯ ⎯ μs
SDA setup time
(stop condition) tSU:STO ⎯ 4.0 ⎯ ⎯ μs
Bus-free time tBUF ⎯ 4.7 ⎯ ⎯ μs
AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kHz)
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Rating
Parameter Symbol Condition
Min. Typ. Max.
Unit
SCL clock frequency fSCL ⎯ 0 ⎯ 400 kHz
SCL hold time
(start/restart condition) tHD:STA ⎯ 0.6 ⎯ ⎯ μs
SCL ”L” level time tLOW ⎯ 1.3 ⎯ ⎯ μs
SCL ”H” level time tHIGH ⎯ 0.6 ⎯ ⎯ μs
SCL setup time
(restart condition) tSU:STA ⎯ 0.6 ⎯ ⎯ μs
SDA hold time tHD:DAT ⎯ 0 ⎯ ⎯ μs
SDA setup time tSU:DAT ⎯ 0.1 ⎯ ⎯ μs
SDA setup time
(stop condition) tSU:STO ⎯ 0.6 ⎯ ⎯ μs
Bus-free time tBUF ⎯ 1.3 ⎯ ⎯ μs
P41/SCL
P40/SDA
Start
condition
Restart
condition Stop
condition
tBUF
tHD:STA t
LOW t
HIGH t
SU:STA tHD:STA tSU:DAT t
HD:DAT tSU:STO
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Electrical Characteristics of Successive Approximation Type A/D Converter
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +85°C, unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
Resolution n ― ― ― 10 bits
Integral non-linearity error IDL 2.7V ≤ VREF ≤ 5.5V −4 ― +4
Differential non-linearity
error DNL 2.7V ≤ VREF ≤ 5.5V −3 ― +3
Zero-scale error VOFF ― −4 ― +4
Full-scale error FSE ― −4 ― +4
LSB
Input impedance RI ― ― ― 5k Ω
Reference voltage VREF 4.5 ― V
DD V
Conversion time tCONV HSCLK=3.0M to 8.4MHz ― 102 ― φ/CH
φ: Period of high-speed clock (HSCLK)
A
VDD
VREF
VDDL
VSS
Analog input
10μF
- RI≤5kΩAIN0
～
AIN15
1μF
0.1μF
+
10μF
Reference
voltage
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PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact LAPIS SEMICONDUCTOR’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature
and times).
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REVISION HISTORY
Page
Document No. Date Previous
Edition
Current
Edition
Description
FEDL610Q178FULL-01 May 18, 2012 – – Formal edition 1
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NOTES
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS
Semiconductor Co., Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
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