Semiconductor Components Industries, LLC, 2002
April, 2002 – Rev. 7 1Publication Order Number:
SN74LS74A/D
SN74LS74A
Dual D-Type Positive
Edge-Triggered Flip-Flop
The SN74LS74A dual edge-triggered flip-flop utilizes Schottky
TTL circuitry to produce high speed D-type flip-flops. Each flip-flop
has individual clear and set inputs, and also complementary Q and Q
outputs.
Information at input D is transferred to the Q output on the
positive-going edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse and is not directly related to the
transition time of the positive-going pulse. When the clock input is at
either the HIGH or the LOW level, the D input signal has no effect.
MODE SELECT – TRUTH TABLE
OPERATING MODE
INPUTS OUTPUTS
OPERATING MODE SDCDD Q Q
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Load “0” (Reset)
L
H
L
H
H
H
L
L
H
H
X
X
X
h
l
H
L
H
H
L
L
H
H
L
H
* Both outputs will be HIGH while both SD and CD are LOW, but the output
states are unpredictable if SD and CD go HIGH simultaneously. If the levels
at the set and clear are near VIL maximum then we cannot guarantee to meet
the minimum level for VOH.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input
i, h (q) = (or output) one set-up time prior to the HIGH to LOW clock transition.
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient
Temperature Range 0 25 70 °C
IOH Output Current – High –0.4 mA
IOL Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
SOIC
D SUFFIX
CASE 751A
PLASTIC
N SUFFIX
CASE 646
14
1
14
1
SOEIAJ
M SUFFIX
CASE 965
14 1
Device Package Shipping
ORDERING INFORMATION
SN74LS74AN 14 Pin DIP 2000 Units/Box
SN74LS74AD SOIC–14 55 Units/Rail
SN74LS74ADR2 SOIC–14 2500/Tape & Reel
SN74LS74AM SOEIAJ–14 See Note 1
SN74LS74AMEL SOEIAJ–14
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
See Note 1
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SN74LS74A
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2
LOGIC DIAGRAM (Each Flip-Flop)
LOGIC SYMBOL
SET (SD)
4 (10)
CLEAR (CD)
1 (13)
CLOCK
3 (11)
D
2 (12)
Q
5 (9)
Q
6 (8)
VCC = PIN 14
GND = PIN 7
2
3
5
DQ
CP
Q
CD
1
4
6
12
11
9
DQ
CP
Q
CD
13
10
8
SDSD
SN74LS74A
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3
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage 0.8 VGuaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
V
Out
p
ut LOW Voltage
0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
V V or V
VOL Output LOW Voltage 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH
per Truth Table
I
IH
Input High Current
Data, Clock
Set, Clear 20
40 µA VCC = MAX, VIN = 2.7 V
IIH
Data, Clock
Set, Clear 0.1
0.2 mA VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
Data, Clock
Set, Clear –0.4
–0.8 mA VCC = MAX, VIN = 0.4 V
IOS Output Short Circuit Current (Note 2) –20 –100 mA VCC = MAX
ICC Power Supply Current 8.0 mA VCC = MAX
2. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
fMAX Maximum Clock Frequency 25 33 MHz Figure 1
t
PLH
Clock Clear Set to Output
13 25 ns
Figure 1
VCC = 5.0 V
CL=15
p
F
tPLH
tPHL Clock, Clear, Set to Output 25 40 ns Figure 1
C
L =
15
p
F
AC SETUP REQUIREMENTS (TA = 25°C)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tW(H) Clock 25 ns Figure 1
tW(L) Clear, Set 25 ns Figure 2
t
Data Setup Time — HIGH 20 ns
Figure 1
VCC = 5.0 V
ts
Data
Setu
Time
HIGH
Data Setup Time — LOW 20 ns Figure 1
CC
thHold Time 5.0 ns Figure 1
SN74LS74A
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4
Figure 1. Clock to Output Delays, Data
Set-Up and Hold Times, Clock Pulse Width
AC WAVEFORMS
*The shaded areas indicate when the input is permitted to change for predictable output performance.
D*
CP
Q
Q
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
1.3 V
tPLH
tPHL
tPLH
tPHL
th(L)
ts(L) tW(H) tW(L)
ts(H)
th(H)
1
fMAX
1.3 V
Figure 2. Set and Clear to Output Delays,
Set and Clear Pulse Widths
tW
1.3 V 1.3 V
tW
1.3 V 1.3 V
1.3 V
1.3 V1.3 V
1.3 V
tPLH tPHL
tPLH
tPHL
SET
CLEAR
Q
Q
SN74LS74A
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5
PACKAGE DIMENSIONS
17
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 18.80
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M--- 10 --- 10
N0.015 0.039 0.38 1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG DK
C
SEATING
PLANE
N
–T–
14 PL
M
0.13 (0.005)
L
M
J0.290 0.310 7.37 7.87
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE M
SN74LS74A
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6
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P7 PL
14 8
71 M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
–T–
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
SN74LS74A
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7
PACKAGE DIMENSIONS
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 1.42 --- 0.056
A1
HE
Q1
LE
10 0
10
LEQ1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.13 (0.005) M0.10 (0.004)
D
Z
E
1
14 8
7
eA
b
VIEW P
c
L
DETAIL P
M
A
b
c
D
E
e
0.50
M
Z
M SUFFIX
SOEIAJ PACKAGE
CASE 965–01
ISSUE O
SN74LS74A
http://onsemi.com
8
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For additional information, please contact your local
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SN74LS74A/D
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