ADS7800 SBAS001A - OCTOBER 1989 - REVISED FEBRUARY 2004 12-Bit 3s Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION 333k SAMPLES PER SECOND STANDARD 10V AND 5V INPUT RANGES DC PERFORMANCE OVER TEMP: No Missing Codes 1/2LSB Integral Linearity Error 3/4LSB Differential Linearity Error AC PERFORMANCE OVER TEMP: 72dB Signal-to-Noise Ratio 80dB Spurious-Free Dynamic Range -80dB Total Harmonic Distortion INTERNAL SAMPLE/HOLD, REFERENCE, CLOCK, AND THREE-STATE OUTPUTS POWER DISSIPATION: 215mW max PACKAGE: 24-Pin Single-Wide DIP 24-Lead SOIC The ADS7800 is a complete 12-bit sampling analog-todigital (A/D) converter using state-of-the-art CMOS structures. It contains a complete 12-bit successive approximation A/D converter with internal sample/hold, reference, clock, digital interface for microprocessor control, and three-state output drivers. The ADS7800 is specified at a 333kHz sampling rate. Conversion time is factory set for 2.70s max over temperature, and the high-speed sampling input stage insures a total acquisition and conversion time of 3s max over temperature. Precision, laser-trimmed scaling resistors provide industry-standard input ranges of 5V or 10V. AC and DC performance are completely specified. Two grades based on linearity and dynamic performance are available to provide the optimum price/performance fit in a wide range of applications. The 24-pin ADS7800 is available in plastic and sidebraze hermetic 0.3" wide DIPs, and in an SOIC package. It operates from a +5V supply and either a -12V or -15V supply. The ADS7800 is available in grades specified over 0C to +70C and -40C to +85C temperature ranges. Control Logic 10VIN Clock Output Latches And Three State Drivers CDAC 5VIN 2V Reference Out BUSY SAR Internal Ref Comparator Three State Parallel Output Data Bus Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright (c) 1989-2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com SPECIFICATIONS ELECTRICAL At TA = TMIN to TMAX, Sampling Frequency, fS, = 333kHz, -VS = -15V, VS = +5V, unless otherwise specified. ADS7800JP/JU/AH PARAMETER CONDITIONS MIN TYP RESOLUTION 10V Range 5V Range 4.4 2.9 10V/5V 6.3 4.2 333 2.5 2.6 380 Conversion Alone Acquisition + Conversion DC ACCURACY Full Scale Error (1) Full Scale Error Drift Integral Linearity Error Differential Linearity Error No Missing Codes Bipolar Zero(1) Bipolar Zero Drift Power Supply Sensitivity * * * * * * * 2.7 3.0 fIN1 fIN2 67 68 77 -74 -74 70 71 2.0 10 -0.3 +2.4 -5 +5 ISINK = 1.6mA ISOURCE = 500A 0.0 +2.4 0.1 -11.4 +4.75 V k k * * s s kHz 0.35 % ppm/C LSB(2) LSB 2 LSB ppm/C * * 1/2 LSB LSB LSB LSB * 69 70 13 150 130 150 1.9 * * * 0.1 77 -77 -77 Bits Ensured 1/2 1/2 1 74 UNITS * 1/2 3/4 1 fIN = 47kHz fIN = 47kHz = 24.4kHz (-6dB) = 28.5kHz (-6dB) fIN = 47kHz fIN = 47kHz MAX * 4 DIGITAL INPUTS Logic Levels VIL VIH IIL IIH 2 * * Ensured INTERNAL REFERENCE VOLTAGE Voltage Source Current Available for External Loads POWER SUPPLIES Rated Voltage -VS VS (VSA and VSD) Current -IS IS Power Consumption 8.1 5.4 1 1 SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response (5) Overvoltage Recovery (6) DIGITAL OUTPUTS Data Format Data Coding VOL VOH ILEAKAGE (High-Z State) TYP 0.50 Transition Noise(3) Signal-to-(Noise + Distortion) Ratio Signal-to-Noise Ratio (SNR) MIN 6 -16.5V < -VS < -13.5V -12.6V < -VS < -11.4V +4.75V < VS < +5.25V AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Two-tone Intermodulation Distortion MAX 12 ANALOG INPUT Voltage Ranges Impedance THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate ADS7800KP/KU/BH 2.1 * +0.8 +5.3 * * * * Parallel, 12-bit or 8-bit/4-bit Binary Offset Binary +0.4 * +5.0 * 5 -15 +5.0 -16.5 +5.25 3.5 18 135 6 25 215 * * 80 -80 -80 -77 -77 dB (4) dB dB 72 73 dB dB * * * * ns ps, rms ns ns * * * V A * * V V A A * * * * V V A * * * * V V * * * * * * mA mA mW ADS7800 www.ti.com SBAS001A SPECIFICATIONS (CONT) ELECTRICAL At TA = TMIN to TMAX, Sampling Frequency, fS, = 333kHz, -VS = -15V, VS = +5V, unless otherwise specified. ADS7800JP/JU/AH PARAMETER TEMPERATURE RANGE Specification Operating Storage CONDITIONS MIN JP/JU/KP/KU AH/BH JP/KP/JU/KU 0 -40 -40 -65 TYP ADS7800KP/KU/BH MAX MIN +70 +85 +85 +150 * * * * TYP MAX UNITS * * * * C C C C * Same as specification for ADS7800JP/JU/AH. NOTES: (1) Adjustable to zero with external potentiometer. (2) LSB means Least Significant Bit. For ADS7800, 1LSB = 2.44mV for the 5V range, 1LSB = 4.88mV for the 10V range. (3) Noise was characterized over temperature near full scale, 0V, and negative full scale. 0.1LSB represents a typical rms level of noise at the worst case, which was near full scale input at +125C. (4) All specifications in dB are referred to a full-scale input, either 10V or 5V. (5) For full scale step input, 12-bit accuracy attained in specified time. (6) Recovers to specified performance in specified time after 2 x FS input overvoltage. ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS -VS to ANALOG COMMON ............................................................ -16.5V VS to DIGITAL COMMON .................................................................... +7V Pin 23 (VSD ) to Pin 24 (VSA ) ........................................................... 0.3V ANALOG COMMON to DIGITAL COMMON ....................................... 1V Control Inputs to DIGITAL COMMON ............................. -0.3 to VS + 0.3V Analog Input Voltage .......................................................................... 20V Maximum Junction Temperature ..................................................... 160C Internal Power Dissipation ............................................................. 750mW Lead Temperature (soldering, 10s) ............................................... +300C Thermal Resistance, JA: Plastic DIP ................................................................................ 100C/W SOIC ......................................................................................... 100C/W Ceramic ...................................................................................... 50C/W The ADS7800 is an ESD (electrostatic discharge) sensitive device. The digital control inputs have a special FET structure, which turns on when the input exceeds the supply by 18V, to minimize ESD damage. However, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. When not in use, devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. ADS7800 SBAS001A www.ti.com 3 PIN ASSIGNMENTS PIN # NAME 1 4 PIN CONFIGURATION Top View DESCRIPTION IN1 10V Analog Input. Connected to GND for 5V range. DIP/SOIC 2 IN2 5V Analog Input. Connected to GND for 10V range. 3 REF +2V Reference Output. Bypass to GND with 22F to 47F Tantalum. Buffer for external loads. IN1 1 24 VSA 4 AGND Analog Ground. Connect to pin 13. IN2 2 23 VSD 5 D11 Data Bit 11. Most Significant Bit (MSB). 6 D10 Data Bit 10. REF 3 22 -VS 7 D9 Data Bit 9. AGND 4 21 BUSY 8 D8 Data Bit 8. 9 D7 Data Bit 7 if HBE is LOW; LOW if HBE is HIGH. D11 5 20 CS 10 D6 Data Bit 6 if HBE is LOW; LOW if HBE is HIGH. D10 6 19 R/C 11 D5 Data Bit 5 if HBE is LOW; LOW if HBE is HIGH. D9 7 18 HBE 12 D4 Data Bit 4 if HBE is LOW; LOW if HBE is HIGH. 13 DGND Digital Ground. Connect to pin 4. D8 8 17 D0 14 D3 Data Bit 3 if HBE is LOW; Data Bit 11 if HBE is HIGH. D7 9 16 D1 15 D2 Data Bit 2 if HBE is LOW; Data Bit 10 if HBE is HIGH. 16 D1 Data Bit 1 if HBE is LOW; Data Bit 9 if HBE is HIGH. D6 10 15 D2 D5 11 14 D3 D4 12 13 DGND 17 D0 Data Bit 0 if HBE is LOW. Least Significant Bit (LSB); Data Bit 8 if HBE is HIGH. 18 HBE High Byte Enable. When held LOW, data output as 12 bits in parallel. When held HIGH, four MSBs presented on pins 14-17, pins 9-12 output LOWs. Must be LOW to initiate conversion. 19 R/C Read/Convert. Falling edge initiates conversion when CS is LOW, HBE is LOW, and BUSY is HIGH. 20 CS Chip Select. Outputs in Hi-Z state when HIGH. Must be LOW to initiate conversion or read data. 21 BUSY Busy. Output LOW during conversion. Data valid on rising edge in Convert Mode. 22 -VS Negative Power Supply. -12V or -15V. Bypass to GND. 23 VSD Positive Digital Power Supply. +5V. Connect to pin 24, and bypass to GND. 24 VSA Positive Analog Power Supply. +5V. Connect to pin 23, and bypass to GND. ADS7800 www.ti.com SBAS001A TYPICAL PERFORMANCE CURVES At +VS = +5V, -VS = -15V, and TA = +25C, unless otherwise noted. All plots use 1024 point FFTs. FREQUENCY SPECTRUM (10kHz fIN ) FREQUENCY SPECTRUM (50kHz fIN ) 0 0 fIN = 10kHz fSAMPLING = 330kHz TA = 25C fIN = 50kHz fSAMPLING = 330kHz TA = 25C -20 Magnitude (dB) Magnitude (dB) -20 -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 50 0 100 Frequency (kHz) 150 165 0 SIGNAL/(NOISE + DISTORTION) vs INPUT FREQUENCY AND AMBIENT TEMPERATURE 150 165 Spurious Free Dynamic Range (dB) 95 -55C 70 C 5 +2 +1 25 C Signal/(Noise + Distortion) (dB) 100 Frequency (kHz) SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY AND AMBIENT TEMPERATURE 75 65 90 85 -5 5C +2 5 +1 C 25 C 80 75 70 65 1 10 50 150 1 10 50 150 Input Frequency (kHz) Input Frequency (kHz) SIGNAL/(NOISE + DISTORTION) vs FREQUENCY AND AMPLITUDE SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY AND NEGATIVE SUPPLY VOLTAGE 95 Spurious Free Dynamic Range (dB) 80 Signal/(Noise + Distortion) (dB) 50 0dB 60 -20dB 40 -40dB 20 -60dB 90 -V S = -15V -V S = -12V 85 80 75 70 65 0 1 10 50 150 ADS7800 SBAS001A 1 10 50 150 Input Frequency (kHz) Input Frequency (kHz) www.ti.com 5 THEORY OF OPERATION +5V The ADS7800 combines the advantages of advanced CMOS technology (logic density, stable capacitors, and good analog switches) with Burr-Brown's proven skills in lasertrimmed thin-film resistors to provide a complete sampling A/D converter. 47F A basic charge-redistribution successive approximation architecture converts analog input voltages into digital words. Figure 1 shows the operation of a simplified 3-bit charge redistribution A/D. Precision laser-trimmed scaling resistors at the input divide standard input ranges (10V or 5V for the ADS7800) into levels compatible with the CMOS characteristics of the internal capacitor array. While in the sampling mode, the capacitor array switch for the MSB capacitor (S1) is in position "S", so that the charge on the MSB capacitor is proportional to the voltage level of the analog input signal, and the remaining array switches (S2 and S3) are set to position "R" to provide an accurate bipolar offset from the reference source REF. At the same time, switch SC is also in the closed position to auto-zero any offset errors in the CMOS comparator. When a convert command is received, switch S1 is opened to trap a charge on the MSB capacitor proportional to the input level at the time of the sampling command, switches S2 and S3 are opened to trap an offset charge, and switch SC is opened to float the comparator input. The charge trapped on the capacitor array can now be moved between the three capacitors in the array by connecting switches S1, S2 and S3 to positions "R" (to connect to REF) or "G" (to connect to GND) successively, changing the voltage generated at the comparator input node. The first approximation connects the MSB capacitor via switch S1 to REF, while switches S2 and S3 are connected to GND. Depending on whether the comparator output is HIGH or LOW, the logic will then latch S1 in position "R" or "G", and moves on to make the next approximation by connecting S2 to REF and S3 to GND. When the three successive approximation steps are made for this simple converter, the voltage level at the comparator will be within 1/2LSB of GND, and the data output word will be based on reading the positions of S1, S2 and S3. Signal Comparator SC Input 4C S 2C S1 C S2 S3 To Switches R G R G R G + Ref - FIGURE 1. 3-Bit Charge Redistribution A/D. 6 L o g i c Out 1 IN 1 +5V 24 2 IN 2 +5V 23 3 REF -15V 22 4 AGND BUSY 21 5 D11 (MSB) CS 20 6 D10 R/C 19 7 D9 HBE 18 8 D8 D0 (LSB) 17 9 D7 D1 16 10 D6 D2 15 11 D5 D3 14 12 D4 DGND 13 Input + + 6.8F 1F + 0.1F -15V Busy D11 (MSB) Convert Command D0 (LSB) Data Out FIGURE 2. Basic 10V Operation. OPERATION BASIC OPERATION Figure 2 shows the simple hookup circuit required to operate the ADS7800 in a 10V range in the Convert Mode. A convert command arriving on pin 19, R/C, (a pulse taking pin 19 LOW for a minimum of 40ns) puts the ADS7800 in the hold mode, and a conversion is started. Pin 21, BUSY, will be held LOW during the conversion, and rises only after the conversion is completed and the data has been transferred to the output latches. Thus, the rising edge of the signal on pin 21 can be used to read the data from the conversion. Also, during conversion, the BUSY signal puts the output data lines in Hi-Z states and inhibits input lines. This means that pulses on pin 19 are ignored, so that new conversions cannot be initiated during a conversion, either as a result of spurious signals or to short-cycle the ADS7800. In the Read Mode, the input to pin 19 is kept normally LOW, and a HIGH pulse is used to read data and initiate a conversion. In this mode, the rising edge of R/C on pin 19 will enable the output data pins, and the data from the previous conversion becomes valid. The falling edge then puts the ADS7800 in a hold mode, and initiates a new conversion. The ADS7800 will begin acquiring a new sample as soon as the conversion is completed, even before the BUSY output rises on pin 21, and will track the input signal until the next conversion is started, whether in the Convert Mode or the Read Mode. ADS7800 www.ti.com SBAS001A R/C tB BUSY tDBC tC Converter Acquisition Mode tAP Conversion Acquisition Conversion FIGURE 3. Acquisition and Conversion Timing. PARAMETER tDBC tB tAP tAP tC BUSY delay from R/C BUSY Low Aperture Delay Aperture Jitter Conversion Time R/C 1 0 0 X 10 1 HBE BUSY X 0 0 1 1 1 0 0 0 X 1 10 0 X 1 1 1 X 1 1 1 0 OPERATION None - Outputs in Hi-Z State. Holds Signal and Initiates Conversion. Output Three-State Buffers Enabled once Conversion has Finished. Enable Hi-Byte in 8-bit Bus Mode. Inhibit Start of Conversion. None - Outputs in Hi-Z State. Conversion in Progress. Outputs Hi-Z State. New Conversion Inhibited until Present Conversion has Finished. TABLE II. Control Line Functions. Hold Time SYMBOL CS MIN TYP MAX UNITS 80 2.5 13 150 2.47 150 2.7 ns s ns ps, rms s 2.70 For stand-alone operation, control of the ADS7800 is accomplished by a single control line connected to R/C. In this mode, CS and HBE are connected to GND. The output data are presented as 12-bit words. The stand-alone mode is used in systems containing dedicated input ports which do not require full bus interface capability. TABLE I. Acquisition and Conversion Timing. For use with an 8-bit bus, the data can be read out in two bytes under the control of pin 18, HBE. With a LOW input on pin 18, at the end of a conversion, the 8 LSBs of data are loaded into the latches on pins 9 through 12 and 14 through 17. Taking pin 18 HIGH then loads the 4 MSBs on pins 14 through 17, with pins 9 through 12 being forced LOW. ANALOG INPUT RANGES The ADS7800 offers two standard bipolar input ranges: 10V and 5V. If a 10V range is required, the analog input signal should be connected to pin 1. A signal requiring a 5V range should be connected to pin 2. In either case, the other pin of the two must be grounded or connected to the adjustment circuits described in the section on calibration. (See Figures 4 and 5, or 10 and 11.) Conversion is initiated by a HIGH-to-LOW transition on R/C. The three-state data output buffers are enabled when R/C is HIGH and BUSY is HIGH. Thus, there are two possible modes of operation: conversion can be initiated with either positive or negative pulses. In either case, the R/C pulse must remain LOW a minimum of 40ns. Figure 6 illustrates timing when conversion is initiated by an R/C pulse which goes LOW and returns HIGH during the conversion. In this case (Convert Mode), the three-state outputs go into the Hi-Z state in response to the falling edge of R/C, and are enabled for external access of the data after completion of the conversion. Figure 7 illustrates the timing when conversion is initiated by a positive R/C pulse. In this mode (Read Mode), the output data from the previous conversion is enabled during the HIGH portion of R/C. A new conversion starts on the falling edge of R/C, and the three-state outputs return to the Hi-Z state until the next occurrence of a HIGH on R/C. CONVERSION START CONTROLLING THE ADS7800 The ADS7800 can be easily interfaced to most microprocessor-based and other digital systems. The microprocessor may take full control of each conversion, or the ADS7800 may operate in a stand-alone mode, controlled only by the R/C input. Full control consists of initiating the conversion and reading the output data at user command, transmitting data either all 12-bits in one parallel word, or in two 8-bit bytes. The three control inputs (CS, R/C and HBE) are all TTL/CMOS compatible. The functions of the control lines are shown in Table II. A conversion is initiated on the ADS7800 only by a negative transition occurring on R/C, as shown in Table I. No other combination of states or transitions will initiate a conversion. Conversion is inhibited if either CS or HBE are HIGH, or if BUSY is LOW. CS and HBE should be stable a minimum of 25ns prior to the transition on R/C. Timing relationships for start of conversion are illustrated in Figure 8. The BUSY output indicates the current state of the converter by being LOW only during conversion. During this time the three-state output buffers remain in a Hi-Z state, and therefore data cannot be read during conversion. During this period, additional transitions on the three digital inputs (CS, R/C and HBE) will be ignored, so that conversion cannot be prematurely terminated or restarted. ADS7800 SBAS001A www.ti.com 7 INTERNAL CLOCK The ADS7800 has an internal clock that is factory trimmed to achieve a typical conversion time of 2.47s, and a maximum conversion time over the full operating temperature range of 2.7s. No external adjustments are required, and with the guaranteed maximum acquisition time of 300ns, throughput performance is assured with convert pulses as close as 3s. 1 ADS7800 5V Input 2 FIGURE 5. 5V Range Without Trims. READING DATA After conversion is initiated, the output buffers remain in a Hi-Z state until the following three logic conditions are simultaneously met: R/C is HIGH, BUSY is HIGH and CS is LOW. Upon satisfaction of these conditions, the data lines are enabled according to the state of HBE. See Figure 9 and Table III for timing relationships and specifications. CALIBRATION PROCEDURE First, trim offset, by applying at the input (pin 1 or 2) the mid-point transition voltage (-2.44mV for the 10V range, -1.22mV for the 5V range.) With the ADS7800 converting continually, adjust potentiometer R1 until the MSB (D11 on pin 5) is toggling alternately HIGH and LOW. CALIBRATION Next adjust full scale, by applying at the input a DC input signal that is 3/2LSB below the nominal full scale voltage (+9.9927V for the 10V range, +4.9963V for the 5V range.) With the ADS7800 converting continually, adjust R2 until the LSB (D0 on pin 17) is toggling HIGH and LOW with all of the other bits HIGH. OPTIONAL EXTERNAL GAIN AND OFFSET TRIM Offset and full-scale errors may be trimmed to zero using external offset and full-scale trim potentiometers connected to the ADS7800 as shown in Figures 10 and 11. LAYOUT CONSIDERATIONS If adjustment of offset and full scale is not required, connections as shown in Figures 4 and 5 should be used. 10V Input Because of the high resolution and linearity of the ADS7800, system design problems such as ground path resistance and contact resistance become very important. ANALOG SIGNAL SOURCE IMPEDANCE The input resistance of the ADS7800 is 6.3k or 4.2k (for the 10V and 5V ranges respectively.) To avoid introducing distortion, the source resistance must be very low, or constant with signal level. The output impedance provided by most op amps is ideal. 1 ADS7800 2 Pins 23 (VSD ) and 24 (VSA ) are not connected internally on the ADS7800, to maximize accuracy on the chip. They should be connected together as close as possible to the unit. FIGURE 4. 10V Range Without Trims. tW R/C tB BUSY tDBC tAP Converter Mode Acquire tDBE Convert Acquire tC tA tDB tHDR and tHL Data BUS Data Valid Convert Hi-Z State Data Valid Hi-Z State FIGURE 6. Convert Mode: R/C Pulse LOW -- Outputs Enabled After Conversion. 8 ADS7800 www.ti.com SBAS001A R/C tW tB BUSY tDBC tAP Converter Mode Acquire tDBE tAP Convert Acquire tC tA tDD Convert tHDR and tHL Data BUS Hi-Z State Data Valid Hi-Z State Data Valid Hi-Z State FIGURE 7. Read Mode: R/C Pulse HIGH-- Outputs Enabled Only When R/C is High. SYMBOL tW tDBC PARAMETER MIN TYP R/C Pulse Width 40 10 MAX UNITS ns BUSY delay from R/C 80 150 ns tB BUSY LOW 2.5 2.7 s tAP Aperture Delay 13 ns tAP Aperture Jitter 150 ps, rms tC 2.70 s 75 200 ns Conversion Time 2.47 tDBE BUSY from End of Conversion 100 tDB BUSY Delay after Data Valid 25 ns tA Acquisition Time 130 300 ns tA+tC Throughput Time 2.6 3.0 s tHDR tS Valid Data Held After R/C LOW 20 50 ns CS or HBE LOW before R/C Falls 25 5 ns 25 tH CS or HBE LOW after R/C Falls tDD Data Valid from CS LOW, R/C HIGH, and HBE in Desired State (Load = 100pF) tHDR Valid Data Held After R/C Low tHL 20 Delay to Hi-Z State after R/C Falls or CS Rises (3k Pullup or Pulldown) 0 65 ns 150 50 50 ns ns 150 ns TABLE III. Timing Specifications (TMIN to TMAX). tS CS or HBE tH To limit the effects of digital switching elsewhere in a system on the analog performance of the system, it often makes sense to run a separate +5V supply conductor from the supply regulator to any analog components requiring +5V, including the ADS7800. tW R/C tDBC BUSY Data Bus Pin 24 may be slightly more sensitive than pin 23 to supply variations, but to maintain maximum system accuracy, both should be well isolated from digital supplies with wide load variations. Data Valid Hi-Z State tHDR and tHL FIGURE 8. Conversion Start Timing. The VS pins (23 and 24) should be connected together and bypassed with a parallel combination of a 6.8F tantalum capacitor and a 0.1F ceramic capacitor located close to the converter to obtain noise-free operation. (See Figure 2.) The -VS pin 22 should be bypassed with a 1F tantalum capacitor, again as close as possible to the ADS7800. Noise on the power supply lines can degrade converter performance, especially noise and spikes from a switching power supply. Appropriate supplies or filters must be used. The GND pins (4 and 13) are also separated internally, and should be directly connected to a ground plane under the ADS7800 SBAS001A www.ti.com 9 converter if at all possible. A ground plane is usually the best solution for preserving dynamic performance and reducing noise coupling into sensitive converter circuits. Where any compromises must be made, the common return of the analog input signal should be referenced to pin 4, AGND, on the ADS7800, which prevents any voltage drops that might occur in the power supply common returns from appearing in series with the input signal. Coupling between analog input and digital lines should be minimized by careful layout. For instance, if the lines must cross, they should do so at right angles. Parallel analog and digital lines should be separated from each other by a pattern connected to common. If external full scale and offset potentiometers are used, the potentiometers and related resistors should be located as close to the ADS7800 as possible. CS R/C HBE BUSY tDB DB11-DB0 Data Valid tDD tHL & tHDR FIGURE 9. Read Cycle Timing. REFERENCE BYPASS Pin 3 (REF) should be bypassed with a 22F to 47F tantalum capacitor. A rated working voltage of 2V or more is acceptable here. This pin is used to enhance the system accuracy of the internal reference circuit, and is not recommended for driving external signals. If there are important system reasons for using the ADS7800 reference externally, the output of pin 3 must be appropriately buffered. "HOT SOCKET" PRECAUTION Two separate +5V VS pins, 23 and 24, are used to minimize noise caused by digital transients. If one pin is powered and the other is not, the ADS7800 may "Latch Up" and draw excessive current. In normal operation, this is not a problem because both pins will be soldered together. However, during evaluation, incoming inspection, repair, etc., where the potential of a "Hot Socket" exists, care should be taken to power the ADS7800 only after it has been socketed. 10 External Gain Adjust 10V Input R2 1 ADS7800 100 2 3 +5V Bipolar Zero Adjust R1 4 10k 10k 49.9 6.65k 5 6 -15V 7 FIGURE 10. 10V Range With External Trims. MINIMIZING "GLITCHES" Coupling of external transients into an A/D converter can cause errors which are difficult to debug. In addition to the discussions earlier on layout considerations for supplies, bypassing and grounding, there are several other useful steps that can be taken to get the best analog performance out of a system using the ADS7800. These potential system problem sources are particularly important to consider when developing a new system, and looking for the causes of errors in breadboards. First, care should be taken to avoid glitches during critical times in the sampling and conversion process. Since the ADS7800 has an internal sample/hold function, the signal that puts it into the hold state (R/C going LOW) is critical, as it would be on any sample/hold amplifier. The R/C falling edge should be sharp and have minimal ringing, especially during the 20ns after it falls. Although not normally required, it is also good practice to avoid glitching the ADS7800 while bit decisions are being made. Since the above discussion calls for a fast, clean rise and fall on R/C, it makes sense to keep the rising edge of the convert pulse outside the time when bit decisions are being made. In other words, the convert pulse should either be short (under 100ns so that it transitions before the MSB decision), or relatively long (over 2.75s to transition after the LSB decision). External Gain Adjust 5V Input 1 R2 2 100 3 +5V Bipolar Zero Adjust 4 R1 10k 10k ADS7800 5 30.1k 301 6 7 -15V FIGURE 11. 5V Range With External Trims. ADS7800 www.ti.com SBAS001A Next, although the data outputs are forced into a Hi-Z state during conversion, fast bus transients can still be capacitively coupled into the ADS7800. If the data bus experiences fast transients during conversion, these transients can be attenuated by adding a logic buffer to the data outputs. The BUSY output can be used to enable the buffer. Naturally, transients on the analog input signal are to be avoided, especially at times within 20ns of R/C going LOW, when they may be trapped as part of the charge on the capacitor array. This requires careful layout of the circuit in front of the ADS7800. Finally, in multiplexed systems, the timing on when the multiplexer is switched may affect the analog performance of the system. In most applications, the multiplexer can be switched as soon as R/C goes LOW (with appropriate delays), but this may affect the conversion if the switched signal shows glitches or significant ringing at the ADS7800 input. Whenever possible, it is safer to wait until the conversion is completed before switching the multiplexer. The extremely fast acquisition time and conversion time of the ADS7800 make this practical in many applications. INPUT VOLTAGE RANGE AND LSB VALUES Input Voltage Range Defined As: Analog Input Connected to Pin Pin Connected to GND One Least Significant Bit (LSB) FSR/212 10V 1 2 20V/212 5V 2 1 10V/212 4.88mV 2.44mV +10V-3/2LSB +9.9927V 0V-1/2LSB -2.44mV -10V+1/2LSB -9.9976V +5V-3/2LSB +4.9963V 0V-1/2LSB -1.22mV -5V+1/2LSB -4.9988V OUTPUT TRANSITION VALUES FFEH to FFFH +Full Scale 7FFH to 800H Mid Scale (Bipolar Zero) -Full Scale 000H to 001H TABLE IV. Input Voltages, Transition Values, and LSB Values. ADS7800 SBAS001A www.ti.com 11 PACKAGE OPTION ADDENDUM www.ti.com 26-Dec-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty JDN 24 1 Green (RoHS & no Sb/Br) AU TBD Call TI 1 Green (RoHS & no Sb/Br) AU Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) (Requires Login) ADS7800AH NRND CDIP SB ADS7800AH-BI OBSOLETE CDIP SB JD 24 ADS7800BH NRND CDIP SB JDN 24 ADS7800BH-BI OBSOLETE CDIP SB JD 24 ADS7800JP ACTIVE PDIP NT 24 15 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type ADS7800JPG4 ACTIVE PDIP NT 24 15 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type ADS7800JU ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7800JU/1K ACTIVE SOIC DW 24 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7800JU/1KE4 ACTIVE SOIC DW 24 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7800JU/1KG4 ACTIVE SOIC DW 24 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7800JUE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7800KP ACTIVE PDIP NT 24 15 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type ADS7800KPG4 ACTIVE PDIP NT 24 15 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type ADS7800KU ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7800KUE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TBD (1) Call TI N / A for Pkg Type Call TI N / A for Pkg Type Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 26-Dec-2011 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS7800JU/1K Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 10.85 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.8 2.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7800JU/1K SOIC DW 24 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MCDI046 - JANUARY 2002 JDN (R-CDIP-T24) CERAMIC SIDE-BRAZE DUAL-IN-LINE 1.212 (30,78) 1.188 (30,18) 24 13 0.310 (7,87) 0.280 (7,11) Index Area 1 12 0.060 (1,52) 0.038 (0,97) 0.010 (0,25) MIN 0.175 (4,45) 0.105 (2,67) E 0.325 (8,26) 0.290 (7,37) Base Plane Seating Plane D 0.065 (1,65) 0.030 (0,76) 0.021 (0,53) E 0.015 (0,38) E 0.055 (1,40) 0.025 (0,64) 0.100 (2,54) TYP 0- 15 0.175 (4,45) 0.125 (3,18) 0.012 (0,30) 0.008 (0,20) 0.300 (7,62) TYP 4204038/A 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Leads within 0.005 (0.13) radius of true position (TP) at gage plane with maximum material condition and unit installed. D. The Package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected ground leads. E. Outlines on which the seating plane is coincident with the plane (standoff = 0), terminal lead standoffs are not required, and lead shoulder may equal lead width along any part of the lead above the seating/base plane. F. A visual index feature must be located within the cross-hatched area. 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