LTC3887/LTC3887-1/
LTC3887-2
1
Rev. F
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n PMBus/I2C Compliant Serial Interface
n
Telemetry Read Back includes VIN, IIN, VOUT, IOUT,
Temperature, Duty Cycle and Faults
n Programmable Voltage, Current Limit, Digital
Soft-Start/Stop, Sequencing, Margining, OV/UV
and Frequency Synchronization (250kHz to 1MHz)
n ±0.5% Output Voltage Accuracy Over Temperature
n Integrated 16-Bit ADC
n VOUT Range: 0.5V to 5.5V (VOUT0, VOUT1)
n Internal EEPROM and Fault Logging with ECC
n Integrated N-Channel MOSFET Gate Drivers (LTC3887)
n Minimum On-Time 45ns
n Wide VIN Range: 4.5V to 24V
n Analog Current Mode Control Loop
n Remote Differential Sense for PolyPhase
®
Applications
n Accurate PolyPhase Current Sharing for Up to Six Phases
n Available in a 40-Pin (6mm × 6mm) QFN Package
n AEC-Q100 Qualified for Automotive Applications
TYPICAL APPLICATION
DESCRIPTION
Dual Output PolyPhase Step-Down DC/DC Controller
with Digital Power System Management
The LTC
®
3887/LTC3887-1/LTC3887-2 are dual,
PolyPhase DC/DC synchronous step-down switching
regulator controllers with an I2C-based PMBus compli-
ant serial interface. The controllers use a constant fre-
quency, current mode architecture that is supported by
LTpowerPlay
®
a software development tool with graphical
user interface(GUI).
Switching frequency, channel phasing, output voltage,
and device address can be programmed using external
configuration resistors. Additionally, parameters can be
set via the digital interface or stored in EEPROM. Voltage,
current, internal/external temperature and fault status can
be read back through the bus interface.
The LTC3887 has integrated gate drivers. The LTC3887-1
has three-state PWM pins to drive DrMOS power stages.
The LTC3887-2 has gate drivers and no LDO and supports
V
IN
up to 34V. The LTC3887 is an enhanced version of
the LTC3880 with greater output voltage range and more
digital features. Refer to Operation section for more detail.
FEATURES
APPLICATIONS
n High Current Distributed Power Systems
n Telecom, Datacom and Storage Systems
n Intelligent Energy Efficient Power Regulation
Regulated Output Voltage vs
Temperature, VOUT = 0.5V
Dual 350kHz 3.3V/0.5V Step-Down Converter
TEMPERATURE (°C)
–50
–0.5
VOUT ERROR (%)
–0.4
0.1
0
–0.1
–0.2
–0.3
0.2
0.3
0.4
0.5
–30 –10 10 30 50 70 90
3887 TA01b
110
VIN
TG0
0.1µF 0.1µF
1µF
10nF
4.99k
PMBus
INTERFACE
TO/FROM
OTHER LTC DEVICES
WRITE PROTECT
2200pF 2200pF
FAULT MANAGEMENT
*SOME DETAILS OMITTED
FOR CLARITY
10µF
2k
V
OUT1
3.3V
20A
6.04k
10nF 530µF
1.58k
0.22µF
0.22µF
1µH
0.56µH
TG1
BG0 BG1
BOOST0 BOOST1
SW0 SW1
INTVCC
LTC3887
TSNS0 TSNS1
ITHO
SHARE_CLK
WP GND
SDA
SCL
ALERT
RUN0
RUN1
GPIO0
GPIO1
VDD33
VDD25
ITH1
ISENSEO+ISENSE1+
VSENSEO+VSENSE1
VSENSEO–
ISENSEO–ISENSE1–
V
OUT0
0.5V
20A
V
IN
6V TO 16V
1µF 1µF
3887 TA01a
+
530µF
+
SYNC
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 5408150,
7420359. Licensed under U.S. Patent 7000125 and other related patents worldwide.
LTC3887/LTC3887-1/
LTC3887-2
2
Rev.F
For more information www.analog.com
TABLE OF CONTENTS
Features ..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Table of Contents .......................................... 2
Absolute Maximum Ratings .............................. 4
Pin Configuration .......................................... 4
Order Information .......................................... 5
Electrical Characteristics ................................. 6
Typical Performance Characteristics .................. 10
Pin Functions .............................................. 13
Block Diagram ............................................. 15
Operation................................................... 16
Overview ................................................................. 16
Main Control Loop .................................................. 17
EEPROM (NVM) ...................................................... 17
Power Up and Initialization ..................................... 18
Soft-Start ................................................................ 18
Sequencing ............................................................. 19
EVENT-Based Sequencing ...................................... 19
Shutdown ...............................................................20
Light Load Current Operation .................................20
Switching Frequency and Phase .............................21
Output Voltage Sensing ..........................................21
Current Sensing ...................................................... 21
PolyPhase Load Sharing ......................................... 22
External/Internal Temperature Sense ......................22
RCONFIG (Resistor Configuration) Pins ..................23
Fault Detection and Handling .................................. 24
Internal EEPROM with CRC Protection
and ECC ..............................................................25
Serial Interface .......................................................25
Communication Protection ................................25
Device Addressing .................................................. 25
Responses to VOUT and IOUT Faults ........................26
Output Overvoltage Fault Response ...................26
Output Undervoltage Response .........................26
Peak Output Overcurrent Fault Response ........... 27
Responses to Timing Faults ....................................27
Responses to VIN OV Faults ....................................27
Responses to OT/UT Faults .....................................27
Internal Overtemperature Fault/Warn
Response ...........................................................27
External Overtemperature and Undertemperature
Fault Response ................................................... 27
Responses to External Faults .................................28
Fault Logging .......................................................... 28
Bus Timeout Protection ..........................................28
Similarity Between PMBus, SMBus and I2C
2-Wire Interface ...................................................... 28
PMBus Serial Digital Interface ................................29
PMBus
Command Summary ............................ 34
PMBus
Commands ................................................. 34
*Data Format ..........................................................39
Applications Information ................................ 40
Current Limit Programming ....................................40
ISENSE+ and ISENSE– Pins .........................................40
Low Value Resistor Current Sensing ....................... 41
Inductor DCR Current Sensing ................................42
Slope Compensation and Inductor Peak Current ....43
Inductor Value Calculation ......................................43
Inductor Core Selection ..........................................44
Power MOSFET and Schottky Diode (Optional)
Selection ................................................................. 44
Variable Delay Time, Soft-Start and Output Voltage
Ramping .................................................................45
Digital Servo Mode .................................................46
Soft Off (Sequenced Off) ........................................ 46
INTVCC Regulator .................................................... 47
Topside MOSFET Driver Supply (CB, DB) (LTC3887,
LTC3887-2) ............................................................. 47
Undervoltage Lockout .............................................48
CIN and COUT Selection ...........................................48
Fault Conditions ......................................................49
Open-Drain Pins .....................................................49
Phase-Locked Loop and Frequency Synchronization 50
Minimum On-Time Considerations.......................... 51
LTC3887/LTC3887-1/
LTC3887-2
3
Rev. F
For more information www.analog.com
TABLE OF CONTENTS
RCONFIG (External Resistor
Configuration Pins) ................................................. 51
Voltage Selection ................................................ 51
Frequency and Phase Selection
Using RCONFIG .................................................52
Address Selection Using RCONFIG .....................53
Efficiency Considerations .......................................53
Checking Transient Response ................................. 54
PC Board Layout Checklist .....................................55
PC Board Layout Debugging ...................................57
Design Example ......................................................58
Additional Design Checks .......................................60
Connecting the USB to the I2C/SMBus/PMBus
Controller to the LTC3887 In System ......................60
LTpowerPlay: An Interactive GUI for
Digital Power ..........................................................62
PMBus Communication and Command
Processing ..............................................................62
PMBus
Command Details ............................... 64
Addressing and Write Protect .................................64
General Configuration Registers ............................. 66
On/Off/Margin ........................................................67
PWM Config ...........................................................69
Voltage ....................................................................71
Input Voltage and Limits .....................................71
Output Voltage and Limits ..................................72
Current .................................................................... 74
Input Current Calibration ................................... 74
Output Current Calibration .................................75
Input Current ......................................................75
Output Current ....................................................76
Temperature ............................................................77
External Temperature Calibration........................77
External Temperature Limits ...............................77
Timing ....................................................................78
Timing—On Sequence/Ramp .............................78
Timing—Off Sequence/Ramp ............................79
Precondition for Restart .....................................80
Fault Response ....................................................... 81
Fault Responses All Faults ..................................81
Fault Responses Input Voltage ...........................81
Fault Responses Output Voltage .........................82
Fault Responses Output Current .........................85
Fault Responses IC Temperature ........................86
Fault Responses External Temperature ...............86
Fault Sharing ...........................................................88
Fault Sharing Propagation ..................................88
Fault Sharing Response ......................................89
Scratchpad .............................................................90
Identification ...........................................................90
Fault Warning and Status ........................................91
Telemetry ................................................................ 98
NVM (EEPROM) Memory Commands .................. 102
Store/Restore ...................................................102
Fault Logging .................................................... 103
Block Memory Write/Read................................ 108
Typical Applications .................................... 109
Package Description ................................... 114
Revision History ........................................ 115
Typical Application ..................................... 116
Related Parts ............................................ 116
LTC3887/LTC3887-1/
LTC3887-2
4
Rev.F
For more information www.analog.com
VIN Voltage ................................................. –0.3V to 28V
VIN Voltage LTC3887-2 ............................... –0.3V to 36V
Top Gate Transient Voltage TG0,
TG1 LTC3887 ................................................ –5V to 34V
Top Gate Transient Voltage PWM0,
PWM1 LTC3887-1 ........................................ –0.3V to 6V
BOOST1, BOOST0, LTC3887 ...................... –0.3V to 34V
BOOST1, BOOST0, LTC3887-2 ................... –0.3V to 42V
VCC1, VCC0 LTC3887-1 .................................. –0.3V to 6V
Switch Transient Voltage SW1,
SW0 LTC3887 ............................................... –5V to 28V
INTVCC, EXTVCC, (BOOST1 – SW1), (BOOST0 – SW0),
BG0, BG1, LTC3887, LTC3887-2 ................... –0.3V to 6V
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
VSENSE0+, VSENSE1, ISENSE0n, ISENSE1n .......... –0.3V to 6V
RUN0, RUN1, SDA, SCL, ALERT ................ –0.3V to 5.5V
FREQ_CFG, VOUTn_CFG, ASEL0/1, VDD25 ....–0.3V to 2.75V
VDD33, GPIO0, GPIO1, TSNS0, TSNS1, VSENSE0–,
SHARE_CLK, WP, SYNC, ITHn ................. –0.3V to 3.6V
INTVCC Peak Output Current ................................100mA
Operating Junction Temperature Range
(Note 2) ................................................ –40°C to 125°C*
Storage Temperature Range ................ –65°C to 150°C*
*See Derating EEPROM Retention at Temperature in the
Applications Information section for junction tempera-
tures in excess of 125°C.
LTC3887/LTC3887-2 LTC3887-1
3940 38 37 36 35 34 33 32 31
11 20
12 13 14 15
TOP VIEW
41
GND
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 125°C, θJA = 33°C/W, θJC = 2.5°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
*EXTVCC FOR LTC3887-2 ONLY
16 17 18 19
22
23
24
25
26
27
28
29
9
8
7
6
5
4
3
2
VSENSE0+
VSENSE0–
ISENSE1+
ISENSE1–
ITH0
ISENSE0+
ISENSE0–
SYNC
SCL
SDA
TG1
SW1
TSNS1
VSENSE1
ITH1
VDD33
SHARE_CLK
WP
VDD25
PHAS_CFG
TSNS0
SW0
TG0
BOOST0
BG0
VIN
GND
INTVCC (EXTVCC*)
BG1
BOOST1
ALERT
GPIO0
GPIO1
RUN0
RUN1
ASEL0
ASEL1
VOUT0_CFG
VOUT1_CFG
FREQ_CFG
21
30
10
1
3940 38 37 36 35 34 33 32 31
11 20
12 13 14 15
TOP VIEW
41
GND
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 125°C, θJA = 33°C/W, θJC = 2.5°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
16 17 18 19
22
23
24
25
26
27
28
29
9
8
7
6
5
4
3
2
VSENSE0+
VSENSE0–
ISENSE1+
ISENSE1–
ITH0
ISENSE0+
ISENSE0–
SYNC
SCL
SDA
PWM1
NC
TSNS1
VSENSE1
ITH1
VDD33
SHARE_CLK
WP
VDD25
PHAS_CFG
TSNS0
NC
PWM0
VCC0
NC
VIN
GND
INTVCC
NC
VCC1
ALERT
GPIO0
GPIO1
RUN0
RUN1
ASEL0
ASEL1
VOUT0_CFG
VOUT1_CFG
FREQ_CFG
21
30
10
1
LTC3887/LTC3887-1/
LTC3887-2
5
Rev. F
For more information www.analog.com
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION JUNCTION TEMPERATURE RANGE
LTC3887EUJ#PBF LTC3887EUJ#TRPBF LTC3887UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3887IUJ#PBF LTC3887IUJ#TRPBF LTC3887UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3887EUJ-1#PBF LTC3887EUJ-1#TRPBF LTC3887UJ-1 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3887IUJ-1#PBF LTC3887IUJ-1#TRPBF LTC3887UJ-1 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3887EUJ-2#PBF LTC3887EUJ-2#TRPBF LTC3887UJ-2 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3887IUJ-2#PBF LTC3887IUJ-2#TRPBF LTC3887UJ-2 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
AUTOMOTIVE PRODUCTS**
LTC3887EUJ#WPBF LTC3887EUJ#WTRPBF LTC3887UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3887IUJ#WPBF LTC3887IUJ#WTRPBF LTC3887UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3887EUJ-1#WPBF LTC3887EUJ-1#WTRPBF LTC3887UJ-1 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3887IUJ-1#WPBF LTC3887IUJ-1#WTRPBF LTC3887UJ-1 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3887EUJ-2#WPBF LTC3887EUJ-2#WTRPBF LTC3887UJ-2 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3887IUJ-2#WPBF LTC3887IUJ-2#WTRPBF LTC3887UJ-2 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
thesemodels.
LTC3887/LTC3887-1/
LTC3887-2
6
Rev.F
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 12V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally
driven) unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Voltage
VIN Input Voltage Range LTC3887, LTC3887-1 (Note 12) l4.5 24 V
VIN Input Voltage Range LTC3887-2 (Note 12) l4.5 34 V
IQInput Voltage Supply Current
Normal Operation
(Note 14)
VRUN0,1 = 3.3V, No Caps on TG and BG
VRUN0,1 = 0V
25
20
mA
mA
VUVLO Undervoltage Lockout Threshold
when VIN > 4.3V
VINTVCC Falling
VINTVCC Rising
3.7
3.95
V
V
TINIT Initialization Time Time from VIN Applied Until the TON_DELAY
Timer Starts.
30 ms
Control Loop
VOUTR0 Full-Scale Voltage High Range
Set Point Accuracy (0.6V to 5V)
Resolution
LSB Step Size
VOUT_COMMAND = 5.500V (Note 9) l
l
5.45
–0.5
12
1.375
5.55
0.5
V
%
Bits
mV
VOUTR1 Full-Scale Voltage Low Range
Set Point Accuracy (0.6V to 2.5V)
Resolution
LSB Step Size
VOUT_COMMAND = 2.75V (Note 9) l
l
2.7
–0.5
12
0.6875
2.8
0.5
V
%
Bits
mV
VLINEREG Line Regulation 6V < VIN < 24V l±0.02 %/V
VLOADREG Load Regulation ∆VITH = 1.35V – 0.7V
∆VITH = 1.35V – 2.0V
l
l
0.01
–0.01
0.1
–0.1
%
%
gm0,1 Error Amplifier gmITH0,1 =1.22V 3 mmho
IISENSE0,1 Input Current VISENSE = 5.5V l±1 ±3 µA
VSENSERIN0 VSENSE Input Resistance to Ground 0V ≤ VPIN ≤ 5.5V 41 kΩ
VSENSERIN1 VSENSE Input Resistance to Ground 0V ≤ VPIN ≤ 5.5V 37 kΩ
VIlLIMIT Resolution 3 bits
VILIMMAX Hi Range
Lo Range
l
l
68
44
75
50
82
56
mV
mV
VILMMIN Hi Range
Lo Range
37.5
25
mV
mV
Gate Drivers LTC3887
TG0,1
tr
tf
TG Transition Time (LTC3887/LTC3887-1)
Rise Time
Fall Time
(Note 4)
CLOAD = 3300pF
CLOAD = 3300pF
30
30
ns
ns
BG0,1
tr
tf
BG Transition Time:
Rise Time
Fall Time
(Note 4)
CLOAD = 3300pF
CLOAD = 3300pF
30
30
ns
ns
TG/BG t1D Top Gate Off to Bottom Gate On Delay Time (Note 4) CLOAD = 3300pF Each Driver 30 ns
BG/TG t2D Bottom Gate Off to Top Gate On Delay Time (Note 4) CLOAD = 3300pF Each Driver 30 ns
tON(MIN) Minimum On-Time (LTC3887/LTC3887-1) 45 ns
OV Output Voltage Supervisor
N Resolution 8 Bits
VRANGE0 Voltage Monitoring Range Range Value = 0 1 5.6 V
VRANGE1 Voltage Monitoring Range Range Value = 1 0.5 2.7 V
VOUSTP0 Threshold Programming Step Range Value = 0 22.5 mV
VOUSTP1 Threshold Programming Step Range Value = 1 11.25 mV
VTHACC0 Threshold Accuracy 2V < VOUT < 5V Range Value = 0 l±2 %
VTHACC1 Threshold Accuracy 1V < VOUT < 2.5V Range Value = 1 l±2 %
tPROPOV OV Comparator to GPIO Low Time VOD = 10% of Threshold 35 µs
LTC3887/LTC3887-1/
LTC3887-2
7
Rev. F
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 12V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally
driven) unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
UV Output Voltage Supervisor
N Resolution 8 bits
VRANGE0 Voltage Range High Range 1 5.5 V
VRANGE1 Voltage Range Low Range 0.5 2.7 V
VOUSTP0 Step Size Range Value = 0, High Range 22 mV
VOUSTP1 Step Size Range Value = 1, Low Range 11 mV
VTHACC0 Threshold Accuracy 2V < VOUT < 5V Range Value = 0, High Range l±2 %
VTHACC1 Threshold Accuracy 1V < VOUT < 2.5V Range Value = 1, Low Range l±2 %
tPROPUV UV Comparator to GPIO Low Time VOD = 10% of Threshold 100 µs
VIN Voltage Supervisor
N Resolution 8 bits
VINRANGE Full-Scale Voltage 4.5 20 V
VINSTP Step Size 82 mV
VINTHACC Threshold Accuracy 9.0V < VIN < 20V l±2.5 %
VINTHACC\M Threshold Accuracy 4.5V < VIN ≤ 9V l±5 %
tPROPVIN Comparator Response Time
(VIN_ON and VIN_OFF)
VOD = 10% of Threshold 100 µs
Output Voltage Readback
N Resolution
LSB Step Size
16
244
Bits
µV
VOFS Full-Scale Voltage (Note 10) VRUNn = 0V (Note 8) 8 V
VOUT_TUE Total Unadjusted Error (Note 8) VOUTn > 0.6V l0.5 %
VOS Zero-Code Offset Voltage ±500 µV
tCONVERT Conversion Time (Note 6) 90 ms
VIN Voltage Readback
N Resolution (Note 5) 10 Bits
VIFS Full-Scale Voltage (Note 11) 38.91 V
VIN_TUE Total Unadjusted Error VVIN > 4.5V (Note 8)
l
0.5
2
%
%
tCONVERT Conversion Time (Note 6) 90 ms
Output Current Readback
N Resolution
LSB Step Size
(Note 5)
0V ≤ |VISENSE+ – VISENSE–| < 16mV
16mV ≤ |VISENSE+ – VISENSE–| < 32mV
32mV ≤ |VISENSE+ – VISENSE–| < 63.9mV
63.9mV ≤ |VISENSE+ – VISENSE–| < 127.9mV
10
15.625
31.25
62.5
125
Bits
µV
µV
µV
µV
IFS Full-Scale Current (Note 7) RISENSE = 1mΩ ±128 A
IOUT_TUE Total Unadjusted Error (Note 8) VISENSE > 6mV l±1 %
VOS Zero-Code Offset Voltage ±28 µV
tCONVERT Conversion Time (Note 6) 90 ms
Input Current and Duty Cycle Readback
D_RES Resolution 10 Bits
D_TUE Total Unadjusted Error 16.3% Duty Cycle –3 3 %
tCONVERT Update Rate (Note 6) 90 ms
Temperature Readback (T0, T1, T2)
TRES_T Resolution 0.25 °C
T0,1_TUE External TSNS TUE ∆VTSNS = 72mV (Note 8) l±3 °C
T2_TUE Internal TSNS TUE VRUN0,1 = 0.0V, fSYNC = 0kHz (Note 8) ±1 °C
tCONVERT_T Update Rate (Note 6) 90 ms
LTC3887/LTC3887-1/
LTC3887-2
8
Rev.F
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 12V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally
driven) unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
INTVCC Regulator
VINTVCC Internal VCC Voltage No Load
(LTC3887, LTC3887-1)
6V < VIN < 24V 4.8 5 5.2 V
VLDO_INT INTVCC Load Regulation
(LTC3887, LTC3887-1)
ICC = 0mA to 50mA 0.5 ±2 %
VDD33 Regulator
VDD33 Internal VDD33 Voltage 4.5V < VINTVCC 3.2 3.3 3.4 V
ILIM(VDD33) VDD33 Current Limit VDD33 = GND 70 mA
VDD33_OV VDD33 Overvoltage Threshold 3.5 V
VDD33_UV VDD33 Undervoltage Threshold 3.1 V
VDD25 Regulator
VDD25 Internal VDD25 Voltage 2.5 V
ILIM(VDD25) VDD25 Current Limit VDD25 = GND 50 mA
Oscillator and Phase-Locked Loop
fOSC Oscillator Frequency Accuracy 250kHz < fSYNC < 1MHz Measured Falling
Edge-to-Falling Edge of SYNC with SWITCH_
FREQUENCY = 250.0 and 1000.0
l±7.5 %
VTH,SYNC SYNC Input Threshold VCLKIN Falling
VCLKIN Rising
1
1.5
V
V
VOL,SYNC SYNC Low Output Voltage ILOAD = 3mA 0.2 0.4 V
ILEAKSYNC SYNC Leakage Current in Slave Mode 0V ≤ VPIN ≤ 3.6V ±5 µA
θSYNC-θ0 SYNC to Ch0 Phase Relationship Based on
the Falling Edge of Sync and Rising Edge of
TG0
MFR_PWM_CONFIG_LTC3887[2:0] = 0, 2, 3
MFR_PWM_CONFIG_LTC3887[2:0] = 5
MFR_PWM_CONFIG_LTC3887[2:0] = 1
MFR_PWM_CONFIG_LTC3887[2:0] = 4, 6
0
60
90
120
Deg
Deg
Deg
Deg
θSYNC-θ1 SYNC to Ch1 Phase Relationship Based on
the Falling Edge of Sync and Rising Edge of
TG1
MFR_PWM_CONFIG_LTC3887[2:0] = 3
MFR_PWM_CONFIG_LTC3887[2:0] = 0
MFR_PWM_CONFIG_LTC3887[2:0] = 2, 4, 5
MFR_PWM_CONFIG_LTC3887[2:0] = 1
MFR_PWM_CONFIG_LTC3887[2:0] = 6
120
180
240
270
300
Deg
Deg
Deg
Deg
Deg
EEPROM Characteristics
Endurance (Note 13) 0°C < TJ < 85°C During EEPROM Write
Operations
l10,000 Cycles
Retention (Note 13) TJ < TJMAX l10 Years
Mass_Write Mass Write Operation Time STORE_USER_ALL, 0°C < TJ < 85°C During
EEPROM Write Operations
l440 4100 ms
Digital Inputs SCL, SDA, RUN0, RUN1, GPIO0, GPIO1
VIH Input High Threshold Voltage SCL, SDA, RUN0, RUN1, GPIO0, GPIO1 l1.35 V
VIL Input Low Threshold Voltage SCL, SDA, RUN0, RUN1, GPIO0, GPIO1 l0.8 V
VHYST Input Hysteresis SCL, SDA 0.08 V
CPIN Input Capacitance 10 pF
Digital Input WP
IPUWP Input Pull-Up Current WP 10 µA
Open-Drain Outputs SCL, SDA, GPIO0, GPIO1, ALERT, RUN0, RUN1, SHARE_CLK
VOL Output Low Voltage ISINK = 3mA l0.4 V
Digital Inputs SHARE_CLK, WP
VIH Input High Threshold Voltage 1.5 1.8 V
VIL Input Low Threshold Voltage 0.6 1 V
Leakage Current SDA, SCL, ALERT, RUN0, RUN1
IOL Input Leakage Current 0V ≤ VPIN ≤ 5.5V l±5 µA
LTC3887/LTC3887-1/
LTC3887-2
9
Rev. F
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 12V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally
driven) unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Leakage Current GPIO0, GPIO1
IGL Input Leakage Current 0V ≤ VPIN < 3.6V l ±5 µA
Digital Filtering of GPIO0, GPIO1
IFLTG Input Digital Filtering GPIO 3 µs
Digital Filtering of RUN0, RUN1
IFLTR Input Digital Filtering RUN 10 µs
PMBus Interface Timing Characteristics
fSMB Serial Bus Operating Frequency l10 400 kHz
tBUF Bus Free Time Between Stop and Start l1.3 µs
tHD,STA Hold time After Repeated Start Condition.
After this Period, the First Clock is Generated
l0.6 µs
tSU,STA Repeated Start Condition Setup Time l0.6 µs
tSU,STO Stop Condition Setup Time l0.6 µs
tHD,DAT Data Hold Time
Receiving Data
Transmitting Data
l
l
0
0.3
0.9
µs
µs
tSU,DAT Data Setup Time
Receiving Data
l
0.1
µs
tTIMEOUT_SMB Stuck PMBus Timer Non-Block Reads
Stuck PMBus Timer Block Reads
Measured from the Last PMBus Start Event 32
150
ms
ms
tLOW Serial Clock Low Period l1.3 10000 µs
tHIGH Serial Clock High Period l0.6 µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3887/LTC3887-1 are tested under pulsed load conditions
such that TJ ≈ TA. The LTC3887E/LTC3887E-1 are guaranteed to meet
performance specifications from 0°C to 85°C. Specifications over the
–40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3887I/LTC3887I-1 are guaranteed over the full –40°C to 125°C
operating junction temperature range. TJ is calculated from the ambient
temperature TA and power dissipation PD according to the following
formula:
TJ = TA + (PD • θJA)
The maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 5: The data format in PMBus is 5 bits exponent (signed) and 11 bits
mantissa (signed). This limits the output resolution to 10 bits though the
internal ADC is 16 bits and the calculations use 32-bit words.
Note 6: The data conversion is done in round robin fashion. All inputs
signals are continuously converted for a typical latency of 90ms. Unless
the MFR_ADC_CONTROL command is utilized.
Note 7: The IOUT_CAL_GAIN = 1.0mΩ and MFR_IOUT_CAL_GAIN_TC =
0.0. Value as read from READ_IOUT in amperes.
Note 8: Part tested with PWM disabled. Evaluation in application
demonstrates capability. TUE (%) = ADC Gain Error (%) + 100 • [Zero
Code Offset + ADC Linearity Error]/Actual Value.
Note 9: All VOUT commands assume the ADC is used to auto-zero the
output to achieve the stated accuracy. LTC3887 is tested in a feedback
loop that servos VOUT to a specified value.
Note 10: The maximum VOUT voltage is 5.5V.
Note 11: The maximum VIN voltage is 28V.
Note 12: When VIN < 6V, INTVCC must be tied to VIN.
Note 13: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM
has been cycled less than the minimum endurance specification. The
RESTORE_USER_ALL command (EEPROM read) is valid over the entire
operating junction temperature range.
Note 14: The LTC3887-2 quiescent current (IQ) equals the IQ of VIN plus
the IQ of EXTVCC.
LTC3887/LTC3887-1/
LTC3887-2
10
Rev.F
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
(Forced Continuous Mode)
Load Step
(Pulse-Skipping Mode)
Efficiency vs Load Current
FSW = 350kHz (LTC3887)
Power Loss vs Load Current
FSW = 350kHz (LTC3887)
Efficiency vs Load Current
FSW = 500kHz (LTC3887)
Inductor Current at Light Load Start-Up into a Prebiased Load Soft-Start Ramp
ILOAD
5A/DIV
INDUCTOR
CURRENT
5A/DIV
VOUT
100mV/DIV
AC-COUPLED
50µs/DIVVIN = 12V
VOUT = 1.8V
0.3A TO 5A STEP
3887 G05
ILOAD
5A/DIV
INDUCTOR
CURRENT
5A/DIV
VOUT
100mV/DIV
AC-COUPLED
50µs/DIVVIN = 12V
VOUT = 1.8V
0.3A TO 5A STEP
3887 G06
RUN
2V/DIV
VOUT
1V/DIV
5ms/DIVtRISE = 10ms
tDELAY = 5ms
3887 G08
RUN
2V/DIV
VOUT
1V/DIV
5ms/DIVtRISE = 10ms
tDELAY = 5ms
3887 G09
Power Loss vs Load Current
FSW = 500kHz (LTC3887)
LOAD CURRENT (A)
0
60
EFFICIENCY (%)
65
75
70
80
85
90
95
5 10 15 20 25
3887 G01
30
12VIN 1.8VOUT 350kHz
12VIN 1.5VOUT 350kHz
12VIN 1.2VOUT 350kHz
12VIN 1.0VOUT 350kHz
LOAD CURRENT (A)
0
0
POWER LOSS (W)
2
1
4
3
5
6
7
8
5 10 15 20 25
3887 G02
30
12VIN 1.8VOUT 350kHz
12VIN 1.5VOUT 350kHz
12VIN 1.2VOUT 350kHz
12VIN 1.0VOUT 350kHz
LOAD CURRENT (A)
0
60
EFFICIENCY (%)
65
75
70
80
85
90
95
5 10 15 20 25
3887 G03
30
12VIN 1.8VOUT 500kHz
12VIN 1.5VOUT 500kHz
12VIN 1.2VOUT 500kHz
12VIN 1.0VOUT 500kHz
LOAD CURRENT (A)
0
0
POWER LOSS (W)
2
1
4
3
5
6
7
8
5 10 15 20 25
3887 G04
30
12VIN 1.8VOUT 500kHz
12VIN 1.5VOUT 500kHz
12VIN 1.2VOUT 500kHz
12VIN 1.0VOUT 500kHz
1µs/DIV
FORCED
CONTINUOUS
MODE
5A/DIV
DISCONTINUOUS
CONDUCTION MODE
5A/DIV
3887 G07
VIN = 12V
VOUT = 1.8V
ILOAD = 1A
LTC3887/LTC3887-1/
LTC3887-2
11
Rev. F
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Soft-Off Ramp
Current Sense Threshold
vs ITH Voltage (Low Range)
Maximum Current Sense Threshold
vs Duty Cycle, VOUT = 0V
Maximum Current Sense Threshold
vs Common Mode Voltage
Regulated Output
vs Temperature
SHARE_CLK Frequency
vs Temperature
SHARE-CLK Frequency vs VIN Quiescent Current vs Temperature VOUT Measurement vs VOUT
RUN
2V/DIV
VOUT
1V/DIV
5ms/DIVtFALL = 5ms
tDELAY = 10ms
3887 G10
VITH (V)
0
CURRENT LIMIT (A) WITH 1mΩ SENSE RESISTOR
10
20
30
1.5 2.5
3887 G11
0
–10
–20 0.5 1 2
40
50
60
VSENSE 50mV
VSENSE 25mV
DUTY CYCLE (%)
0
MAXIMUM CURRENT SENSE THRESHOLD (mV)
51
53
55
90
3887 G12
49
47
50
52
54
48
46
45 30 50 70
50mV SENSE CONDITION
COMMON MODE VOLTAGE (V)
0
45
MAXIMUM CURRENT SENSE THRESHOLD (mV)
47
49
51
123 4
3887 G13
5
53
55
46
48
50
52
54
6
50mV SENSE CONDITION
TEMPERATURE (°C)
–50
0.4975
VOUT (V)
0.4980
0.4990
0.4995
0.5000
0.5025
0.5010
–10 30 50
3887 G14
0.4985
0.5015
0.5020
0.5005
–30 10 70 90 110
TEMPERATURE (°C)
–50
90
SHARE_CLK FREQUENCY (kHz)
95
100
105
110
–30 –10 10 30
3887 G15
50 70 90 110
VIN (V)
6
SHARE_CLOCK FREQUENCY (kHz)
100.0
100.5
22
3887 G16
99.5
99.0 10 14 16 2826
101.0
18
812 24
20
TEMPERATURE (°C)
–50
15
QUIESCENT CURRENT (mA)
20
25
30
–30 –10 10 30
3887 G17
50 70 90 110
VOUT (V)
0.5
MEASSURED ERROR (mV)
0.30
0.20
0.10
0
–0.10
–0.20
–0.30
–0.40
4.5
3887 G18
1.5 2.5 3.5 5.541 2 3 5
LTC3887/LTC3887-1/
LTC3887-2
12
Rev.F
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT Command INL VOUT Command DNL INTVCC Line Regulation
VOUT OV Threshold
vs Temperature (1V Target)
VOUT OV Threshold
vs Temperature (2V Target)
VOUT OV Threshold
vs Temperature (4V Target)
VOUT (V)
–1.0
INL (LSBs)
0
1.0
2.0
–0.5
0.5
1.5
1.5 2.5 3.5 4.5
3887 G19
5.510.5 2 3 4 5
VOUT (V)
–0.3
DNL (LSBs)
–0.1
0.1
0.3
–0.2
0
0.2
1.5 2.5 3.5 4.5
3887 G20
5.510.5 2 3 4 5
VIN (V)
5
4.50
4.75
5.25
20
3887 G21
4.25
4.00
10 15 25
3.75
3.50
5.00
INTV
CC
(V)
TEMPERATURE (°C)
–50
0.990
1V OV THRESHOLD (V)
0.995
1.000
1.005
1.010
–30 –10 10 30
3887 G22
50 70 90 110
TEMPERATURE (°C)
–50
1.97
2V OV THRESHOLD (V)
1.98
1.99
2.00
2.01
0 50 100 150
3887 G23
2.02
2.03
–25 25 75 125
TEMPERATURE (°C)
–50
3.96
4V OV THRESHOLD (V)
3.97
3.98
3.99
4.00
0 50 100 150
3887 G24
4.02
4.01
4.03
4.04
–25 25 75 125
Temperature Error
vs Temperature
IOUT Error vs IOUT Room
Temperature IIN Measurement Error vs IIN
ACTUAL TEMPERATURE (°C)
–45
–1.0
MEASUREMENT ERROR (°C)
–0.8
–0.4
–0.2
0
1.0
0.4
–5 35 55
3887 G25
–0.6
0.6
0.8
0.2
–25 15 75 95 115
OUTPUT CURRENT (A)
0
MEASUREMENT ERROR (mA)
0
2
4
20
3887 G26
–2
–4
–8 510 15
–6
8
6
IIN (A)
0
I
IN
MEASUREMENT ERROR (mA)
–4
–2
0
1.2
3887 G27
–6
–8
0.4 0.8
0.2 1.4
0.6 1.0 1.6
–10
–12
2
LTC3887/LTC3887-1/
LTC3887-2
13
Rev. F
For more information www.analog.com
V
SENSE0+
(Pin 1): Channel 0 Positive Voltage Sense Input.
V
SENSE0–
(Pin 2): Channel 0 Negative Voltage Sense Input.
ITH0/ITH1 (Pin 5/Pin 26 ): Current Control Threshold and
Error Amplifier Compensation Nodes. Each associated
channel’s current comparator tripping threshold increases
with its ITH voltage.
ISENSE0+/ISENSE1+ (Pins 6/Pin 3): Current Sense
Comparator Inputs. The (+) inputs to the current compar-
ators are normally connected to DCR sensing networks
or current sensing resistors.
ISENSE0–/ISENSE1– (Pin 7/Pin 4): Current Sense Comparator
Inputs. The (–) inputs are connected to the low side of the
current sense element.
SYNC (Pin 8): External Clock Synchronization Input and
Open-Drain Output Pin. If an external clock is present at
this pin, the switching frequency will be synchronized to
the external clock. If the SYNC output is enabled, this
pin will pull low at the switching frequency with a 500ns
pulse to ground. A resistor pull up to 3.3V is required in
the application if the LTC3887 SYNC output is enabled.
SCL (Pin 9): Serial Bus Clock Input. Open-drain output,
can hold the output low if clock stretching is enabled. A
pull-up resistor to 3.3V is required in the application.
SDA (Pin 10): Serial Bus Data Input and Output. A pull-up
resistor to 3.3V is required in the application.
ALERT (Pin 11): Open-Drain Digital Output. Connect the
SMBALERT signal to this pin. A pull-up resistor to 3.3V
is required in the application.
GPIO0/GPIO1 (Pin 12/Pin 13): Digital Programmable
General Purpose Inputs and Outputs. Open-drain output.
A pull-up resistor to 3.3V is required in the application.
RUN0/RUN1 (Pin 14/Pin 15): Enable Run Input and Output.
Logic high on these pins enables the controller. Open-drain
output holds the pin low until the LTC3887 is out of reset.
A pull-up resistor to 3.3V is required in the application.
ASEL0 (Pin 16): Serial Bus Address Configuration Input.
Connect a ±1% resistor divider between the chip V
DD25
ASEL0 and SGND in order to select the 4LSBs of the serial
bus interface address. A resistor divider on ASEL0 is rec-
ommended if there are more than one LTC3887s on the
same board to assure the user can independently program
each IC. If the pin is left open, the IC will use the value
programmed in the EEPROM. Minimize capacitance when
the pin is open to assure accurate detection of the pin state.
ASEL1 (Pin 17): Serial Bus Address Configuration Input.
Connect a ±1% resistor divider between the chip V
DD25
ASEL1 and SGND in order to select the 3MSBs of the serial
bus interface address. A resistor divider on ASEL1 is rec-
ommended if there are more than 16 LTC3887s on the
same board to assure the user can independently program
each IC. If the pin is left open, the IC will use the value
programmed in the EEPROM. Minimize capacitance when
the pin is open to assure accurate detection of the pin state.
TYPICAL PERFORMANCE CHARACTERISTICS
DC Output Current Matching in a
2-Phase System (LTC3887)
TOTAL CURRENT (A)
0
CHANNEL CURRENT (A)
15
20
25
15 25 40
3887 G28
10
5
05 10 20 30 35
CHAN 0
CHAN 1
Dynamic Current Sharing During a
Load Transient in a 4-Phase System
10
0
INDUCTOR
CURRENT
5A/DIV
5µs/DIV 3887 G29
10
0
INDUCTOR
CURRENT
5A/DIV
5µs/DIV 3887 G30
Dynamic Current Sharing During a
Load Transient in a 4-Phase System
PIN FUNCTIONS
LTC3887/LTC3887-1/
LTC3887-2
14
Rev.F
For more information www.analog.com
FREQ_CFG (Pin 20): Frequency Select Pin. Connect a
±1% resistor divider between the chip VDD25 FREQ_CFG
and GND in order to select switching frequency. If the pin
is left open, the IC will use the value programmed in the
EEPROM. Minimize capacitance when the pin is open to
assure accurate detection of the pin state.
PHAS_CFG (Pin 21): Phase Select Pin. Connect a ±1%
resistor divider between the chip VDD25 PHAS_CFG and
GND in order to select channel phasing. If the pin is
left open, the IC will use the value programmed in the
EEPROM. Minimize capacitance when the pin is open to
assure accurate detection of the pin state.
VOUT0_CFG/VOUT1_CFG (Pin 18/Pin 19): Voltage Select Pin.
Connect a ±1% resistor divider between the chip VDD25
VOUTn_CFG and GND in order to adjust the output voltage
set point. If the pin is left open, the IC will use EEPROM.
Minimize capacitance when the pin is open to assure
accurate detection of the pin state.
VDD25 (Pin 22): Internally Generated 2.5V power Supply
Output Pin. Bypass this pin to GND with a low ESR 1µF
capacitor. Do not load this pin with external current except
for the ±1% resistor dividers required for the configura-
tion pins.
WP (Pin 23): Write Protect Pin Active High. An internal
10µA current source pulls the pin to VDD33. If WP is high,
the PMBus writes are restricted.
SHARE_CLK (Pin 24): Share Clock, Bidirectional Open-
Drain Clock Sharing Pin. Nominally 100kHz. Used to syn-
chronize the timing between multiple LTC388Xs. Tie all
SHARE_CLK pins together. All LTC388Xs will synchronize
to the fastest clock. A pull-up resistor to 3.3V is required.
VDD33 (Pin 25): Internally Generated 3.3V Power Supply
Output Pin. Bypass this pin to GND with a low ESR 1µF
capacitor. Do not load this pin with external current except
for the pull-up resistors required for GPIOn, SCLK, SYNC
and possibly RUNn, ALERT, SDA and SCL.
V
SENSE1
(Pin 27): Channel 1 Voltage Sense Input. This
input voltage is referenced to the GND pin.
INTV
CC
(Pin 33): LTC3887, LTC3887-1, Internal Regulator
5V Output. The control circuits are powered from this voltage.
Decouple this pin to power ground with a minimum of
4.7µF low ESR tantalum or ceramic capacitor.
EXTVCC (Pin 33): LTC3887-2, External 5V Regulator
Input. The control circuits are powered from this voltage.
Decouple this pin to power ground with a minimum of
4.7µF low ESR tantalum or ceramic capacitor.
GNDSNS (Pin 34): Ground Sense Pin. This pin is con-
nected to the back paddle ground and can be used to
detect if there is a good ground connection between the
back paddle and the board.
VIN (Pin 35): Main Input Supply. Decouple this pin to
PGND with a capacitor (0.1µF to 1µF). For applications
where the main input power is 5V, tie the VIN and INTVCC
pins together.
BG0/BG1 (Pin 36/Pin 32): Bottom Gate Driver Outputs.
These pins drive the gates of the bottom N-Channel
MOSFETs between PGND and INTVCC. BG0/BG1 are not
connected on the LTC3887-1. They may be floated or tied
to ground.
BOOST0/BOOST1 (LTC3887) (Pin 37/Pin 31): Boosted
Floating Driver Supplies. The (+) terminal of the bootstrap
capacitors connect to these pins. These pins swing from
a diode voltage drop below INTVCC up to VIN + INTVCC.
VCC0/VCC1 (LTC3887-1) (Pins 37/31): These pins should
be connected to INTVCC or VDD33.
TG0/TG1 (LTC3887) (Pin 38/Pin 30): Top Gate Driver
Outputs. These are the outputs of floating drivers with
a voltage swing equal to INTVCC superimposed on the
switch node voltages.
PWM0/PWM1 (LTC3887-1) (Pin 38/Pin 30): PWM
Outputs. These are the three-state control outputs with a
voltage swing of GND to VCC used to control gate drivers.
The LTC3887-1 PWM pin is three-state which is required
to produce discontinuous operation in some gate driver
or DrMOS circuits.
SW0/SW1 (LTC3887) (Pin 39/Pin 29): Switch Node
Connections to Inductors. Voltage swings at the pins are
from a Schottky diode (external) voltage drop below ground
to VIN. In the LTC3887-1 these pins are not connected to
internal circuitry. They may be floated or tied to ground.
TSNS0/TSNS1 (Pin 40/Pin 28): Channel 0,1 External
Diode Temperature Sense. Connect to the anode of a
diode connected PNP transistor and directly connect the
cathode to SGND in order to sense remote temperature.
If external temperature sense elements are not installed,
short pin to ground and set the UT_FAULT_LIMIT to
–275°C, IOUT_CAL_GAIN_TC set to zero and the UT_
FAULT_RESPONSE to ignore.
PIN FUNCTIONS
LTC3887/LTC3887-1/
LTC3887-2
15
Rev. F
For more information www.analog.com
BLOCK DIAGRAM
Figure1. Block Diagram
One of two channels (CH0) shown. (LTC3887 application only)
16-BIT
ADC
8-BIT VIN
DAC
PWM1
+
–
–
+
–
–
+
+
+
+
–
–
PWM0
–
+
VSENSE1
–
+ISENSE1–
–ISENSE1+
+
8:1
MUX
TMUX
2µA
ILIM DAC
(3 BITS)
OV
8-BIT
OV
DAC
8-BIT
UV
DAC
12-BIT
SET POINT
DAC
UVEA
+
0.56V
1.22V
BURST
ITH0
RC
CC1
30µA
–
+
–
+
AO
R
R
9R
2R
PWM
CLOCK
VOUT0_CFG
R
VSENSE0+
GND
PGND
TSNS0
VSENSE0–
NO DIFF AMP ON CH1
R
SWITCH
LOGIC
AND
ANTI-
SHOOT-
THROUGH
OV
RUN
SS
UVLO
REV
UV
ON
FCNT
1
2
41
40
18
VOUT1_CFG
19
FREQ_CFG
20
PHAS_CFG
21
ASEL1
17
ASEL0
3887 F01
16
13
12
15
14
CVCC
BG0
DB
M1
VIN
CIN
INTVCC
VDD33
FOR LTC3887-1 POWER
STAGE EXAMPLE GO TO
PAGE 111
36
ISENSE0–
7
ISENSE0+
6
SW0
39
TG0 CB
38
BOOST0
37
VDD33
25
INTVCC
33
M2
COUT
VOUT0
+
3.3V
SUBREG
2.5V
SUBREG
V
IN
35
5V REG
38R
R
–
+
–
+
–
+
1
71.1k
ACTIVE
CLAMP
UVLOINTVCC
SLOPE
COMPENSATION
SLAVE
VDD33
MISO
MOSICLK
MASTER
RAM
RUN0
RUN1
24
SHARE_CLK
GPIO0
GPIO1
EEPROM
MAIN
CONTROL
PROGRAM
ROM
VDD33
COMPARE
ILIM RANGE SELECT
HI: 1:1
LO: 1:1.5
3k
ICMP IREV
5
+
–
+
–
VIN ON/OFF
+
–
S
REF
VSTBY
Q
PWM_CLOCK
R
PHASE DET
VCO
PHASE SELECTOR
CLOCK DIVIDER
SINC3UVLO OSC
(32MHz)
CONFIG
DETECT
CHANNEL
TIMING
MANAGEMENT
11
10
9
23
WP
SCL
SDA
ALERT
PMBus
INTERFACE
(400kHz
COMPATIBLE)
SYNC
SGND
M3
VDD33
8
VDD25
22
VDD25
+
19R
R
LTC3887/LTC3887-1/
LTC3887-2
16
Rev.F
For more information www.analog.com
OPERATION
OVERVIEW
The LTC3887/LTC3887-1 are a dual channel/dual phase,
constant frequency, analog current mode controller for
DC/DC step-down applications with a digital interface. The
LTC3887 is used in applications where the gate driver is
required. The LTC3887-1 is used in applications where the
gate driver is external, for example a DrMOS power stage.
The LTC3887-1 allows the TG pin to three-state which is
required to produce discontinuous operation in some gate
driver DrMOS circuits. Discontinuous operation assures
the inductor current remains positive and is required to
start up into a prebiased load.
The LTC3887 is very similar in features to the LTC3880.
The major improvements are as follows:
n TINIT start-up time 30ms
n tON(MIN) reduced to 45ns to support higher step down
ratios
n VOUT0/VOUT1 are both programmable up to 5.5 Volts
n
PWM synchronization circuit, review Frequency and
Phasing section for details
n MFR_ADC_CONTROL for fast ADC sampling of one
parameter. See PMBus Command Details.
n PMBus compliant to version 1.2 which adds PAGE _PLUS
and SMBALERT mask. See PMBus Command Details.
n
Improved fault logging. See PMBus Command Details.
n Share EA for channel 0/1 for 2-phase operation
n
Resistor configuration pins modified. There are two
Address select pins, VOUTn_CONFIG, PHAS_CONFIG and
FREQ_CONFIG. The VOUTn_TRIM pins were removed.
The LTC3887 digital interface is compatible with PMBus
which supports bus speeds of up to 400kHz. A typical
application circuit is shown on the first page of this data
sheet.
Major features include:
n Programmable Output Voltage
n Programmable Input Voltage Comparator
n Programmable Current Limit
n Programmable Switching Frequency
n Programmable OV and UV Comparators
n Programmable On and Off Delay Times
n Programmable Output Rise/Fall Times
n
Phase-Locked Loop for Synchronous, Polyphase
Operation (2, 3, 4 or 6 Phases)
n
Input and Output Voltage/Current, Temperature and
Duty Cycle Telemetry
n Fully Differential Load Sense
n Integrated Gate Drivers (LTC3887)
n Non-Volatile Configuration Memory with ECC
n
Optional External Configuration Resistors for Key
Operating Parameters
n Optional Time-Base Interconnect for Synchronization
Between Multiple Controllers
n Fault Logging
n WP Pin to Protect Internal Configuration
n Standalone Operation After User Factory Configuration
n PMBus, 400kHz Compliant Interface
The PMBus interface provides access to important power
management data during system operation including:
n Internal Die Temperature
n External System Temperature via Optional Diode Sense
Elements
n Average Output Current
n Average PWM Duty Cycle
n Average Output Voltage
n Average Input Voltage
n Average Input Current
n Configurable, Latched and Unlatched Individual Fault
and Warning Status
Individual channels are accessed through the PMBus
using the PAGE command, i.e., PAGE 0 or 1.
LTC3887/LTC3887-1/
LTC3887-2
17
Rev. F
For more information www.analog.com
OPERATION
Fault reporting and shutdown behavior are fully configu-
rable. Two individual GPIO outputs are provided (GPIO0,
GPIO1), both of which can be masked independently.
A dedicated pin for ALERT is provided. The shutdown
operation also allows all faults to be individually masked
and can be operated in either unlatched (hiccup) or
latched modes.
Individual status commands enable fault reporting over
the serial bus to identify the specific fault event. Fault or
warning detection includes the following:
n Output Undervoltage/Overvoltage
n Input Undervoltage/Overvoltage
n Input and Output Overcurrent
n Internal Overtemperature
n External Overtemperature
n Communication, Memory or Logic (CML) Fault
MAIN CONTROL LOOP
The LTC3887 is a constant frequency, current mode step-
down controller containing two channels operating with
various user-defined relative phasing. During normal
operation each top MOSFET is turned on when the clock
for that channel sets the RS latch, and turned off when
the main current comparator, ICMP
, resets the RS latch.
The peak inductor current at which ICMP resets the RS
latch is controlled by the voltage on the ITH pin which is
the output of each error amplifier, EA. The EA negative
terminal is equal to the VSENSE voltage divided by 5.5
(2.75 if range = 1). The positive terminal of the EA is
connected to the output of a 12-bit DAC with values
ranging from 0V to 1.024V. The output voltage, through
feedback of the EA, will be regulated to 5.5 times the
DAC output (2.75 times if range = 1). The DAC value is
calculated by the part to synthesize the users desired
output voltage. The output voltage is programmed by the
user either with the resistor configuration pins detailed in
Table3 or by the VOUT command (either from EEPROM
or by PMBus command). Refer to the PMBus command
section of the data sheet or the PMBus specification for
more details. The output voltage can be modified by the
user at any time with a PMBus VOUT_COMMAND. This
command will typically have a latency less than 10ms.
The user is encouraged to reference the PMBus Power
System Management Protocol Specification to under-
stand how to program the LTC3887. This specification
can be found at http://www.pmbus.org/specs.html.
Continuing the basic operation description, the current
mode controller will turn off the top gate when the peak
current is reached. If the load current increases, VSENSE
will slightly droop with respect to the DAC reference. This
causes the I
TH
voltage to increase until the average induc-
tor current matches the new load current. After the top
MOSFET has turned off, the bottom MOSFET is turned
on. In continuous conduction mode, the bottom MOSFET
stays on until the end of the switching cycle.
EEPROM (NVM)
The LTC3887 contains internal EEPROM with Error
Correction Coding (ECC) or NVM (nonvolatile memory)
to store configuration settings and fault log information.
EEPROM endurance retention and mass write operation
time are specified in the Electrical Characteristics and
Absolute Maximum Ratings sections. Write operations
above TJ = 85°C are possible although the Electrical
Characteristics are not guaranteed and the EEPROM will
be degraded. Read operations performed at temperatures
between –40°C and 125°C will not degrade the EEPROM.
Writing to the EEPROM above 85°C will result in a degra-
dation of retention characteristics. The fault logging func-
tion, which is useful in debugging system problems that
may occur at high temperatures, only writes to fault log
EEPROM locations. If occasional writes to these registers
occur above 85°C, the slight degradation in the data reten-
tion characteristics of the fault log will not take away from
the usefulness of the function.
It is recommended that the EEPROM not be written when
the die temperature is greater than 85°C. If the die tem-
perature exceeds 130°C, the LTC3887 will disable all
EEPROM write operations. All EEPROM write operations
will be re-enabled when the die temperature drops below
125°C. (The controller will also disable when the die tem-
perature exceeds the internal overtemperature fault limit
160°C with a 10°C hysteresis).
LTC3887/LTC3887-1/
LTC3887-2
18
Rev.F
For more information www.analog.com
OPERATION
The degradation in EEPROM retention for temperatures
>125°C can be approximated by calculating the dimen-
sionless acceleration factor using the following equation:
AF =e
Ea
k
⎛
⎝
⎜⎞
⎠
⎟•1
TUSE+273–1
TSTRESS+273
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢⎤
⎦
⎥
where:
AF = acceleration factor
Ea = activation energy = 1.4eV
K = 8.617 • 10–5 eV/°K
TUSE = 125°C specified junction temperature
TSTRESS = actual junction temperature in °C
Example: Calculate the effect on retention when operating
at a junction temperature of 135°C for 10 hours.
TSTRESS = 130°C
TUSE = 125°C
AF= e[(1.4/8.617 • 10–5) • (1/398 – 1/403)] = 1.66
The equivalent operating time at 125°C = 16.6 hours.
Thus the overall retention of the EEPROM was degraded
by 6.6 hours as a result of operating at a junction tempera-
ture of 130°C for 10 hours. The effect of the overstress is
negligible when compared to the overall EEPROM reten-
tion rating of 87,600 hours at a maximum junction tem-
perature of 125°C.
The integrity of the EEPROM is checked with a CRC calcu-
lation each time its data is read, such as after a power-on
reset or execution of a RESTORE_USER_ALL command. If
CRC error occurs, the MFR bit is set in the STATUS_BYTE
and STATUS_WORD commands. The NVM CRC error bit
in the STATUS_MFR_SPECIFIC command is set and the
ALERT and RUN pins are pulled low disabling the output
as a safety measure. The device will only respond at spe-
cial address 0x7C or global addresses 0x5A and 0x5B.
POWER UP AND INITIALIZATION
The LTC3887 and LTC3887-1 are designed to provide
standalone supply sequencing and controlled turn-on and
turn-off operation. It operates from a single input supply
(4.5V to 24V) while three on-chip linear regulators generate
internal 2.5V, 3.3V and 5V. If VIN does not exceed 6V, the
INTVCC and VIN pins must be tied together. The controller
configuration is initialized by an internal threshold based
UVLO where VIN must be approximately 4V and the 5V,
3.3V and 2.5V linear regulators must be within approxi-
mately 20% of the regulated values. The LTC3887-2 does
not have an internal regulator and requires an external 5V
supply. This also reduces the chip power, possibly reducing
die temperature. The UVLO threshold and other linear regu-
lators operate the same as the LTC3887 and LTC3887-1.
During initialization, the external configuration resistors
are identified and/or contents of the EEPROM are read
into the controller’s commands. The GPIOn pins are in
high impedance (Hi-Z) mode. The TGn, BGn and RUNn
pins are held low. (The LTC3887-1 PWM pins are three-
state.) The LTC3887 will use the contents of Table3 to
Table6 to determine the resistor defined parameters. See
the Resistor Configuration section for more detail. The
resistor configuration pins only control some of the preset
values of the controller. The remaining values are pro-
grammed in EEPROM either at the factory or by the user.
If the configuration resistors are not inserted or if the
ignore RCONFIG bit is asserted (bit 6 of the MFR_
CONFIG_ALL_LTC3887 configuration command), the
LTC3887 will use only the contents of EEPROM to deter-
mine the DC/DC characteristics. The ASEL0 and 1 values
read at power-up or reset or after a RESTORE_USER _ALL
command are always respected unless the pins are open.
See the Applications Information section for more detail.
After the part has initialized, an additional comparator
monitors VIN. The VIN_ON threshold must be exceeded
before the output power sequencing can begin. After VIN
is initially applied, the part will typically require 30ms to
initialize and begin the TON_DELAY timer. The readback of
voltages and currents require an additional 0ms to 90ms.
SOFT-START
The part must enter the run state prior to soft-start.
The run pins are released by the LTC3887 after the part
initializes and VIN is greater than the VIN_ON threshold.
If multiple LTC3887s are used in an application, they all
hold their respective run pins low until all devices initialize
and VIN exceeds the VIN_ON threshold for every device.
LTC3887/LTC3887-1/
LTC3887-2
19
Rev. F
For more information www.analog.com
OPERATION
The SHARE_CLK pin assures all the devices connected to
the signal use the same time base. The SHARE_CLK pin
is held low until the part has initialized after VIN is applied
and V
IN
exceeds the VIN_ON threshold. The LTC3887 can
be set to turn off (or remain off) if SHARE_CLK is low
(set bit 2 of MFR_CHAN_CONFIG_LTC3887 to a 1). This
allows the user to assure synchronization across numer-
ous ADI ICs even if the RUN pins can not be connected
together due to board constraints. In general, if the user
cares about synchronization between chips it is best to
connect all the respective RUN pins together and to con-
nect all the respective SHARE_CLK pins together. This
assures all chips begin sequencing at the same time and
use the same time base.
After the RUN pin releases and prior to entering a con-
stant output voltage regulation state, the LTC3887 per-
forms a monotonic initial ramp or “soft-start”. Soft-start
is performed by actively regulating the load voltage while
digitally ramping the target voltage from 0V to the com-
manded voltage set-point. Once the LTC3887 is com-
manded to turn on, (after power up and initialization)
the controller waits for the user specified turn-on delay
(TON_DELAY) prior to initiating this output voltage ramp.
The rise time of the voltage ramp can be programmed
using the TON_RISE command to minimize inrush cur-
rents associated with the start-up voltage ramp. The soft-
start feature is disabled by setting the value of TON_RISE
to any value less than 0.25ms. The LTC3887 PWM always
uses discontinuous mode during the TON_RISE opera-
tion. In discontinuous mode, the bottom gate is turned
off as soon as reverse current is detected in the inductor.
In the LTC3887-1 this causes the TG pin to three-state.
This will allow the regulator to start up into a prebiased
load. When the TON_MAX_FAULT_LIMIT is reached, the
part transitions to continuous mode, if so programmed.
If TON_MAX_FAULT_LIMIT is set to zero, there is no time
limit and the part transitions to the desired conduction
mode after TON_RISE completes and VOUT has exceeded
the VOUT_UV_FAULT_LIMIT and IOUT_OC is not pres-
ent. Setting TON_MAX_FAULT_LIMIT to a value of 0 is
not recommended. This described method of start-up
sequencing is time based.
SEQUENCING
The default mode for sequencing the outputs on and off
is time based. Each output is enabled after waiting TON_
DELAY amount of time following either a RUN pin going
high, a PMBus command to turn on or the VIN rising above
a preprogrammed voltage. Off sequencing is handled in a
similar way. To assure proper sequencing, make sure all
ICs connect the SHARE_CLK pin together and RUN pins
together. If the RUN pins can not be connected together for
some reason, set bit 2 of MFR_CHAN_CONFIG_LTC3887
to a 1. This bit requires the SHARE_CLK pin to be clocking
before the power supply output can start. When the RUN pin
is pulled low, the LTC3887 will hold the pin low for the MFR_
RESTART_DELAY. The minimum MFR_RESTART_DELAY
is TOFF_DELAY + TOFF_FALL + 136ms. This delay assures
proper sequencing of all rails. The LTC3887 calculates
this delay internally and will not process a shorter delay.
However, a longer commanded MFR_RESTART_DELAY
will be used by the part. The maximum allowed value is
65.52 seconds.
EVENT-BASED SEQUENCING
The GPIOn pins can be asserted when the UV threshold is
exceeded for each output. It is possible to feed the GPIO
pin from one output into the RUN pin of the next output
in the sequence. To use the GPIOn pin for voltage based
sequencing, set bit 12 of the MFR_GPIOn_PROPAGATE
command = 1. Bit 12 is the VOUT_UVUF which is the
unfiltered VOUT_UV comparator. Using the unfiltered
VOUT_UV fault limit is recommended because there is
little appreciable time delay between the comparator
crossing the UV threshold and the GPIO pin releasing
This can be implemented across multiple LTC3887s. The
Figure2. Event (Voltage) Based Sequencing
Voltage Based Sequencing by Cascading GPIOs into RUN Pins
GPIO0 = V
OUT0_UVUF
GPIO1 = V
OUT1_UVUF
RUN 1
RUN 0
START
LTC3887/
LTC3887-1
3887 F02
RUN 0 GPIO0 = V
OUT0_UVUF
GPIO1 = V
OUT1_UVUF
TO NEXT CHANNEL
IN THE SEQUENCE
RUN 1
LTC3887/
LTC3887-1
LTC3887/LTC3887-1/
LTC3887-2
20
Rev.F
For more information www.analog.com
OPERATION
VOUT_UVUF has a 70µs filter. If the V
OUT
voltage bounces
around the UV threshold for a long period of time it is
possible for the GPIO output to toggle more than once.
To minimize this problem, set the TON_RISE time under
100ms. If a fault in the string of rails is detected, only the
faulted rail and downstream rails will fault off. The rails in
the string of devices in front of the faulted rail will remain
on unless commanded off.
SHUTDOWN
The LTC3887 supports two shutdown modes. The first
mode is closed-loop shutdown response, with user-
defined turn-off delay (TOFF_DELAY) and ramp down rate
(TOFF_FALL). The controller will maintain the mode of
operation for TOFF_FALL. In discontinuous conduction
mode, the controller will not draw current from the load
and the fall time will be set by the output capacitance and
load current.
The other shutdown mode occurs in response to a fault
condition or loss of SHARE_CLK (if bit 2 of MFR_CHAN_
CONFIG_LTC3887 is set to a 1) or VIN falling below the
VIN_OFF threshold or GPIO pulled low externally (if the
MFR_GPIO_RESPONSE is set to inhibit). Under these
conditions the power stage is disabled in order to stop
the transfer of energy to the load as quickly as possible.
The shutdown state can be entered from the soft-start or
active regulation states either through user intervention
(deasserting RUNn or the PMBus OPERATION command)
or in response to a detected fault or an external fault via
the bidirectional GPIOn pins, or loss of SHARE_CLK (if
bit 2 of MFR_CHAN_CONFIG_LTC3887 is set to a 1) or
VIN falling below the VIN_OFF threshold.
In hiccup mode, the controller responds to a fault by
shutting down and entering the inactive state for a
programmable delay time (MFR_RETRY_DELAY). This
delay minimizes the duty cycle associated with autono-
mous retries if the fault that caused the shutdown disap-
pears once the output is disabled. The retry delay time
is determined by the longer of the MFR_RETRY_DELAY
command or the time required for the regulated output
to decay below 12.5% of the programmed value. If mul-
tiple outputs are controlled by the same GPIO pin, the
decay time of the faulted output determines the retry
delay. If the natural decay time of the output is too long,
it is possible to remove the voltage requirement of the
MFR_RETRY_DELAY command by asserting bit 0 of
MFR_CHAN_CONFIG_LTC3887. Alternatively, the con-
troller can be configured so that it remains latched-off
following a fault and clearing requires user intervention
such as toggling RUNn or commanding the part OFF
then ON.
LIGHT LOAD CURRENT OPERATION
The LTC3887 has two modes of operation including discon-
tinuous conduction mode and forced continuous conduc-
tion mode. Mode selection is done using the MFR_PWM_
MODE_LTC3887 command (discontinuous conduction is
always the start-up mode, forced continuous is the default
running mode).
If a controller is enabled for discontinuous operation, the
inductor current is not allowed to reverse. The reverse
current comparator, IREV
, turns off the bottom gate exter-
nal MOSFET just before the inductor current reaches
zero, preventing it from reversing and going negative.
The LTC3887-1 three-states the TG pin to accomplish the
same result. In forced continuous operation, the inductor
current is allowed to reverse at light loads or under large
transient conditions. The peak inductor current is deter-
mined solely by the voltage on the ITH pin. In this mode,
the efficiency at light loads is lower than in discontinu-
ous mode operation. However, continuous mode exhibits
lower output ripple and less interference with audio cir-
cuitry. Forced continuous conduction mode may result in
reverse inductor current, which can cause the input sup-
ply to boost. The VIN_OV_FAULT_LIMIT can detect this
and turn off the offending channel. However, this fault is
based on an ADC read and can take up to 120ms to detect.
If there is a concern about the input supply boosting, keep
the part in discontinuous conduction operation.
If the part is set to discontinuous mode operation, as
the inductor average current increases, the controller will
automatically modify the operation from discontinuous
mode to continuous mode.
LTC3887/LTC3887-1/
LTC3887-2
21
Rev. F
For more information www.analog.com
OPERATION
SWITCHING FREQUENCY AND PHASE
The switching frequency of the LTC3887’s controller can
be established with internal clock references or with an
external time-base. The LTC3887 can be configured for
an external clock input through the programmed value in
EEPROM, a PMBus command or setting the SYNC out-
put to disable with the PHAS_CFG pin. The MFR_PWM_
CONFIG_LTC3887 command determines the relative phas-
ing. The rails should be selected to be out of phase with
each other. Both RUN pins must be low or both channels
commanded off before the FREQUENCY and MFR_
PWM_CONFIG_LTC3887 commands can be written to
the LTC3887. The relative phasing of all devices in a
PolyPhase rail should be optimally phased. The relative
phasing of each rail is 360/n where n is the number of
phases in the rail.
The LTC3887 will automatically accept an external SYNC
input, disabling its own SYNC output if necessary, as long
as the external clock frequency is greater than 1/2 of the
internal PWM clock. Whether configured to drive SYNC
output or not, the LTC3887 can continue PWM operation
using its own internal oscillator if an external clock signal
is subsequently lost.
If the LTC3887 is configured as the oscillator output
on SYNC, SYNC ENABLED, the switching frequency
source can be selected with either external configuration
resistors or through serial bus programming. The
FREQ_CFG configuration resistor pin can be used to
select the FREQUENCY_SWITCH. The PHAS_CFG pin
can be used to set the MFR_PWM_CONFIG_LTC3887
and enable the SYNC output to produce the output
frequency as outlined in Table4 and Table5. Otherwise,
the FREQUENCY_SWITCH and MFR_PWM_CONFIG_
LTC3887 PMBus commands can be used to select
PWM switching frequency and the PWM channel phase
relationship. The phase and frequency relationships are
completely independent of each other providing the
numerous application options for the user.
If the LTC3887 is configured to drive the SYNC output
by setting bit 4 of MFR_CONFIG_ALL_LTC3887 to a 0
the SYNC pin will pull low at the desired clock rate, set
with the FREQUENCY_SWITCH command, with 500ns
low pulse. Care must be taken in the application to
assure the capacitance on SYNC is minimized to assure
the pull-up resistor versus the capacitor load has a low
enough time constant for the application. In addition,
a phase-locked loop (PLL) is available to synchronize
the internal oscillator to an external clock source that is
connected to the SYNC pin. All phase relationships are
between the falling edge of SYNC and the rising edge
of the LTC3887 TG outputs. Multiple LTC3887s can be
synchronized in order to realize PolyPhase arrays.
OUTPUT VOLTAGE SENSING
The channel 0 differential amplifier allows remote, dif-
ferential sensing of the load voltage with VSENSE0n pins.
The channel 1 sense pin (VSENSE1) is referenced to GND.
The telemetry ADC is fully differential and makes mea-
surements of channels 0 and 1 output voltages at the
VSENSE0n and VSENSE1/GND pins, respectively. The maxi-
mum allowed sense voltage is 5.5V.
CURRENT SENSING
For DCR current sense applications, a resistor in series
with a capacitor is placed across the inductor. In this
configuration, the resistor is tied to the FET side of the
inductor while the capacitor is tied to the load side of the
inductor as shown in Figure3. If the RC values are cho-
sen such that the RC time constant matches the inductor
time constant (L/DCR, where DCR is the inductor series
resistance), the resultant voltage appearing across the
capacitor will equal the voltage across the inductor series
resistance (VDCR) and thus represent the current flowing
through the inductor. The RC calculations are based on
the room temperature DCR of the inductor.
The RC time constant should remain constant, as a func-
tion of temperature. This assures the transient response of
the circuit is the same regardless of the temperature. The
DCR of the inductor has a large temperature coefficient,
approximately 3900ppm/°C. The temperature coefficient
of the inductor must be written to the MFR_IOUT_CAL_
GAIN_TC register. The external temperature is sensed near
the inductor and used to modify the internal current limit
circuit to maintain an essentially constant current limit with
temperature. In this application, the ISENSEn+ pin is con-
nected to the power stage side of the capacitor while the
LTC3887/LTC3887-1/
LTC3887-2
22
Rev.F
For more information www.analog.com
Figure3. Load Sharing Connections for 3-Phase Operation
LTC3887/LTC3887-1
+ POWER STAGE
ITH0
1/2 LTC3887/LTC3887-1
+ POWER STAGE
ITH0
VDD33
NOTE: SOME CONNECTORS
AND COMPONENTS OMITTED
FOR CLARITY
BOTH CHIPS HAVE THE INTERNAL
FREQUENCY COMMAND SET TO THE
SAME DESIRED PWM FREQUENCY
ISENSE0+
ISENSE0–
VSENSE0+
VSENSE0–
ITH1
10k
GPIO0
RUN0
RUN1
ALERT
GPIO1
SYNC(Enabled)
SHARE_CLK
VDD33
RUN0
ALERT
GPIO1
SYNC(Disabled)
SHARE_CLK
ISENSE0+
ISENSE0–
ISENSE1+
ISENSE1–
VSENSE1
GND
1µF
GND
3887 F03
VSENSE0+
VSENSE0–
1µF
LOAD
10k10k4.99k10k
RUN
SHARE_CLK
ALERT
GPIO
SYNC
Figure4. Temperature Sense Circuit
TSNS
MMBT3906
LTC3887/
LTC3887-1 10nF
GND
SGND
3887 F04
OPERATION
ISENSEn– pin is placed on the load side of the capacitor.
The current sensed from the input is then given by the
expression VDCR/DCR. VDCR is digitized by the LTC3887’s
telemetry ADC with an input range of ±128mV, a noise
floor of 7µVRMS, and a peak-peak noise of approximately
46.5µV. The LTC3887 computes the inductor current
using the DCR value stored in the IOUT_CAL_GAIN com-
mand and the temperature coefficient stored in command
MFR_IOUT_CAL_GAIN_TC. The resulting current value is
returned by the READ_IOUT command.
POLYPHASE LOAD SHARING
Multiple LTC3887’s can be arrayed in order to provide a
balanced load-share solution by bussing the necessary
pins. Figure3. Load Sharing Connections for 3-Phase
Operation illustrates the shared connections required for
load sharing.
If an external oscillator is not provided, the SYNC out-
put should only be enabled on one of the LTC3887s. The
other(s) should be programmed to disable the SYNC out-
put using bit 4 of MFR_CONFIG_ALL_LTC3887. Set the
oscillator to the desired PWM frequency in both chips. If
an external oscillator is present, the chip with the SYNC
output enabled will detect the presence of the external
clock and stop driving the SYNC output.
The error amp of two PWM controls on the same chip
can be shared by asserting bit 7 of MFR_PWM_CONFIG_
LTC3887. Both error amps remain in the circuit so the
loop gain does not change. Do not assert this bit unless
both VOUT pins are connected together and both ITH pins
are tied together in the application. This allows remote
differential voltage sensing for PolyPhase rails.
EXTERNAL/INTERNAL TEMPERATURE SENSE
External temperature can be best measured using a remote
diode-connected PNP transistor such as the MMBT3906.
The emitter should be connected to the TSNSn pin while
the base and collector terminals of the PNP transistor
must be connected and returned directly to the LTC3887’s
LTC3887/LTC3887-1/
LTC3887-2
23
Rev. F
For more information www.analog.com
OPERATION
GND pin. Place the PNP in close proximity to the induc-
tor to accurately measure the inductor temperature.
For best noise immunity, the connections should be routed
differentially and a 10nF capacitor should be placed in
parallel with the diode connected PNP. Two different currents
are applied to the diode (nominally 2µA and 32µA) and the
temperature is calculated from the ∆VBE measurement. The
external transistor temperature is digitized by the telem-
etry ADC, and the value is returned by the PMBus READ_
TEMPERATURE_1 (Chn) command.
The READ_TEMPERATURE_2 command returns the junc-
tion temperature of the LTC3887 using an on-chip diode.
The slope of the external temperature sensor can be
modified with the temperature slope coefficient stored in
MFR_TEMP_1_GAIN. Typical PNPs require temperature
slope adjustments slightly less than 1. The MMBT3906 has
a recommended value in this command of approximately
MFR_TEMP_1_GAIN = 0.991 based on the ideality factor
of 1.01. Simply invert the ideality factor to calculate the
MFR_TEMP_1_GAIN. Different manufacturers and differ-
ent lots may have different ideality factors. Consult with
the manufacturer to set this value.
The offset of the external temperature sense can be
adjusted by MFR_TEMP_1_OFFSET. A value of 0 in this
register sets the temperature offset to –273.15°C.
If the PNP cannot be placed in direct contact with the
inductor, the slope or offset can be increased to account
for temperature mismatches. If the user is adjusting the
slope, the intercept point is at absolute zero, –273.15°C,
so small adjustments in slope can change the appar-
ent measured temperature significantly. Another way to
artificially increase the slope of the temperature term is
to increase the MFR_IOUT_CAL_GAIN_TC term. This
will modify the temperature slope with respect to room
temperature.
RCONFIG (RESISTOR CONFIGURATION) PINS
There are six input pins utilizing 1% resistor dividers
between V
DD25
and GND to select key operating param-
eters. The pins are ASEL0, ASEL1, FREQ_CFG, VOUT0_CFG,
VOUT1_CFG, PHAS_CFG. If pins are floated, the value stored
in the corresponding EEPROM command is used. If bit 6 of
the MFR_CONFIG_ALL_LTC3887 configuration command
is asserted in EEPROM, the resistor inputs are ignored
upon power-up except for ASEL0 and ASEL1 which are
always respected. The resistor configuration pins are only
measured during a power-up reset, after an MFR_RESET or
after a RESTORE_USER_ALL command is executed.
The VOUTn_CFG pin settings are described in Table3. These
pins select the output voltages for the LTC3887’s analog
PWM controllers. If the pin is open, the VOUT_COMMAND
command is loaded from EEPROM to determine the out-
put voltage. The default factory EEPROM setting is to have
the switcher off unless the voltage configuration pins are
installed. The user may reprogram the EEPROM to the
desired setting for the application. When the EEPROM
configuration is loaded, it is recommended the user assert
bit 6 of MFR_CONFIG_ALL_LTC3887 to disable the resis-
tor configuration pins for all subsequent reset operations.
The following parameters are set as a percentage of the
output voltage if the RCONFIG pins are used to deter-
mined output voltage:
n VOUT_OV_FAULT_LIMIT .................................... +10%
n VOUT_OV_WARN .............................................. +7.5%
n VOUT_MAX....................................................... +7.5%
n VOUT_MARGIN_HIGH ......................................+5%%
n VOUT_MARGIN_LOW ..........................................–5%
n VOUT_UV_WARN ..............................................–6.5%
n VOUT_UV_FAULT_LIMIT ......................................–7%
The FREQ_CFG pin settings are described in Table5. This
pin selects the switching frequency. The phase relationships
between the two channels and SYNC pin is determined by
the PHAS_CFG pin described in Table4. To synchronize to
an external clock, the part should be put into external clock
mode (SYNC output disabled but frequency set to the nominal
value). If no external clock is supplied, the part will clock at
the programmed frequency. If the application is multi-phase
and the SYNC signal between chips is lost, the parts will not
be at the same frequency increasing the ripple voltage on
the output, possibly producing undesirable operation. If the
SYNC signal is being generated internally and SYNC output
enabled is not selected, bit 10 of MFR_PADS_LTC3887 will
be asserted. If no frequency is selected and the external SYNC
frequency is not present, a PLL_FAULT will occur. If the user
does not wish to see the ALERT from a PLL_FAULT even
if there is not a valid synchronization signal at power-up,
LTC3887/LTC3887-1/
LTC3887-2
24
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OPERATION
the ALERT mask for PLL_FAULT must be written. See the
description on SMBALERT_MASK for more details. If the
SYNC pin is connected between multiple ICs only one of the
ICs should should have the SYNC output enabled, all other
ICs should be configured to SYNC output disabled.
The ASEL0 and 1 pin settings are described in Table6.
ASLE1 selects the top three bits of the slave address for
the LTC3887. If ASEL1 is floating, the three most signifi-
cant bits are retrieved from the EEPROM MFR_ADDRESS
command. ASEL0 selects the bottom four bits of the
slave address for the LTC3887. If ASEL0 is floating, the
four LSB bits stored in EEPROM MFR_ADDRESS com-
mand are used to determine the four LSB bits of the slave
address. For more detail, refer to Table6.
Note: Per the PMBus specification, pin programmed
parameters can be overridden by commands from the
digital interface with the exception of ASEL0 and ASEL1
which are always honored. Do not set any part address
to 0x0C, 0x5A, 0x5B or 0x7C because these are global
addresses and all ADI PMBus parts may respond to them.
FAULT DETECTION AND HANDLING
A variety of fault and warning reporting and handling
mechanisms are available. Fault and warning detection
capabilities include:
n Input OV/FAULT Protection and UV Warning
n Average Input OC Warn
n Output OV/UV Fault and Warn Protection
n Output OC Fault and Warn Protection
n Internal and External Overtemperature Fault and Warn
Protection
n External Undertemperature Fault Protection
n CML Fault (Communication, Memory or Logic)
n External Fault Detection via the Bidirectional GPIOn Pins.
In addition, the LTC3887 can map any combination of
fault indicators to their respective GPIOn pin using the
propagate GPIOn response commands, MFR_GPIO_
PROPAGATE_LTC3887. Typical usage of a GPIO pin is as
a driver for an external crowbar device, overtemperature
alert, overvoltage alert or as an interrupt to cause a micro-
controller to poll the fault commands. Alternatively, the
GPIOn pins can be used as inputs to detect external faults
downstream of the controller that require an immediate
response. The GPIO0 and/or GPIO1 pins can also be con-
figured as power good outputs. Power good indicates the
controller output is within the OV/UV fault thresholds. At
power-up the pin will initially be three-state. If it is neces-
sary to have the desired polarity on the pin at power-up
in this configuration, attach a Schottky diode between the
RUN pin of the propagated power good signal and the
GPIO pin. The Cathode must be attached to RUN and the
Anode to the GPIO pin. If the GPIO pin is set to a power
good status, the MFR_GPIO_RESPONSE must be ignore
otherwise a latched off condition exists.
As described in the Soft-Start section, it is possible to control
start-up through concatenated events. If GPIOn is used to
drive the RUN pin of another controller, the unfiltered VOUT_
UV fault limit should be mapped to the GPIO pin.
Any fault or warning event will cause the ALERT pin to assert
low unless the ALERT is masked by the SMBALERT_MASK
command. The pin will remain asserted low until the CLEAR_
FAULTS command is issued, the fault bit is written to a 1, the
PMBus master successfully reads the device ARA register,
bias power is cycled a MFR_RESET or RESTORE_USER_ALL
command is issued. Channel specific faults are cleared if the
RUN pins are toggled OFF/ON or the part is commanded
OFF/ON via PMBus. If bit 0 of MFR_CONFIG_ALL_LTC3887
is set to a 1, toggling the RUN pins OFF/ON or command-
ing the part OFF/ON via PMBus clears all faults. The MFR_
GPIO_PROPAGATE_LTC3887 command determines if the
GPIO pins are pulled low when a fault is detected; however,
the ALERT pin is always pulled low if a fault or warning is
detected and the status bits are updated unless the ALERT pin
is masked using the SMBALERT_MASK command.
Output and input fault event handling is controlled by the
corresponding fault response byte as specified in Table10
to Table14. Shutdown recovery from these types of faults
can either be autonomous or latched. For autonomous
recovery, the faults are not latched, so if the fault condi-
tion is not present after the retry interval has elapsed,
a new soft-start is attempted. If the fault persists, the
controller will continue to retry. The retry interval is speci-
fied by the MFR_RETRY_DELAY command and prevents
LTC3887/LTC3887-1/
LTC3887-2
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Rev. F
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OPERATION
damage to the regulator components by repetitive power
cycling. The MFR_RETRY_DELAY must be greater than
120ms. It can not exceed 83.88 seconds.
Channel-to-channel fault dependencies can be created by
connecting GPIOn pins together. In the event of an internal
fault, one or more of the channels is configured to pull the
bussed GPIOn pins low. The other channels are then con-
figured to shut down when the GPIOn pins are pulled low.
For autonomous group retry, the faulted channel is con-
figured to release the GPIOn pin(s) after a retry interval,
assuming the original fault has cleared. All the channels
in the group then begin a soft-start sequence. If the fault
response is LATCH_OFF, the GPIO pin remains asserted
low until either the RUN pin is toggled OFF/ON or the part
is commanded OFF/ON. The toggling of the RUN either
by the pin or OFF/ON command will clear faults associ-
ated with the channel. If it is desired to have all faults
cleared when either RUN pin is toggled, set bit 0 of MFR_
CONFIG_ALL_LTC3887 to a 1.
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
Additional fault detection and handling capabilities are:
Internal EEPROM with CRC Protection and ECC
The LTC3887 contains internal EEPROM with Error
Correction Coding (ECC) to store user configuration set-
tings and fault log information. EEPROM endurance and
retention for user space and fault log pages are speci-
fied in the Absolute Maximum Ratings and Electrical
Characteristics table.
The integrity of the EEPROM memory is checked with a
CRC calculation each time its data is to be read, such as
after a power-on reset. A CRC error will prevent the con-
troller from leaving the OFF state. If a CRC error occurs,
the CML bit is set in the STATUS_BYTE and STATUS_
WORD commands, the appropriate bit is set in the
STATUS_MFR_SPECIFIC command, and the ALERT and
RUN pins will be pulled low. At that point the device will
respond at special address 0x7C, which is only activated
after an invalid CRC has been detected. The chip will also
respond to global addresses 0x5A and 0x5B, but all ADI
PSM chips will respond to these addresses so users must
be careful when using global addresses. EEPROM repair
can be attempted by writing the desired configuration to
the controller and executing a STORE_USER_ALL com-
mand followed by a CLEAR_FAULTS command. Contact
the factory if EEPROM repair is unsuccessful.
See the Applications Information section or contact the
factory for details on efficient in-system EEPROM pro-
gramming, including bulk EEPROM programming, which
the LTC3887 also supports.
SERIAL INTERFACE
The LTC3887 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using either the
EEPROM or an external resistor divider. In addition the
LTC3887 always responds to the global broadcast address
of 0x5A (7 bit) or 0x5B (7 bit). Address 0x5A is not paged
and is performed on both channels. 0x5B respects the page
command. Because address 0x5A does not support page,
it can not be used for any paged reading commands.
The serial interface supports the following protocols
defined in the PMBus specifications: 1) send command,
2) write byte, 3) write word, 4) group, 5) read byte, 6)
read word and 7) read block 8) PAGE_PLUS_READ,
9) PAGE_PLUS_WRITE 10) SMBALERT_MASK read,
11) SMBALERT_MASK write. All read operations will return
a valid PEC if the PMBus master requests it. If the PEC_
REQUIRED bit is set in the MFR_CONFIG_ALL_LTC3887
command, the PMBus write operations will not be acted
upon until a valid PEC has been received by the LTC3887.
Communication Protection
PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.
DEVICE ADDRESSING
The LTC3887 offers four different types of addressing over
the PMBus interface, specifically: 1) global, 2) device, 3)
rail addressing and 4) alert response address (ARA).
LTC3887/LTC3887-1/
LTC3887-2
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OPERATION
Global addressing provides a means of the PMBus master to
address all LTC3887 devices on the bus. The LTC3887 global
address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and cannot be
disabled. Commands sent to the global address act the same
as if PAGE is set to a value of 0xFF. Commands sent are writ-
ten to both channels simultaneously. Global command 0x5B
(7 bit) or 0xB6 (8 bit) is paged and allows channel specific
command of all LTC3887 devices on the bus. Other ADI device
types may respond at one or both of these global addresses;
therefore do not read from global addresses.
Rail addressing provides a means for the bus master to
simultaneously communicate with all channels connected
together to produce a single output voltage (PolyPhase).
While similar to global addressing, the rail address can
be dynamically assigned with the paged MFR_RAIL_
ADDRESS command, allowing for any logical grouping
of channels that might be required for reliable system
control. Do not read from rail addresses because multiple
ADI devices may respond.
Device addressing provides the standard means of the
PMBus master communicating with a single instance of
an LTC3887. The value of the device address is set by a
combination of the ASEL0 and ASEL1 configuration pins
and the MFR_ADDRESS command. When this addressing
means is used, the PAGE command determines the chan-
nel being acted upon. Device addressing can be disabled
by writing a value of 0x80 to the MFR_ADDRESS.
All four means of PMBus addressing require the user
to employ disciplined planning to avoid addressing
conflicts.
Communication to LTC3887 devices at global
and rail addresses should be limited to command write
operations.
RESPONSES TO VOUT AND IOUT FAULTS
VOUT OV and UV conditions are monitored by compara-
tors. The OV and UV limits are set in three ways.
n
As a Percentage of the VOUT if Using the Resistor
Configuration Pins
n In EEPROM if Either Programmed at the Factory or
Through the GUI
n By PMBus Command
The IIN and IOUT overcurrent monitors are performed by
ADC readings and calculations. Thus these values are
based on average currents and can have a time latency of
up to 120ms. The IOUT calculation accounts for the sense
resistor and the temperature coefficient of the resistor.
The input current is equal to the sum of output current
times the respective channel duty cycle plus the input
offset current for each channel. If this calculated input
current exceeds the IN_OC_WARN_LIMIT the ALERT pin
is pulled low and the IIN_OC_WARN bit is asserted in the
STATUS_INPUT register.
The LTC3887 provides the ability to ignore the fault, shut
down and latch off or shut down and retry indefinitely
(hiccup). The retry interval is set in MFR_RETRY_DELAY
and can be from 120ms to 83.88 seconds in 1ms incre-
ments. The shutdown for OV/UV and OC can be done
immediately or after a user selectable deglitch time.
Output Overvoltage Fault Response
A programmable overvoltage comparator (OV) guards
against transient overshoots as well as long-term over-
voltages at the output. In such cases, the top MOSFET is
turned off and the bottom MOSFET is turned on until the
overvoltage condition is cleared regardless of the PMBus
VOUT_OV_FAULT_RESPONSE command byte value. This
hardware level fault response delay is typically 2µs from
the overvoltage condition to BG asserted high. Using the
VOUT_OV_FAULT_RESPONSE command, the user can
select any of the following behaviors:
n OV Pull-Down Only (OV cannot be ignored)
n Shut Down (Stop Switching) Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely using the
Time Interval Specified in MFR_RETRY_DELAY
Either the Latch Off or Retry fault responses can be
deglitched in increments of (0 to 7) • 10µs. See Table10.
Output Undervoltage Response
The response to an undervoltage comparator output can
be either:
n Ignore
n Shut Down Immediately—Latch Off
LTC3887/LTC3887-1/
LTC3887-2
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n Shut Down Immediately—Retry Indefinitely using the
Time Interval Specified in MFR_RETRY_DELAY
Either the Latch Off or Retry fault responses can be
deglitched in increments of (0 to 7) • 10µs. See Table11.
Peak Output Overcurrent Fault Response
Due to the current mode control algorithm, peak output
current across the inductor is always limited on a cycle by
cycle basis. The value of the peak current limit is speci-
fied in sense voltage in the EC table. The current limit
circuit operates by limiting the ITH maximum voltage. If
DCR sensing is used, the ITH maximum voltage has a
temperature dependency directly proportional to the TC
of the DCR of the inductor. The LTC3887 automatically
monitors the external temperature sensors and modifies
the maximum allowed ITH to compensate for this term.
The overcurrent fault processing circuitry can execute the
following behaviors:
n Current Limit Indefinitely
n Shut Down Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely using the
Time Interval Specified in MFR_RETRY_DELAY
The overcurrent responses can be deglitched in incre-
ments of (0 to 7) • 16ms. SeeTable12.
RESPONSES TO TIMING FAULTS
TON_MAX_FAULT_LIMIT is the time allowed for VOUT to
rise and settle at start-up. The TON_MAX_FAULT_LIMIT
condition is predicated upon detection of the VOUT_UV_
FAULT_LIMIT as the output is undergoing a SOFT_START
sequence. The TON_MAX_FAULT_LIMIT time is started
after TON_DELAY has been reached and a SOFT_START
sequence is started. The resolution of the TON_MAX_
FAULT_LIMIT is 10µs. If the VOUT_UV_FAULT_LIMIT is
not reached within the TON_MAX_FAULT_LIMIT time,
the response of this fault is determined by the value of
the TON_MAX_FAULT_RESPONSE command value. This
response may be one of the following:
n Ignore
n Shut Down (Stop Switching) Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely using the
Time Interval Specified in MFR_RETRY_DELAY
This fault response is not deglitched. A value of 0 in
TON_MAX_FAULT_LIMIT means the fault is ignored. The
TON_MAX_FAULT_LIMIT should be set longer than the
TON_RISE time. It is recommended TON_MAX_FAULT_
LIMIT always be set to a non-zero value, otherwise the out-
put may never come up and no flag will be set to the user.
See Table14.
RESPONSES TO VIN OV FAULTS
VIN overvoltage is measured with the ADC; therefore,
the response is naturally deglitched by the 90ms typical
response time of the ADC. The fault responses are:
n Ignore
n Shut Down Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely using the
Time Interval Specified in MFR_RETRY_DELAY
See Table14.
RESPONSES TO OT/UT FAULTS
Internal Overtemperature Fault/Warn Response
An internal temperature sensor protects against EEPROM
damage. Above 85°C, no writes to EEPROM are recom-
mended. Above 130°C, the internal over temperature warn
threshold is exceeded and the part disables the EEPROM
writes and does not re-enable until the temperature has
dropped to 125°C. When the die temperature exceed
160°C the internal over temperature fault response is
enabled and the PWM is disabled until the die temperature
drops below 150°C. Temperature is measured by the ADC.
Internal temperature faults cannot be ignored. Internal
temperature limits cannot be adjusted by the user.
See Table13.
External Overtemperature and Undertemperature
Fault Response
Two external temperature sensors can be used to sense
critical circuit elements like inductors and power MOSFETs.
The OT_FAULT_RESPONSE and UT_FAULT_RESPOSE
LTC3887/LTC3887-1/
LTC3887-2
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OPERATION
commands are used to determine the appropriate response
to an overtemperature and undertemperature condition,
respectively. If no external sense elements are used
(not recommended) set the UT_FAULT_RESPONSE to
ignore and set the UT_FAULT_LIMIT to –275°C and set
the MFR_IOUT_CAL_GAIN_TC to 0.
The fault responses are:
n Ignore
n Shut Down Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely using the
Time Interval Specified in MFR_RETRY_DELAY
See Table14.
RESPONSES TO EXTERNAL FAULTS
When either GPIOn pin is pulled low, the OTHER bit is
set in the STATUS_WORD command, the appropriate bit
is set in the STATUS_MFR_SPECIFC command, and the
ALERT pin is pulled low. Responses are not deglitched.
Each channel can be configured to ignore or shut down
then retry in response to its GPIOn pin going low by mod-
ifying the MFR_GPIO_RESPONSE command. To avoid
the ALERT pin asserting low when GPIO is pulled low,
assert bit 1 of MFR_CHAN_CONFIG_LTC3887, or mask
the ALERT using the SMBALERT_MASK command.
FAULT LOGGING
The LTC3887 has fault logging capability. Data is logged
into memory in the order shown in Table2. The data to
be stored in the fault log is being continuously stored in
internal volatile memory. When a fault event occurs, the
recording into internal volatile memory is halted, the fault
log information is available from the MFR_FAULT_LOG
command, and the contents of the internal memory are
copied into EEPROM. Fault logging is allowed at tempera
-
tures above 85°C; however, retention of 10 years is not
guaranteed. When the die temperature exceeds 130°C the
fault logging is delayed until the die temperature drops
below 125°C. After the fault condition that created the
fault log event has been removed, clear the fault before the
fault log data is erased, or else the part will immediately
issue another fault log.
When the LTC3887 powers-up, it checks the
EEPROM
for a valid fault log. If a valid fault log exists in
EEPROM
,
the “Valid Fault Log” bit in the STATUS_MFR_SPECIFIC
command will be set and an ALERT event will be gener-
ated. Also, fault logging will be blocked until the LTC3887
has received a MFR_FAULT_LOG_CLEAR command
before fault logging will be re-enabled.
The information is stored in EEPROM in the event of any
fault that disables the controller on either channel. An exter-
nal GPIOn pulling low will not trigger a fault logging event.
BUS TIMEOUT PROTECTION
The LTC3887 implements a timeout feature to avoid hang-
ing the serial interface. The data packet timer begins at
the first START event before the device address write byte.
Data packet information must be completed within 25ms
or the LTC3887 will three-state the bus and ignore the
given data packet. If more time is required, assert bit 3
of MFR_CONFIG_ALL_LTC3887 to allow typical bus time-
outs of 255ms. Data packet information includes the device
address byte write, command byte, repeat start event (if a
read operation), device address byte read (if a read opera-
tion), all data bytes and the PEC byte if applicable.
The LTC3887 allows longer PMBus timeouts for block
read data packets. This timeout is proportional to the
length of the block read. The additional block read timeout
applies primarily to the MFR_FAULT_LOG command. In
no circumstances will the timeout period be less than the
tTIMEOUT_SMB specification of 32ms (typical).
The user is encouraged to use as high a clock rate as pos-
sible to maintain efficient data packet transfer between all
devices sharing the serial bus interface. The LTC3887 sup-
ports the full PMBus frequency range from 10kHz to 400kHz.
SIMILARITY BETWEEN PMBUS, SMBUS AND I2C
2-WIRE INTERFACE
The PMBus 2-wire interface is an incremental extension
of the SMBus. SMBus is built upon I2C with some minor
differences in timing, DC parameters and protocol. The
PMBus/SMBus protocols are more robust than simple I2C
byte commands because PMBus/SMBus provide time-outs
to prevent bus errors and optional packet error checking
LTC3887/LTC3887-1/
LTC3887-2
29
Rev. F
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OPERATION
(PEC) to ensure data integrity. In general, a master device
that can be configured for I2C communication can be
used for PMBus communication with little or no change
to hardware or firmware. Repeat start (restart) is not
supported by all I
2
C controllers but is required for SMBus/
PMBus reads. If a general purpose I2C controller is used,
check that repeat start is supported.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.2: Paragraph 5: Transport.
For a description of the differences between SMBus
and I2C, refer to System Management Bus (SMBus)
Specification Version 2.0: Appendix B—Differences
Between SMBus and I2C.
PMBUS SERIAL DIGITAL INTERFACE
The LTC3887 communicates with a host (master) using
the standard PMBus serial bus interface. The Timing
Diagram, Figure5, shows the timing relationship of the
signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources are required on these lines.
The LTC3887 is a slave device. The master can communi-
cate with the LTC3887 using the following formats:
n Master transmitter, slave receiver
n Master receiver, slave transmitter
The following PMBus protocols are supported:
n Write Byte, Write Word, Send Byte, Block Write
n Read Byte, Read Word, Block Read
n Alert Response Address
Figure7 to Figure23 illustrate the aforementioned PMBus
protocols. All transactions support PEC (parity error
check) and GCP (group command protocol). The Block
Read supports 255 bytes of returned data. For this reason,
the PMBus timeout may be extended when reading the
fault log.
Figure6 is a key to the protocol diagrams in this section.
PEC is optional.
A value shown below a field in the following figures is a
mandatory value for that field.
The data formats implemented by PMBus are:
n
Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
n Master reads slave immediately after the first byte. At
the moment of the first acknowledgment (provided by
the slave receiver) the master transmitter becomes a
master receiver and the slave receiver becomes a slave
transmitter.
n Combined format. During a change of direction within
a transfer, the master repeats both a start condition and
the slave address but with the R/W bit reversed. In this
case, the master receiver terminates the transfer by
generating a NACK on the last byte of the transfer and
a STOP condition.
Figure5. Timing Diagram
SDA
SCL
tHD(STA) tHD(DAT)
tSU(STA) tSU(STO)
tSU(DAT)
tLOW
tHD(SDA) tSP tBUF
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
tr
tftr
tf
tHIGH 3887 F05
LTC3887/LTC3887-1/
LTC3887-2
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Figure6. PMBus Packet Protocol Diagram Element Key
SLAVE ADDRESS DATA BYTEWr A A P
3887 F06
S
7
S START CONDITION
Sr REPEATED START CONDITION
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
x SHOWN UNDER A FIELD INDICATES THAT THAT
FIELD IS REQUIRED TO HAVE THE VALUE OF x
A ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
P STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
CONTINUATION OF PROTOCOL
81 1 1
x x
11
...
OPERATION
Figure7. Quick Command Protocol
Figure8. Send Byte Protocol
Figure9. Send Byte Protocol with PEC
SLAVE ADDRESS Rd/Wr A P
3887 F07
S
7 1 1 11
SLAVE ADDRESS COMMAND CODEWr A A P
3887 F08
S
7 81 1 1 11
SLAVE ADDRESS COMMAND CODE PECWr A A A P
3887 F09
S
7 8 81 1 1 1 11
Figure11. Write Byte Protocol with PEC
Figure10. Write Byte Protocol
SLAVE ADDRESS COMMAND CODE DATA BYTEWr A A A P
3887 F10
S
7 8 81 1 1 1 11
SLAVE ADDRESS COMMAND CODE DATA BYTEWr A A A P
3887 F11
S
7 8 8 1
PEC
81 1 1 1 11
A
LTC3887/LTC3887-1/
LTC3887-2
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OPERATION
Figure14. Read Byte Protocol
Figure17. Read Word Protocol with PEC
Figure12. Write Word Protocol
Figure15. Read Byte Protocol with PEC
Figure18. Block Read Protocol
Figure13. Write Word Protocol with PEC
Figure16. Read Word Protocol
Figure19. Block Read Protocol with PEC
SLAVE ADDRESS COMMAND CODE DATA BYTE LOWWr A A A P
3887 F12
S
7 8 8 1
DATA BYTE HIGH
81 1 1 1 11
A
SLAVE ADDRESS COMMAND CODE DATA BYTE LOWWr A A A P
3887 F13
S
7 8 8 1
DATA BYTE HIGH
8
PEC
811 1 1 1 11
A A
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A Sr P
3887 F14
S
7 8 7 11
DATA BYTE
8 11 1 1 11 1
ARd NA
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A Sr P
3887 F15
S
7 8 7 11
DATA BYTE
8 8 11 1 1 11 1
ARd A
1
A PEC
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A NA P
3887 F16
S
7 8 7 1
DATA BYTE LOW
8
DATA BYTE HIGH
811 1 1
Sr
1 1 11
A
1
Rd A
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A A PA
3887 F17
S
7 8 7 1
DATA BYTE LOW
8
DATA BYTE HIGH PEC
8 811 1 1 1 111
Sr
1
A
1
Rd A
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A SrS
7 8 7 11
BYTE COUNT = N
8 11 1 11 1
ARd A …
A PNA
3887 F18
DATA BYTE 1
8
DATA BYTE 2 DATA BYTE N
8 81 1 11
A …
…
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A SrS
7 8 7 11
BYTE COUNT = N
8 11 1 11 1
ARd A …
…
…
ADATA BYTE 1
8
DATA BYTE 2
81 1
A A PNA
3887 F19
DATA BYTE N PEC
8 81 11
LTC3887/LTC3887-1/
LTC3887-2
32
Rev.F
For more information www.analog.com
OPERATION
Figure22. Alert Response Address Protocol
Figure23. Alert Response Address Protocol with PEC
Figure24. Block Write – Block Read Process Call
Figure25. Block Write – Block Read Process Call with PEC
SLAVE ADDRESS COMMAND CODE BYTE COUNT = MWr A AS
7 8 8 1
DATA BYTE 1
8 11 1 11
A A …
……
ADATA BYTE 2
8 1
ADATA BYTE M
8 1
SLAVE ADDRESS BYTE COUNT = NRd A ASr
7 8
DATA BYTE 1
8 11 1 11
A …
P
3887 F20
1
…
…ADATA BYTE 2
8
NADATA BYTE N
8 1
SLAVE ADDRESS COMMAND CODE BYTE COUNT = MWr A AS
7 8 8 1
DATA BYTE 1
8 11 1 11
A A …
…
…
ADATA BYTE 2
8 1
ADATA BYTE M
8 1
SLAVE ADDRESS BYTE COUNT = NRd A ASr
7 8
DATA BYTE 1
81 1 11
A …
…
…ADATA BYTE 2
8 1
ADATA BYTE N
8 1
P
3887 F21
1
NAPEC
8 1
ALERT RESPONSE
ADDRESS Rd A NA P
3887 F22
S
7 71 1 1 11
DEVICE ADDRESS
ALERT RESPONSE
ADDRESS Rd A AS
7 71 1 11
DEVICE ADDRESS NA P
3887 F23
8 1 1
PEC
LTC3887/LTC3887-1/
LTC3887-2
33
Rev. F
For more information www.analog.com
Handshaking features are included to ensure robust
system communication. Please refer to the PMBus
Communication and Command Processing subsec-
tion of the Applications Information section for further
details.
OPERATION
Table1. Data Format Terminology
PMBus
TERMINOLOGY MEANING
TERMINOLOGY FOR: SPECS,
GUI, APPLICATION NOTES
ABBREVIATIONS FOR
SUMMARY COMMAND TABLE
FOR MORE DETAIL REFER TO
THE DATA FORMAT SECTION
OF Table2
Linear Linear Linear_5s_11s L11 Page 39
Linear (for Voltage
Related Commands)
Linear Linear_16u L16 Page 39
Direct Direct-Manufacturer
Customized
DirectMfr CF Page 39
Hex Hex I16
ASCII ASCII ASC
Register Fields Reg Reg
LTC3887/LTC3887-1/
LTC3887-2
34
Rev.F
For more information www.analog.com
PMBUS
COMMANDS
The following tables list supported PMBus commands and
manufacturer specific commands. A complete description
of these commands can be found in the “PMBus Power
System Mgt Protocol Specification – Part II – Revision
1.2”. Users are encouraged to reference this specification.
Exceptions or manufacturer specific implementations
are listed below in Table 2. Floating point values listed
in the “DEFAULT VALUE” column are either Linear 16-bit
Signed (PMBus Section 8.3.1) or Linear_5s_11s (PMBus
Section 7.1) format, whichever is appropriate for the com-
mand. All commands from 0xD0 through 0xFF not listed
in this table are implicitly reserved by the manufacturer.
Users should avoid blind writes within this range of com-
mands to avoid undesired operation of the part. All com-
mands from 0x00 through 0xCF not listed in this table are
implicitly not supported by the manufacturer. Attempting
to access non-supported or reserved commands may
result in a CML command fault event. All output volt-
age settings and measurements are based on the VOUT_
MODE setting of 0x14. This translates to an exponent of
2–12.
If PMBus commands are received faster than they are
being processed, the part may become too busy to handle
new commands. In these circumstances the part follows
the protocols defined in the PMBus Specification v1.2,
Part II, Section 10.8.7, to communicate that it is busy.
The part includes handshaking features to eliminate busy
errors and simplify error handling software while ensur-
ing robust communication and system behavior. Please
refer to the subsection titled PMBus Communication and
Command Processing in the
Applications Information
section for further details.
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE PAGE
PAGE 0x00 Channel or page currently selected for any
command that supports paging.
R/W Byte N Reg 0x00 64
OPERATION 0x01 Operating mode control. On/off, margin high
and margin low.
R/W Byte Y Reg Y 0x40 68
ON_OFF_CONFIG 0x02 RUN pin and PMBus bus on/off command
configuration.
R/W Byte Y Reg Y 0x1E 67
CLEAR_FAULTS 0x03 Clear any fault bits that have been set. Send Byte N NA 91
PAGE_PLUS_WRITE 0x05 Write a command directly to a specified page. W Block N 64
PAGE_PLUS_READ 0x06 Read a command directly from a specified page. Block R/W N 65
WRITE_PROTECT 0x10 Level of protection provided by the device
against accidental changes.
R/W Byte N Reg Y 0x00 65
STORE_USER_ALL 0x15 Store user operating memory to EEPROM. Send Byte N NA 102
RESTORE_USER_ALL 0x16 Restore user operating memory from EEPROM. Send Byte N NA 102
CAPABILITY 0x19 Summary of PMBus optional communication
protocols supported by this device.
R Byte N Reg 0xB0 90
SMBALERT_MASK 0x1B Mask ALERT activity. Block R/W Y
Reg
see CMD 92
VOUT_MODE 0x20 Output voltage format and exponent (2–12). R Byte Y
Reg
2–12
0x14
72
VOUT_COMMAND 0x21 Nominal output voltage set point. R/W Word Y L16 V Y 1.0
0x1000
73
VOUT_MAX 0x24 Upper limit on the commanded output voltage
including VOUT_MARGIN_HI.
R/W Word Y L16 V Y 5.6
0x599A
72
VOUT_MARGIN_HIGH 0x25 Margin high output voltage set point. Must be
greater than VOUT_COMMAND.
R/W Word Y L16 V Y 1.05
0x10CD
73
VOUT_MARGIN_LOW 0x26 Margin low output voltage set point. Must be
less than VOUT_COMMAND.
R/W Word Y L16 V Y 0.95
0x0F33
73
Table2. Summary (Note: The Data Format abbreviations are detailed at the end of this table, NVM and EEPROM are the same.)
PMBus
COMMAND SUMMARY
LTC3887/LTC3887-1/
LTC3887-2
35
Rev. F
For more information www.analog.com
PMBus
COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE PAGE
VOUT_TRANSITION_RATE
0X27 Rate the output changes when VOUT
commanded to a new value.
R/W Word Y L11 V/ms Y 0.25
AA00
79
FREQUENCY_SWITCH 0x33 Switching frequency of the controller. R/W Word N L11 kHz Y 350
0xFABC
70
VIN_ON 0x35 Input voltage at which the unit should start
power conversion.
R/W Word N L11 V Y 6.5
0xCB40
71
VIN_OFF 0x36 Input voltage at which the unit should stop
power conversion.
R/W Word N L11 V Y 6.0
0xCB00
71
IOUT_CAL_GAIN 0x38 The ratio of the voltage at the current sense pins
to the sensed current. For devices using a fixed
current sense resistor, it is the resistance value
in mΩ.
R/W Word Y L11 mΩ Y 1.8
0xBB9A
75
VOUT_OV_FAULT_LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 1.1
0x119A
72
VOUT_OV_FAULT_
RESPONSE
0x41 Action to be taken by the device when an output
overvoltage fault is detected.
R/W Byte Y Reg Y 0xB8 74
VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 1.075
0x1133
73
VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 0.925
0x0ECD
72
VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit. R/W Word Y L16 V Y 0.9
0x0E66
72
VOUT_UV_FAULT_
RESPONSE
0x45 Action to be taken by the device when an output
undervoltage fault is detected.
R/W Byte Y Reg Y 0xB8 82
IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 A Y 29.75
0xDBB8
76
IOUT_OC_FAULT_
RESPONSE
0x47 Action to be taken by the device when an output
overcurrent fault is detected.
R/W Byte Y Reg Y 0x00 85
IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A Y 20.0
0xDA80
76
OT_FAULT_LIMIT 0x4F External overtemperature fault limit. R/W Word Y L11 C Y 100.0
0xEB20
77
OT_FAULT_RESPONSE 0x50 Action to be taken by the device when an
external overtemperature fault is detected,
R/W Byte Y Reg Y 0xB8 87
OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word Y L11 C Y 85.0
0xEAA8
78
UT_FAULT_LIMIT 0x53 External undertemperature fault limit. R/W Word Y L11 C Y –40.0
0xE580
78
UT_FAULT_RESPONSE 0x54 Action to be taken by the device when an
external undertemperature fault is detected.
R/W Byte Y Reg Y 0xB8 87
VIN_OV_FAULT_LIMIT 0x55 Input supply overvoltage fault limit. R/W Word N L11 V Y 15.5
0xD3E0
71
VIN_OV_FAULT_
RESPONSE
0x56 Action to be taken by the device when an input
overvoltage fault is detected.
R/W Byte Y Reg Y 0x80 81
VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W Word N L11 V Y 6.3
0xCB26
71
IIN_OC_WARN_LIMIT 0x5D Input supply overcurrent warning limit. R/W Word N L11 A Y 10.0
0xD280
75
LTC3887/LTC3887-1/
LTC3887-2
36
Rev.F
For more information www.analog.com
PMBus
COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE PAGE
TON_DELAY 0x60 Time from RUN and/or Operation on to output
rail turn-on.
R/W Word Y L11 ms Y 0.0
0x8000
79
TON_RISE 0x61 Time from when the output starts to rise
until the output voltage reaches the VOUT
commanded value.
R/W Word Y L11 ms Y 8.0
0xD200
79
TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for
VOUT to cross the VOUT_UV_FAULT_LIMIT.
R/W Word Y L11 ms Y 10.00
0xD280
79
TON_MAX_FAULT_
RESPONSE
0x63 Action to be taken by the device when a TON_
MAX_FAULT event is detected.
R/W Byte Y Reg Y 0xB8 84
TOFF_DELAY 0x64 Time from RUN and/or Operation off to the start
of TOFF_FALL ramp.
R/W Word Y L11 ms Y 0.0
0x8000
79
TOFF_FALL 0x65 Time from when the output starts to fall until
the output reaches zero volts.
R/W Word Y L11 ms Y 8.00
0xD200
80
TOFF_MAX_WARN_LIMIT 0x66 Maximum allowed time, after TOFF_FALL
completed, for the unit to decay below 12.5%.
R/W Word Y L11 ms Y 150
0xF258
80
STATUS_BYTE 0x78 One byte summary of the unit’s fault condition. R/W Byte Y Reg NA 93
STATUS_WORD 0x79 Two byte summary of the unit’s fault condition. R/W Word Y Reg NA 93
STATUS_VOUT 0x7A Output voltage fault and warning status. R/W Byte Y Reg NA 94
STATUS_IOUT 0x7B Output current fault and warning status. R/W Byte Y Reg NA 94
STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg NA 94
STATUS_TEMPERATURE 0x7D External temperature fault and warning status
for READ_TEMERATURE_1.
R/W Byte Y Reg NA 95
STATUS_CML 0x7E Communication and memory fault and warning
status.
R/W Byte N Reg NA 95
STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state
information.
R/W Byte Y Reg NA 95
READ_VIN 0x88 Measured input supply voltage. R Word N L11 V NA 99
READ_IIN 0x89 Measured input supply current. R Word N L11 A NA 99
READ_VOUT 0x8B Measured output voltage. R Word Y L16 V NA 99
READ_IOUT 0x8C Measured output current. R Word Y L11 A NA 99
READ_TEMPERATURE_1 0x8D External temperature sensor. This is the value
used for all temperature related processing,
including IOUT_CAL_GAIN.
R Word Y L11 C NA 99
READ_TEMPERATURE_2 0x8E Internal die temperature. Does not affect any
other registers.
R Word N L11 C NA 99
READ_DUTY_CYCLE 0x94 Duty cycle of the top gate control signal. R Word Y L11 % NA 100
READ_FREQUENCY 0x95 Measured PWM switching frequency. R Word N L11 kHz NA 100
READ_POUT 0x96 Measured output power. R Word Y L11 W NA 100
PMBUS_REVISION 0x98 PMBus revision supported by this device.
Current revision is 1.2.
R Byte N Reg 0x22 90
MFR_ID 0x99 The manufacturer ID of the LTC3887 in ASCII. R String N ASC LTC 90
MFR_MODEL 0x9A Manufacturer part number in ASCII. R String N ASC LTC3887 91
MFR_SERIAL 0x9E Serial number of this specific unit. R Block N CF NA 91
MFR_VOUT_MAX 0xA5 Maximum allowed output voltage including
VOUT_OV_FAULT_LIMIT..
R Word Y L16 V 5.7
0x5B34
74
LTC3887/LTC3887-1/
LTC3887-2
37
Rev. F
For more information www.analog.com
PMBus
COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE PAGE
USER_DATA_00 0xB0 OEM RESERVED. Typically used for part
serialization.
R/W Word N Reg Y NA 90
USER_DATA_01 0xB1 Manufacturer reserved for LTpowerPlay. R/W Word Y Reg Y NA 90
USER_DATA_02 0xB2 OEM RESERVED. Typically used for part
serialization
R/W Word N Reg Y NA 90
USER_DATA_03 0xB3 A NVM word available for the user. R/W Word Y Reg Y 0x0000 90
USER_DATA_04 0xB4 A NVM word available for the user. R/W Word N Reg Y 0x0000 90
MFR_INFO 0xB6 Manufacturing Specific Information R Word N Reg NA 98
MFR_EE_UNLOCK 0xBD Unlock user EEPROM for access by MFR_EE_
ERASE and MFR_EE_DATA commands.
R/W Byte N Reg NA 108
MFR_EE_ERASE 0xBE Initialize user EEPROM for bulk programming
by MFR_EE_DATA.
R/W Byte N Reg NA 108
MFR_EE_DATA 0xBF Data transferred to and from EEPROM using
sequential PMBus word reads or writes.
Supports bulk programming.
R/W Word N Reg NA 108
MFR_CHAN_CONFIG_
LTC3887
0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x1D 66
MFR_CONFIG_ALL_
LTC3887
0xD1 Configuration bits that are common to all pages. R/W Byte N Reg Y 0x21 67
MFR_GPIO_PROPAGATE_
LTC3887
0xD2 Configuration that determines which faults are
propagated to the GPIO pins.
R/W Word Y Reg Y 0x6993 89
MFR_PWM_MODE_
LTC3887
0xD4 Configuration for the PWM engine of each
channel.
R/W Byte Y Reg Y 0xC1 69
MFR_GPIO_RESPONSE 0xD5 Action to be taken by the device when the GPIO
pin is externally asserted low.
R/W Byte Y Reg Y 0xC0 89
MFR_OT_FAULT_
RESPONSE
0xD6 Action to be taken by the device when an
internal overtemperature fault is detected.
R Byte N Reg 0xC0 86
MFR_IOUT_PEAK 0xD7 Report the maximum measured value of
READ_IOUT since last MFR_CLEAR_PEAKS.
R Word Y L11 A NA 100
MFR_ADC_CONTROL 0xD8 ADC telemetry parameter selected for repeated
fast ADC read back.
R/W Byte N Reg 0x00 101
MFR_ADC_TELEMETRY_
STATUS
0xDA ADC telemetry status indicating which
parameter is most recently converted when the
short round robin ADC loop is enabled
R/W Byte N Reg Y NA 101
MFR_RETRY_DELAY 0xDB Retry interval during FAULT retry mode R/W Word Y L11 ms Y 350
0xFABC
81
MFR_RESTART_DELAY 0xDC Minimum time the RUN pin is held low by the
LTC3887.
R/W Word Y L11 ms Y 500
0xFBE8
80
MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT since
last MFR_CLEAR_PEAKS.
R Word Y L16 V NA 100
MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since
last MFR_CLEAR_PEAKS.
R Word N L11 V NA 100
MFR_TEMPERATURE_1_
PEAK
0xDF Maximum measured value of external
Temperature (READ_TEMPERATURE_1)
since last MFR_CLEAR_PEAKS.
R Word Y L11 C NA 100
MFR_CLEAR_PEAKS 0xE3 Clears all peak values. Send Byte N NA 92
MFR_PADS 0xE5 Digital status of the I/O pads. R Word N Reg NA 96
MFR_ADDRESS 0xE6 Sets the 7-bit I2C address byte. R/W Byte N Reg Y 0x4F 64
LTC3887/LTC3887-1/
LTC3887-2
38
Rev.F
For more information www.analog.com
PMBus
COMMAND SUMMARY
Note 1: Commands indicated with Y indicate that these commands are
stored and restored using the STORE_USER_ALL and RESTORE_USER_
ALL commands, respectively.
Note 2: Commands with a default value of NA indicate “not applicable”.
Commands with a default value of FS indicate “factory set on a per part
basis”.
Note 3: The LTC3887 contains additional commands not listed in this
table. Reading these commands is harmless to the operation of the IC;
however, the contents and meaning of these commands can change
without notice.
Note 4: Some of the unpublished commands are read-only and will
generate a CML bit 6 fault if written.
Note 5: Writing to commands not published in this table is not permitted.
Note 6: The user should not assume compatibility of commands
between different parts based upon command names. Always refer to
the manufacturer’s data sheet for each part for a complete definition of a
command’s function.
ADI has made every reasonable attempt to keep command functionality
compatible between parts; however, differences may occur to address
product requirements.
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE PAGE
MFR_SPECIAL_ID 0xE7 Manufacturer code representing the LTC3887. R Word N Reg 0x470X 91
MFR_IIN_OFFSET 0xE9 Coefficient used to add to the input current to
account for the IQ of the part.
R/W Word Y L11 A Y 0.050
0X9333
74
MFR_FAULT_LOG_STORE 0xEA Command a transfer of the fault log from RAM
to EEPROM.
Send Byte N NA 104
MFR_FAULT_LOG_CLEAR 0xEC Initialize the EEPROM block reserved for fault
logging.
Send Byte N NA 104
MFR_READ_IIN 0xED Measured input current per channel R Word Y L11 A NA 99
MFR_FAULT_LOG 0xEE Fault log data bytes. This sequentially retrieved
data is used to assemble a complete fault log.
R Block N Reg Y NA 104
MFR_COMMON 0xEF Manufacturer status bits that are common
across multiple ADI chips.
R Byte N Reg NA 96
MFR_COMPARE_USER_
ALL
0xF0 Compares current command contents with
NVM.
Send Byte N NA 103
MFR_TEMPERATURE_2_
PEAK
0xF4 Peak internal die temperature since last
MFR_CLEAR_PEAKS.
R Word N L11 C NA 100
MFR_PWM_CONFIG_
LTC3887
0xF5 Set numerous parameters for the DC/DC
controller including phasing.
R/W Byte N Reg Y 0x10 70
MFR_IOUT_CAL_GAIN_TC
0xF6 Temperature coefficient of the current sensing
element.
R/W Word Y CF Y 3900
0x0F3C
75
MFR_TEMP_1_GAIN 0xF8 Sets the slope of the external temperature
sensor.
R/W Word Y CF Y 1.0
0x4000
77
MFR_TEMP_1_OFFSET 0xF9 Sets the offset of the external temperature
sensor with respect to –273.1°C
R/W Word Y L11 C Y 0.0
0x8000
77
MFR_RAIL_ADDRESS 0xFA Common address for PolyPhase outputs to
adjust common parameters.
R/W Byte Y Reg Y 0x80 64
MFR_RESET 0xFD Commanded reset without requiring a power
down.
Send Byte N NA 68
LTC3887/LTC3887-1/
LTC3887-2
39
Rev. F
For more information www.analog.com
*DATA FORMAT
L11 Linear_5s_11s PMBus data field b[15:0]
Value = Y • 2N
where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit
two’s complement integer
Example:
For b[15:0] = 0xF258 = ‘b11110_010_0101_1000
Value = 600 • 2–2 = 150
From “PMBus Spec Part II: Paragraph 7.1”
L16 Linear_16u PMBus data field b[15:0]
Value = Y • 2N
where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two’s
complement exponent that is hardwired to –12 decimal
Example:
For b[15:0] = 0x4C00 = ‘b0100_1100_0000_0000
Value = 19456 • 2–12 = 4.75
From “PMBus Spec Part II: Paragraph 8.2”
Reg Register PMBus data field b[15:0] or b[7:0].
Bit field meaning is defined in detailed PMBus Command Register Description.
I16 Integer Word PMBus data field b[15:0]
Value = Y
where Y = b[15:0] is a 16 bit unsigned integer
Example:
For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111
Value = 38919 (decimal)
CF Custom Format Value is defined in detailed PMBus Command Register Description.
This is often an unsigned or two’s complement integer scaled by an MFR specific
constant.
ASC ASCII Format A variable length string of text characters conforming to ISO/IEC 8859-1 standard.
PMBus
COMMAND SUMMARY
LTC3887/LTC3887-1/
LTC3887-2
40
Rev.F
For more information www.analog.com
APPLICATIONS INFORMATION
The Typical Applications on the back page is a common
LTC3887 application circuit. The LTC3887 can be con-
figured to use either DCR (inductor resistance) sensing
or low value resistor sensing. The choice between the
two current sensing schemes is largely a design trade-
off between cost, power consumption and accuracy. DCR
sensing is popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. The LTC3887 can nominally
account for the temperature dependency of the DCR sens
-
ing element. The accuracy of the current reading and cur-
rent limit are typically limited by the accuracy of the DCR
resistance (accounted for in the IOUT_CAL_GAIN register
of the LTC3887). Thus current sensing resistors provide
more accurate current sensing and limiting for the appli-
cation. Other external component selection are driven by
the load requirement, and begins with the selection of
RSENSE (if RSENSE is used) and inductor value. Next, the
power MOSFETs are selected. Then the input and output
capacitors are selected. Finally the current limit is selected.
All of these components and ranges are required to be
determined prior to calculating the external compensation
components. The current limit range is required because
the two ranges (25mV to 50mV vs 37.5mV to 70mV) have
different EA gains set with bit 7 of the MFR_PWM_MODE_
LTC3887 command. The voltage RANGE bit also modi-
fies the loop gain and impacts the compensation network
set with bit 1 of MFR_PWM_MODE_LTC3887. All other
programmable parameters do not affect the loop gain,
allowing parameters to be modified without impact to the
transient response to load.
CURRENT LIMIT PROGRAMMING
The LTC3887 has two ranges of current limit program-
ming and a total of eight levels within each range. Refer to
the IOUT_OC_FAULT_LIMIT section of the PMBus com-
mands. Within each range the error amp gain is fixed,
resulting in constant loop gain. The LTC3887 will account
for the temperature coefficient of the DCR of the inductor
and automatically update the current limit as the inductor
temperature changes. The temperature coefficient of the
DCR is stored in the MFR_IOUT_CAL_GAIN_TC register.
For the best current limit accuracy, use the 75mV setting.
The 25mV setting will allow for the use of very low DCR
inductors or sense resistors, at the expense of current limit
accuracy. Current limiting is on a cycle-by-cycle basis and
is only a function of the peak inductor current. The average
inductor current is monitored by the ADC converter and
can provide a warning if too much average output cur-
rent is detected. The overcurrent fault is detected when the
ITH voltage hits the maximum value. The digital processor
within the LTC3887 provides the ability to either ignore
the fault, shut down and latch off or shut down and retry
indefinitely (hiccup). Refer to the overcurrent portion of the
Operation section for more detail.
ISENSE+ AND ISENSE– PINS
The ISENSE+ and ISENSE– pins are the inputs to the current
comparators and the A/D. The common mode input volt-
age range of the current comparators is 0V to 5.5V. Both
the SENSE pins are high impedance inputs with small
base currents typically less than 1µA. When the I
SENSE
pins ramp up from 0V to 1.4V, the small base currents
flow out of the SENSE pins. When the ISENSE pins are
greater than 1.4V, the base currents flow into the ISENSE
pins. The high impedance inputs to the current compara-
tors allow accurate DCR sensing. Do not to float these
pins during normal operation.
Filter components connected to the ISENSE lines should
be placed close to the IC. The positive and negative traces
should be routed differentially and Kelvin connected to the
current sense element, see Figure24. A non-Kelvin con-
nection can add parasitic inductance and capacitance to
the current sense element, degrading the information at
the sense terminals and making the programmed current
limit perform poorly. In a PolyPhase system, poor place-
ment of the sensing element will result in sub-optimal
current sharing between power stages. If DCR sensing
Figure24. Optimal Sense Line Placement
COUT
TO SENSE FILTER,
NEXT TO THE CONTROLLER
INDUCTOR OR RSENSE 3887 F24
LTC3887/LTC3887-1/
LTC3887-2
41
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LOW VALUE RESISTOR CURRENT SENSING
A typical sensing circuit using a discrete resistor is shown
in Figure25b. R
SENSE
is chosen based on the required
output current.
The current comparator has a maximum threshold
VSENSE(MAX) determined by the ILIMIT setting. The input
common mode range of the current comparator is 0V to
5.5V (if VIN is greater than 6V). The current comparator
threshold sets the peak of the inductor current, yield-
ing a maximum average output current IMAX equal to the
peak value less half the peak-to-peak ripple current ∆IL.
To calculate the sense resistor value, use the equation:
RSENSE =
V
SENSE(MAX)
IMAX +ΔIL
2
Due to possible PCB noise in the current sensing loop, the
AC current sensing ripple of ∆VSENSE = ∆IL • RSENSE also
needs to be checked in the design to get a good signal-to-
noise ratio. In general, for a reasonably good PCB layout,
a 15mV minimum ∆VSENSE voltage is recommended as
a conservative number to start with, either for RSENSE or
DCR sensing applications.
For previous generation current mode controllers, the
maximum sense voltage was high enough (e.g., 75mV
for the LTC1628/LTC3728 family) that the voltage drop
across the parasitic inductance of the sense resistor rep-
resented a relatively small error. In the newer higher cur-
rent density solutions; however, the value of the sense
resistor can be less than 1mΩ and the peak sense voltage
can be less than 20mV. In addition, inductor ripple cur-
rents greater than 50% with operation up to 1MHz are
becoming more common. Under these conditions, the
voltage drop across the sense resistor’s parasitic induc-
tance is no longer negligible. A typical sensing circuit
using a discrete resistor is shown in Figure25b. In previ-
ous generations of controllers, a small RC filter placed
near the IC was commonly used to reduce the effects of
the capacitive and inductive noise coupled in the sense
traces on the PCB. A typical filter consists of two series
100Ω resistors connected to a parallel 1000pF capacitor,
resulting in a time constant of 200ns.
(a) Inductor DCR Current Sense Circuit
Figure25.
is used (Figure25a), sense resistor R1 should be placed
close to the switching node (SW) to prevent noise from
coupling into sensitive small-signal nodes. The capacitor
C1 should be placed close to the IC pins. This imped-
ance difference can result in loss of accuracy in the cur-
rent reading of the ADC. The current reading accuracy
can be improved by matching the impedance of the two
I
SENSE
inputs. To accomplish this add a series resistor
between VOUT and ISENSE– equal to R1. A capacitor of 1µF
or greater should be placed in parallel with this resistor.
If the peak voltage is <75mV at room temperature, R2 is
not required.
VIN VIN
INTVCC
BOOST
TG
SW
BG
GND
INDUCTOR
DCR
R3
OPTIONAL
[(R1 + R3)||R2] • C1 = IOUT_CAL_GAIN = DCR • R3 = R1
*PLACE C1 NEAR SENSE+, SENSE– PINS
C2 >1µF
L
ISENSE+
ISENSE–
LTC3887 VOUT
3887 F25a
R1
R2
2 • L
DCR
C1*
R2
R1 + R2 + R3
VIN VIN
INTVCC
BOOST
TG
SW
BG
GND
FILTER COMPONENTS
PLACED NEAR SENSE PINS
ISENSE+
ISENSE–
LTC3887 VOUT
3887 F025b
CF • 2RF ≤ ESL/RS
POLE-ZERO
CANCELLATION
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
RSESL
CF
RF
RF
(b) Resistor Current Sense Circuit
LTC3887/LTC3887-1/
LTC3887-2
42
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This same RC filter with minor modifications, can be used
to extract the resistive component of the current sense sig-
nal in the presence of parasitic inductance. For example,
Figure26 illustrates the voltage waveform across a 2mΩ
resistor with a 2010 footprint. The waveform is the super-
position of a purely resistive component and a purely induc-
tive component. It was measured using two scope probes
and waveform math to obtain a differential measurement.
Based on additional measurements of the inductor ripple
current and the on-time and off-time of the top switch,
the value of the parasitic inductance was determined to be
0.5nH using the equation:
ESL =
V
ESL(STEP)
ΔI
L
•tON • tOFF
t
ON
+t
OFF
(1)
If the RC time constant is chosen to be close to the para-
sitic inductance divided by the sense resistor (L/R), the
resultant waveform looks resistive, as shown in Figure27.
For applications using low maximum sense voltages,
check the sense resistor manufacturer’s data sheet for
information about parasitic inductance. In the absence
of data, measure the voltage drop directly across the
sense resistor to extract the magnitude of the ESL step
and use Equation 1 to determine the ESL. However, do
not overfilter the signal. Keep the RC time constant less
than or equal to the inductor time constant to maintain a
sufficient ripple voltage on VRSENSE for optimal operation
of the current loop controller.
INDUCTOR DCR CURRENT SENSING
For applications requiring the highest possible efficiency
at high load currents, the LTC3887 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure25a. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such an
inductor, conduction loss through a sense resistor would
cost a few points of efficiency compared to DCR sensing.
If the external (R1+R3)||R2 • C1 time constant is chosen to
be exactly equal to the 2 • L/DCR time constant, assuming
R1 = R3, the voltage drop across the external capacitor is
equal to the drop across the inductor DCR multiplied by
R2/(R1+R2+R3). R2 scales the voltage across the sense
terminals for applications where the DCR is greater than
the target sense resistor value. The DCR value is entered as
the IOUT_CAL_GAIN in mΩ unless R2 is required. If R2 is
used, IOUT_CAL_GAIN = DCR • R2/(R1+R2+R3). If there
is no need to attenuate the signal, R2 can be removed. To
properly dimension the external filter components, the DCR
of the inductor must be known. It can be measured using
a good RLC meter, but the DCR tolerance is not always the
same and varies with temperature. Consult the manufac-
turers’ data sheets for detailed information. The LTC3887
will account for temperature variation if the correct param-
eter is entered into the MFR_IOUT_CAL_GAIN_TC register.
Typically the resistance has a 3900ppm/°C coefficient.
C2 can be optimized for a flat frequency response, assum
-
ing R1 = R3 by the following equation:
C2 =[2R1 • R2 • C1 – L/DCR • (2R1+R2)]/R12
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
RSENSE(EQUIV) =
V
SENSE(MAX)
IMAX +ΔIL
2
To ensure that the application will deliver full load current
over the full operating temperature range, be sure to pick
Figure26. Voltage Measured Directly Across RSENSE
Figure27. Voltage Measured After the RSENSE Filter
500ns/DIV
VSENSE
20mV/DIV
3887 F26
VESL(STEP)
500ns/DIV
VSENSE
20mV/DIV
3887 F27
LTC3887/LTC3887-1/
LTC3887-2
43
Rev. F
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the optimum I
LIMIT
value accounting for errors in the DCR
versus the MFR_IOUT_CAL_GAIN parameter entered.
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given
at 20°C. Increase this value to account for errors in the
temperature sensing element of 3°C to 5°C and any addi-
tional errors associated with the proximity of the tempera-
ture sensor element to the inductor.
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
RD =RSENSE(EQUIV)
DCR(MAXERROR) at TL(MAX)
C1 is usually selected to be in the range of 0.047µF to
4.7µF. This forces R1||R2 to be approximately 2k. This
resistance minimizes errors caused by the SENSE pin
leakage currents. Adding optional elements R3 and C2
shown in Figure25a will minimize offset errors associated
with these leakage currents.
The equivalent resistance (R1+R3)||R2 is scaled to the
room temperature inductance and maximum DCR:
(R1+R3)||R2 = 2 •L
DCR at 20°C
( )
•C1
The sense resistor values are:
R1=R3; R1= R1||R2
RD
; R2 = R1•RD
1– RD
The maximum power loss in R1 is related to the duty
cycle, and will occur in continuous mode at the maximum
input voltage:
PLOSS R1=VIN(MAX) – VOUT
( )
• VOUT
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reduc-
ing conduction losses and provides higher efficiency at
heavy loads. Peak efficiency is about the same with either
method. Selecting discontinuous mode will improve the
converter efficiency at light loads regardless of the current
sensing method.
To maintain a good signal-to-noise ratio for the current
sense signal, use a minimum ∆VSENSE of 10mV to 15mV.
For a DCR sensing application, the actual ripple voltage
will be determined by the equation:
ΔVSENSE =
V
IN
– V
OUT
R1•C1 •
V
OUT
V
IN
• f
OSC
SLOPE COMPENSATION AND INDUCTOR PEAK
CURRENT
Slope compensation provides stability in constant fre-
quency current mode architectures by preventing sub-
harmonic oscillations at high duty cycles. This is accom-
plished internally by adding a compensation ramp to the
inductor current signal at duty cycles in excess of 35%.
The LTC3887 uses a patented current limit technique
that counteracts the compensating ramp. This allows the
maximum inductor peak current to remain unaffected
throughout all duty cycles.
INDUCTOR VALUE CALCULATION
Given the desired input and output voltages, the inductor
value and operating frequency, f
OSC
, directly determine
the inductor peak-to-peak ripple current:
IRIPPLE =VOUT VIN – VOUT
( )
V
IN
• f
OSC
•L
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at the
lowest frequency with a small ripple current. Achieving
this, however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of I
OUT(MAX)
. Note that the largest ripple
LTC3887/LTC3887-1/
LTC3887-2
44
Rev.F
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current occurs at the highest input voltage. To guarantee
that the ripple current does not exceed a specified maxi-
mum, the inductor should be chosen according to:
L≥VOUT VIN – VOUT
( )
V
IN
• f
OSC
•I
RIPPLE
INDUCTOR CORE SELECTION
Once the inductor value is determined, the type of induc-
tor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance. As the inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core materials saturate hard, which means that the induc-
tance collapse abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
POWER MOSFET AND SCHOTTKY DIODE (OPTIONAL)
SELECTION
Two external power MOSFETs must be selected for each
controller in the LTC3887: one N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTVCC volt-
age. This voltage is typically 5V. Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected (VIN
< 5V); then, sub-logic level threshold MOSFETs (VGS(TH)
< 3V) should be used. Pay close attention to the BVDSS
specification for the MOSFETs as well; most of the logic-
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the on-
resistance, R
DS(ON)
, Miller capacitance, C
MILLER
, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =VOUT
VIN
Synchronous Switch Duty Cycle =VIN – VOUT
V
IN
The MOSFET power dissipations at maximum output cur-
rent are given by:
P
MAIN =
V
OUT
VIN
IMAX
( )
21+δ
( )
RDS(ON) +
VIN
( )
2IMAX
2
⎛
⎝
⎜⎞
⎠
⎟RDR
( )
CMILLER
( )
•
1
VINTVCC – VTH(MIN)
+1
VTH(MIN)
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥• fOSC
PSYNC =VIN – VOUT
V
IN
IMAX
( )
21+δ
( )
RDS(ON)
where d is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTH(MIN) is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rap-
idly increase to the point that the use of a higher RDS(ON)
device with lower CMILLER actually provides higher effi-
ciency. The synchronous MOSFET losses are greatest at
high input voltage when the top switch duty factor is low
LTC3887/LTC3887-1/
LTC3887-2
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or during a short-circuit when the synchronous switch is
on close to 100% of the period.
The term (1 + d) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
d = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes conduct during the dead
time between the conduction of the two power MOSFETs.
These prevent the body diodes of the bottom MOSFETs
from turning on, storing charge during the dead time and
requiring a reverse recovery period that could cost as
much as 3% in efficiency at high VIN. A 1A to 3A Schottky
is generally a good compromise for both regions of opera-
tion due to the relatively small average current. Larger
diodes result in additional transition losses due to their
larger junction capacitance.
VARIABLE DELAY TIME, SOFT-START AND OUTPUT
VOLTAGE RAMPING
The LTC3887 must enter the run state prior to soft-start.
The RUN pins are released after the part initializes and
VIN is greater than the VIN_ON threshold. If multiple
LTC3887s are used in an application, they should be
configured to share the same RUN pins. They all hold
their respective RUN pins low until all devices initialize
and VIN exceeds the VIN_ON threshold for all devices.
The SHARE_CLK pin assures all the devices connected
to the signal use the same time base.
After the RUN pin releases, the controller waits for the user-
specified turn-on delay (TON_DELAY) prior to initiating an
output voltage ramp. Multiple LTC3887s and other ADI
parts can be configured to start with variable delay times.
To work correctly, all devices use the same timing clock
(SHARE_CLK) and all devices must share the RUN pin. This
allows the relative delay of all parts to be synchronized. The
actual variation in the delay will be dependent on the highest
clock rate of the devices connected to the SHARE_CLK pin
(all Analog Devices, Inc. ICs are configured to allow the fast-
est SHARE_CLK signal to control the timing of all devices).
The SHARE_CLK signal can be ±10% in frequency, thus the
actual time delays will have some variance.
Soft-start is performed by actively regulating the load
voltage while digitally ramping the target voltage from 0V
to the commanded voltage set point. The rise time of the
voltage ramp can be programmed using the TON_RISE
command to minimize inrush currents associated with the
start-up voltage ramp. The soft-start feature is disabled
by setting TON_RISE to any value less than 0.250ms. The
LTC3887 will perform the necessary math internally to
assure the voltage ramp is controlled to the desired slope.
However, the voltage slope can not be any faster than
the fundamental limits of the power stage. The shorter
TON_RISE time is set, the more jagged the TON_RISE
ramp will appear. The number of steps in the ramp is equal
to TON_RISE/0.1ms.
The LTC3887 PWM will always use discontinuous mode
during the TON_RISE operation. In discontinuous mode,
the bottom gate is turned off as soon as reverse current
is detected in the inductor. This will allow the regulator to
start up into a prebiased load.
There is no tracking feature in the LTC3887; however,
two outputs can be given the same TON_RISE and
TON_DELAY times to effectively ramp up at the same
time. Because the RUN pins are released at the same time
and both units use the same time base, the outputs will
track very closely. If the circuit is in a PolyPhase configu-
ration, all timing parameters must be the same.
The described method of start-up sequencing is time based.
For concatenated events it is possible to control the RUN
pin based on the GPIO pin of a different controller. The GPIO
pin can be configured to release when the output voltage of
the converter is greater than the VOUT_UV_FAULT_LIMIT.
It is recommended to use the unfiltered VOUT UV fault limit
because there is little appreciable time delay between the
converter crossing the UV threshold and the GPIO pin
releasing. The unfiltered output can be enabled using the
MFR_GPIO_PROPAGATE_VOUT_UVUF command. (Refer
to the MFR section of the PMBus commands in this docu-
ment). The unfiltered signal may have some glitching as the
VOUT signal transitions through the comparator threshold.
A small internal digital filter of 70µs has been added to
minimize this problem. To minimize the risk of GPIO pins
glitching, make the TON_RISE times less than 100ms. If
unwanted transitions still occur on GPIO, place a capacitor
LTC3887/LTC3887-1/
LTC3887-2
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to ground on the GPIO pin to filter the waveform. The RC
time-constant of the filter should be set sufficiently fast to
assure no appreciable delay is incurred. A value of 300µs
to 500µs will provide some additional filtering without sig-
nificantly delaying the trigger event.
DIGITAL SERVO MODE
For maximum accuracy in the regulated output voltage,
enable the digital servo loop by asserting bit 6 of the
MFR_PWM_MODE_LTC3887 command. In digital servo
mode, the LTC3887 will adjust the regulated output voltage
based on the ADC voltage reading. Every 90ms the digital
servo loop will step the LSB of the DAC (nominally 1.375mV
or 0.6875mV depending on the voltage range bit) until the
output is at the correct ADC reading. At power-up this mode
engages after TON_MAX_FAULT_LIMIT unless the limit is
set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is set to
0 (infinite), the servo begins after TON_RISE is complete
and VOUT has exceeded the VOUT_UV_FAULT_LIMIT and
IOUT_OC is not present. This same point in time is when
the output changes from discontinuous to the programmed
mode as indicated in MFR_PWM_MODE_LTC3887 bit 0.
Refer to Figure28 for details on the VOUT waveform under
time based sequencing.
2. After the TON_MAX_FAULT_LIMIT time is reached;
and
3. After the VOUT_UV_FAULT_LIMIT has been exceed or
the IOUT_OC_FAULT_LIMIT is not longer active.
If the TON_MAX_FAULT_IMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is not set
to ignore 0X00, the servo begins:
1. After the TON_RISE sequence is complete;
2. After the TON_MAX_FAULT_LIMIT time has expired
and both VOUT_UV_FAULT and IOUT_OC_FAULT are
not present.
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase configuration it is recommended only one
of the control loops have the digital servo mode enabled.
This will assure the various loops do not work against each
other due to slight differences in the reference circuits.
SOFT OFF (SEQUENCED OFF)
In addition to a controlled start-up, the LTC3887 also sup-
ports controlled turn-off. The TOFF_DELAY and TOFF_
FALL functions are shown in Figure29. TOFF_FALL is
processed when the RUN pin goes low or if the part is
commanded off. If the part faults off or GPIO is pulled
low externally and the part is programmed to respond
to this, the output will three-state rather than exhibiting
a controlled ramp. The output will decay as a function of
the load.
Figure28. Timing Controlled VOUT Rise
Figure29. TOFF_DELAY and TOFF_FALL
If the TON_MAX_FAULT_LIMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is set to
ignore 0x00, the servo begins:
1. After the TON_RISE sequence is complete
DAC VOLTAGE
ERROR (NOT
TO SCALE)
TIME DELAY OF
200ms TO 400ms
DIGITAL SERVO
MODE ENABLED FINAL OUTPUT
VOLTAGE REACHED
TON_MAX_FAULT_LIMIT
TON_RISE TIME 3887 F28
TON_DELAY
VOUT
RUN
VOUT_UV_FAULT_LIMIT
TOFF_FALLTOFF_DELAY TIME 3887 F29
VOUT
RUN
LTC3887/LTC3887-1/
LTC3887-2
47
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The output voltage will operate as shown in Figure29 so
long as the part is in forced continuous mode and the
TOFF_FALL time is sufficiently slow that the power stage
can achieve the desired slope. The TOFF_FALL time can
only be met if the power stage and controller can sink suf-
ficient current to assure the output is a zero volts by the end
of the fall time interval. If the TOFF_FALL time is set shorter
than the time required to discharge the load capacitance,
the output will not reach the desired zero volt state. At the
end of TOFF_FALL, the controller will cease to sink current
and VOUT will decay at the natural rate determined by the
load impedance. If the controller is in discontinuous mode,
the controller will not pull negative current and the output
will be pulled low by the load, not the power stage. The
maximum fail time is limited to 1.3 seconds. The shorter
TOFF_FALL time is set, the more jagged the TOFF_FALL
ramp will appear. The number of steps in the ramp is equal
to TOFF_FALL/0.1ms.
INTVCC REGULATOR
The LTC3887, LTC3887-1 features an NPN linear regula-
tor that supplies power to INTVCC from the VIN supply.
INTVCC powers the gate drivers, VDD33 and much of the
internal circuitry. The linear regulator produces the volt-
age at the INTVCC pin to nominally 5V when VIN is greater
than 6.5V. The regulator can supply a peak current of
100mA and must be bypassed to ground with a minimum
of 1µF ceramic capacitor or low ESR electrolytic capacitor.
No matter what type of bulk capacitor is used, an addi-
tional 0.1µF ceramic capacitor placed directly adjacent to
the INTVCC and GND pins is highly recommended. Good
bypassing is needed to supply the high transient currents
required by the MOSFET gate drivers and to prevent inter-
action between the channels.
H
igh input voltage application in which large MOSFETs
are being driven at high frequencies may cause the
LTC3887 die temperature to increase. The INTVCC cur-
rent, of which a large percentage is due to the gate charge
current, is supplied by the internal 5V linear regulator.
The power through the IC is equal to VIN • IINTVCC. The
gate charge current is dependent on operating frequency
as discussed in the Efficiency Considerations section.
The junction temperature can be estimated by using the
equations in Note 2 of the Electrical Characteristics. For
example, the LTC3887 INTVCC current is limited to less
than 69mA from a 24V supply:
TJ = 70°C + 69mA • 24V • 33°C/W = 125°C
Do not tie INTV
CC
on the LTC3887 or LTC3887-1 to an
external supply unless VIN is also tied to this supply because
INTVCC will attempt to pull the external supply high and hit
current limit, significantly increasing the die temperature.
Tying the EXTVCC pin to a 5V supply (LTC3887-2 only)
reduces the junction temperature in the previous example
from 125°C to: TJ = 70°C + 69mA • 5V • 33°C/W + 2mA
• 24V • 33°C/W = 83°C.
For applications where VIN is 5V, tie the VIN and INTVCC
pins together and tie the combined pins to the 5V input
with a 1Ω or 2.2Ω resistor as shown in Figure30. To
minimize the voltage drop caused by the gate charge cur-
rent, a low ESR capacitor must be connected to the VIN/
INTVCC pins. This configuration will override the INTVCC
linear regulator and will prevent INTVCC/EXTVCC from
dropping too low and will minimize the chip power con-
sumption. Make sure the INTV
CC
/EXTV
CC
voltage exceeds
the RDS(ON) test voltage for the MOSFETs which is typi-
cally 4.5V for logic level devices. The UVLO on INTVCC/
EXTVCC is set to approximately 4V.
Figure30. Setup for a 5V Input
TOPSIDE MOSFET DRIVER SUPPLY (CB, DB)
(LTC3887, LTC3887-2)
External bootstrap capacitors CB connected to the BOOST
pins supply the gate drive voltages for the topside
MOSFETs. Capacitor CB in the Block Diagram is charged
though external diode DB from INTVCC when the SW pin
is low. When one of the topside MOSFETs is to be turned
on, the driver places the CB voltage across the gate source
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage, SW,
RVIN
1Ω
CIN
3887 F30
5V
CINTVCC
4.7µF
+
INTVCC/EXTVCC
LTC3887/
LTC3887-1/
LTC3887-2
VIN
LTC3887/LTC3887-1/
LTC3887-2
48
Rev.F
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APPLICATIONS INFORMATION
rises to VIN and the BOOST pin follows. With the topside
MOSFET on, the boost voltage is above the input supply:
VBOOST = VIN + VINTVCC. The value of the boost capacitor
CB needs to be 100 times that of the total input capacitance
of the topside MOSFET(s). The reverse breakdown of the
external Schottky diode must be greater than V
IN(MAX)
.
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the efficiency has
improved. If there is no change in input current, then there
is no change in efficiency.
PWM jitter has been observed in some designs operating
at higher V
IN
/V
OUT
ratios. This jitter does not substantially
affect the circuit accuracy. Referring to Figure31, PWM
jitter can be removed by inserting a series resistor with a
value of 1Ω to 5Ω between the cathode of the diode and
the BOOSTn pin. A resistor case size of 0603 or larger is
recommended to reduce ESL and achieve the best results.
controller will restart. The normal start-up sequence will
be allowed after the VIN_ON threshold is crossed.
It is possible to program the contents of the EEPROM in the
application if the VDD33 supply is externally driven. This will
activate the digital portion of the LTC3887 without engaging
the high voltage sections. PMBus communications are valid
in this supply configuration. If VIN has not been applied to
the LTC3887, bit 3 (NVM Not Initialized)in MFR_COMMON
will be asserted low. If this condition is detected, the part will
only respond to addresses 5A and 5B. To initialize the part
issue the following set of commands: global address 0x5B
command 0xBD data 0x2B followed by global address 5B
command 0xBD and data 0xC4. The part will now respond
to the correct address. Configure the part as desired then
issue a STORE_USER_ALL. When VIN is applied a MFR_
RESET command must be issued to allow the PWM to be
enabled and valid ADC conversions to be read.
CIN AND COUT SELECTION
The selection of CIN is simplified by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The con-
troller with the highest (VOUT)(IOUT) product needs to be
used in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output cur-
rent drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value. The
out-of-phase technique typically reduces the input capaci-
tor’s RMS ripple current by a factor of 30% to 70% when
compared to a single phase power supply solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
CINRequiredIRMS ≈
I
MAX
V
IN
VOUT
( )
VIN – VOUT
( )
⎡
⎣⎤
⎦1/2
This formula has a maximum at VIN = 2VOUT
, where
IRMS = IOUT/2. This simple worst-case condition is com-
monly used for design because even significant deviations
Figure31. Boost Circuit to Minimize PWM Jitter
UNDERVOLTAGE LOCKOUT
The LTC3887 is initialized by an internal threshold-based
UVLO where VIN must be approximately 4V and INTVCC/
EXTV
CC
, V
DD33
, V
DD25
must be within approximately 20%
of the regulated values. In addition, VDD33 must be within
approximately 7% of the targeted value before the RUN
pins and SHARE_CLK pin are released. After the part has
initialized, an additional comparator monitors VIN. The
VIN_ON threshold must be exceeded before the power
sequencing can begin. When VIN drops below the VIN_
OFF threshold, the SHARE_CLK pin will be pulled low and
VIN must increase above the VIN_ON threshold before the
VIN
TGATE
LTC3887/
LTC3887-2
SW
INTVCC/EXTVCC
BOOST
0.2µF
VIN
10µF
3887 F31
BGATE
GND
LTC3887/LTC3887-1/
LTC3887-2
49
Rev. F
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do not offer much relief. Note that capacitor manufactur-
ers’ ripple current ratings are often based on only 2000
hours of life. This makes it advisable to further derate
the capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be par-
alleled to meet size or height requirements in the design.
Due to the high operating frequency of the LTC3887,
ceramic capacitors can also be used for CIN. Always con-
sult the manufacturer if there is any question.
The benefit of the LTC3887 2-phase operation can be cal-
culated by using the equation above for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the same
time. The total RMS power lost is lower when both control-
lers are operating due to the reduced overlap of current
pulses required through the input capacitor’s ESR. This is
why the input capacitor’s requirement calculated above for
the worst-case controller is adequate for the dual controller
design. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2-phase
system. The overall benefit of a multiphase design will
only be fully realized when the source impedance of the
power supply/battery is included in the efficiency testing.
The sources of the top MOSFETs should be placed within
1cm of each other and share a common C
IN
(s). Separating
the sources and CIN may produce undesirable voltage and
current resonances at VIN.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3887, is also
suggested. A 2.2Ω – 10Ω resistor placed between C
IN
(C1) and the VIN pin provides further isolation between
the two channels.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
ΔVOUT ≈IRIPPLE ESR+1
8fCOUT
⎛
⎝
⎜⎞
⎠
⎟
where f is the operating frequency, COUT is the out-
put capacitance and IRIPPLE is the ripple current in the
inductor. The output ripple is highest at maximum input
voltage since IRIPPLE increases with input voltage.
FAULT CONDITIONS
The LTC3887 GPIOn pins are configurable to indicate a
variety of faults including OV/UV, OC, OT, timing faults,
peak overcurrent faults. In addition the GPIOn pins can
be pulled low by external sources indicating a fault in
some other portion of the system. The fault response is
configurable and allow the following options:
n Ignore
n Shut Down Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely using the
Time Interval Specified in MFR_RETRY_DELAY
Refer to the PMBus section of the data sheet and the
PMBus specification for more details.
The analog OV response is automatic and virtually imme-
diate. If an OV is detected, TG goes low and BG is asserted.
Fault logging is available on the LTC3887. The fault log-
ging is configurable to automatically store data when a
fault occurs that causes the unit to fault off. The header
portion of the fault logging table contains peak values. It
is possible to read these values at any time. This data will
be useful while troubleshooting the fault.
If the LTC3887 internal temperature is in excess of 85°C,
writes to EEPROM (other than fault logging) are not rec-
ommended. The data will still be held in RAM, unless
the 3.3V supply UVLO threshold is reached. If the die
temperature exceeds 130°C all EEPROM communication
is disabled until the die temperature drops below 125°C
with the exception of the RESTORE_USER_ALL command
which is valid at any temperature.
OPEN-DRAIN PINS
The LTC3887 has the following open-drain pins:
3.3V Pins
1. GPIOn
2. SYNC
3. SHARE_CLK
LTC3887/LTC3887-1/
LTC3887-2
50
Rev.F
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5V Pins (5V pins operate correctly when pulled to 3.3V.)
1. RUNn
2. ALERT
3. SCL
4. SDA
All the above pins have on-chip pull-down transistors that
can sink 3mA at 0.4V. The low threshold on the pins is
0.8V; thus, plenty of margin on the digital signals with
3mA of current. For 3.3V pins, 3mA of current is a 1k
resistor. Unless there are transient speed issues associ-
ated with the RC time constant of the resistor pull-up and
parasitic capacitance to ground, a 10k resistor or larger
is generally recommended.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time con-
stant should be set to 1/3 to 1/5 the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA and SCL pins
with the time constant set to 1/3 the rise time:
RPULLUP =tRISE
3 •100pF =1k
Be careful to minimize parasitic capacitance on the SDA
and SCL pins to avoid communication problems. To
estimate the loading capacitance, monitor the signal in
question and measure how long it takes for the desired
signal to reach approximately 63% of the output value.
This is one time constant.
The SYNC pin has an on-chip pull-down transistor with the
output held low for nominally 500ns. If the internal oscil-
lator is set for 500kHz and the load is 100pF and a 3x time
constant is required, the resistor calculation is as follows:
RPULLUP =2µs – 500ns
3 •100pF =5k
The closest 1% resistor is 4.99k.
If timing errors are occurring or if the SYNC frequency is
not as fast as desired, monitor the waveform and deter-
mine if the RC time constant is too long for the application.
If possible reduce the parasitic capacitance. If not reduce
the pull up resistor sufficiently to assure proper timing.
The SHARE_CLK pull-up resistor has a similar equation
with a period of 10µs and a pull-down time of 1µs. The
RC time constant should be approximately 3µs or faster.
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIZATION
The LTC3887 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. The PLL is locked to the falling edge of the SYNC
pin. The phase relationship between channel 0, channel 1 and
the falling edge of SYNC is controlled by the lower 3 bits of
the MFR_PWM_CONFIG_LTC3887 command. For PolyPhase
applications, it is recommended all the phases be spaced
evenly. Thus for a 2-phase system the signals should be 180°
out of phase and a 4-phase system should be spaced 90°.
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the internal filter
network. The PLL lock range is guaranteed between 250kHz
and 1MHz. Nominal parts will have a range beyond this; how-
ever, operation to a wider frequency range is not guaranteed.
The PLL has a lock detection circuit. If the PLL should
lose lock during operation, bit 4 of the STATUS_MFR_
SPECIFIC command is asserted and the ALERT pin is
pulled low. The fault can be cleared by writing a 1 to the
bit. If the user does not wish to see the ALERT pin assert
if a PLL_FAULT, occurs, use the SMBALERT_MASK
command.
If the SYNC signal is not clocking in the application, the
nominal programmed frequency will control the PWM
circuitry. However, if more than one chip share the SYNC
pins and the signal is not clocking, the parts will not be
synchronized and excess voltage ripple on the output
might be present. Bit 10 of MFR_PADS_LTC3887 will be
asserted low if this condition exists. If the frequency com-
mand is programmed to external oscillator the LTC3887
PWM engine will run at the lowest free running frequency
LTC3887/LTC3887-1/
LTC3887-2
51
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of the PLL oscillator. This may result in excess inductor
current and undesirable operation.
If the PWM signal appears to be running at too high a
frequency, monitor the SYNC pin. Extra transitions on
the falling edge will result in the PLL trying to lock on to
noise versus the intended signal. Review routing of digital
control signals and minimize crosstalk to the SYNC signal
to avoid this problem. Multiple LTC3887s are required to
share the SYNC pin in PolyPhase configurations, for other
configurations it is optional. If the SYNC pin is shared
between LTC3887s, only one LTC3887 should be pro-
grammed with the SYNC output enabled. All the other
LTC3887s should be programmed to disable the SYNC
output. However their frequency should be programmed
to the nominal desired value.
MINIMUM ON-TIME CONSIDERATIONS
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3887 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <VOUT
VIN • f
OSC
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3887 is approximately
45ns, with reasonably good PCB layout, minimum 30%
inductor current ripple and at least 10mV – 15mV ripple
on the current sense signal. The minimum on-time can be
affected by PCB switching noise in the voltage and cur-
rent loop. As the peak current sense voltage decreases,
the minimum on-time gradually increases to 130ns. This
is of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with cor-
respondingly larger current and voltage ripple.
RCONFIG (EXTERNAL RESISTOR
CONFIGURATION PINS)
The LTC3887 default EEPROM is programmed to respect
the RCONFIG pins. If a user wishes the output voltage,
PWM frequency and phasing and the address to be set
without programming the part or purchasing specially pro-
grammed parts, the RCONFIG pins can be used to establish
these parameters. The RCONFIG pins all require a resistor
divider between the V
DD25
and SGND of the LTC3887. The
RCONFIG pins are only monitored at initial power up and
during a reset so modifying their values perhaps using an
A/D after the part is powered will have no effect. 1% resis-
tors or better must be used to assure proper operation.
Noisy clock signals should not be routed near these pins.
Voltage Selection
When an output voltage is set using the RCONFIG pins
on VOUTn_CFG, the following parameters are set as a
percentage of the output voltage:
• VOUT_OV_FAULT_LIMIT +10%
• VOUT_OV_WARN +7.5%
• VOUT_MAX +7.5%
• VOUT_MARGIN_HIGH +5%
• VOUT_MARGIN_LOW –5%
• VOUT_UV_WARN –6.5%
• VOUT_UV_FAULT_LIMIT –7%
Refer to Table3 to set the output voltage using RCONFIG
pins VOUTn_CFG a RTOP is connected between VDD25
and the pin and RBOTTOM is connected between the pin
and SGND. 1% resistors must be used to assure proper
operation.
The output voltage set point is equal to:
VSETPOINT = VOUTn_CFG
For example, if the VOUTn_CFG pin has R
TOP
equal to
24.9k and RBOTTOM equal to 4.32k:
VSETPOINT = 0.75V
If the output set point is 5V, the VOUTn_CFG must have
RTOP equal to 10k and RBOTTOM equal to 23.2k. If VOUT
is 2.5 volts or lower, low range is used. The maximum
LTC3887/LTC3887-1/
LTC3887-2
52
Rev.F
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voltage command on channel 0 or 1 is 5.5 volts includ-
ing VOUT_MARGIN_HIGH and VOUT. When VOUT is set
using the VOUTn_CFG pins, the part will turn on the rail
modifying the ON_OFF_CONFIG command, if required, to
respond to PMBus commands.
Table3. VOUTn_CFG
RTOP (kΩ) RBOTTOM (kΩ) VOUT (V) ON/OFF
0 or Open Open NVM NVM
10 23.2 5.0 ON
10 15.8 3.3 ON
16.2 20.5 2.5 ON
16.2 17.4 1.8 ON
20 17.8 1.5 ON
20 15 1.35 ON
20 12.7 1.25 ON
20 11 1.2 ON
24.9 11.3 1.15 ON
24.9 9.09 1.1 ON
24.9 7.32 1.05 ON
24.9 5.76 0.9 ON
24.9 4.32 0.75 ON
30.1 3.57 0.65 ON
30.1 1.96 0.6 ON
Open 0 NVM OFF
Table4. PHAS_CFG
RTOP (kΩ) RBOTTOM (kΩ)
θSYNC TO θ0θSYNC TO θ
SYNC DIS/EN
0 or Open Open NVM NVM NVM
10 23.2 NVM NVM NVM
10 15.8 NVM NVM NVM
16.2 20.5 120 300 DISABLE
16.2 17.4 60 240 DISABLE
20 17.8 120 240 DISABLE
20 15 0 120 DISABLE
20 12.7 0 240 DISABLE
20 11 90 270 DISABLE
24.9 11.3 0 180 DISABLE
24.9 9.09 120 300 ENABLE
24.9 7.32 60 240 ENABLE
24.9 5.76 120 240 ENABLE
24.9 4.32 0 120 ENABLE
30.1 3.57 0 240 ENABLE
30.1 1.96 90 270 ENABLE
Open 0 0 180 ENABLE
Frequency and Phase Selection Using RCONFIG
The frequency and phase commands are not linked either
using RCONFIG pins or PMBus commands. The SYNC
pins must be shared in PolyPhase configurations where
multiple LTC3887s are used to produce the output. If
the configuration is not PolyPhase the SYNC pins do not
have to be shared. If the SYNC pins are shared between
LTC3887s only one SYNC output should be enabled, all
other SYNC outputs should be disabled. If the SYNC out-
put is enabled, the oscillator frequency is present on the
open-drain SYNC pin. A resistor pull-up to V
DD33
on SYNC
is required.
For example in a 4-phase configuration clocked at 425kHz,
all of the LTC3887s must be set to the desired frequency
and phase and one LTC3887 should be set to the desired
frequency with the SYNC output disabled. All phasing is
with respect to the falling edge of SYNC.
LTC3887 chip 1 set the frequency to 425kHz with 90° and
270° phase shift with the SYNC output enabled:
Frequency RTOP = 24.9kΩ and RBOTTOM = 4.32kΩ
Phase RTOP = 20kΩ and RBOTTOM = 11kΩ
LTC3887 chip 2 set the frequency to 425kHz with 0° and
180° phase shift and the SYNC output disabled:
Frequency 24.9kΩ and RBOTTOM = 4.32kΩ
Phase RTOP open and RBOTTOM = 0Ω
All configurations in frequency and phase can be achieved
using the FREQ_CFG and PHAS_CFG pins. In the above
application, if the SYNC pin connection is lost from chip
1, chip 2 will internally detect the frequency is missing
and continue switching at 425kHz. However, because the
SYNC pin is disconnected between the chips, the output
voltage ripple will likely be higher than desired. Bit 10 of
MFR_PADS will assert low on chip 2 indicating chip 2 is
providing its own internal oscillator when it is expecting
an external SYNC input.
LTC3887/LTC3887-1/
LTC3887-2
53
Rev. F
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Address Selection Using RCONFIG
The LTC3887 address is selected using a combination
of the address stored in EEPROM and the ASEL0 and
ASLE1 pins. The MSB of ASEL is either the MSB in the
EEPROM or the value decoded in ASEL1 and the LSB
is the value decoded in ASEL0. This allows all available
PMBus addresses to be decoded by LTC3887s on a single
board with one programmed address in EEPROM. If 16 or
less LTC3887s are on a board, the user need only popu-
late resistors on ASEL 0 if all LTC3887s can share the
same MSB address.
If the address stored in EEPROM is 0x4F, then the part
address can be set from 0x40 to 0x4F using ASEL0 and
ASEL1. (The standard default address is 0x4F). Do not set
any part address to 0x5A or 0x5B because these are global
addresses and all parts will respond to them.
To choose address 0x40 ASEL0 RTOP is open and
RBOTTOM = 0Ω
ASEL1 is open
To choose address 0x45 ASEL0 RTOP = 24.9k and
RBOTTOM = 7.32k
ASEL1 is open
To choose address 0x3E ASEL0 RTOP = 10.0k and
RBOTTOM = 15.8k
ASEL1 RTOP = 24.9k and RBOTTOM = 4.32k
Table6. ASELn Resistor Programming
RTOP (kΩ) RBOT (kΩ)
ASEL1 ASEL0
LTC3886 DEVICE
ADDRESS BITS[6:4]
LTC3886 DEVICE
ADDRESS BITS[3:0]
BINARY HEX BINARY HEX
0 or Open Open NVM NVM
10 23.2 1111 F
10 15.8 1110 E
16.2 20.5 1101 D
16.2 17.4 1100 C
20 17.8 1011 B
20 15 1010 A
20 12.7 1001 9
20 11 1000 8
24.9 11.3 111 7 0111 7
24.9 9.09 110 6 0110 6
24.9 7.32 101 5 0101 5
24.9 5.76 100 4 0100 4
24.9 4.32 011 3 0011 3
30.1 3.57 010 2 0010 2
30.1 1.96 001 1 0001 1
Open 0 000 0 0000 0
EFFICIENCY CONSIDERATIONS
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Table5. FREQ_CFG (Phase Based on Falling Edge of SYNC)
RTOP (kΩ) RBOTTOM (kΩ) FREQUENCY (kHz)
0 or Open Open NVM
10 23.2 NVM
10 15.8 NVM
16.2 20.5 NVM
16.2 17.4 NVM
20 17.8 NVM
20 15 NVM
20 12.7 NVM
20 11 1000
24.9 11.3 750
24.9 9.09 650
24.9 7.32 575
24.9 5.76 500
24.9 4.32 425
30.1 3.57 350
30.1 1.96 250
Open 0 External Clock
LTC3887/LTC3887-1/
LTC3887-2
54
Rev.F
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Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3887 circuits: 1) IC VIN current, 2) INTVCC
regulator current, 3) I2R losses, 4) Topside MOSFET tran-
sition losses.
1. The VIN current is the DC supply current given in
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. VIN current typi-
cally results in a small (<0.1%) loss.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTVCC to ground. The resulting dQ/dt is a cur-
rent out of INTV
CC
that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
On the LTC3887-2, supplying EXTVCC from an output
derived source will scale the VIN current required for
the driver and control circuits by a factor of:
(VEXT/VIN) • (1/Efficiency)
3. I
2
R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor.
In continuous mode, the average output current flows
through L and RSENSE, but is “chopped” between the
topside MOSFET and the synchronous MOSFET. If the
two MOSFETs have approximately the same RDS(ON),
then the resistance of one MOSFET can simply be
summed with the resistances of L and RSENSE to obtain
I2R losses. For example, if each RDS(ON) = 10mΩ,
RL = 10mΩ, RSENSE = 5mΩ, then the total resistance
is 25mΩ. This results in losses ranging from 2% to
8% as the output current increases from 3A to 15A for
a 5V output, or a 3% to 12% loss for a 3.3V output.
Efficiency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digi-
tal systems is not doubling but quadrupling the impor-
tance of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) VIN2 IO(MAX) CRSS f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that CIN has
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having
a maximum of 20mΩ to 50mΩ of ESR. The LTC3887
2-phase architecture typically halves this input capacitance
requirement over competing solutions. Other losses
including Schottky conduction losses during dead time
and inductor core losses generally account for less than
2% total additional loss.
CHECKING TRANSIENT RESPONSE
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
Table7. B1. LTC3887 MFR_ADDRESS Command Examples
Expressing Both 7- or 8-Bit Addressing
DESCRIPTION
HEX DEVICE
ADDRESS BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0 R/W7 BIT 8 BIT
Rail40x5A 0xB4 0 1 0 1 1 0 1 0 0
Global40x5B 0xB6 0 1 0 1 1 0 1 1 0
Default 0x4F 0x9E 0 1 0 0 1 1 1 1 0
Example 1 0x60 0xC0 0 1 1 0 0 0 0 0 0
Example 2 0x61 0xC2 0 1 1 0 0 0 0 1 0
Disabled2,3,5 10000000 0
Note 1: This table can be applied to the MFR_RAIL_ADDRESS command
as well as the MFR_ADDRESS command.
Note 2: A disabled value in one command does not disable the device, nor
does it disable the Global address.
Note 3: A disabled value in one command does not inhibit the device from
responding to device addresses specified in other commands.
Note 4: It is not recommended to write the value 0x00, 0x0C (7 bit),
or 0x5A or 0x5B(7 bit) to the MFR_ADDRESS, or the MFR_RAIL_
ADDRESS commands.
Note 5: To disable the address enter 0x80 in the MFR_ADDRESS
command. The 0x80 is greater than the 7-bit address field, disabling
the address.
LTC3887/LTC3887-1/
LTC3887-2
55
Rev. F
For more information www.analog.com
APPLICATIONS INFORMATION
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge
or discharge COUT generating the feedback error signal
that forces the regulator to adapt to the current change
and return VOUT to its steady-state value. During this
recovery time VOUT can be monitored for excessive over-
shoot or ringing, which would indicate a stability problem.
The availability of the ITH pin not only allows optimization
of control loop behavior but also provides a DC-coupled
and AC-filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed loop response. Assuming a predominantly
second order system, phase margin and/or damping fac-
tor can be estimated using the percentage of overshoot
seen at this pin. The bandwidth can also be estimated
by examining the rise time at the pin. The I
TH
external
components shown in the Typical Applications circuit
will provide an adequate starting point for most applica-
tions. The only two programmable parameters that affect
loop gain are the voltage range, bit 1 of the MFR_PWM_
MODE_LTC3887 command and the current range, bit 7 of
the MFR_PWM_MODE_LTC3887 command. Be sure to
establish these settings prior to compensation calculation.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the
loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1µs to
10µs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. Placing a power MOSFET with
a resistor to ground directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce to a load step. The MOSFET
+ RSERIES will produce output currents approximately
equal to VOUT/RSERIES. RSERIES values from 0.1Ω to 2Ω
are valid depending on the current limit settings and the
programmed output voltage. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
why it is better to look at the ITH pin signal which is in the
feedback loop and is the filtered and compensated con-
trol loop response. The gain of the loop will be increased
by increasing RC and the bandwidth of the loop will be
increased by decreasing C
C
. If R
C
is increased by the same
factor that C
C
is decreased, the zero frequency will be kept
the same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • C
LOAD
. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
PC BOARD LAYOUT CHECKLIST
When laying out the printed circuit board, the follow-
ing checklist should be used to ensure proper operation
of the IC. These items are also illustrated graphically in
the layout diagram of Figure32. Figure33 illustrates the
current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M2 located
within 1 cm of each other with a common drain
connection at CIN? Do not attempt to split the input
decoupling for the two channels as it can cause a
large resonant loop.
2. Are the signal and power grounds kept separate?
The combined IC signal ground pin and the ground
return of C
INTVCC
must return to the combined C
OUT
(–) terminals. The ITH traces should be as short as pos-
sible. The path formed by the top N-channel MOSFET,
LTC3887/LTC3887-1/
LTC3887-2
56
Rev.F
For more information www.analog.com
APPLICATIONS INFORMATION
Figure32. Recommended Printed Circuit Layout Diagram
Figure33. Branch Current Waveforms
CB0
CB1
CINTVCC
+
CIN
D1
1µF
CERAMIC
M1 M2
M3 M4 D2
+
CVIN
VIN
RIN
L1
L0
COUT1
VOUT1
GND
VOUT0
3887 F32
+
COUT2
+
RSENSE0
RSENSE1
fIN
1µF
CERAMIC
ITH1
VSENSE1
ISENSE1+
ISENSE1–
ISENSE0–
ISENSE0+
VSENSE0+
ITH0
TG1
SW1
BOOST1
BG1
VIN
GND
INTVCC
BG0
BOOST0
SW0
TG0
SYNC
RUN0
RUN1
LTC3887
VSENSE0–
RL1
D1
L1
SW1 RSENSE1 VOUT1
COUT1
VIN
CIN
RIN
RL0
D0
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
L0
SW0
3887 F33
RSENSE0 VOUT0
COUT0
LTC3887/LTC3887-1/
LTC3887-2
57
Rev. F
For more information www.analog.com
APPLICATIONS INFORMATION
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Does the LTC3887 VSENSE lines equal VOUT? VOUT0 is
differential. VOUT1 should reference the GND (Pin 41)
to the Load 1 ground.
4. Are the ISENSE+ and ISENSE– leads routed together
with minimum PC trace spacing? The filter capacitor
between ISENSE+ and ISENSE– should be as close as pos-
sible to the IC. Ensure accurate current sensing with
Kelvin connections at the sense resistor or inductor,
whichever is used for current sensing.
5. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET drivers cur-
rent peaks. An additional 1µF ceramic capacitor placed
immediately next to the INTVCC and GND pins can help
improve noise performance substantially.
6. Keep the switching nodes (SW1, SW0), top gate nodes
(TG1, TG0), and boost nodes (BOOST1, BOOST0) away
from sensitive small-signal nodes, especially from the
opposite channel’s voltage and current sensing feed-
back pins. All of these nodes have very large and fast
moving signals and therefore should be kept on the
“output side” of the LTC3887 and occupy minimum
PC trace area. If DCR sensing is used, place the top
resistor (Figure25a, R1) close to the switching node.
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feed-
back resistive divider and the GND pin of the IC.
PC BOARD LAYOUT DEBUGGING
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output volt-
age as well. Check for proper performance over the operat-
ing voltage and current range expected in the application.
The frequency of operation should be maintained over the
input voltage range down to dropout.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or volt-
age sensing inputs or inadequate loop compensation.
Overcompensation of the loop can be used to tame a
poor PC layout if regulator bandwidth optimization is not
required. Only after each controller is checked for its indi-
vidual performance should both controllers be turned on
at the same time. A particularly difficult region of opera-
tion is when one controller channel is nearing its current
comparator trip point when the other channel is turning
on its top MOSFET. This occurs around 50% duty cycle
on either channel due to the phasing of the internal clocks
and may cause minor duty cycle jitter.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V
IN
while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent
to the pins of the IC. This capacitor helps to minimize
the effects of differential noise injection due to high fre-
quency capacitive coupling. If problems are encountered
with high current output loading at lower input voltages,
look for inductive coupling between CIN, Schottky and
the top MOSFET components to the sensitive current and
voltage sensing traces. In addition, investigate common
ground path voltage pickup between these components
and the GND pin of the IC.
LTC3887/LTC3887-1/
LTC3887-2
58
Rev.F
For more information www.analog.com
DESIGN EXAMPLE
As a design example for a two channel medium current
regulator, assume VIN = 12V nominal, VIN = 20V maxi-
mum, VOUT0 = 3.3V, VOUT1 = 1.8V, IMAX0,1 = 15A and f =
500kHz (see Figure34).
The regulated output is established by the VOUT_
COMMAND stored in EEPROM or placing the following
resistor divider between VDD25 the RCONFIG pin and GND:
1. VOUT0_CFG, RTOP = 10k, RBOTTOM = 15.8k
2. VOUT1_CFG, RTOP = 16.2k, RBOTTOM = 17.4k
The frequency and phase are set by EEPROM or by setting
the resistor divider between VDD25 FREQ_CFG and GND
and VDD25 PHAS_CFG and GND with:
Frequency RTOP = 24.9kΩ and RBOTTOM = 5.76kΩ
Phase RTOP = Open and RBOTTOM = 0Ω
The address is set to XF where X is the MSB stored in
EEPROM.
The following parameters are set as a percentage of the
output voltage if the resistor configuration pins are used
to determined output voltage:
n VOUT_OV_FAULT_LIMIT .................................... +10%
n VOUT_OV_WARN .............................................. +7.5%
n VOUT_MAX....................................................... +7.5%
APPLICATIONS INFORMATION
Figure34. High Efficiency Dual 500kHz 3.3V/1.8V Step-Down Converter
VIN
VDD33 VDD25
GND
TG0
0.1µF
4.99k
0.1µF
1µF
1µF
L0, L1: VISHAY IHLP-4040DZ-11 1µH, 0.56µH
M1, M2: INFINEON BSC050NE2LS
M3, M4: INFINEON BSC010NE2LSI
530µF: 330µF SANYO 4TPF330ML, 2x 100µF 12106D107KAT2A
1µF
4700pF
0.22µF 0.22µF
2200pF
22µF
VIN
6V TO 24V
10µF
+
530µF
D2
M2
M4
10k
15.8k
VDD25
M1
M3
VOUT1
1.8V
15A
4.99k 4.99k
2.0k
1µF
L1
0.56µH
L0
1.0µH
D1
TG1
BG0
SYNC
10k
16.2k
17.4k
10k
1µF
1.58k
23.2k
GPIO0
10k
GPIO1
10k
SDA
10k
SCL
ALERT
10k
RUN0
FREQ_CFG
VOUT0_CFG
VOUT1_CFG
ASEL1
PHAS_CFG
ASEL0
RUN1
WP
10k
2.0k 1.58k
SHARE_CLK
VDD33
BG1
BOOST0 BOOST1
SW0 SW1
INTVCC
LTC3887
TSNS0 TSNS1
ITHO ITH1
ISENSEO+ISENSE1+
VSENSEO+VSENSE1
VSENSEO–
ISENSEO–ISENSE1–
VOUT0
3.3V
15A
VOUT1
1.8V
15A
VOUT1
1.8V
15A
+
530µF
3887 F34
220pF 220pF10nF 10nF
24.9k
5.76k
LTC3887/LTC3887-1/
LTC3887-2
59
Rev. F
For more information www.analog.com
APPLICATIONS INFORMATION
n VOUT_MARGIN_HIGH .........................................+5%
n VOUT_MARGIN_LOW ..........................................–5%
n VOUT_UV_WARN ..............................................–6.5%
n VOUT_UV_FAULT_LIMIT ......................................–7%
All other user defined parameters must be programmed
into the EEPROM. The GUI can be utilized to quickly set
up the part with the desired operating parameters.
The inductance values are based on a 35% maximum
ripple current assumption (5.25A for each channel). The
highest value of ripple current occurs at the maximum
input voltage:
L=VOUT
f • ΔIL(MAX)
1– VOUT
VIN(MAX)
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
Channel 0 will require 1.05µH and channel 1 will require
0.624µH. The nearest standard values are 1µH and 0.68µH
respectively. At the nominal input the ripple will be:
ΔIL(NOM) =VOUT
f •L 1– VOUT
VIN(NOM)
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
Channel 0 will have 4.79A (32%) ripple, and channel 1 will
have 5.5A (30%) ripple. The peak inductor current will be
the maximum DC value plus one-half the ripple current
or 17.39A for channel 0 and 17.75A for channel 1. The
minimum on time occurs on channel 1 at the maximum
VIN, and should not be less than 45ns:
tON(MIN) =VOUT
VIN(MAX) • f =1.8V
20V 500kHz
( )
=180ns
The Vishay IHLP4040DZ-11 1µH (2.3mΩ DCRTYP at
25°C) channel 0 and the Vishay IHLP4040DZ-11 0.56µH
(1.61mΩ DCRTYP at 25°C) channel 1 are chosen.
Assuming the temperature measurement of the induc-
tor temperature is accurate and C1 is set to 0.2µF, RD is
infinite and removed from the equations.
R0 = L
DCR at 25°C
( )
•C1=1 µH
2.3mΩ • 0.22µF = 2k
The maximum power loss in R0 is related to the duty
cycle, and will occur in continuous mode at the maximum
input voltage:
PLOSSR0 =VIN(MAX) – VOUT
( )
• VOUT
R1
=20 – 3.3
( )
• 3.3
2k =27.55mW
The respective values for channel 1 are R1 = 2k, R2 is
open and PLOSSR1 = 20.73mW.
The current limit will be set 20% higher than the peak
value to assure variation in components and noise in the
system do not limit the average current.
VILIMIT = IPEAK • RDCR(MAX) = 17.39A • 2.5mΩ = 43mV
The closest VILIMIT setting is 42.9mV or 46.4mV. The val-
ues are entered with the IOUT_OC_FAULT_LIMIT com-
mand. Based on expected variation and measurement in
the lab across the sense capacitor the user can deter-
mine the optimal setting. For channel 1 the VILIMT value
is 28.6mV. The closest value is 28.6mV.
The power dissipation on the top side MOSFET can be eas-
ily estimated. Choose a INFINEON BSC050NE2LS topside
MOSFET. R
DS(ON)
= 5.7mΩ, C
MILLER
= 35pF. At maximum
input voltage with T estimated = 50°C and a bottom side
MOSFET a INFINEON BSC010NE2LSI, RDS(ON) = 1.1mΩ:
P
MAIN =
3.3V
20V • 17.39
( )
2• 1+ 0.005
( )
50°C – 25°C
( )
⎡
⎣⎤
⎦
•0.0057Ω+ 20V
( )
28.695A
( )
•1
5– 2.3 +1
2.3
⎛
⎝
⎜⎞
⎠
⎟
35pF
( )
500kHz
( )
= 0.369W
The loss in the bottom side MOSFET is:
PSYNC =
20V – 3.3V
( )
20V • 17.39A
( )
2•
1+ 0.005
( )
50°C – 25°C
( )
⎡
⎣⎤
⎦•0.0011Ω
= 0.312W
LTC3887/LTC3887-1/
LTC3887-2
60
Rev.F
For more information www.analog.com
APPLICATIONS INFORMATION
Both MOSFETS have I2R losses while the PMAIN equation
includes an additional term for transition losses, which
are highest at high input voltages.
CIN is chosen for an RMS current rating of:
CIN RequiredIRMS =
17.39
20 3.3
( )
• 20 – 3.3
( )
⎡
⎣⎤
⎦1/2
=6.5A
at temperature assuming only channel 0 or 1 is on. COUT
is chosen with an ESR of 0.006Ω for low output ripple.
The output ripple in continuous mode will be highest at
the maximum input voltage. The output voltage ripple due
to ESR is
VORIPPLE = R(∆IL) = 0.006Ω • 5.5A = 33mV.
ADDITIONAL DESIGN CHECKS
• Tie GPIO0 and GPIO1 together and pull up to VDD33
with a 10k resistor.
• Tie RUN0 and RUN1 together and pull up to V
DD33
with
a 10k resistor.
• If there are other ADI PSM parts, connect the RUN
pins between chips and connect the GPIO pins between
chips.
• Be sure all PMBus pins have resistor pull up to VDD33
and connect these inputs across all ADI PSM parts in
the application.
• Tie SHARE_CLK high with a 4.99k resistor to VDD33 and
share between all ADI PSM parts in the application.
• Be sure a unique address for each chip can be decoded
with the ASEL0 and ASEL1 pins. Refer to Table6.
• For maximum flexibility, allow board space for R
TOP
and RBOTTOM for any parameter that is set with resis-
tors such as ASEL0 and ASEL1.
CONNECTING THE USB TO THE I2C/SMBus/PMBus
CONTROLLER TO THE LTC3887 IN SYSTEM
The ADI USB to I2C/SMBus/PMBus controller can
be interfaced to the LTC3887 on the user’s board for
programming, telemetry and system debug. The control-
ler, when used in conjunction with LTpowerPlay, provides
a powerful way to debug an entire power system. Faults
are quickly diagnosed using telemetry, fault status reg-
isters and the fault log. The final configuration can be
quickly developed and stored to the LTC3887 EEPROM.
Figure35 illustrates the application schematic for pow-
ering, programming and communication with one or
more LTC3887s via the ADI I2C/SMBus/PMBus control-
ler regardless of whether or not system power is present.
If system power is not present the dongle will power
the LTC3887 through the V
DD33
supply pin. To initial-
ize the part when VIN is not applied and the VDD33 pin
is powered use global address 5B command 0xBD data
0x2B followed by address 5B command 0xBD data 0xC4.
The part can now be communicated with, and the proj-
ect file updated. To write the updated project file to the
EEPROM issue a STORE_USER_ALL command. When
VIN is applied, a MFR_RESET must be issued to allow the
PWM to be enabled and valid ADCs to be read.
Because of the controllers limited current sourcing capa-
bility, only the LTC3887s, their associated pull-up resis-
tors and the I2C pull-up resistors should be powered from
the ORed 3.3V supply from the ADI dongle DC1613A. In
addition any device sharing the I2C bus connections with
the LTC3887 should not have body diodes between the
SDA/SCL pins and their respective V
DD
node because this
will interfere with bus communication in the absence of
system power. If VIN is applied to the board, the dongle
will not supply power to the LTC3887s on the board. It
is recommended the RUN pins be held low or no voltage
configuration resistors inserted to avoid providing power
to the load until the part is fully configured.
The ADI controller I2C connections are opto-isolated
from the PC USB using ADI dongle DC1613A. The 3.3V
from the controller and the LTC3887 VDD33 pin must be
driven to each LTC3887 with a separate PFET. If VIN is
not applied, the VDD33 pins can be in parallel because the
on-chip LDO is off. The DC1613A 3.3V current limit is
100mA but typical VDD33 currents are under 15mA. The
VDD33 does back drive the INTVCC/EXTVCC pin. Normally
this is not an issue if VIN is open.
LTC3887/LTC3887-1/
LTC3887-2
61
Rev. F
For more information www.analog.com
APPLICATIONS INFORMATION
Figure35. ADI Controller Connection
Figure36.
VIN
VIN
VDD33 VDD25
SDA
1µF
1µF
VGS MAX ON THE TP0101K IS 8V IF VIN > 16V
CHANGE THE RESISTOR DIVIDER ON THE PFET GATE
1µF
1µF
3887 F35
10k
100k
TP0101K
ISOLATED 3.3V
SDA
SCL
TP0101K
100k
LTC
CONTROLLER
HEADER
TO LTC DC1613
USB TO I2C/SMBus/PMBus
CONTROLLER
SCL
WP GND
VIN
VDD33
SDA
SCL
WP GND
10k
VDD25
LTC3887
LTC3887
LTC3887/LTC3887-1/
LTC3887-2
62
Rev.F
For more information www.analog.com
APPLICATIONS INFORMATION
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL
POWER
LTpowerPlay is a powerful Windows-based development
environment that supports Analog Devices, Inc. digital
power ICs including the LTC3887. The software supports
a variety of different tasks. LTpowerPlay can be used to
evaluate Analog Devices, Inc. ICs by connecting to a demo
board or the user application. LTpowerPlay can also be
used in an offline mode (with no hardware present) in
order to build multiple IC configuration files that can be
saved and re-loaded at a later time. LTpowerPlay pro-
vides unprecedented diagnostic and debug features. It
becomes a valuable diagnostic tool during board bring-up
to program or tweak the power system or to diagnose
power issues when bring up rails. LTpowerPlay utilizes the
Analog Devices, Inc. USB-to-I2C/SMBus/PMBus controller
to communication with one of the many potential targets
including the DC1590B-A/B demo board, the DC1709A
socketed programming board, or a customer target sys-
tem. The software also provides an automatic update
feature to keep the revisions current with the latest set of
device drivers and documentation. A great deal of context
sensitive help is available with LTpowerPlay along with sev-
eral tutorial demos. Complete information is available at
LTpowerPlay.
PMBus COMMUNICATION AND COMMAND
PROCESSING
The LTC3887 have a one deep buffer to hold the last data
written for each supported command prior to processing
as shown in Figure37; Write Command Data Processing.
When the part receives a new command from the bus,
it copies the data into the Write Command Data Buffer,
indicates to the internal processor that this command data
needs to be fetched, and converts the command to its
internal format so that it can be executed.
Two distinct parallel blocks manage command buffer-
ing and command processing (fetch, convert, and exe-
cute) to ensure the last data written to any command is
never lost. Command data buffering handles incoming
PMBus writes by storing the command data to the Write
Command Data Buffer and marking these commands
for future processing. The internal processor runs in
parallel and handles the sometimes slower task of fetch-
ing, converting and executing commands marked for
processing.
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internal processor execution times that may be long rela-
tive to PMBus timing. If the part is busy processing a
command, and new command(s) arrive, execution may
be delayed or processed in a different order than received.
The part indicates when internal calculations are in pro-
cess via bit5 of MFR_COMMON (‘calculations not pend-
ing’). When the part is busy calculating, bit 5 is cleared.
When this bit is set, the part is ready for another com-
mand. An example polling loop is provided in Figure37
which ensures that commands are processed in order
while simplifying error handling routines.
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads. It
may also generate a BUSY fault and ALERT notification,
or stretch the SCL clock low. For more information refer
Figure37. Write Command Data Processing
DECODER
CMD
INTERNAL
PROCESSOR
WRITE COMMAND
DATA BUFFER
PAGE
CMDS
0x00
0x21
0xFD
3887 F37
x1
•
•
•
•
•
•
MFR_RESET
VOUT_COMMAND
S
CALCULATIONS
PENDING
PMBus
WRITE
R
FETCH,
CONVERT
DATA
AND
EXECUTE
DATA
MUX
LTC3887/LTC3887-1/
LTC3887-2
63
Rev. F
For more information www.analog.com
APPLICATIONS INFORMATION
to PMBus Specification v1.2, Part II, Section 10.8.7 and
SMBus v2.0 section 4.3.3. Clock stretching can be enabled
by asserting bit 1 of MFR_CONFIG_ALL_LTC3887. Clock
stretching will only occur if enabled and the bus com-
munication speed exceeds 100kHz.
PMBus busy protocols are well accepted standards, but
can make writing system level software somewhat com-
plex. The part provides three ‘hand shaking’ status bits
which reduce complexity while enabling robust system
level communication.
The three hand shaking status bits are in the MFR_
COMMON register. When the part is busy executing an
internal operation, it will clear bit 6 of MFR_COMMON
(‘chip not busy’). When the part is busy specifically
because it is in a transitional VOUT state (margining hi/lo,
power off/on, moving to a new output voltage set point,
etc.) it will clear bit 4 of MFR_COMMON (‘output not in
transition’). When internal calculations are in process,
the part will clear bit5 of MFR_COMMON (‘calculations
not pending’). These three status bits can be polled with
a PMBus read byte of the MFR_COMMON register until
all three bits are set. A command immediately follow-
ing the status bits being set will be accepted without
NACKing or generating a BUSY fault/ALERT notification.
The part canNACK commands for other reasons, how-
ever, as required by the PMBus spec (for instance, an
invalid command or data). An example of a robust com-
mand write algorithm for the VOUT_COMMAND register
is provided in Figure38.
Figure38. Example of a Command Write of VOUT_COMMAND
// wait until bits 6, 5, and 4 of MFR_COMMON are all set
do
{
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x68) == 0x68;
}
while(!partReady)
// n
ow the part is ready to receive the next command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V
It is recommended that all command writes (write byte,
write word, etc.) be preceded with a polling loop to avoid
the extra complexity of dealing with busy behavior and
unwanted ALERT notification. A simple way to achieve this
is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_
WORD() subroutine. The above polling mechanism allows
your software to remain clean and simple while robustly
communicating with the part. For a detailed discussion
of these topics and other special cases please refer to
the application note section located at www.linear.com/
designtools/app_notes.
When communicating using bus speeds at or below
100kHz, the polling mechanism shown here provides a
simple solution that ensures robust communication with-
out clock stretching. At bus speeds in excess of 100kHz,
it is strongly recommended that the part be configured to
enable clock stretching. This requires a PMBus master that
supports clock stretching. System software that detects
and properly recovers from the standard PMBus NACK/
BUSY faults as described in the PMBus Specification v1.2,
Part II, Section 10.8.7 is required to communicate.
The LTC3887 is not recommended in applications with
bus speeds in excess of 400kHz.
LTC3887/LTC3887-1/
LTC3887-2
64
Rev.F
For more information www.analog.com
PMBus
COMMAND DETAILS
PAGE
The PAGE command provides the ability to configure, control and monitor both PWM channels through only one physi-
cal address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating commands for
one PWM channel.
Pages 0x00 and 0x01 correspond to channel 0 and channel 1, respectively, in this device.
Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF the LTC3887
will respond to read commands as if PAGE were set to 0x00 (channel 0 results).
This command has one data byte.
PAGE_PLUS_WRITE
The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command and then send
the data for the command, all in one communication packet. Commands allowed by the present write protection level
may be sent with PAGE_PLUS_WRITE.
The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send
a non-paged command, the Page Number byte is ignored.
This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a com-
mand that has two data bytes is shown in Figure39.
ADDRESSING AND WRITE PROTECT
COMMAND NAME
CMD
CODE DESCRIPTION TYPE
PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
PAGE 0x00 Channel (page) presently selected for any
paged command.
R/W Byte N Reg 0x00
PAGE_PLUS_WRITE 0x05 Write a command directly to a specified page. W Block N
PAGE_PLUS_READ 0x06 Read a command directly from a specified
page.
Block R/W
Process
N
WRITE_PROTECT 0x10 Protect the device against unintended PMBus
modifications.
R/W Byte N Reg l0x00
MFR_ADDRESS 0xE6 Specify right-justified 7-bit device address. R/W Byte N Reg l0x4F
MFR_RAIL_ADDRESS 0xFA Specify unique right-justified 7-bit address
for channels comprising a PolyPhase output.
R/W Byte Y Reg l0x80
Related commands: MFR_COMMON.
Figure39. Example of PAGE_PLUS_WRITE
SLAVE
ADDRESS
PAGE_PLUS
COMMAND CODE
BLOCK COUNT
(= 4)
W A AS
7 8 8 1
PAGE
NUMBER
8 11 1 11
A A …
COMMAND
CODE
8 1
A
UPPER DATA
BYTE A A P
3887 F39
A
8 81 1 11
PEC BYTE
LOWER DATA
BYTE
8
LTC3887/LTC3887-1/
LTC3887-2
65
Rev. F
For more information www.analog.com
PAGE_PLUS_READ
The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command and then read
the data returned by the command, all in one communication packet .
The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access
data from a non-paged command, the Page Number byte is ignored.
This command uses Block Write – Block Read Process Call protocol. An example of the PAGE_PLUS_READ command
with PEC is shown in Figure40.
NOTE: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another
PAGE_PLUS command. If this is attempted, the LTC3887 will NACK the entire PAGE_PLUS packet and issue a CML
fault for Invalid/Unsupported Data.
PMBus
COMMAND DETAILS
WRITE_PROTECT
The WRITE_PROTECT command is used to control writing to the LTC3887 device. This command does not indicate
the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the
value of this command.
BYTE MEANING
0x80 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_
EE_UNLOCK and STORE_USER_ALL command
0x40 Disable all writes except to the WRITE_PROTECT, PAGE,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL,
OPERATION and CLEAR_FAULTS command. individual fault
bits can be cleared by writing a 1 to the respective bits in the
STATUS registers.
0x20 Disable all writes except to the WRITE_PROTECT, OPERATION,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS,
PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_
ALL. Individual fault bits can be cleared by writing a 1 to the
respective bits in the STATUS registers.
0x10 Reserved, must be 0
0x08 Reserved, must be 0
0x04 Reserved, must be 0
0x02 Reserved, must be 0
0x01 Reserved, must be 0
When WRITE_PROTECT is set to 0x00, writes to all commands are enabled.
This command has one data byte.
Figure40. Example of PAGE_PLUS_READ
P
1
SLAVE
ADDRESS
PAGE_PLUS
COMMAND CODE
BLOCK COUNT
(= 2)
W A AS
7 8 8 1
PAGE
NUMBER
8 11 1 11
A A …
COMMAND
CODE
8 1
A
SLAVE
ADDRESS
BLOCK COUNT
(= 2)
LOWER DATA
BYTE
R A ASr
7 8 8 1
UPPER DATA
BYTE
8 11 1 11
A A PEC BYTE
8 1
NA
3887 F40
LTC3887/LTC3887-1/
LTC3887-2
66
Rev.F
For more information www.analog.com
If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK and CLEAR_FAULTS commands are
supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS registers.
MFR_ADDRESS
The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device.
Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B,
cannot be deactivated. If RCONFIG is set to ignore, the ASEL0 and ASEL1 pins are still used to determine the LSB
and MSB respectively of the channel address. If the ASEL1 pin is open, the LTC3887 will use the three MSBs of the
MFR_ADDRESS stored in EEPROM. If the ASEL0 pin is open, the LTC3887 will use the four LSBs of the MFR_ADDRESS
stored in EEPROM.
This command has one data byte.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value
of this command should be common to all devices attached to a single power supply rail.
The user should only perform command writes to this address. If a read is performed from this address and the rail
devices do not respond with EXACTLY the same value, the LTC3887 will detect bus contention and set a CML com-
munications fault.
Setting this command to a value of 0x80 disables rail device addressing for the channel.
This command has one data byte.
GENERAL CONFIGURATION REGISTERS
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_CHAN_CONFIG_LTC3887 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x1D
MFR_CONFIG_ALL_LTC3887 0xD1 Configuration bits that are common to all
pages.
R/W Byte N Reg Y 0x21
MFR_CHAN_CONFIG_LTC3887
General purpose configuration command common to multiple ADI products.
BIT MEANING
7 Reserved
6 Reserved
5 Reserved
4 Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF
3 Enable Short Cycle.
2 SHARE_CLOCK control, if SHARE_CLOCK is held low, the output is disabled
1 No GPIO ALERT, ALERT is not pulled low if GPIO is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are propagated
on GPIO
0 Disables the VOUT decay value requirement for MFR_RETRY_TIME processing. When this bit is set to a 0, the output must decay to less than
12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from high to low
to high.
This command has one data byte.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
67
Rev. F
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Bit[3]:A Short Cycle event occurs whenever the PWM channel is turned OFF and commanded back ON before the
TOFF_DELAY plus TOFF_FALL time has elapsed. If a Short Cycle event occurs and the bit is set to a 1 (enabled), the
output rail will IMMEDIATE_OFF and restart with a 120ms delay. If the Short Cycle event occurs and this bit is set to
a 0, the TOFF_DELAY plus TOFF_FALL times will be honored as a normal sequence off event, and the part will restart
after an additional 120ms delay.
MFR_CONFIG_ALL_LTC3887
General purpose configuration command common to multiple ADI products
BIT MEANING
7 Enable Fault Logging
6 Ignore Resistor Configuration Pins
5 Disable CML fault for Quick Command message
4 Disable SYNC out
3 Enable 255ms Time Out
2 A valid PEC required for PMBus writes to be accepted. If this bit is not set,
the part will accept commands with invalid PEC.
1 Enable the use of PMBus clock stretching
0 Enables a low to high transition on either RUN pin to issue a
CLEAR_FAULTS command
This command has one data byte.
ON/OFF/MARGIN
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
ON_OFF_CONFIG 0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte Y Reg Y 0x1E
OPERATION 0x01 Operating mode control. On/off, margin high and margin
low.
R/W Byte Y Reg Y 0x40
MFR_RESET 0xFD Commanded reset without requiring a power-down. Send Byte N NA
ON_OFF_CONFIG
The ON_OFF_CONFIG command configures the combination of RUNn pin input and serial bus commands needed to
turn the unit on and off. This includes how the unit responds when power is applied.
Table8. Supported Values
VALUE MEANING
0x1F OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off.
0x1E OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when
commanded off.
0x17 RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored.
0x16 RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.
Note: A high on the RUN pin is always required to start power conversion. Power conversion will always stop with a low on RUN.
Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored.
This command has one data byte.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
68
Rev.F
For more information www.analog.com
OPERATION
The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It
is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in
the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin
instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET
or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed
to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation
command is sequence off. If VIN is applied to a default part and the VOUT_CONFIG resistor configuration pins are not
installed, the outputs will be commanded off. If the voltage resistor configuration pins are installed, the output opera-
tion will be set to on and the part will regulate at the resistor configured output voltage.
Margin High (Ignore Faults) and Margin Low (Ignore Faults) operations are not supported by the LTC3887.
The part defaults to the Sequence Off state.
This command has one data byte.
Table9. OPERATION Command Detail Register OPERATION Data Contents
When On_Off_Config_Use_PMBus Enables Operation_Control
SYMBOL Action Value
BITS
FUNCTION
Turn off immediately 0x00
Turn on 0x80
Margin Low 0x98
Margin High 0xA8
Sequence off 0x40
OPERATION Data Contents When On_Off_Config is Configured Such That
OPERATION Command Is Not Used to Command Channel On or Off
SYMBOL Action Value
BITS
FUNCTION
Output at Nominal 0x80
Margin Low 0x98
Margin High 0xA8
Note: Attempts to write a reserved value will cause a CML fault.
MFR_RESET
This command provides a means by which the user can perform a reset of the LTC3887.
This write-only command has no data bytes.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
69
Rev. F
For more information www.analog.com
PWM CONFIG
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_PWM_MODE_
LTC3887
0xD4 Configuration for the PWM engine of each channel. R/W Byte Y Reg Y 0xC1
MFR_PWM_CONFIG_
LTC3887
0xF5 Set numerous parameters for the DC/DC controller
including phasing.
R/W Byte N Reg Y 0x10
FREQUENCY_SWITCH 0x33 Switching frequency of the controller. R/W Word N L11 kHz Y 350
0xFABC
MFR_PWM_MODE_LTC3887
The MFR_PWM_MODE_LTC3887 command allows the user to program the PWM controller to use, discontinuous
(pulse-skipping mode), or forced continuous conduction mode. Bits 7 and 1 of this command affect the loop gain of
the respective channels which may require modifications to the external compensation network.
BIT MEANING
7 Range of ILIMIT
0 – Low Current Range
1 – High Current Range
6 Enable Servo Mode
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Voltage Range
0 - Hi Voltage Range 5.5 volts max
1 - Lo Voltage Range 2.75 volts max
0 PWM Mode
0 - Discontinuous Mode
1 - Continuous Mode
Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this
command.
Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command.
Changing this bit value changes the PWM loop gain and compensation. Changing this bit value whenever an output is
active may have detrimental system results.
Bit [6] The LTC3887 will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo
is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC
and the VOUT_COMMAND (or the appropriate margined value).
Bit [1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes
the PWM loop gain and compensation. The respective channel must be off to modify this bit.
This command has one data byte.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
70
Rev.F
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PMBus
COMMAND DETAILS
MFR_PWM_CONFIG_LTC3887
The MFR_PWM_CONFIG_LTC3887 command sets the switching frequency phase offset with respect to the falling
edge of the SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low
or the part must be commanded off. If the part is in the RUN state and this command is written, the command will be
ignored and a BUSY fault will be asserted. Bit 7 allows remote differential voltage sensing for PolyPhase rail applications.
BIT MEANING
7 EA Connection
0 – Independent EA and Channel Outputs
1 – EA1 uses EA0 input for PolyPhase operation
6 Reserved.
5 Reserved
4 Share Clock Enable : If this bit is 1, the
SHARE_CLK pin will not be released until
VIN > VIN_ON. The SHARE_CLK pin will be
pulled low when VIN < VIN_OFF. If this bit is 0, the
SHARE_CLK pin will not be pulled low when VIN <
VIN_OFF except for the initial application of VIN.
3 Reserved
BIT [2:0] CHANNEL 0 (DEGREES) CHANNEL 1 (DEGREES)
000b 0 180
001b 90 270
010b 0 240
011b 0 120
100b 120 240
101b 60 240
110b 120 300
Do not assert Bit [7] unless it is a PolyPhase application and both VOUT pins are tied together and both ITH pins are
tied together.
This command has one data byte.
FREQUENCY_SWITCH
The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of a PMBus device.
Supported Frequencies:
VALUE [15:0] RESULTING FREQUENCY (TYP)
0x0000 External Oscillator
0xF3E8 250kHz
0xFABC 350kHz
0xFB52 425kHz
0xFBE8 500kHz
0x023F 575kHz
0x028A 650kHz
0x02EE 750kHz
0x03E8 1000kHz
LTC3887/LTC3887-1/
LTC3887-2
71
Rev. F
For more information www.analog.com
The part must be in the OFF state to process this command. Either the RUN pins must be low or the part must be
commanded off. If the part is in the RUN state and this command is written, the command will be ignored and a BUSY
fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be
detected as the PLL locks onto the new frequency.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOLTAGE
Input Voltage and Limits
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
VIN_OV_FAULT_ LIMIT 0x55 Input supply overvoltage fault limit. R/W Word N L11 V Y 15.5
0xD3E0
VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W Word N L11 V Y 6.3
0xCB26
VIN_ON 0x35 Input voltage at which the unit should start power
conversion.
R/W Word N L11 V Y 6.5
0xCB40
VIN_OFF 0x36 Input voltage at which the unit should stop power
conversion.
R/W Word N L11 V Y 6.0
0xCB00
VIN_OV_FAULT_LIMIT
The VIN_OV_FAULT_LIMIT command sets the value of the measured input voltage, in volts, that causes an input
overvoltage fault. The fault is detected with the A/D converter resulting in latency up to 120ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
VIN_UV_WARN_LIMIT
The VIN_UV_WARN_LIMIT command sets the value of the input voltage that causes an input undervoltage warning.
The warning is detected with the A/D converter resulting in latency up to 120ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
VIN_ON
The VIN_ON command sets the input voltage, in volts, at which the unit should start power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
VIN_OFF
The VIN_OFF command sets the input voltage, in volts, at which the unit should stop power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
72
Rev.F
For more information www.analog.com
PMBus
COMMAND DETAILS
Output Voltage and Limits
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
VOUT_MODE 0x20 Output voltage format and exponent (2–12). R Byte Y Reg 2–12
0x14
VOUT_MAX 0x24 Upper limit on the commanded output voltage
including VOUT_MARGIN_HIGH.
R/W Word Y L16 V Y 5.6
0x599A
VOUT_OV_FAULT_ LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 1.1
0x119A
VOUT_OV_WARN_ LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 1.075
0x1133
VOUT_MARGIN_HIGH 0x25 Margin high output voltage set point. Must be
greater than VOUT_COMMAND.
R/W Word Y L16 V Y 1.05
0x10CD
VOUT_COMMAND 0x21 Nominal output voltage set point. R/W Word Y L16 V Y 1.0
0x1000
VOUT_MARGIN_LOW 0x26 Margin low output voltage set point. Must be
less than VOUT_COMMAND.
R/W Word Y L16 V Y 0.95
0x0F33
VOUT_UV_WARN_ LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 0.925
0x0ECD
VOUT_UV_FAULT_ LIMIT 0x44 Output undervoltage fault limit. R/W Word Y L16 V Y 0.9
0x0E66
MFR_VOUT_MAX 0xA5 Maximum allowed output voltage including
VOUT_OV_FAULT_LIMIT.
R Word Y L16 V 5.7
0x5B33
VOUT_MODE
The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode
(only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write
commands.
This read-only command has one data byte.
VOUT_MAX
The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can com-
mand regardless of any other commands or combinations. The maximum allowed value of this command is 5.7 volts.
The maximum output voltage the LTC3887 can produce is 5.5 volts including VOUT_MARGIN_HIGH. However, the
VOUT_OV_FAULT_LIMIT can be commanded as high as 5.7 volts.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_FAULT_LIMIT
The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured at the sense pins, in volts, which
causes an output overvoltage fault.
If the VOUT_OV_FAULT_LIMIT is modified and the switcher is active, allow 10ms after the command is modified to
assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of
MFR_COMMON. Either bit is low if the part is busy. If this wait time is not met, and the VOUT_COMMAND is modified
above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior and
possible damage to the switcher.
LTC3887/LTC3887-1/
LTC3887-2
73
Rev. F
For more information www.analog.com
PMBus
COMMAND DETAILS
If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN, the GPIO pin will not assert if VOUT_OV_FAULT is propa-
gated. The LTC3887 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_WARN_LIMIT
The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured at the sense pins, in volts, which
causes an output voltage high warning. The READ_VOUT value will be used to determine if this limit has been exceeded.
In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 120ms.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_HIGH
The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in volts, when
the OPERATION command is set to “Margin High”. The value must be greater than VOUT_COMMAND. The maximum
guaranteed value on VOUT_MARGIN_HIGH is 5.5 volts.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_
RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_COMMAND
The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed
value on VOUT is 5.5 volts.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_
RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_LOW
The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts,
when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_
RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
LTC3887/LTC3887-1/
LTC3887-2
74
Rev.F
For more information www.analog.com
PMBus
COMMAND DETAILS
VOUT_UV_WARN_LIMIT
The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured at the sense pins, in volts,
which causes an output voltage low warning.
In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 120ms.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_FAULT_LIMIT
The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured at the sense pins, in volts,
which causes an output undervoltage fault.
This command has two data bytes and is formatted in Linear_16u format.
MFR_VOUT_MAX
The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel including VOUT_OV_FAULT_
LIMIT. If the output voltages are set to high range (Bit 1 of MFR_PWM_MODE_LTC3887 set to a 0) MFR_VOUT_MAX
for channel 0 and 1 is 5.7V. If the output voltages are set to low range (Bit 1 of MFR_PWM_MODE_LTC3887 set to a
1) the MFR_VOUT_MAX for both channels is 2.75V. Entering VOUT_COMMAND values greater than this will result in
a CML fault and the output voltage setting will be clamped to the maximum level.
This read-only command has 2 data bytes and is formatted in Linear_16u format.
CURRENT
Input Current Calibration
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_IIN_OFFSET 0xE9 Coefficient used to add to the input current to
account for the IQ of the part.
R/W
Word
Y L11 A Y 0.050
0x9333
MFR_IIN_OFFSET
The MFR_IIN_OFFSET command allows the user to set an input current representing the quiescent current of each
channel. For accurate results at low output current, the part should be in continuous conduction mode.
This command has 2 data bytes and is formatted in Linear_5s_11s format.
LTC3887/LTC3887-1/
LTC3887-2
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COMMAND DETAILS
Output Current Calibration
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
IOUT_CAL_GAIN 0x38 The ratio of the voltage at the current sense pins
to the sensed current. For devices using a fixed
current sense resistor, it is the resistance value
in mΩ.
R/W Word Y L11 mΩ Y 1.8
0xBB9A
MFR_IOUT_CAL_GAIN_TC 0xF6 Temperature coefficient of the current sensing
element.
R/W Word Y CF Y 3900
0x0F3C
IOUT_CAL_GAIN
The IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms. (see
also MFR_IOUT_CAL_GAIN_TC).
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_IOUT_CAL_GAIN_TC
The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the IOUT_CAL_
GAIN sense resistor or inductor DCR in ppm/°C.
This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 •
10–6. Nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by:
[1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)]. DCR sensing will have a typical value of 3900.
The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT, READ_IIN,
IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT.
Input Current
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
IIN_OC_WARN_LIMIT 0x5D Input overcurrent warning limit. R/W Word N L11 A Y 10.0
0xD280
IIN_OC_WARN_LIMIT
The IIN_OC_WARN_LIMIT command sets the value of the input current, in amperes, that causes a warning indicating
the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded.
In response to the IIN_OC_WARN_LIMIT being exceeded, the device:
• Sets the OTHER bit in the STATUS_BYTE
• Sets the INPUT bit in the upper byte of the STATUS_WORD
• Sets the IIN Overcurrent Warning bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin, unless masked
This condition is detected by the ADC so the response time may be up to 120ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
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Output Current
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 A Y 29.75
0xDBB8
IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A Y 20.0
0xDA80
IOUT_OC_FAULT_LIMIT
The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in amperes. When the controller
is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The programmed overcurrent
fault limit value is rounded up to the nearest one of the following set of discrete values:
25mV/IOUT_CAL_GAIN Low Range (1.5x Nominal Loop Gain)
MFR_PWM_MODE_LTC3887 [7]=0
28.6mV/IOUT_CAL_GAIN
32.1mV/IOUT_CAL_GAIN
35.7mV/IOUT_CAL_GAIN
39.3mV/IOUT_CAL_GAIN
42.9mV/IOUT_CAL_GAIN
46.4mV/IOUT_CAL_GAIN
50mV/IOUT_CAL_GAIN
37.5mV/IOUT_CAL_GAIN High Range (Nominal Loop Gain)
MFR_PWM_MODE_LTC3887 [7]=1
42.9mV/IOUT_CAL_GAIN
48.2mV/IOUT_CAL_GAIN
53.6mV/IOUT_CAL_GAIN
58.9mV/IOUT_CAL_GAIN
64.3mV/IOUT_CAL_GAIN
69.6mV/IOUT_CAL_GAIN
75mV/IOUT_CAL_GAIN
Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output
current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation:
IOUT_OC_FAULT_LIMIT = IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)).
The LTpowerPlay GUI automatically convert the voltages to currents.
The IOUT range is set with bit 7 of the MFR_PWM_MODE_LTC3887 command.
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format.
IOUT_OC_WARN_LIMIT
This command sets the value of the output current that causes an output overcurrent warning in amperes. The
READ_IOUT value will be used to determine if this limit has been exceeded.
In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
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• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 120ms.
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format
TEMPERATURE
External Temperature Calibration
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT
UNITS
NVM
DEFAULT
VALUE
MFR_TEMP_1_GAIN 0xF8 Sets the slope of the external temperature
sensor.
R/W Word Y CF Y 1
0x4000
MFR_TEMP_1_OFFSET 0xF9 Sets the offset of the external temperature
sensor with respect to –273.1°C.
R/W Word Y L11 C Y 0
0x8000
MFR_TEMP_1_GAIN
The MFR_TEMP_1_GAIN command will modify the slope of the external temperature sensor to account for non-idealities
in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in 16-bit 2’s complement integer. N = 8192 to 32767. The effective
adjustment is N • 2–14. The nominal value is 1.
MFR_TEMP_1_OFFSET
The MFR_TEMP_1_OFFSET command will modify the offset of the external temperature sensor to account for non-
idealities in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in Linear_5s_11s format. The part starts the calculation with a
value of –273.15 so the default adjustment value is zero.
External Temperature Limits
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
OT_FAULT_LIMIT 0x4F External overtemperature fault limit. R/W Word Y L11 C Y 100.0
0xEB20
OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word Y L11 C Y 85.0
0xEAA8
UT_FAULT_LIMIT 0x53 External undertemperature fault limit. R/W Word Y L11 C Y –40.0
0xE580
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COMMAND DETAILS
OT_FAULT_LIMIT
The OT_FAULT_LIMIT command sets the value of the external sense temperature, in degrees Celsius, which causes an
overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
This condition is detected by the ADC so the response time may be up to 120ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
OT_WARN_LIMIT
The OT_WARN_LIMIT command sets the value of the external sense temperature, in degrees Celsius, which causes an
overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
In response to the OT_WARN_LIMIT being exceeded, the device:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 120ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
UT_FAULT_LIMIT
The UT_FAULT_LIMIT command sets the value of the external sense temperature, in degrees Celsius, which causes
an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been
exceeded.
Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response
set to ignore to avoid ALERT being asserted.
This condition is detected by the ADC so the response time may be up to 120ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
TIMING
Timing—On Sequence/Ramp
COMMAND NAME CMD CODE DESCRIPTION
TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
TON_DELAY 0x60 Time from RUN and/or Operation on to output
rail turn-on.
R/W Word Y L11 ms Y 0.0
0x8000
TON_RISE 0x61 Time from when the output starts to rise
until the output voltage reaches the VOUT
commanded value.
R/W Word Y L11 ms Y 8.0
0xD200
TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for
VOUT to cross the VOUT_UV_FAULT_LIMIT.
R/W Word Y L11 ms Y 10.0
0xD280
VOUT_TRANSITION_RATE
0x27 Rate the output changes when VOUT
commanded to a new value.
R/W Word Y L11 V/ms Y 0.25
0xAA00
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COMMAND DETAILS
TON_DELAY
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output
voltage starts to rise. Values from 0ms to 83 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
TON_RISE
The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output
enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during
TON_RISE events. If TON_RISE is less than 0.25ms, the LTC3887 digital slope will be bypassed. The output voltage
transition will be controlled by the analog performance of the PWM switcher. The maximum allowed slope is 4V/ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
TON_MAX_FAULT_LIMIT
The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power
up the output without reaching the output undervoltage fault limit.
A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely.
The maximum limit is 83 seconds.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOUT_TRANSITION_RATE
When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the
output voltage to change this command set the rate in V/ms at which the output voltage changes. This commanded
rate of change does not apply when the unit is commanded on or off.
Values of greater than 0.1V/ms are recommended.
This command has two data bytes and is formatted in Linear_5s_11s format.
Timing—Off Sequence/Ramp
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
TOFF_DELAY 0x64 Time from RUN and/or Operation off to the start
of TOFF_FALL ramp.
R/W Word Y L11 ms Y 0.0
0x8000
TOFF_FALL 0x65 Time from when the output starts to fall until the
output reaches zero volts.
R/W Word Y L11 ms Y 8.0
0xD200
TOFF_MAX_WARN_LIMIT 0x66 Maximum allowed time, after TOFF_FALL
completed, for the unit to decay below 12.5%.
R/W Word Y L11 ms Y 150
0xF258
TOFF_DELAY
The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output
voltage starts to fall. Values from 0 to 83 seconds are valid.
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COMMAND DETAILS
This command is excluded from fault events.
This command has two data bytes and is formatted in Linear_5s_11s format.
TOFF_FALL
The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt-
age is commanded to zero. It is the ramp time of the VOUT DAC. When the VOUT DAC is zero, the part will three-state.
The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part
to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate.
The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum fall
time is 1.3 seconds. The maximum allowed slope is 4V/ms.
In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by
the output capacitance and load current.
This command has two data bytes and is formatted in Linear_5s_11s format.
TOFF_MAX_WARN_LIMIT
The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to turn off
the output until a warning is asserted. The output is considered off when the VOUT voltage is less than 12.5% of the
programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete. TOFF_MAX_WARN is not
enabled in VOUT_DECAY is disabled.
A data value of 0ms means that there is no limit and that the unit can attempt to turn off the output voltage indefinitely.
Other than 0, values from 120ms to 524 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
Precondition for Restart
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_RESTART_ DELAY 0xDC Delay from actual RUN active edge to virtual
RUN active edge.
R/W Word Y L11 ms Y 500
0xFBE8
MFR_RESTART_DELAY
This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length
of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms.
Note: The restart delay is different than the retry delay. The restart delay pulls run low for the specified time, after which
a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_FALL
+ 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time, set
the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_
RESTART_DELAY after the RUN pin is pulled high if the output decay bit 1 is enabled in MFR_CHAN_CONFIG_LTC3887
and the output takes a long time to decay below 12.5% of the programmed value.
This command has two data bytes and is formatted in Linear_5s_11s format.
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COMMAND DETAILS
FAULT RESPONSE
Fault Responses All Faults
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_RETRY_ DELAY 0xDB Retry interval during FAULT retry mode. R/W Word Y L11 ms Y 350
0xFABC
MFR_RETRY_DELAY
This command sets the time in milliseconds between restarts if the fault response is to retry the controller at specified
intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has
been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 1ms increments.
Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required
for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is
too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of
MFR_CHAN_CONFIG_LTC3887.
This command has two data bytes and is formatted in Linear_5s_11s format.
Fault Responses Input Voltage
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
VIN_OV_FAULT_RESPONSE 0x56 Action to be taken by the device when an
input supply overvoltage fault is detected.
R/W Byte Y Reg Y 0x80
VIN_OV_FAULT_RESPONSE
The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input over-
voltage fault. The data byte is in the format given in Table14.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Set the INPUT bit in the upper byte of the STATUS_WORD
• Sets the VIN Overvoltage Fault bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin, unless masked.
This command has one data byte.
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COMMAND DETAILS
Fault Responses Output Voltage
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
VOUT_OV_FAULT_RESPONSE 0x41 Action to be taken by the device when an
output overvoltage fault is detected.
R/W Byte Y Reg Y 0xB8
VOUT_UV_FAULT_RESPONSE 0x45 Action to be taken by the device when an
output undervoltage fault is detected.
R/W Byte Y Reg Y 0xB8
TON_MAX_FAULT_
RESPONSE
0x63 Action to be taken by the device when a
TON_MAX_FAULT event is detected.
R/W Byte Y Reg Y 0xB8
VOUT_OV_FAULT_RESPONSE
The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overvoltage fault. The data byte is in the format given in Table10.
The device also:
• Sets the VOUT_OV bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked.
The only value recognized for this command are:
0x80–The device shuts down (disables the output) and the unit does not attempt to retry. The output remains disabled
until the fault is cleared (PMBus, Part II, Section 10.7).
0xB8–The device shuts down (disables the output) and device attempts retry continuously, without limitation, until
it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault
condition causes the unit to shut down.
0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is com-
manded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN.
The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared
or the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or
removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
Any other value will result in a CML fault and the write will be ignored.
This command has one data byte.
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COMMAND DETAILS
Table10. VOUT_OV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION VALUE MEANING
7:6 Response
For all values of bits [7:6], the LTC3887:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUNn pin, the
OPERATION command, or the combined action of the RUNn pin
and OPERATION command, to turn off and then to turn back on,
or
• Bias power is removed and reapplied to the LTC3887.
00 Part performs OV pull down only (i.e., turns off the top
MOSFET and turns on lower MOSFET while VOUT is >
VOUT_OV_FAULT)
01 The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for that
particular fault. If the fault condition is still present at the end of
the delay time, the unit responds as programmed in the Retry
Setting (bits [5:3]).
10 The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11 Not supported. Writing this value will generate a CML fault.
5:3 Retry Setting 000-110 The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
111 The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUNn pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
2:0 Delay Time XXX The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state
VOUT_UV_FAULT_RESPONSE
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
undervoltage fault. The data byte is in the format given in Table11.
The device also:
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked.
The UV fault and warn are masked until the following criteria are achieved:
1) The TON_MAX_FAULT_LIMIT has been reached
2) The TON_DELAY sequence has completed
3) The TON_RISE sequence has completed
4) The VOUT_UV_FAULT_LIMIT threshold has been reached
5) The IOUT_OC_FAULT_LIMIT is not present
The UV fault and warn are masked whenever the channel is not active.
The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing.
This command has one data byte.
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COMMAND DETAILS
Table11. VOUT_UV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION VALUE MEANING
7:6 Response
For all values of bits [7:6], the LTC3887:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the
OPERATION command, or the combined action of the RUNn pin
and OPERATION command, to turn off and then to turn back on,
or
• Bias power is removed and reapplied to the LTC3887
00 The PMBus device continues operation without interruption.
(Ignores the fault functionally)
01 The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for
that particular fault. If the fault condition is still present at the
end of the delay time, the unit responds as programmed in the
Retry Setting (bits [5:3]).
10 The device shuts down (disables the output) and responds
according to the retry setting in bits [5:3].
11 Not supported. Writing this value will generate a CML fault.
5:3 Retry Setting 000-110 The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
111 The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUNn pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
2:0 Delay Time XXX The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state.
TON_MAX_FAULT_RESPONSE
The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX
fault. The data byte is in the format given in Table4.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and
• Notifies the host by asserting ALERT pin, unless masked.
• A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0.
This command has one data byte.
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Fault Responses Output Current
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
IOUT_OC_FAULT_RESPONSE 0x47 Action to be taken by the device when an
output overcurrent fault is detected.
R/W Byte Y Reg Y 0x00
IOUT_OC_FAULT_RESPONSE
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overcurrent fault. The data byte is in the format given in Table12.
The device also:
• Sets the IOUT_OC bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked.
This command has one data byte.
Table12. IOUT_OC_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION VALUE MEANING
7:6 Response
For all values of bits [7:6], the LTC3887:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the
OPERATION command, or the combined action of the RUNn pin
and OPERATION command, to turn off and then to turn back on,
or
• Bias power is removed and reapplied to the LTC3887.
00 The LTC3887 continues to operate indefinitely while maintaining
the output current at the value set by IOUT_OC_FAULT_LIMIT
without regard to the output voltage (known as constant-
current or brick-wall limiting).
01 Not supported.
10 The LTC3887 continues to operate, maintaining the output
current at the value set by IOUT_OC_FAULT_LIMIT without
regard to the output voltage, for the delay time set by bits [2:0].
If the device is still operating in current limit at the end of the
delay time, the device responds as programmed by the Retry
Setting in bits [5:3].
11 The LTC3887 shuts down immediately and responds as
programmed by the Retry Setting in bits [5:3].
5:3 Retry Setting 000-110 The unit does not attempt to restart. The output remains
disabled until the fault is cleared by cycling the RUNn pin or
removing bias power.
111 The device attempts to restart continuously, without limitation,
until it is commanded OFF (by the RUNn pin or OPERATION
command or both), bias power is removed, or another fault
condition causes the unit to shut down. Note: The retry interval
is set by the MFR_RETRY_DELAY command.
2:0 Delay Time XXX The number of delay time units in 16ms increments. This
delay time is used to determine the amount of time a unit is
to continue operating after a fault is detected before shutting
down. Only valid for deglitched off state.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
86
Rev.F
For more information www.analog.com
Fault Responses IC Temperature
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_OT_FAULT_RESPONSE
0xD6 Action to be taken by the device when an
internal overtemperature fault is detected.
R Byte N Reg 0xC0
MFR_OT_FAULT_RESPONSE
The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal
overtemperature fault. The data byte is in the format given in Table13.
The LTC3887 also:
• Sets the MFR bit in the STATUS_WORD, and
• Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command
• Notifies the host by asserting ALERT pin, unless masked.
This command has one data byte.
Table13. Data Byte Contents MFR_OT_FAULT_RESPONSE
BITS DESCRIPTION VALUE MEANING
7:6 Response
For all values of bits [7:6], the LTC3887:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the
OPERATION command, or the combined action of the RUNn pin
and OPERATION command, to turn off and then to turn back on,
or
• Bias power is removed and reapplied to the LTC3887
00 Not supported. Writing this value will generate a CML fault.
01 Not supported. Writing this value will generate a CML fault
10 The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11 The device’s output is disabled while the fault is present.
Operation resumes and the output is enabled when the fault
condition no longer exists.
5:3 Retry Setting 000 The unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001-111 Not supported. Writing this value will generate CML fault.
2:0 Delay Time XXX Not supported. Value ignored
Fault Responses External Temperature
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
OT_FAULT_ RESPONSE 0x50 Action to be taken by the device when an external
overtemperature fault is detected,
R/W Byte Y Reg Y 0xB8
UT_FAULT_ RESPONSE 0x54 Action to be taken by the device when an external
undertemperature fault is detected.
R/W Byte Y Reg Y 0xB8
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
87
Rev. F
For more information www.analog.com
OT_FAULT_RESPONSE
The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an external overtem-
perature fault on the external temp sensors. The data byte is in the format given in Table14.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 120ms.
This command has one data byte.
UT_FAULT_RESPONSE
The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external under-
temperature fault on the external temp sensors. The data byte is in the format given in Table14.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 120ms.
This command has one data byte.
Table14. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE,
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE
BITS DESCRIPTION VALUE MEANING
7:6 Response
For all values of bits [7:6], the LTC3887:
• Sets the corresponding fault bit in the status commands, and
• Notifies the host by asserting ALERT pin, unless masked.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the
OPERATION command, or the combined action of the RUNn pin
and OPERATION command, to turn off and then to turn back on,
or
• Bias power is removed and reapplied to the LTC3887
00 The PMBus device continues operation without interruption.
01 Not supported. Writing this value will generate a CML fault.
10 The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11 Not supported. Writing this value will generate a CML fault.
5:3 Retry Setting 000-110 The unit does not attempt to restart. The output remains disabled
until the fault is cleared until the device is commanded OFF bias
power is removed.
111 The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUNn pin or
OPERATION command or both), bias power is removed, or another
fault condition causes the unit to shut down without retry. Note:
The retry interval is set by the MFR_RETRY_DELAY command.
2:0 Delay Time XXX Not supported. Values ignored
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
88
Rev.F
For more information www.analog.com
FAULT SHARING
Fault Sharing Propagation
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_GPIO_
PROPAGATE_LTC3887
0xD2 Configuration that determines which faults are
propagated to the GPIO pins.
R/W Word Y Reg Y 0x6993
MFR_GPIO_PROPAGATE_LTC3887
The MFR_GPIO_PROPAGATE_LTC3887 command enables the faults that can cause the GPIOn pin to assert low. The
command is formatted as shown in Table15. Faults can only be propagated to the GPIO if they are programmed to
respond to faults.
This command has two data bytes.
Table15. GPIOn Propagate Fault Configuration
The GPIO0 and GPIO1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output
channels. Others are specific to an output channel. They can also be used to share faults between channels.
BIT(S) SYMBOL OPERATION
B[15] VOUT disabled while not decayed. This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_LTC3887 is a
zero. If the channel is turned off, by toggling the RUN pin or commanding the part OFF, and then
the RUN is reasserted or the part is commanded back on before the output has decayed, VOUT
will not restart until the 12.5% decay is honored. The GPIO pin is asserted during this condition if
bit 15 is asserted.
B[14] Mfr_gpio_propagate_short_CMD_cycle 0: No action
1: Asserts low when the channel is off due to a Short Cycle event.
b[13] Mfr_gpio_propagate_ton_max_fault 0: No action if a TON_MAX_FAULT fault is asserted
1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted
GPIO0 is associated with page 0 TON_MAX_FAULT faults
GPIO1 is associated with page 1 TON_MAX_FAULT faults
b[12] Mfr_gpio0_propagate_vout_uvuf,
Mfr_gpio1_propagate_vout_uvuf
Unfiltered VOUT_UV_FAULT_LIMIT comparator output
GPIO0 is associated with channel 0
GPIO1 is associated with channel 1
b[11] Mfr_gpio0_propagate_int_ot,
Mfr_gpio1_propagate_int_ot
0: No action if the MFR_OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted
b[10] Mfr_pwrgd1_en 0: No action if channel 1 POWER_GOOD is not true
1: Associated output will be asserted low if channel 1 POWER_GOOD is not true
If this bit is asserted, the GPIO_FAULT_RESPONSE must be ignore. If the GPIO_FAULT_
RESPONSE is not set to ignore, the part will latch off and never be able to start.
b[9] Mfr_pwrgd0_en 0: No action if channel 0 POWER_GOOD is not true
1: Associated output will be asserted low if channel 0 POWER_GOOD is not true
If this bit is asserted, the GPIO_FAULT_RESPONSE must be ignore. If the GPIO_FAULT_
RESPONSE is not set to ignore, the part will latch off and never be able to start.
b[8] Mfr_gpio0_propagate_ut,
Mfr_gpio1_propagate_ut
0: No action if the UT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 UT faults
GPIO1 is associated with page 1 UT faults
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
89
Rev. F
For more information www.analog.com
BIT(S) SYMBOL OPERATION
b[7] Mfr_gpio0_propagate_ot,
Mfr_gpio1_propagate_ot
0: No action if the OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 OT faults
GPIO1 is associated with page 1 OT faults
b[6] Reserved
b[5] Reserved
b[4] Mfr_gpio0_propagate_input_ov,
Mfr_gpio1_propagate_input_ov
0: No action if the VIN_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted
b[3] Reserved
b[2] Mfr_gpio0_propagate_iout_oc,
Mfr_gpio1_propagate_iout_oc
0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 OC faults
GPIO1 is associated with page 1 OC faults
b[1] Mfr_gpio0_propagate_vout_uv,
Mfr_gpio1_propagate_vout_uv
0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 UV faults
GPIO1 is associated with page 1 UV faults
b[0] Mfr_gpio0_propagate_vout_ov,
Mfr_gpio1_propagate_vout_ov
0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 OV faults
GPIO1 is associated with page 1 OV faults
Fault Sharing Response
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_GPIO_RESPONSE 0xD5 Action to be taken by the device when the GPIO pin
is asserted low.
R/W Byte Y Reg Y 0xC0
MFR_GPIO_RESPONSE
This command determines the controller’s response to the GPIOn pin being pulled low by an external source.
VALUE MEANING
0xC0 GPIO_INHIBIT The LTC3887 will three-state the output in response to the GPIO pin pulled low.
0x00 GPIO_IGNORE The LTC3887 continues operation without interruption.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the MFR bit in the STATUS_WORD
• Sets the GPIOB bit in the STATUS_MFR_SPECIFIC command, and
• Notifies the host by asserting ALERT pin, unless masked. The ALERT pin pulled low can be disabled by setting bit[1]
of MFR_CHAN_CFG_LTC3887.
This command has one data byte.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
90
Rev.F
For more information www.analog.com
SCRATCHPAD
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT
UNITS
NVM
DEFAULT
VALUE
USER_DATA_00 0xB0 OEM reserved. Typically used for part serialization. R/W Word N Reg Y NA
USER_DATA_01 0xB1 Manufacturer reserved for LTpowerPlay. R/W Word Y Reg Y NA
USER_DATA_02 0xB2 OEM reserved. Typically used for part serialization. R/W Word N Reg Y NA
USER_DATA_03 0xB3 A NVM word available for the user. R/W Word Y Reg Y 0x0000
USER_DATA_04 0xB4 A NVM word available for the user. R/W Word N Reg Y 0x0000
USER_DATA_00 through USER_DATA_04
These commands are non-volatile memory locations for customer storage. The customer has the option to write any
value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of
these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable
inventory control and incompatibility with these products.
These commands have 2 data bytes and are in register format.
IDENTIFICATION
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
PMBUS_REVISION 0x98 PMBus revision supported by this device. Current revision
is 1.2.
R Byte N Reg 0x22
CAPABILITY 0x19 Summary of PMBus optional communication protocols
supported by this device.
R Byte N Reg 0xB0
MFR_ID 0x99 The manufacturer ID of the LTC3887 in ASCII. R String N ASC LT C
MFR_MODEL 0x9A Manufacturer part number in ASCII. R String N ASC LTC3887
MFR_SERIAL 0x9E Serial number of this specific unit in ASCII. R Block N CF NA
MFR_SPECIAL_ID 0xE7 Manufacturer code representing the LTC3887. R Word N Reg 0x470X
PMBus_REVISION
The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTC3887
is PMBus Version 1.2 compliant in both Part I and Part II.
This read-only command has one data byte.
CAPABILITY
This command provides a way for a host system to determine some key capabilities of a PMBus device.
The LTC3887 supports packet error checking, 400kHz bus speeds, and ALERT pin.
This read-only command has one data byte.
MFR_ID
The MFR_ID command indicates the manufacturer ID of the LTC3887 using ASCII characters.
This read-only command is in block format.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
91
Rev. F
For more information www.analog.com
MFR_MODEL
The MFR_MODEL command indicates the manufacturer’s part number of the LTC3887 using ASCII characters.
This read-only command is in block format.
MFR_SERIAL
The MFR_SERIAL command contains up to 9 bytes of custom formatted data used to uniquely identify the LTC3887
configuration.
This read-only command is in block format.
MFR_SPECIAL_ID
The 16-bit word representing the part name. 0x470 denotes the part is an LTC3887, X is adjustable by the manufacturer.
This read-only command has 2 data bytes.
FAULT WARNING AND STATUS
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM
DEFAULT
VALUE
CLEAR_FAULTS 0x03 Clear any fault bits that have been set. Send Byte N NA
SMBALERT_MASK 0x1B Mask ALERT Activity. Block R/W Y Reg Y See CMD
Details
MFR_CLEAR_PEAKS 0xE3 Clears all peaks values. Send Byte N NA
STATUS_BYTE 0x78 One byte summary of the unit’s fault
condition.
R/W Byte Y Reg NA
STATUS_WORD 0x79 Two byte summary of the unit’s fault condition. R/W Word Y Reg NA
STATUS_VOUT 0x7A Output voltage fault and warning status. R/W Byte Y Reg NA
STATUS_IOUT 0x7B Output current fault and warning status. R/W Byte Y Reg NA
STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg NA
STATUS_ TEMPERATURE 0x7D External temperature fault and warning status
for READ_TEMERATURE_1.
R/W Byte Y Reg NA
STATUS_CML 0x7E Communication and memory fault and
warning status.
R/W Byte N Reg NA
STATUS_MFR_ SPECIFIC 0x80 Manufacturer specific fault and state
information.
R/W Byte Y Reg NA
MFR_PADS 0xE5 Digital status of the I/O pads. R Word N Reg NA
MFR_COMMON 0xEF Manufacturer status bits that are common
across multiple ADI chips.
R Byte N Reg NA
MFR_INFO 0xB6 Manufacturing Specific information R Word N Reg NA
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all
status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output
if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain
set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault
occurs within that time frame it may be cleared before the status register is set.
This write-only command has no data bytes.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
92
Rev.F
For more information www.analog.com
The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut
down for a fault condition are restarted when:
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin
and OPERATION command, to turn off and then to turn back on, or
• MFR_RESET or RESTORE_USER_ALL command is issued.
• Bias power is removed and reapplied to the integrated circuit
MFR_CLEAR_PEAKS
The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A reset will initiate this command.
This write-only command has no data bytes.
SMBALERT_MASK
The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they
are asserted. Only supported bits can be masked.
Figure41 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in
the mask byte align with bits in the specified status register. For example, if the STATUS_TEMPERATURE command code
is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning
would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE
bits would continue to assert ALERT if set.
Figure42 shows an example of the Block Write – Block Read Process Call protocol used to read back the present state
of any supported status register, again without PEC.
SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_LTC3887.
Factory default masking for applicable status registers is shown below. Providing an unsupported command code to
SMBALERT_MASK will generate a CML for Invalid/Unsupported Data.
PMBus
COMMAND DETAILS
Figure41. Example of Reading SMBALERT_MASK
Figure42. Example of Setting SMBALERT_MASK
P
1
SLAVE
ADDRESS
SMBALERT_MASK
COMMAND CODE
STATUS_x
COMMAND CODE
W A AS
7 8 8 1 8 11 1 11
A AMASK BYTE
3887 F41
SLAVE
ADDRESS
SMBALERT_MASK
COMMAND CODE
BLOCK COUNT
(= 1)
W A AS
7 8 8 1
STATUS_x
COMMAND CODE
8 11 1 11
A A …
Sr
1
BLOCK COUNT
(= 1) A NA P
3887 F42
A
8 81 1 11
MASK BYTE
SLAVE
ADDRESS
7
R
1
LTC3887/LTC3887-1/
LTC3887-2
93
Rev. F
For more information www.analog.com
SMBALERT_MASK Default Setting: (Refer Also to Summary of the Status Register Figure43)
STATUS RESISTER ALERT Mask Value MASKED BITS
STATUS_VOUT 0x00 None
STATUS_IOUT 0x00 None
STATUS_TEMPERATURE 0x00 None
STATUS_CML 0x00 None
STATUS_INPUT 0x00 None
STATUS_MFR_SPECIFIC 0x11 Bit 4 (internal PLL unlocked), bit 0 (GPIO pulled low by external device)
STATUS_BYTE
The STATUS_BYTE command returns a one-byte summary of the most critical faults.
STATUS_BYTE Message Contents:
BIT STATUS BIT NAME MEANING
7 BUSY A fault was declared because the LTC3887 was unable to respond.
6 OFF This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not
being enabled.
5 VOUT_OV An output overvoltage fault has occurred.
4 IOUT_OC An output overcurrent fault has occurred.
3 VIN_UV Not supported (LTC3887 returns 0).
2 TEMPERATURE A temperature fault or warning has occurred.
1 CML A communications, memory or logic fault has occurred.
0 NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred.
This command has one data byte
Any supported fault bit in this command will initiate an ALERT event.
STATUS_WORD
The STATUS_WORD command returns a two-byte summary of the channel’s fault condition. The low byte of the
STATUS_WORD is the same as the STATUS_BYTE command.
STATUS_WORD High Byte Message Contents:
BIT STATUS BIT NAME MEANING
15 VOUT An output voltage fault or warning has occurred.
14 IOUT An output current fault or warning has occurred.
13 INPUT An input voltage fault or warning has occurred.
12 MFR_SPECIFIC A fault or warning specific to the LTC3887 has occurred.
11 POWER_GOOD# The POWER_GOOD state is false if this bit is set.
10 FANS Not supported (LTC3887 returns 0).
9 OTHER Not supported (LTC3887 returns 0).
8 UNKNOWN Not supported (LTC3887 returns 0).
Any supported fault bit in this command will initiate an ALERT event.
This command has two data bytes.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
94
Rev.F
For more information www.analog.com
PMBus COMMAND DETAILS
(Fault Response and Communication)
STATUS_VOUT
The STATUS_VOUT command returns one byte of VOUT status information.
STATUS_VOUT Message Contents:
BIT MEANING
7 VOUT overvoltage fault.
6 VOUT overvoltage warning.
5 VOUT undervoltage warning.
4 VOUT undervoltage fault.
3 VOUT_MAX warning.
2 TON_MAX fault.
1 TOFF_MAX warning.
0 Not supported by the LTC3887 (returns 0).
ALERT can be asserted if any of bits[7:1] are set. These may be cleared by writing a 1 to their bit position in STATUS_VOUT, in lieu of a CLEAR_FAULTS
command.
This command has one data byte.
STATUS_IOUT
The STATUS_IOUT command returns one byte of IOUT status information.
STATUS_IOUT Message Contents:
BIT MEANING
7 IOUT overcurrent fault.
6 Not supported (LTC3887 returns 0).
5 IOUT overcurrent warning.
4:0 Not supported (LTC3887 returns 0).
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_IOUT, in lieu of a
CLEAR_FAULTS command.
This command has one data byte.
STATUS_INPUT
The STATUS_INPUT command returns one byte of VIN (VINSNS) status information.
STATUS_INPUT Message Contents:
BIT MEANING
7 VIN overvoltage fault.
6 Not supported (LTC3887 returns 0).
5 VIN undervoltage warning.
4 Not supported (LTC3887 returns 0).
3 Unit off for insufficient VIN.
2 Not supported (LTC3887 returns 0).
1 Input over current warning.
0 Not supported (LTC3887 returns 0)
ALERT can be asserted if bit 7 is set. Bit 7 may be cleared by writing it to a 1, in lieu of a CLEAR_FAULTS command.
This command has one data byte.
LTC3887/LTC3887-1/
LTC3887-2
95
Rev. F
For more information www.analog.com
STATUS_TEMPERATURE
The STATUS_TEMPERATURE command returns one byte of sensed external temperature status information.
STATUS_TEMPERATURE Message Contents:
BIT MEANING
7 External overtemperature fault.
6 External overtemperature warning.
5 Not supported (LTC3887 returns 0).
4 External undertemperature fault.
3:0 Not supported (LTC3887 returns 0).
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_TEMPERATURE, in
lieu of a CLEAR_FAULTS command.
This command has one data byte.
STATUS_CML
The STATUS_CML command returns one byte of status information on received commands, internal memory and logic.
STATUS_CML Message Contents:
BIT MEANING
7 Invalid or unsupported command received.
6 Invalid or unsupported data received.
5 Packet error check failed.
4 Memory fault detected.
3 Processor fault detected.
2 Reserved (LTC3887 returns 0).
1 Other communication fault.
0 Other memory or logic fault.
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_CML, in lieu of a
CLEAR_FAULTS command.
This command has one data byte.
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information.
Each channel has a copy of the same information. Only bit 0 is page specific.
The format for this byte is:
BIT MEANING
7 Internal Temperature Fault Limit Exceeded.
6 Internal Temperature Warn Limit Exceeded.
5 NVM CRC Fault.
4 PLL is Unlocked
3 Fault Log Present
2 VDD33 UV or OV Fault
1 Short Cycle Event Occurred
0GPIO Pin Asserted Low by External Device (paged)
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
96
Rev.F
For more information www.analog.com
PMBus
COMMAND DETAILS
If any of these bits are set, the MFR bit in the STATUS_WORD will be set.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command. Exception: The fault log present bit can only be
cleared by issuing the MFR_FAULT_LOG_CLEAR command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
MFR_PADS
This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit
assignments of this command are as follows:
BIT ASSIGNED DIGITAL PIN
15 VDD33 OV Fault
14 VDD33 UV Fault
13 Reserved
12 Reserved
11 ADC Values Invalid, Occurs During Start-Up
10 SYNC Output Disabled Due to External Clock
9 PowerGood1
8 PowerGood0
7 Device Driving RUN1 Low
6 Device Driving RUN0 Low
5 RUN1
4 RUN0
3 Device Driving GPIO1 Low
2 Device Driving GPIO0 Low
1GPIO1
0GPIO0
A 1 indicates the condition is true.
This read-only command has two data bytes.
MFR_COMMON
The MFR_COMMON command contains bits that are common to all ADI digital power and telemetry products.
BIT MEANING
7 CHIP NOT DRIVING ALERT LOW
6 CHIP NOT BUSY
5 CALCULATIONS NOT PENDING
4 OUTPUT NOT IN TRANSITION
3 NVM Initialized
2 Reserved
1 SHARE_CLK Timeout
0 WP Pin Status
This read-only command has one data byte.
LTC3887/LTC3887-1/
LTC3887-2
97
Rev. F
For more information www.analog.com
PMBus
COMMAND DETAILS
Figure43. Summary of the Status Registers
(PAGED)
MFR_PADS_LTC3887
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VDD33 0V
VDD33 UV
(reads 0)
(reads 0)
Invalid ADC Result(s)
SYNC Output Disabled Externally
Channel 1 is POWER_GOOD
Channel 0 is POWER_GOOD
LTC3887 Forcing RUN1 Low
LTC3887 Forcing RUN0 Low
RUN1 Pin State
RUN0 Pin State
LTC3887 Forcing GPIO1 Low
LTC3887 Forcing GPIO0 Low
GPIO1 Pin State
GPIO0 Pin State
STATUS_MFR_SPECIFIC
7
6
5
4
3
2
1
0
(PAGED)
3887 SR01
STATUS_INPUT
7
6
5
4
3
2
1
0
MFR_INFO
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EEPROM ECC Status
Reserved
Reserved
Reserved
Reserved
STATUS_WORD
STATUS_BYTE
7
6
5
4
3
2
1
0
(PAGED)
MFR_COMMON
7
6
5
4
3
2
1
0
Chip Not Driving ALERT Low
Chip Not Busy
Internal Calculations Not Pending
Output Not In Transition
EEPROM Initialized
(reads 0)
SHARE_CLK_LOW
WP Pin High
STATUS_TEMPERATURE
7
6
5
4
3
2
1
0
STATUS_CML
7
6
5
4
3
2
1
0
STATUS_VOUT*
7
6
5
4
3
2
1
0
(PAGED)
STATUS_IOUT
7
6
5
4
3
2
1
0
(PAGED)
MASKABLEDESCRIPTION
General Fault or Warning Event
Dynamic
Status Derived from Other Bits
Yes
No
No
GENERATES ALERT
Yes
No
Not Directly
BIT CLEARABLE
Yes
No
No
VOUT_OV Fault
VOUT_OV Warning
VOUT_UV Warning
VOUT_UV Fault
VOUT_MAX Warning
TON_MAX Fault
TOFF_MAX Warning
(reads 0)
IOUT_OC Fault
(reads 0)
IOUT_OC Warning
(reads 0)
(reads 0)
(reads 0)
(reads 0)
(reads 0)
OT Fault
OT Warning
(reads 0)
UT Fault
(reads 0)
(reads 0)
(reads 0)
(reads 0)
Invalid/Unsupported Command
Invalid/Unsupported Data
Packet Error Check Failed
Memory Fault Detected
Processor Fault Detected
(reads 0)
Other Communication Fault
Other Memory or Logic Fault
Internal Temperature Fault
Internal Temperature Warning
EEPROM CRC Error
Internal PLL Unlocked
Fault Log Present
(reads 0)
VOUT Short Cycled
GPIO Pulled Low By External Device
VIN_OV Fault
(reads 0)
VIN_UV Warning
(reads 0)
Unit Off for Insuffcient VIN
(reads 0)
IIN_OC Warning
(reads 0)
15
14
13
12
11
10
9
8
VOUT
IOUT
INPUT
MFR_SPECIFIC
POWER_GOOD#
(reads 0)
(reads 0)
(reads 0)
BUSY
OFF
VOUT_OV
IOUT_OC
(reads 0)
TEMPERATURE
CML
NONE OF THE ABOVE
LTC3887/LTC3887-1/
LTC3887-2
98
Rev.F
For more information www.analog.com
PMBus
COMMAND DETAILS
MFR_INFO
The MFR_INFO command contains additional status bits that are LTC3887-specific and may be common to multiple
ADI PSM products.
MFR_INFO Data Contents:
BIT MEANING
15:6 Reserved.
5 EEPROM ECC status.
0: Corrections made in the EEPROM user space.
1: No corrections made in the EEPROM user space.
4:0 Reserved
EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM
bulk read operation. This read-only command has two data bytes.
TELEMETRY
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED
FORMAT
UNITS NVM
DEFAULT
VALUE
READ_VIN 0x88 Measured input supply voltage. R Word N L11 V NA
READ_VOUT 0x8B Measured output voltage. R Word Y L16 V NA
READ_IIN 0x89 Calculated input supply current. R Word N L11 A NA
MFR_READ_IIN 0xED Calculated input current per channel. R Word Y L11 A NA
READ_IOUT 0x8C Measured output current. R Word Y L11 A NA
READ_TEMPERATURE_1 0x8D External temperature sensor. This is the value used
for all temperature related processing, including
IOUT_CAL_GAIN.
R Word Y L11 C NA
READ_TEMPERATURE_2 0x8E Internal die temperature. Does not affect any other
registers. R Word N L11 C NA
READ_DUTY_CYCLE 0x94 Duty cycle of the top gate control signal. R Word Y L11 % NA
READ_FREQUENCY 0x95 Measured PWM switching frequency R Word N L11 kHz NA
READ_POUT 0x96 Calculated output power. R Word Y L11 W NA
MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT since last
MFR_CLEAR_PEAKS. R Word Y L16 V NA
MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since last
MFR_CLEAR_PEAKS. R Word N L11 V NA
MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of external
Temperature (READ_TEMPERATURE_1) since last
MFR_CLEAR_PEAKS.
R Word Y L11 C NA
MFR_TEMPERATURE_2_PEAK 0xF4 Maximum measured value of external
Temperature (READ_TEMPERATURE_2) since last
MFR_CLEAR_PEAKS.
R Word N L11 C NA
MFR_IOUT_PEAK 0xD7 Report the maximum measured value of READ_IOUT
since last MFR_CLEAR_PEAKS. R Word Y L11 A NA
MFR_ADC_CONTROL 0xD8 ADC telemetry parameter selected for repeated fast
ADC read back. R/W
Byte
N Reg 0x00
MFR_ADC_TELEMETRY_
STATUS
0xDA ADC telemetry status indicating which parameter is
most recently converted when the short round robin
ADC loop is enabled
R/W
Byte
N Reg NA
LTC3887/LTC3887-1/
LTC3887-2
99
Rev. F
For more information www.analog.com
READ_VIN
The READ_VIN command returns the measured input voltage, in volts.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_VOUT
The READ_VOUT command returns the measured output voltage in the same format as set by the VOUT_MODE
command.
This read-only command has two data bytes and is formatted in Linear_16u format.
READ_IIN
The READ_IIN command returns the input current in Amperes. Note: Input current is calculated from READ_IOUT
current and the READ_DUTY_CYCLE value from both outputs plus the MFR_IIN_OFFSET. For accurate values at low
currents the part must be in continuous conduction mode. The greatest source of error if DCR sensing is used, is the
accuracy of the inductor parasitic DC resistance (DCR) at room temperature IOUT_CAL_GAIN.
READ_IIN = MFR_READ_IIN_PAGE0 + MFR_READ_IIN_PAGE1
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_READ_IIN
The MFR_READ_IIN command is a paged reading of the input current that applies the paged MFR_IIN_OFFSET
parameter. This calculation is similar to READ_IIN except the paged values are used.
MFR_READ_IIN = MFR_IIN_OFFSET + (IOUT • DUTYCYCLE)
This command has 2 data bytes and is formatted in Linear_5s_11s format.
READ_IOUT
The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of:
a) the differential voltage measured across the ISENSE pins
b) the IOUT_CAL_GAIN value
c) the MFR_IOUT_CAL_GAIN_TC value, and
d) READ_TEMPERATURE_1 value
e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_TEMPERATURE_1
The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_TEMPERATURE_2
The READ_TEMPERATURE_2 command returns the temperature, in degrees Celsius, of the internal sense element.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
100
Rev.F
For more information www.analog.com
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_DUTY_CYCLE
The READ_DUTY_CYCLE command returns the duty cycle of controller, in percent.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_FREQUENCY
The READ_FREQUENCY command returns the PWM switching frequency in kHz.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_POUT
The READ_POUT command is a paged reading of the DC/DC converter output power in Watts. The POUT is calculated
based on the most recent correlated output voltage and current readings.
This command has 2 data bytes and is formatted in Linear_5s_11s format.
MFR_VOUT_PEAK
The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_16u format.
MFR_VIN_PEAK
The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_1_PEAK
The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_1 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_2_PEAK
The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_2 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_IOUT_PEAK
The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
101
Rev. F
For more information www.analog.com
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_ADC_CONTROL
The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command
runs the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of 90ms.
The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms.
This command has a latency of up to two ADC conversions or approximately 16ms (external temperature conversions
may have a latency of up to three ADC conversion or approximately 24ms). Selecting a value of 0x0D will enable a
short round robin loop. This commanded value runs a short telemetry loop only selecting VOUT0, IOUT0, VOUT1 and
IOUT1 in a round robin manner. The round robin typical latency is 27ms. It is recommended the part remain in standard
telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be
commanded to monitor the desired parameter for a limited period of time (less then one second) then set the command
back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all
warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage
servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled.
COMMANDED VALUE TELEMETRY SELECTED
0x0E-0xFF Reserved
0x0D ADC Short Round Robin
0x0C Channel 1 External Temperature
0x0B Reserved
0x0A Channel 1 IOUT
0x09 Channel 1 VOUT
0x08 Channel 0 External Temperature
0x07 Reserved
0x06 Channel 0 IOUT
0x05 Channel 0 VOUT
0x04 Internal IC Temperature
0x03 Reserved
0x02 Reserved
0x01 VIN
0x00 Standard ADC Round Robin Telemetry
If a reserved command value is entered, the part will default to Internal IC Temperature and issue a CML[6] fault.
CML[6] faults will continue to be issued by the LTC3887 until a valid command value is entered.
This read/write command has 1 data byte and is formatted in register format.
MFR_ADC_TELEMETRY_STATUS
The MFR_ADC_TELEMETRY_STATUS command provides the user the means to determine the most recent ADC
conversion when the MFR_ADC_CONTROL short round robin loop is enabled using command 0xD8 value 0x0D. The
bit assignments of this command are as follows:
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
102
Rev.F
For more information www.analog.com
BIT TELEMETRY DATA AVAILABLE
7 Reserved returns 0
6 Reserved returns 0
5 Reserved returns 0
4 Reserved returns 0
3 Channel 1 IOUT readback (IOUT1)
2 Channel 1 VOUT readback (VOUT1)
1 Channel 0 IOUT readback (IOUT0)
0 Channel 0 VOUT readback (VOUT0)
Write to MFR_ADC_TELEMETRY_STATUS with data bits set to 1 clear the respective bits.
This read/write command has 1 data byte and is formatted in register format.
NVM (EEPROM) MEMORY COMMANDS
Store/Restore
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED FORMAT
UNITS
NVM
DEFAULT
VALUE
STORE_USER_ALL 0x15 Store user operating memory to EEPROM. Send Byte N NA
RESTORE_USER_ALL 0x16 Restore user operating memory from EEPROM. Send Byte N NA
MFR_COMPARE_USER_ALL 0xF0 Compares current command contents with NVM. Send Byte N NA
STORE_USER_ALL
The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating
Memory to the matching locations in the non-volatile User NVM memory (EEPROM).
Executing this command if the die temperature exceeds 85°C is not recommended and the data retention of 10 years
cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is disabled. The com-
mand is re-enabled when the IC temperature drops below 125°C.
Communication with the LTC3887 and programming of the EEPROM can be initiated when VDD33 is available and
VIN is not applied. To enable the part in this state, using global address 0x5B write 0x2B followed by 0xC4. The part
can now be communicated with, and the project file updated. To write the updated project file to the EEPROM issue a
STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be issued to allow the PWM to be enabled
and valid ADCs to be read.
This write-only command has no data bytes.
RESTORE_USER_ALL
The RESTORE_USER_ALL command provides a means by which the user can perform a reset of the LTC3887.
This write-only command has no data bytes.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
103
Rev. F
For more information www.analog.com
MFR_COMPARE_USER_ALL
The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with
what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated.
MFR_COMPARE_USER_ALL commands are disabled if the die exceeds 130°C and are not re-enabled until the die
temperature drops below 125°C.
This write-only command has no data bytes.
Fault Log Operation
A conceptual diagram of the fault log is shown in Figure44. The fault log provides telemetry recording capability to
the LTC3887. During normal operation the contents of the status registers, the output voltage readings, temperature
readings as well as peak values of these quantities are stored in a continuously updated buffer in RAM. You can think
of the operation as being similar to a strip chart recorder. When a fault occurs, the contents are written into EEPROM
for nonvolatile storage. The EEPROM fault log is then locked. The part can be powered down with the fault log available
for reading at a later time. As a consequence of adding ECC, the area in the EEPROM available for fault log is reduced.
When reading the fault log from RAM all 6 events of cyclical data remain. However, when the fault log is read from
EEPROM (after a reset), the last 2 events are lost. The read length of 147 bytes remains the same, but the fifth and
sixth events are a repeat of the fourth event.
PMBus
COMMAND DETAILS
Figure44. Fault Log Conceptual Diagram
3887 F44
TIME OF FAULT
TRANSFER TO
EEPROM AND
LOCK
AFTER FAULT
READ FROM
EEPROM AND
LOCK BUFFER
ADC READINGS
CONTINUOUSLY
FILL BUFFER
RAM 255 BYTES EEPROM 255 BYTES
8
•
•
•
•
•
•
Fault Logging
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_FAULT_LOG 0xEE Fault log data bytes. This sequentially retrieved
data is used to assemble a complete fault log.
R Block N CF Y NA
MFR_FAULT_LOG_ STORE 0xEA Command a transfer of the fault log from RAM
to EEPROM.
Send Byte N NA
MFR_FAULT_LOG_CLEAR 0xEC Initialize the EEPROM block reserved for fault
logging.
Send Byte N NA
LTC3887/LTC3887-1/
LTC3887-2
104
Rev.F
For more information www.analog.com
MFR_FAULT_LOG
The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occur-
rence since the last MFR_FAULT_LOG_CLEAR command was last written. The contents of this command are stored
in non-volatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this
command are listed in Table16. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the
command will return a data length of 0. If a fault log is present, the MFR_FAUTL_LOG will always return a block of
data 147 bytes long. If a fault occurs within the first second of applying power, some of the earlier pages in the fault
log may not contain valid data.
NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock.
This read-only command is in block format.
MFR_FAULT_LOG_STORE
The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to EEPROM just as if a fault
event occurred. This command will generate a MFR_SPECIFIC fault if the “Enable Fault Logging” bit is set in the MFR_
CONFIG_ALL_LTC3887 command.
If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature
drops below 125°C.
Up-Time Counter is in the Fault Log header. The counter is the time since the last reset in 200µs increments. This is
a 48-bit binary counter.
This write-only command has no data bytes.
PMBus
COMMAND DETAILS
Table16. Fault Logging
This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.
Data Format Definitions LIN 11 = PMBus = Rev 1.2, Part 2, section 7.1
LIN 16 = PMBus Rev 1.2, Part 2, section 8. Mantissa portion only
BYTE = 8 bits interpreted per definition of this command
DATA BITS
DATA
FORMAT BYTE NUM BLOCK READ COMMAND
Block Length BYTE 147 The MFR_FAULT_LOG command is a fixed length of 147 bytes
The block length will be zero if a data log event has not been captured
HEADER INFORMATION
Fault Log Preface [7:0] ASC 0 Returns LTxx beginning at byte 0 if a partial or complete fault log exists.
Word xx is a factory identifier that may vary part to part.
[7:0] 1
[15:8] Reg 2
[7:0] 3
Fault Source [7:0] Reg 4 Refer to Table8.
MFR_REAL_TIME [7:0] Reg 5 48 bit share-clock counter value when fault occurred (200µs resolution).
[15:8] 6
[23:16] 7
[31:24] 8
[39:32] 9
[47:40] 10
MFR_VOUT_PEAK (PAGE 0) [15:8] L16 11 Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS
command.
[7:0] 12
MFR_VOUT_PEAK (PAGE 1) [15:8] L16 13 Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS
command.
[7:0] 14
MFR_IOUT_PEAK (PAGE 0) [15:8] L11 15 Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS
command.
[7:0] 16
MFR_IOUT_PEAK (PAGE 1) [15:8] L11 17 Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS
command.
[7:0] 18
MFR_VIN_PEAK [15:8] L11 19 Peak READ_VIN since last power-on or CLEAR_PEAKS command.
[7:0] 20
READ_TEMPERATURE1 (PAGE 0) [15:8] L11 21 External temperature sensor 0 during last event.
[7:0] 22
READ_TEMPERATURE1 (PAGE 1) [15:8] L11 23 External temperature sensor 1 during last event.
[7:0] 24
READ_TEMPERATURE2 [15:8] L11 25 Internal temperature sensor during last event.
[7:0] 26
LTC3887/LTC3887-1/
LTC3887-2
105
Rev. F
For more information www.analog.com
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
106
Rev.F
For more information www.analog.com
CYCLICAL DATA
EVENT n
(Data at Which Fault Occurred; Most Recent Data)
Event “n” represents one complete cycle of ADC reads through the MUX
at time of fault. Example: If the fault occurs when the ADC is processing
step 15, it will continue to take readings through step 25 and then store
the header and all 6 event pages to EEPROM
READ_VOUT (PAGE 0) [15:8] LIN 16 27
[7:0] LIN 16 28
READ_VOUT (PAGE 1) [15:8] LIN 16 29
[7:0] LIN 16 30
READ_IOUT (PAGE 0) [15:8] LIN 11 31
[7:0] LIN 11 32
READ_IOUT (PAGE 1) [15:8] LIN 11 33
[7:0] LIN 11 34
READ_VIN [15:8] LIN 11 35
[7:0] LIN 11 36
READ_IIN [15:8] LIN 11 37
[7:0] LIN 11 38
STATUS_VOUT (PAGE 0) BYTE 39
STATUS_VOUT (PAGE 1) BYTE 40
STATUS_WORD (PAGE 0) [15:8] WORD 41
[7:0] WORD 42
STATUS_WORD (PAGE 1) [15:8] WORD 43
[7:0] WORD 44
STATUS_MFR_SPECIFIC (PAGE 0) BYTE 45
STATUS_MFR_SPECIFIC (PAGE 1) BYTE 46
EVENT n-1
(data measured before fault was detected)
READ_VOUT (PAGE 0) [15:8] LIN 16 47
[7:0] LIN 16 48
READ_VOUT (PAGE 1) [15:8] LIN 16 49
[7:0] LIN 16 50
READ_IOUT (PAGE 0) [15:8] LIN 11 51
[7:0] LIN 11 52
READ_IOUT (PAGE 1) [15:8] LIN 11 53
[7:0] LIN 11 54
READ_VIN [15:8] LIN 11 55
[7:0] LIN 11 56
READ_IIN [15:8] LIN 11 57
[7:0] LIN 11 58
STATUS_VOUT (PAGE 0) BYTE 59
STATUS_VOUT (PAGE 1) BYTE 60
STATUS_WORD (PAGE 0) [15:8] WORD 61
[7:0] WORD 62
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
107
Rev. F
For more information www.analog.com
STATUS_WORD (PAGE 1) [15:8] WORD 63
[7:0] WORD 64
STATUS_MFR_SPECIFIC (PAGE 0) BYTE 65
STATUS_MFR_SPECIFIC (PAGE 1) BYTE 66
*
*
*
EVENT n-5
(Oldest Recorded Data)
READ_VOUT (PAGE 0) [15:8] LIN 16 127
[7:0] LIN 16 128
READ_VOUT (PAGE 1) [15:8] LIN 16 129
[7:0] LIN 16 130
READ_IOUT (PAGE 0) [15:8] LIN 11 131
[7:0] LIN 11 132
READ_IOUT (PAGE 1) [15:8] LIN 11 133
[7:0] LIN 11 134
READ_VIN [15:8] LIN 11 135
[7:0] LIN 11 136
READ_IIN [15:8] LIN 11 137
[7:0] LIN 11 138
STATUS_VOUT (PAGE 0) BYTE 139
STATUS_VOUT (PAGE 1) BYTE 140
STATUS_WORD (PAGE 0) [15:8] WORD 141
[7:0] WORD 142
STATUS_WORD (PAGE 1) [15:8] WORD 143
[7:0] WORD 144
STATUS_MFR_SPECIFIC (PAGE 0) BYTE 145
STATUS_MFR_SPECIFIC (PAGE 1) BYTE 146
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
108
Rev.F
For more information www.analog.com
Table17. Explanation of Position_Fault Values
POSITION_FAULT VALUE SOURCE OF FAULT LOG
0xFF MFR_FAULT_LOG_STORE
0x00 TON_MAX_FAULT Channel 0
0x01 VOUT_OV_FAULT Channel 0
0x02 VOUT_UV_FAULT Channel 0
0x03 IOUT_OC_FAULT Channel 0
0x05 OT_FAULT Channel 0
0x06 UT_FAULT Channel 0
0x07 VIN_OV_FAULT Channel 0
0x0A MFR_OT_FAULT Channel 0
0x10 TON_MAX_FAULT Channel 1
0x11 VOUT_OV_FAULT Channel 1
0x12 VOUT_UV_FAULT Channel 1
0x13 IOUT_OC_FAULT Channel 1
0x15 OT_FAULT Channel 1
0x16 UT_FAULT Channel 1
0x17 VIN_OV_FAULT Channel 1
0x1A MFR_OT_FAULT Channel 1
MFR_FAULT_LOG_CLEAR
The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the
STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear.
This write-only command is send bytes.
Block Memory Write/Read
COMMAND NAME CMD CODE DESCRIPTION TYPE
PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_EE_UNLOCK 0xBD Unlock user EEPROM for access by MFR_EE_ERASE and
MFR_EE_DATA commands.
R/W Byte N Reg NA
MFR_EE_ERASE 0xBE Initialize user EEPROM for bulk programming by
MFR_EE_DATA.
R/W Byte N Reg NA
MFR_EE_DATA 0xBF Data transferred to and from EEPROM using sequential
PMBus word reads or writes. Supports bulk programming.
R/W
Word
N Reg NA
All the (EEPROM) commands are disabled if the die temperature exceeds 130°C. (EEPROM) commands are re-enabled
when the die temperature drops below 125°C.
MFR_EE_xxxx
MFR_EE_XXXX commands are used to facilitate bulk programming of the internal EEPROM. Contact the factory for
more details.
PMBus
COMMAND DETAILS
LTC3887/LTC3887-1/
LTC3887-2
109
Rev. F
For more information www.analog.com
TYPICAL APPLICATIONS
High Efficiency Quad 500kHz 1.2 Volt Step-Down Converter with a LTC3887 and LTC3870
L0 TO L3: VISHAY IHLP-4040DZ-11 0.36µH
M1, M2, M5, M6: INFINEON BSC050NE2LS
M3, M4, M7, M8: INFINEON BSC010NE2LSI
530µF Capacitors: 330µF SANYO 4TPF330ML
AND 2 x 100µF AVX 12106D107KAT2A
VIN
GND
TG0
0.1µF 0.1µF
1µF
4700pF
220pF
0.22µF 0.22µF
22µF
10µF
+
530µF
D2
M2
M4
M1
M3
2.55k
1.58k
1µF
L1
0.36µH
L2
0.36µH
L3
0.36µH
L0
0.36µH
D1
TG1
BG0
SYNC 1µF
1µF
1.58k 1.58k
GPIO0
GPIO1
SDA
SCL
ALERT
RUN0
ASEL1
VOUT0_CFG
VOUT1_CFG
FREQ
ASEL0
PHASE
RUN1
WP
1.58k 1.58k
SHARE_CLK
VDD33
BG1
BOOST0 BOOST1
SW0 SW1
INTVCC
LTC3887
TSNS0 TSNS1
ITHO ITH1
ISENSEO+ISENSE1+
VSENSEO+VSENSE1
VSENSEO–
ISENSEO–ISENSE1–
+
530µF
10nF 10nF
VIN
SGND
TG0
0.1µF 0.1µF
1µF
0.22µF 0.22µF
22µF
VIN
6V TO 24V
10µF
+530µF
D4
M6
M8
EXTVCC
M5
M7
VOUT
1.2V
100A
1µF
D3
TG1
BG0
1µF
1.58k
FAULT0
FAULT1
RUN0
RUN1
MODE0
1.58k 1.58k
BG1
PGND
BOOST0 BOOST1
SW0 SW1
INTVCC
LTC3870
ITHO ITH1
ISENSEO+ISENSE1+
ISENSEO–ISENSE1–
+
530µF
3887 TA02
20k
11k
VDD25
30.1k
1.96k
220pF
MODE1
SYNC
FREQ
ILIM
24.9k
5.76k
100k
PHASMD
1µF
10k
5k
5k
4.99k
10k
10k
10k
LTC3887/LTC3887-1/
LTC3887-2
110
Rev.F
For more information www.analog.com
TYPICAL APPLICATIONS
High Efficiency 350kHz 2-Phase 1.5V Dual Step-Down Converter with Sense Resistors
VIN
VDD33 VDD25
GND
TG0
0.1µF
4.99k
0.1µF
1µF
1µF1µF
4700pF
1000pF 1000pF
22µF
V
IN
6V TO 34V
5V
EXTERNAL
SUPPLY 10µF
+
530µF
D2
M2
M4
VDD25
M1
M3
V
OUT1
1.5V
40A
2.55k
L1
0.42µH 0.0015Ω
L0
0.42µH
0.0015Ω
D1
TG1
BG0
SYNC
10k
20k
17.8k
20k
17.8k
GPIO0
10k
GPIO1
10k
SDA
SCL
10k
ALERT
10k
RUN0
PHAS_CFG
VOUT0_CFG
VOUT1_CFG
FREQ_CFG
ASEL1
ASEL0
RUN1
WP
10k
100Ω
100Ω 100Ω
100Ω
SHARE_CLK
VDD33
BG1
BOOST0 BOOST1
SW0 SW1
EXTVCC
LTC3887-2
TSNS0 TSNS1
ITHO ITH1
ISENSEO+ISENSE1+
VSENSEO+VSENSE1
VSENSEO–
ISENSEO–ISENSE1–
+
530µF
3887 TA03
220pF10nF 10nF
L0, L1: VITEC 59PR9875 0.42µH
M1, M2: INFINEON BSC050NE2LS
M3, M4: INFINEON BSC010NE2LSI
530µF: 330µF SANYO 4TPF330ML, 2x 100µF 12106D107KAT2A
LTC3887/LTC3887-1/
LTC3887-2
111
Rev. F
For more information www.analog.com
TYPICAL APPLICATIONS
High Efficiency 425kHz 1.05V Step-Down Dual Phase Converter with Power Blocks Using the LTC3887
VIN
GND
VIN
P1
PWMH
PWML
VGATE
VDD33 VDD25
GND
TG0
4.99k
1µF10µF
1µF 1µF
1µF1µF
4700pF
0.22µF 0.22µF
1µF
22µF
VIN
7V TO 13.2V
7V
GATE DRIVE
+
530µF
VDD25
VOUT1
1.05V
60A
2.55k
TG1
BG0
SYNC
10k
24.9k
7.32k
20k
17.8k
24.9k
4.32k
GPIO0
10k
GPIO1
10k
SDA
SCL
10k
ALERT
10k
RUN0
FREQ_CFG
VOUT0_CFG
VOUT1_CFG
ASEL1
PHAS_CFG
ASEL0
RUN1
WP
10k
1.2k
SHARE_CLK
VDD33
BG1
SW0
SW1
BOOST0
VOUT
CS–
CS+
TEMP+
TEMP–
GND
VIN
P2
PWMH
PWML
VGATE
VOUT
CS–
CS+
TEMP+
TEMP–
BOOST1
INTVCC
LTC3887
TSNS0 TSNS1
ITHO ITH1
ISENSEO+ISENSE1+
VSENSEO+VSENSE1
VSENSEO–
ISENSEO–ISENSE1–
+
530µF
3887 TA04
220pF
P1, P2: VRA001-4C3G ACBEL POWER BLOCK
530µF: 330µF SANYO 4TPF330ML, 2x 100µF 12106D107KAT2A
1µF
1.2k
LTC3887/LTC3887-1/
LTC3887-2
112
Rev.F
For more information www.analog.com
TYPICAL APPLICATIONS
High Efficiency 425kHz 3-Phase 1.8V and 1-Phase 2.5V Step-Down Converter
L0 TO L3: VISHAY IHLP-4040DZ-11 0.56µH, 1µH
M1, M2, M5, M6: INFINEON BSC050NE2LS
M3, M4, M7, M8: INFINEON BSC010NE2LSI
VIN
GND
TG0
0.1µF 0.1µF
1µF
0.22µF 0.22µF
4700pF
22µF
10µF
+
530µF
D4
M2
M4
16.2k
17.4k
VDD25
M1
M3
2.55k
1.58k
1µF 1µF
L1
0.56µH
L2
0.56µH
L3
1µH
L0
0.56µH
D3
TG1
BG0
SYNC
10k
1µF
1µF
1.58k 1.58k
15.8k
24.9k
4.32k
GPIO0
GPIO1
SDA
SCL
ALERT
RUN0
FREQ_CFG
VOUT0_CFG
VOUT1_CFG
ASLE1
PHAS_CFG
ASEL0
RUN1
WP
1.58k 1.58k
SHARE_CLK
VDD33
BG1
BOOST0 BOOST1
SW0 SW1
INTVCC
LTC3887
TSNS0 TSNS1
ITHO ITH1
ISENSEO+ISENSE1+
VSENSEO+VSENSE1
VSENSEO–
ISENSEO–ISENSE1–
VOUT0
1.8V
75A
+
530µF
220pF
10nF
10nF
VIN
GND
TG0
0.1µF 0.1µF
1µF
2200pF 2200pF
220pF
0.22µF
1µF
0.22µF
22µF
VIN
6V TO 24V
10µF
+
530µF
D4
M6
M8
16.2k
17.4k
VDD25
M5
M7
VOUT1
2.5V
25A
4.99k 6.04k
1µF
D3
TG1
BG0
SYNC
16.2k
1µF
1µF
2k
20.5k
20k
15k
GPIO0
GPIO1
SDA
SCL
ALERT
RUN0
10k
FREQ_CFG
VOUT0_CFG
VOUT1_CFG
ASEL1
PHAS_CFG
ASEL0
RUN1
WP
1.58k
10k
10k
10k
10k
10k
5k
5k
4.99k
2k
SHARE_CLK
VDD33
BG1
BOOST0 BOOST1
SW0 SW1
INTVCC
LTC3887
TSNS0 TSNS1
ITHO ITH1
ISENSEO+ISENSE1+
VSENSEO+VSENSE1
VSENSEO–
ISENSEO–ISENSE1–
+
530µF
3880 TA05
220pF
10nF 10nF
30.1k
1.96k
24.9k
4.32k
LTC3887/LTC3887-1/
LTC3887-2
113
Rev. F
For more information www.analog.com
TYPICAL APPLICATIONS
High Efficiency 1.2V/25A and 1.8V/25A 500kHz Converter with DrMOS Power Stage Using the LTC3887-1
LTC3887-1
SCL
RUN1
RUN0
ISENSE0+
ISENSE0–
VSENSE0+
VSENSE0–
R20
4.99k
GPIO0
GPIO1
SHARE_CLK
SYNC
TNS0
TNS1
3887 TA06
PWM0
VSENSE1+
ISENSE1–
ISENSE1+
PWM1
GND
R19
4.99k
R18
10k
R17
10k
R15
10k
SCL
SDA
RUN
ALERT
SDA
ALERT
WP
C18
4.7µF
INTVCC
C17
1µF
VDD25
C16
2.2µF
VDD33
5V
VDD25
VDD33
C8
100nF
C4
22µF
VIN
VOUT0_CFG
ASEL1
ASEL0
VOUT1_CFG
FREQ_CFG
PHAS_CFG
R14
4.99k
17.4k16.2k
VIN
7V TO 14V
+
C28
10nF
PLACE Q1,Q2
NEAR L1, L2
RESPECTIVELY
Q1
C29
10nF Q2
R8
1k
C24
0.22µF
L1
0.16µH
R55
1k
C66
0.22µF
L2
0.16µH C48
100µF
×4
C49
470µF
×4
V
OUT1
1.8V
GNDSW1
SW0
+
C12
100µF
×4
C14
470µF
×4
VOUT0
1.2V
GND
+
FDMF6820A
PGND
18
PGND
17
PGND
20
PGND
19
VSWH 34
VSWH 33
VSWH 32
VSWH 31
PGND
21
PGND
22
PGND
23
PGND
24
PGND
25
PGND
26
PGND
27
PGND
28
VSWH
43
VSWH
29
VSWH
30
VIN
10
VIN
9
VIN
42
NC
8
PHASE
7
GH
6
CGND
5
GND
41
BOOT
4
VDRV
3
VCIN
2
SMOD
1
VSWH
15
VIN
14
PGND
16
CGND 37
GL 36
VSWH 35
VIN
12
VIN
VIN
11
VIN
13
PWM 40
DISB 39
NC 38
PWM0
PWM1
L1: WURTH ELEKTRONIK 744325016
L2: WURTH ELEKTRONIK 744325016
C33
1µF
PWM1
C34
1µF R52
2k
R51
10Ω
C40
22µF
×2
C37
1µF
FDMF6820A
PGND
18
PGND
17
PGND
20
PGND
19
VSWH 34
VSWH 33
VSWH 32
VSWH 31
PGND
21
PGND
22
PGND
23
PGND
24
PGND
25
PGND
26
PGND
27
PGND
28
VSWH
43
VSWH
29
VSWH
30
VIN
10
VIN
9
VIN
42
NC
8
PHASE
7
GH
6
CGND
5
GND
41
BOOT
4
VDRV
3
VCIN
5V
BIAS
2
SMOD
1
VSWH
SW0 15
VIN
14
PGND
16
CGND 37
GL 36
VSWH 35
VIN
12
VIN
VIN
11
VIN
13
PWM 40
DISB 39
NC 38
C1
1µF
PWM0
C2
2.2µF R4
2k
R3
10Ω
C7
22µF
×2
C3
1µF
SW1
R10
10k
ITH0
ITH1
R33
5k
C31
2200pF C30
220pF
R30
5k
C26
2200pF C27
220pF
VCC1
VCC0
VDD25
24.9k
5.76k
20k
11k
16.2k
17.4k
5VBIAS
RUN
RUN
LTC3887/LTC3887-1/
LTC3887-2
114
Rev.F
For more information www.analog.com
PACKAGE DESCRIPTION
6.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
0.40 ±0.10
4039
1
2
BOTTOM VIEW—EXPOSED PAD
4.50 REF
(4-SIDES)
4.42 ±0.10
4.42 ±0.10
4.42 ±0.05
4.42 ±0.05
0.75 ±0.05 R = 0.115
TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UJ40) QFN REV Ø 0406
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
4.50 ±0.05
(4 SIDES)
5.10 ±0.05
6.50 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
R = 0.10
TYP
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
LTC3887/LTC3887-1/
LTC3887-2
115
Rev. F
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/15 Added LTC3887-1 part number All
B 01/16 Clarified PolyPhase
®
Load Sharing section 21
C 04/16 Minor text edits 6, 8, 40, 42,
47, 56, 68, 80
and 102
D 05/17 Reduced start-up/initialization time
Added error correction coding
All
E 07/18 Increased VIN ABS max rating
Reduced minimum on-time
Added LTC3887-2 part number
4
15
All
F 08/19 Added AEC-Q100 Qualified for Automotive Applications and orderable part numbers 1, 5
LTC3887/LTC3887-1/
LTC3887-2
116
Rev.F
For more information www.analog.com
D17091-0-8/19
www.analog.com
© ANALOG DEVICES, INC. 2015 -2019
RELATED PARTS
TYPICAL APPLICATION
High Efficiency Dual 500kHz 3.3V/1.8V Step-Down Converter
PART NUMBER DESCRIPTION COMMENTS
LTM4676A Dual 13A or Single 26A Step-Down DC/DC µModule Regulator
with Digital Power System Management
4.5V ≤ VIN ≤26.5V; 0.5V ≤ VOUT ≤ 5.5V, ±0.5% VOUT Accuracy I2C/
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LTM4675 Dual 9A or Single 18A Step-Down DC/DC μModule Regulator
with Digital Power System Management
4.5V ≤ VIN ≤17V; 0.5V ≤ VOUT ≤ 5.5V, ±0.5% VOUT Accuracy I2C/PMBus
Interface, 11.9mm × 16mm × 3.51mm, BGA Package
LTM4677 Dual 18A or Single 36A μModule Regulator with Digital Power
System Management
4.5V ≤ VIN ≤16V; 0.5V ≤ VOUT (±0.5%) ≤ 1.8V, I2C/PMBus Interface,
16mm × 16mm × 5.01mm, BGA Package
LTC3870/
LTC3870-1
60V Dual Output Multiphase Step-Down Slave Controller for
Current Mode Control Applications with Digital Power System
Management
VIN Up to 60V, 0.5V ≤ VOUT ≤ 14V, Very High Output Current Applications
with Accurate Current Share Between Phases Supporting LTC3887/
LTC3887-1, LTC3883/LTC3883-1, LTC3886, LTC3880/LTC3880-1
LTC3884 Dual Output MultiPhase Step-Down Controller with Sub
MilliOhm DCR Sensing Current Mode Control and Digital
Power System Management
4.5V ≤ VIN ≤ 38V, 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface,
Programmable Analog Loop Compensation, Input Current Sense
LTC3882/
LTC3882-1
Dual Output Multiphase Step-Down DC/DC Voltage Mode
Controller with Digital Power System Management
3V ≤ VIN ≤ 38V, 0.5V ≤ VOUT1,2 ≤ 5.25V, ±0.5% VOUT Accuracy I2C/
PMBus Interface, uses DrMOS or Power Blocks
LTC3886 60V Dual Output Step-Down DC/DC Controller with Digital
Power System Management
4.5V ≤ VIN ≤ 60V, 0.5V ≤ VOUT0,1 (±0.5%) ≤ 13.8V, ±0.5% VOUT
Accuracy I2C/PMBus Interface, Input Current Sense
LTC3883/
LTC3883-1
Single Phase Step-Down DC/DC Controller with Digital Power
System Management
VIN Up to 24V, 0.5V ≤ VOUT ≤ 5.5V, Input Current Sense Amplifier, I2C/
PMBus Interface with EEPROM and 16-Bit ADC, ±0.5% VOUT Accuracy
LTC3880/
LTC3880-1
Dual Output Multiphase Step-Down DC/DC Controller with
Digital Power System Management
4.5V ≤ VIN ≤ 24V, 0.5V ≤ VOUT ≤ 5.4V, ±0.5% VOUT Accuracy I2C/PMBus
Interface with EEPROM and 16-Bit ADC. 145ms Start-Up
LTC3815 6A Monolithic Synchronous DC/DC Step-Down Converter with
Digital Power System Management
2.25V ≤ VIN ≤ 5.5V, 0.4V ≤ VOUT ≤ 0.72 VIN, Programmable VOUT Range
±25% with 0.1% Resolution, Up to 3MHz Operation with 13-Bit ADC
VIN
VDD33 VDD25
GND
TG0
0.1µF
4.99k
0.1µF
1µF
1µF
L0, L1: VISHAY IHLP-4040DZ-11 1µH, 0.56µH
M1, M2: INFINEON BSC050NE2LS
M3, M4: INFINEON BSC010NE2LSI
530µF: 330µF SANYO 4TPF330ML, 2x 100µF 12106D107KAT2A
1µF
4700pF
0.22µF 0.22µF
2200pF
22µF
VIN
6V TO 24V
10µF
+
530µF
D2
M2
M4
10k
15.8k
VDD25
M1
M3
VOUT1
1.8V
15A
4.99k 4.99k
2.0k
1µF
L1
0.56µH
L0
1.0µH
D1
TG1
BG0
SYNC
10k
16.2k
17.4k
10k
1µF
1.58k
23.2k
GPIO0
10k
GPIO1
10k
SDA
10k
SCL
ALERT
10k
RUN0
FREQ_CFG
VOUT0_CFG
VOUT1_CFG
ASEL1
PHAS_CFG
ASEL0
RUN1
WP
10k
2.0k 1.58k
SHARE_CLK
VDD33
BG1
BOOST0 BOOST1
SW0 SW1
INTVCC
LTC3887
TSNS0 TSNS1
ITHO ITH1
ISENSEO+ISENSE1+
VSENSEO+VSENSE1
VSENSEO–
ISENSEO–ISENSE1–
VOUT0
3.3V
15A
VOUT1
1.8V
15A
VOUT1
1.8V
15A
+
530µF
3887 TA07
220pF 220pF10nF 10nF
24.9k
5.76k