REV. A
AD9854
–34–
3. External Single-Ended Clock Input, J7.
This mode bypasses the MC100LVEL16 and directly drives
the AD9854 with a user-supplied reference clock. Attach a
50 Ω, 2 V p-p sine source that is dc offset to 1.65 V, or a 50 Ω
CMOS-level clock source to J7. Remove the shorting jumper
from W5 altogether to make certain that the device (U3) is not
Toggling or Self-Oscillating. Set the shorting jumper at W9
to Pins 1 and 2 (the left two pins) to route the REFCLK signal
from J7 to Pin 69 of the AD9854. Finally, set the shorting
jumper at W3 to Pins 1 and 2 (the left two pins) to place the
AD9854 in the single-ended clock mode.
Regardless of the origination, the signals arriving at the AD9854
are called the Reference Clock. If the on-chip REFCLK Multiplier
is engaged, this signal is the reference clock for the REFCLK
Multiplier and the REFCLK Multiplier output becomes the
SYSTEM CLOCK. If the REFCLK Multiplier is bypassed, the
reference clock supplied is directly operating the AD9854 and
is, therefore, the system clock.
Three-state control or switch headers W11, W12, W14, and
W15 must be shorted to allow the provided software to control
the AD9854 evaluation board via the printer port connector J11.
If programming of the AD9854 is not to be provided by the host
PC via the ADI software, then headers W11, W12, W14, and W15
should be opened (shorting jumpers removed). This effectively
detaches the PC interface and allows the 40-pin header, J10, to
assume control without bus contention. Input signals on J10 going
to the AD9854 should be 3.3 V CMOS logic levels.
Low-Pass Filter Testing
The purpose of 2-pin headers W7 and W10 (associated with J1
and J2) are to allow the two 50 Ω, 120 MHz filters to be tested
during PCB assembly without interference from other circuitry
attached to the filter inputs. Normally, a shorting jumper will be
attached to each header to allow the DAC signals to be routed to the
filters. If the user wishes to test the filters, the shorting jumpers
at W7 and W10 should be removed and 50 Ω test signals applied
at J1 and J2 inputs to the 50 Ω elliptic filters. User should refer
to Figure 63 and the following sections to properly position the
remaining shorting jumpers.
Observing the Unfiltered I
OUT1
and the Unfiltered I
OUT2
DAC
Signals
This allows the user to observe the unfiltered DAC outputs at J2
(the “I” signal) and J1 (the “Q” signal). The procedure below sim-
ply routes the two 50 Ω terminated analog DAC outputs to the
BNC connectors and disconnects any other circuitry. The “raw”
DAC outputs will be a series of quantized (stepped) output levels.
The default 10 mA output current will develop a 0.5 V p-p signal
across the on-board 50 Ω termination. When connected to an
external 50 Ω input, the DAC will therefore develop 0.25 V p-p due to
the double termination.
1. Install shorting jumpers at W7 and W10.
2. Remove shorting jumper at W16.
3. Remove shorting jumper from 3-pin header W1.
4. Install shorting jumper on Pins 1 and 2 (bottom two pins) of
3-pin header W4.
Observing the Filtered I
OUT1
and the Filtered I
OUT2
This allows viewer to observe the filtered I and Q DAC outputs
at J4 (the “I” signal) and J3 (the “Q” signal). This places the
50 Ω (input and output Z) low-pass filters in the I and Q DAC
pathways to remove images and aliased harmonics and other
spurious signals above the dc to approximately 120 MHz band-
pass. These signals will appear as nearly pure sine waves and
exactly 90 degrees out-of-phase with each other. These filters
are designed with the assumption that the system clock speed is
at or near maximum (300 MHz). If the system clock utilized is
much less than 300 MHz, for example 200 MHz, unwanted DAC
products other than the fundamental signal will be passed by the
low-pass filters.
1. Install shorting jumpers at W7 and W10.
2. Install shorting jumper at W16.
3. Install shorting jumper on Pins 1 and 2 (bottom two pins) of
3-pin header W1.
4. Install shorting jumper on Pins 1 and 2 (bottom two pins) of
3-pin header W4.
5. Install shorting jumper on Pins 1 and 2 (top two pins) of 3-
pin header W2 and W8.
Observing the Filtered I
OUT
and the Filtered I
OUTB
This allows the user to observe only the filtered “I” DAC out-
puts at J4 (the “true” signal) and J3 (the “complementary” signal).
This places the 120 MHz low pass filters in the true and comple-
mentary output paths of the I DAC to remove images and aliased
harmonics and other spurious signals above approximately
120 MHz. These signals will appear as nearly pure sine waves
and exactly 180 degrees out-of-phase with each other. Again, if
the system clock used is much less than 300 MHz, for example
200 MHz, then unwanted DAC products other than the funda-
mental signal will be passed by the low-pass filters.
1. Install shorting jumpers at W7 and W10.
2. Install shorting jumper at W16.
3. Install shorting jumper on Pins 2 and 3 (top two pins) of 3-
pin header W1.
4. Install shorting jumper on Pins 2 and 3 (top two pins) of 3-
pin header W4.
5. Install shorting jumper on Pins 1 and 2 (top two pins) of 3-
pin header W2 and W8.
To connect the high-speed comparator to the DAC output signals
choose either the quadrature (90⬚) filtered output configuration
or the complementary (180⬚) filtered output configuration as
outlined above. Follow Steps 1 through 4 above, for the desired
filtered configuration. Step 5 below will reroute the filtered sig-
nals away from their connectors (J3 and J4) and connect them to
the 100 Ω configured comparator inputs. This configures the
comparator for differential input without control of the comparator
output duty cycle. The comparator output duty cycle should
be approximately 50% in this configuration.
5. Install shorting jumper on Pins 2 and 3 (bottom two pins) of
3-pin header W2 and W8.
User may elect to change the R
SET
resistor, R2 from 3.9 kΩ to
2 kΩ to get a more robust signal at the comparator inputs. This
will decrease jitter and extend comparator operating range. This
can be accomplished by soldering a second 3.9 kΩ chip resistor
in parallel with the 3.9 kΩ resistor already on board.