DS2401P+T&R - Hytronics

AVAILABLE

Functional Diagrams

Pin Configurations appear at end of data sheet.

Functional Diagrams continued at end of data sheet.

UCSP is a trademark of Maxim Integrated Products, Inc.

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

FEATURES

 Upgrade and Drop-In Replacement for

DS2400

Extended 2.8V to 6.0V Range

Multiple DS2401 Devices Can Reside on a

Common 1-Wire Net

 Unique, Factory-Lasered and Tested 64-Bit

Registration Number (8-Bit Family Code +

48-Bit Serial Number + 8-Bit CRC Tester);

Guaranteed No Two Parts Alike

 Built-In Multidrop Controller Ensures

Compatibility with Other 1-Wire Net

Products

 8-Bit Family Code Specifies DS2401

Communications Requirements to Reader

 Presence Pulse Acknowledges When the

Reader First Applies Voltage

 Low-Cost TO-92, SOT-223, and TSOC

Surface-Mount Packages

 Reduces Control, Address, Data, and Power

to a Single Pin

 Zero Standby Power Required

 Directly Connects to a Single Port Pin of a

Microprocessor and Communicates at Up to

16.3kbps

 TO-92 Tape-and-Reel Version with Leads

Bent to 100-mil Spacing (Default) or with

Straight Leads (DS2401-SL)

 -40°C to +85°C Industrial Temperature

Range

APPLICATIONS

PCB Identification

Network Node ID

Equipment Registration

PIN CONFIGURATIONS

1 2

01rrd

Flip Chip, Top View

with Laser Mark,

Contacts Not Visible.

“rrd” = Revision/Date

PIN DESCRIPTIONS

TO-92,

SOT-223

TSOC

FLIP

CHIP

Ground

Data (DQ)

Ground

No Connect

—

Ground*

No Connect

—

5, 6

—

No Connect

—

*SOT-223 only.

DS2401

Silicon Serial Number

TOP VIEW

BOTTOM VIEW

TO-92

DS2401

1 2 3

Wire is a registered trademark of Maxim I ntegrated Products, Inc.

TSOC

19-5860; Rev 5/11

DS2401

ORDERING INFORMATION

PART

TEMP RANGE

PIN-PACKAGE

DS2401+

-40°C to +85°C

3 TO-92

DS2401+T&R

-40°C to +85°C

3 TO-92 (formed leads)

DS2401-SL+T&R

-40

C to +85

3 TO-92 (straight leads)

DS2401P+

-40

C to +85

6 TSOC

DS2401P+T&R

-40°C to +85°C

6 TSOC

DS2401Z+

-40°C to +85°C

4 SOT-223

DS2401Z+T&R

-40

C to +85

4 SOT-223

DS2401X1-S#T

-40

C to +85

2 Flip Chip (2.5k pieces)

+Denot es a lead(Pb)-free/RoHS-compliant package.

T&R/T = Tape and ree l.

SL = Straight leads .

#Denot es a RoHS-c ompliant device t hat may include lead that is exempt under t he RoHS requirem e nts.

DESCRIPTION

The DS2401 enhanced silicon serial number is a low-cost, electronic registration number that provides an

absolutely unique identity which can be determined with a minimal electronic interface (typically, a

single port pin of a microcontroller). The DS2401 consists of a factory-lasered, 64-bit ROM that includes

a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (01h). Data is transferred serially

via the 1-Wire protocol that requires only a single data lead and a ground return. Power for reading and

writing the device is derived from the data line itself with no need for an external power source. The

DS2401 is an upgrade to the DS2400. The DS2401 is fully reverse-compatible with the DS2400 but

provides the additional multi-drop capability that enables many devices to reside on a single data line.

The familiar TO-92, SOT-223 or TSOC package provides a co mpact enclosure that allows standard

assembly equipment to handle the device easily.

OPERATION

The DS2401’s internal ROM is accessed via a single data line. The 48-bit serial number, 8-bit family

code and 8-bit CRC are retrieved using the Maxim 1-Wire protocol. This protocol defines bus

transactions in terms of the bus state during specified time slots that are initiated on the falling edge of

sync pulses from the bus master. All data is read and written least significant bit first.

1-Wire BUS SYST EM

The 1-Wire bus is a system which has a single bus master system and one or more slaves. In all instances,

the DS2401 is a slave device. The bus master is typically a microcontroller. The discussion of this bus

system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire

signaling (signal type and timing).

Hardware Configuration

The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to

drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an

open-drain connection or 3-state outputs. The DS2401 is an open-drain part with an internal circuit

equivalent to that shown in Figure 2. The bus master can be the same equivalent circuit. If a bidirectional

pin is not available, separate output and input pins can be tied together. The bus master requires a pullup

resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in Figure 3.

The value of the pullup resistor should be approximately 5kΩ for short line lengths. A multidrop bus

consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of

16.3kbits per second.

DS2401

The idle state for the 1-Wire bus is high. If, for any reason, a transaction needs to be suspended, the bus

MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low

for more than 120µs, one or more of the devices on the bus may be reset.

DS2401 MEMORY MAP Fi gu re 1

8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code (01h)

MSB LSB MSB LSB MSB LSB

DS2401 EQUIVALENT CIRCUIT Figure 2

BUS MASTER CIRCUIT Figure 3 A) Open Dra in

Note:

Depending on the 1-Wire communication speed and the bus load characteristics, the optimal pullup

resistor (RPU) value will be in the 1.5kΩ to 5kΩ range.

To data connection

of DS2401

B) Stan da r d TTL

To data connection

of DS2401

See note

VPUP

PUP

DS2401

TRANSACTION SEQUENCE

The sequence for accessing the DS2401 via the 1-Wire port is as follows:

 Initialization

 ROM Function Command

 Read Data

INITIALIZATION

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence

consists of a reset pulse transmitted by the bus master followed by a Presence Pulse(s) transmitted by the

slave(s).

The Presence Pulse lets the bus master know that the DS2401 is on the bus and is ready to operate. For

more details, see the 1-Wire Signaling section.

ROM FUNCTION COMMANDS

Once the bus master has detected a presence, it can issue one of the four ROM function commands. All

ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure

4).

Read ROM [33h] or [0 Fh ]

This command allows the bus master to read the DS2401’s 8-bit family code, unique 48-bit serial

number, and 8-bit CRC. This command can only be used if there is a single DS2401 on the bus. If more

than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same

time (open drain will produce a wired-AND result). The DS2401 Read ROM function will occur with a

command byte of either 33h or 0Fh in order to ensure compatibility with the DS2400, which will only

respond to a 0Fh command word with its 64-bit ROM data.

Match R OM [55h] / Skip ROM [CCh]

The complete 1-Wire protocol for all Maxim iButtons® contains a Match ROM and a Skip ROM

command. Since the DS2401 contains only the 64-bit ROM with no additional data fields, the Match

ROM and Skip ROM are not applicable and will cause no further activity on the 1-Wire bus if executed.

The DS2401 does not interfere with other 1-Wire parts on a multidrop bus that do respond to a Match

ROM or Skip ROM (for example, a DS2401 and DS1994 on the same bus).

Search ROM [F0h]

When a system is initially brought up, the bus master might not know the number of devices on the 1-

Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process

of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search process

is the repetition of a simple 3-step routine: read a b it, read the complement of the bit, then write the

desired value of that bit. The bus master performs this simple 3-step routine on each bit of the ROM.

After one complete pass, the bus master knows the contents of the ROM in one device. The remaining

number of devices and their ROM codes may be identified by additional passes. Refer to Application

Note 187: 1-Wire Search Algorithm for a comprehensive discussion of a ROM search, including an actual

example.

iButton is a regist e red trademark of Maxim Int egrated Products, Inc.

DS2401

1-Wire SIGNALING

The DS2401 requires a strict protocol to ensure data integrity. The protocol consists of four types of

signaling on one line: reset sequence with Reset Pulse and Presence Pulse, write 0, write 1, and read data.

All these signals except Presence Pulse are initiated by the bus master.

The initialization sequence required to begin any communication with the DS2401 is shown in Figure 5.

A reset pulse followed by a Presence Pulse indicates the DS2401 is ready to send or receive data given

the correct ROM command.

The bus master transmits (TX ) a reset pulse (tRSTL , minimum 480µs). The bus master then releases the

line and goes into receive mode (RX ). The 1-Wire bus is pulled to a high state via the 5kΩ pullup resistor.

After detecting the rising edge on the data pin, the DS2401 waits (tPDH, 15-60µs) and then transmits the

Presence Pulse (tPDL, 60-240µs). The 1-Wire bus requires a pullup resistor range of 1.5kΩ to 5kΩ,

depending on bus load characteristics.

READ/WRITE TIME SLOTS

The definitions of write and read time slots are illustrated in Figure 6. All time slots are initiated by the

master driving the data line low. The falling edge of the data line synchronizes the DS2401 to the master

by triggering a delay circuit in the DS2401. During write time slots, the delay circuit determines when the

DS2401 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit

determines how long the DS2401 will hold the data line low overriding the “1” generated by the master.

If the data bit is a 1, the DS2401 will leave the read data time slot unchanged.

DS2401

ROM FUNCTIONS FLOW CHART Figure 4

DS2401

INIT IALIZATION PROCEDURE “RESET AND PRESENCE PUL SES” Figure 5

480µs ≤ tRSTL < ∞ *

480µs ≤ tRSTH < ∞ (includes recovery time)

15µs ≤ tPDH < 60µs

60µs ≤ tPDL < 240µs

∗ In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always

be less than 960µs.

READ/WRITE TIMING DIAGRAM Figure 6

Write-One Time Slot

60µs ≤ tSLOT < 120µs

1µs ≤ tLOW1 < 15µs

1µs ≤ tREC < ∞

RESISTOR

MASTER

RESISTOR

MASTER

DS2401

READ/WRITE TIMING DIAGRAM (cont’d) Figure 6

Write-zero Time Slot

60µs ≤ tLOW0 < tSLOT < 120µs

1µs ≤ tREC < ∞

Read-data Time Slot

60µs ≤ tSLOT < 120µs

1µs ≤ tLOWR < 15µs

0 ≤ tRELEASE < 45µs

1µs ≤ tREC < ∞

tRDV = 15µs

tSU < 1µs

CRC GENERATION

To validate the data transmitted from the DS2401, the bus master may generate a C RC value from the

data as it is received. This generated value is compared to the value stored in the last 8 bi ts of the

DS2401. If the two CRC values match, the transmission is error-free.

The equivalent polynomial function of this CRC is: CRC = x8 + x5 + x4 + 1. Additional information about

the Maxim 1-Wire CRC is available in Application Note 27.

CUSTOM DS2401

Customization of a portion of the unique 48-bit serial number by the customer is available. Maxim will

significant bits are selectable by the customer as a starting value, and the least significant bits are non-

selectable and will be automatically incremented by one. Certain quantities and conditions apply for these

custom parts. Contact your Maxim sales representative for more information.

RESISTOR

MASTER

DS2401

ABSOLUTE MAXIMUM RA TINGS

Voltage Range on Any Pin Relative to Ground -0.5V to +7.0V

Operating Temperature Range -40°C to +85°C

Storage Temperature Range -55°C to +125°C

Lead Temperature (TO-92, TSOC, SOT-223 only; soldering, 10s) +300°C

Soldering Temperature (reflow)

TO-92 +250°C

TSOC, SOT-223 +260°C

Flip Chip +240°C

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this

speci fication is not implied. Exposure to abs olute maxim um rating conditions for extended periods of time may affect reliability.

DC ELECTRICAL CHARACTERISTICS

(TA = -40°C to +85°C, unless otherwise not ed. )

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Pullup Voltage

VPUP

2.8

6.0

Logic 1

VIH

2.2

1, 6

Logic 0

VIL

-0.3

+0.3

Output Logic-Low at 4mA

VOL

0.4

Input Load Current

5 µ

Operating Charge

QOP

7, 8

CAPACITANCE

(TA = +2 5 °C, unless otherwi se noted. )

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

I/O (1-Wire)

CIN/OUT

800

AC ELECTRICAL CHARACTERISTICS

(TA = -40°C to +85°C, unless otherwis e noted.)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Time Slot

tSLOT

120

µs

Write 1 Low Time

LOW1

µs

Write 0 Low Time

LOW0

120

Read Data Valid

RDV

Release Time

tRELEASE

µs

Read Data Setup

tSU

µs

Recovery Time

REC

µs

Reset Time High

RSTH

480

Reset Time Low

RSTL

480

960

Presence Detect High

PDH

15 60 µ

Presence Detect Low

tPDL

240

µs

DS2401

NOTES:

1) All voltages are referenced to ground.

2) VPUP = external pullup voltage.

3) Input load is to ground.

4) An additional reset or communication sequence cannot begin until the reset high time has expired.

5) Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is

guaranteed to be valid within 1µs of this falling edge and will remain valid for 14µs minimum (15µs

total from falling edge on 1-Wire bus).

6) VIH is a function of the external pullup resistor and VPUP.

7) 30 nanocoulombs per 72 time slots at 5.0V.

8) At VPUP = 5.0V with a 5kΩ pullup to VPUP and a maximum time slot of 120µs.

9) Capacitance on the I/O pin could be 800pF when power is first applied. If a 5 kΩ resistor is used to

pullup the I/O line to VPUP, 5µs after power has been applied the parasite capacitance will not affect

normal communications.

10) The reset low time (tRSTL) should be restricted to a maximum of 960µs, to allow interrupt signaling,

otherwise it could mask or conceal interrupt pulses if this device is used in parallel with a DS2404 or

DS1994.

11) The optimal sampling point for the master is as close as possible to the end time of the tRDV period

without exceeding tRDV. For the case of a Read-One Time slot, this maximizes the amount of time for

the pullup resistor to recover to a high level. For a Read-Zero Time slot, it ensures that a r ead will

occur before the fastest 1-Wire device(s) releases the line.

12) The duration of the low pulse sent by the master should be a minimum of 1μs with a maximum value

as short as possible to allow time for the pullup resistor to recover the line to a high level before the

1-Wire device samples in the case of a Write-One Time or before the master samples in the case of a

Read-One Time.

PACKAGE INFORMATION

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”,

“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the

drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

3 TO-92

(straight leads) Q3+1 21-0248 —

3 TO-92

(formed leads)

Q3+4 21-0250 —

6 TSOC D6+1 21-0382 90-0321

4 SOT-223 K3+1 21-0264 —

2 Flip Chip BF211#1 21-0378 Refer to 21-0378

DS2401

REVISION HISTORY

REVISION

DATE

DESCRIPTION

PAGES

CHANGED

040601

Changed MicroLAN to 1-Wire Net; updated ordering information for

tape and reel

Changed soldering temperature from 260°C for 10 seconds to See J-STD-

020A Specification

022202

Below Figure 3, added a note on the optimal R

PUP

range; added a similar

note before the Read/Write Time Slots section

3, 6

Added notes 11 to 13 to the EC table 9, 10

122106

Added flip chip package; added lead-free ordering information 1, 2

References to the Book of iButton Standards replaced with references to

corresponding application notes Various

VILMAX changed from 0.8V to 0.3V, EC table note 11 deleted 9, 10

5/11

Deleted standard (Pb) parts from ordering information; changed flip chip

part number from DS2401X1 to DS2401X1-S#T 2

Deleted V

from the EC table; moved V

PUP

from the EC table header

into the EC table; changed soldering temperature from J-STD-020A

reference to explicit package specific numbers

Added Package Information and Revision History sections 10, 11

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.

Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical

Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.