Order Now Product Folder Support & Community Tools & Software Technical Documents Reference Design DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 DS90UB926Q-Q1 5- to 85-MHz, 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel 1 Features 2 Applications * * * * * 1 * * * * * * * * * * * * * * * * AEC-Q100 Qualified for Automotive Applications - Device Temperature Grade 2: -40C to +105C Ambient Operating Temperature - Device HBM ESD Classification Level 3B - Device CDM ESD Classification Level C6 - Device MM ESD Classification Level M3 Bidirectional Control Interface Channel Interface With I2C-Compatible Serial Control Bus Supports High-Definition (720p) Digital Video Format RGB888 + VS, HS, DE and Synchronized I2S Audio Supported 5- to 85-MHz PCLK Supported Single 3.3-V Operation With 1.8-V or 3.3-V Compatible LVCMOS I/O Interface AC-Coupled STP Interconnect up to 10 Meters Parallel LVCMOS Video Outputs I2C-Compatible Serial Control Bus for Configuration DC-Balanced and Scrambled Data With Embedded Clock Adaptive Cable Equalization Supports Repeater Application @ SPEED Link BIST Mode and LOCK Status Pin Image Enhancement (White Balance and Dithering) and Internal Pattern Generation EMI Minimization (SSCG and EPTO) Low Power Modes Minimize Power Dissipation Backward-Compatible With FPD-Link II Automotive Display for Navigation Rear Seat Entertainment Systems Automotive Drive Assistance Automotive Megapixel Camera Systems 3 Description The DS90UB926Q-Q1 deserializer, in conjunction with the DS90UB925Q-Q1 serializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image-sensing applications. This chipset translates a parallel RGB video interface into a single-pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed forward data transmission and lowspeed backchannel communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design. The DS90UB926Q-Q1 deserializer recovers the RGB data, three video control signals, and four synchronized I2S audio signals. The device extracts the clock from a high-speed serial stream. An output LOCK pin provides the link status if the incoming data stream is locked, without the use of a training sequence or special SYNC patterns, as well as a reference clock. Device Information(1) PART NUMBER DS90UB926Q-Q1 PACKAGE WQFN (60) BODY SIZE (NOM) 9.00 mm x 9.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Display System Diagram VDDIO VDD33 (3.3V) (1.8V or 3.3V) HOST Graphics Processor RGB Digital Display Interface VDDIO VDD33 (1.8V or 3.3V) (3.3V) R[7:0] G[7:0] B[7:0] HS VS DE PCLK DOUT+ SCL SDA IDx RIN+ DOUT- RIN- 100: STP Cable DS90UB925Q Serializer PDB I2S AUDIO (STEREO) R[7:0] G[7:0] B[7:0] HS VS DE PCLK FPD-Link III 1 Pair / AC Coupled 0.1 PF 0.1 PF 3 MODE_SEL INTB DAP PDB OSS_SEL OEN MODE_SEL DS90UB926Q Deserializer SCL SDA IDx LOCK PASS 3 INTB_IN RGB Display 720p 24-bit color depth I2S AUDIO (STEREO) MCLK DAP 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 8 1 1 1 2 4 5 8 Absolute Maximum Ratings ..................................... 8 ESD Ratings.............................................................. 8 Recommended Operating Conditions....................... 8 Thermal Information .................................................. 9 DC Electrical Characteristics .................................... 9 AC Electrical Characteristics................................... 11 DC and AC Serial Control Bus Characteristics....... 12 Timing Requirements .............................................. 12 Timing Requirements for the Serial Control Bus .... 13 Switching Characteristics ...................................... 13 Timing Diagrams ................................................... 14 Typical Characteristics .......................................... 17 Detailed Description ............................................ 18 8.1 Overview ................................................................. 18 8.2 8.3 8.4 8.5 8.6 9 Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 18 18 31 35 36 Application and Implementation ........................ 48 9.1 Application Information............................................ 48 9.2 Typical Application .................................................. 49 10 Power Supply Recommendations ..................... 51 10.1 Power Up Requirements and PDB Pin ................. 51 11 Layout................................................................... 52 11.1 Layout Guidelines ................................................. 52 11.2 Layout Examples................................................... 54 12 Device and Documentation Support ................. 55 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 55 55 55 55 55 55 13 Mechanical, Packaging, and Orderable Information ........................................................... 55 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (February 2017) to Revision D Page * Reverted all previous MLCK content changes made in Revision C back to Revision B........................................................ 1 * Deleted the disable I2S jitter cleaner note.............................................................................................................................. 6 Changes from Revision B (January 2015) to Revision C Page * Changed pin 60 from MCLK to RES2 ................................................................................................................................... 5 * Changed MCLK to RES2 ....................................................................................................................................................... 6 * Added note to disable I2S jitter cleaner ................................................................................................................................ 6 * Changed MCLK to RES2 ....................................................................................................................................................... 6 * Deleted reference to MCLK in this section ............................................................................................................................ 9 * Deleted reference to MCLK in this section .......................................................................................................................... 13 * Deleted reference to MCLK .................................................................................................................................................. 28 * Changed MCLK section ....................................................................................................................................................... 28 * Changed MCLK columns of Audio Interface Frequencies table ......................................................................................... 28 * Changed the values in columns 2 through 5 in Configuration Select (MODE_SEL) table................................................... 32 * Changed the values in columns 2 to 5 in Serial Control Bus Addresses for IDx table ........................................................ 35 * Changed register reference to MCLK .................................................................................................................................. 45 * Changed Typical Display System Diagram (removed reference to MCLK) ........................................................................ 49 * Changed wording of Power Up Requirements and PDB Pin subsection and added Power-Up Sequence graphic............ 51 2 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Changes from Revision A (April 2013) to Revision B * Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1 Changes from Original (July 2012) to Revision A Page * Corrected typo in table "DC and AC Serial Control Bus Characteristics" from VDDIO to VDD33, added "Note: BIST is not available in backwards compatible mode.", added Recommended FRC settings table, changed entire layout of Data Sheet to TI format, added to Absolute Maximum Rating section, note (3): The maximum limit (VDDIO +0.3V) does not apply to the PDB pin during the transition to the power down state (PDB transitioning from HIGH to LOW), deleted derate from Maximum Power Dissipation Capacity at 25C...................................................................................... 4 * "Note: BIST is not available in backwards compatible mode." ............................................................................................. 26 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 3 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com 5 Description (continued) The DS90UB926Q-Q1 deserializer has a 31-bit parallel LVCMOS output interface to accommodate the RGB, video control, and audio data. An adaptive equalizer optimizes the maximum cable reach. EMI is minimized by output SSC generation (SSCG) and enhanced progressive turnon (EPTO) features. 4 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 6 Pin Configuration and Functions ROUT3 / R3 ROUT4 / R4 ROUT5 / R5 ROUT6 / R6 ROUT7 / R7 LOCK OEN 36 35 34 33 32 31 40 37 ROUT1 / R1 / GPIO1 41 38 ROUT0 / R0 / GPIO0 42 ROUT2 / R2 PASS 43 VDDIO RES1 44 39 I2S_DA / GPO_REG6 BISTEN 45 NKB Package 60-Pin WQFN With Exposed Thermal Pad Top View OSS_SEL 46 30 I2S_WC / GPO_REG7 RES0 47 29 VDD33_B VDD33_A 48 28 ROUT8 / G0 / GPIO2 RIN+ 49 27 ROUT9 / G1 / GPIO3 RIN- 50 26 ROUT10 / G2 CMF 51 25 ROUT11 / G3 CMLOUTP 52 24 VDDIO CMLOUTN 53 TOP VIEW 23 ROUT12 / G4 NC 54 DAP = GND 22 ROUT13 / G5 CAPR12 55 21 ROUT14 / G6 IDx 56 20 ROUT15 / G7 CAPP12 57 19 ROUT16 / B0 / GPO_REG4 CAPI2S 58 18 ROUT17 / B1 / GPO_REG5 / I2S_DB PDB 59 17 ROUT18 / B2 MCLK 60 16 BISTC / INTB_IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GPO_REG8 / I2S_CLK SDA SCL CAPL12 PCLK DE VS HS B7 / ROUT23 B6 / ROUT22 B5 / ROUT21 B4 / ROUT20 VDDIO B3 / ROUT19 MODE_SEL DS90UB926Q-Q1 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 5 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com Pin Functions PIN NAME NO. I/O, TYPE DESCRIPTION LVCMOS PARALLEL INTERFACE ROUT[23:0] / R[7:0], G[7:0], B[7:0] 41, 40, 39, 37, 36, 35, 34, 33, 28, 27, 26, 25, O, LVCMOS 23, 22, 21, 20, with pulldown 19, 18, 17, 14, 12, 11, 10, 9 Parallel Interface Data Output Pins Leave open if unused. ROUT0 / R0 can optionally be used as GPIO0 and ROUT1 / R1 can optionally be used as GPIO1. ROUT8 / G0 can optionally be used as GPIO2 and ROUT9 / G1 can optionally be used as GPIO3. ROUT16 / B0 can optionally be used as GPO_REG4 and ROUT17/ B1 can optionally be used as I2S_DB / GPO_REG5. HS 8 Horizontal Sync Output Pin Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the O, LVCMOS Control Signal Filter is enabled. There is no restriction on the minimum transition pulse with pulldown when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs. See Table 11 VS 7 Vertical Sync Output Pin O, LVCMOS Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width with pulldown is 130 PCLKs. DE 6 Data Enable Output Pin Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the O, LVCMOS Control Signal Filter is enabled. There is no restriction on the minimum transition pulse with pulldown when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs. See Table 11 PCLK 5 O, LVCMOS Pixel Clock Output Pin. Strobe edge set by RFB configuration register. See Table 11 with pulldown 1, 30, 45 Digital Audio Interface Data Output Pins O, LVCMOS Leave open if unused with pulldown I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as GPO_REG7, and I2S_DA can optionally be used as GPO_REG6. I2S_CLK, I2S_WC, I2S_DA MCLK 60 O, LVCMOS I2S Master Clock Output with pulldown x1, x2, or x4 of I2S_CLK Frequency OPTIONAL PARALLEL INTERFACE 18 Second Channel Digital Audio Interface Data Output pin at 18-bit color mode and set by O, LVCMOS MODE_SEL or configuration register with pulldown Leave open if unused I2S_B can optionally be used as BI or GPO_REG5. GPIO[3:0] 27, 28, 40, 41 Standard General Purpose IOs. I/O, Available only in 18-bit color mode, and set by MODE_SEL or configuration register. See LVCMOS Table 11 with pulldown Leave open if unused Shared with G1, G0, R1 and R0. GPO_REG[8: 4] 1, 30, 45, 18, 19 O, LVCMOS General Purpose Outputs and set by configuration register. See Table 11 with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0. I2S_DB INTB_IN 16 Input, Interrupt Input LVCMOS Shared with BISTC with pulldown OPTIONAL PARALLEL INTERFACE PDB 59 Power-down Mode Input Pin PDB = H, device is enabled (normal operation) I, LVCMOS Refer to Power Up Requirements and PDB Pin. with pulldown PDB = L, device is powered down. When the device is in the POWER DOWN state, the LVCMOS Outputs are in TRI-STATE, the PLL is shutdown and IDD is minimized. . OEN 31 Input, Output Enable Pin LVCMOS See Table 8 with pulldown OSS_SEL 46 Input, Output Sleep State Select Pin LVCMOS See Table 8 with pulldown 6 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Pin Functions (continued) PIN NAME NO. I/O, TYPE DESCRIPTION MODE_SEL 15 I, Analog Device Configuration Select. See Table 9 IDx 56 I, Analog I2C Serial Control Bus Device ID Address Select External pullup to VDD33 is required under all conditions, DO NOT FLOAT. Connect to external pullup and pulldown resistor to create a voltage divider. See Figure 23 SCL 3 I/O, LVCMOS Open-Drain I2C Clock Input / Output Interface Must have an external pullup to VDD33, DO NOT FLOAT. Recommended pullup: 4.7 k. SDA 2 I/O, LVCMOS Open-Drain I2C Data Input / Output Interface Must have an external pullup to VDD33, DO NOT FLOAT. Recommended pullup: 4.7 k. BISTEN 44 BIST Enable Pin I, LVCMOS 0: BIST Mode is disabled. with pulldown 1: BIST Mode is enabled. BISTC 16 BIST Clock Select I, LVCMOS Shared with INTB_IN with pulldown 0: PCLK; 1: 33 MHz LOCK 32 LOCK Status Output Pin O, LVCMOS 0: PLL is unlocked, ROUT[23:0]/RGB[7:0], I2S[2:0], HS, VS, DE and PCLK output states with pulldown are controlled by OEN. May be used as Link Status or Display Enable 1: PLL is Locked, outputs are active PASS 42 PASS Output Pin O, LVCMOS 0: One or more errors were detected in the received payload with pulldown 1: ERROR FREE Transmission Leave Open if unused. Route to test point (pad) recommended STATUS FPD-LINK III SERIAL INTERFACE RIN+ 49 I, LVDS True Input. The interconnection should be AC-coupled to this pin with a 0.1-F capacitor. RIN- 50 I, LVDS Inverting Input. The interconnection should be AC-coupled to this pin with a 0.1-F capacitor. CMLOUTP 52 O, LVDS True CML Output Monitor point for equalized differential signal CMLOUTN 53 O, LVDS Inverting CML Output Monitor point for equalized differential signal CMF 51 POWER AND GROUND VDD33_A, VDD33_B Analog Common Mode Filter. Connect 0.1-F capacitor to GND (1) Power to on-chip regulator 3 V - 3.6 V. Requires 4.7 F to GND at each VDD pin. 48, 29 Power VDDIO 13, 24, 38 Power LVCMOS I/O Power 1.8 V 5% OR 3 V - 3.6 V. Requires 4.7 F to GND at each VDDIO pin. GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias. REGULATOR CAPACITOR CAPR12, CAPP12, CAPI2S 55, 57, 58 CAP CAPL12 4 CAP 54 NC 43.47 GND Decoupling capacitor connection for on-chip regulator. Requires a 4.7 F to GND at each CAP pin. Decoupling capacitor connection for on-chip regulator. Requires two 4.7 F to GND at this CAP pin. OTHERS NC RES[1:0] (1) No connect. This pin may be left open or tied to any level. Reserved - tie to Ground. The VDD (VDD33 and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 7 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings See (1) (2) (3) (4) MIN MAX UNIT Supply voltage - VDD33 -0.3 4 V Supply voltage - VDDIO -0.3 4 V LVCMOS I/O voltage -0.3 (VDDIO + 0.3) V Deserializer input voltage -0.3 2.75 V Junction temperature Maximum power dissipation capacity at 25C 150 C RJA 31 C/W RJC 2.4 C/W 150 C -65 Storage temperature, Tstg (1) (2) (3) (4) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The maximum limit (VDDIO + 0.3 V) does not apply to the PDB pin during the transition to the power down state (PDB transitioning from HIGH to LOW). For soldering specifications: see product folder at www.ti.com and Absolute Maximum Ratings for Soldering (SNOA549). 7.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) 8000 Charged-device model (CDM), per AEC Q100-011 1250 Machine model 250 (IEC, powered-up only) RD = 330 , CS = 150 pF Air Discharge (Pin 49 and 50) Contact Discharge (Pin 49 and 50) 8000 (ISO1060SN5), RD = 330 CS = 150 pF Air Discharge (Pin 49 and 50) 15000 Contact Discharge (Pin 49 and 50) 8000 (ISO10605), RD = 2 k CS = 150 and 330 pF Air Discharge (Pin 49 and 50) 15000 Contact Discharge (Pin 49 and 50) 8000 UNIT 15000 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions Supply voltage (VDD33) LVCMOS supply voltage (VDDIO) Operating free air MAX UNIT 3 3.3 3.6 V 3 3.3 3.6 V Connect VDDIO to 1.8 V and use 1.8-V IOs 1.71 1.8 1.89 V -40 25 105 C 85 MHz 100 mVP-P temperature (TA) 5 Supply noise (1) 8 NOM Connect VDDIO to 3.3 V and use 3.3-V IOs PCLK frequency (1) MIN Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDD33 and VDDIO supplies with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 7.4 Thermal Information DS90UB926Q-Q1 THERMAL METRIC (1) NKB (WQFN) UNIT 60 PINS RJA Junction-to-ambient thermal resistance 26.2 C/W RJC(top) Junction-to-case (top) thermal resistance 8.1 C/W RJB Junction-to-board thermal resistance 5.2 C/W JT Junction-to-top characterization parameter 0.1 C/W JB Junction-to-board characterization parameter 5.2 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 1.1 C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. 7.5 DC Electrical Characteristics over recommended operating supply and temperature ranges unless otherwise specified. (1) PARAMETER TEST CONDITIONS PIN/FREQ. (2) (3) MIN TYP MAX UNIT LVCMOS I/O DC SPECIFICATIONS VIH High Level Voltage VDDIO = 3 to 3.6 V 2 VIL Low Level Input VDDIO = 3 to 3.6 V IIN Input Current VIN = 0 V or VDDIO = 3 to 3.6 V VIH High Level Input Voltage VIL Low Level Input Voltage PDB VDDIO = 1.71 to 1.89 V VDDIO = 3 to 3.6 V IIN VOH VOL Input Current High Level Output Voltage Low Level Output Voltage VDDIO = 1.71 to 1.89 V VIN = 0 V or VDDIO IOH = -4 mA IOL = 4 mA VDDIO = 3 to 3.6 V A 2 VDDIO 0.65 x VDDIO VDDIO GND 0.8 GND 0.35 x VDDIO VDDIO = 1.7 to 1.89 V -10 1 10 VDDIO = 3 to 3.6 V 2.4 VDDIO VDDIO - 0.45 VDDIO GND 0.4 GND 0.35 VDDIO = 3 to 3.6 V VDDIO = 1.7 to 1.89 V VOUT = 0 V IOZ Tri-state Output Current VOUT = 0 V or VDDIO, PDB = L (3) V 10 10 VDDIO = 1.7 to 1.89 V V 0.8 1 Output Short Circuit Current (2) OEN, OSS_SEL, BISTEN, BISTC / INTB_IN, GPIO[3:0] 1 -10 IOS (1) GND -10 VDDIO = 3 to 3.6 V VDDIO V V A ROUT[23:0], HS, VS, DE, PCLK, LOCK, PASS, MCLK, I2S_CLK, I2S_WC, I2S_DA, I2S_DB, GPO_REG[8:4] V V -60 -10 mA 10 A The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and VOD, which are differential voltages. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 9 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com DC Electrical Characteristics (continued) over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3) PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT FPD-LINK III CML RECEIVER INPUT DC SPECIFICATIONS VTH Differential Threshold High Voltage VTL Differential Threshold Low Voltage VCM Differential Common-mode Voltage RT Internal Termination Resistor Differential 50 VCM = 2.5 V (Internal VBIAS) -50 mV mV RIN+, RIN- 1.8 80 100 V 120 CML MONITOR DRIVER OUTPUT DC SPECIFICATIONS VODp-p Differential Output Voltage CMLOUTP, CMLOUTN RL = 100 360 mVp-p SUPPLY CURRENT IDD1 IDDIO1 IDD2 IDDIO2 Supply Current (includes load current) f = 85 MHz VDD33= 3.6 V VDD33 CL = 12 pF, Checker Board VDDIO= 3.6 V VDDIO Pattern (Figure 1) VDDIO = 1.89 V 125 145 110 118 60 75 Supply Current (includes load current) f = 85MHz VDD33 = 3.6 V VDD33 CL = 4 pF Checker Board VDDIO = 3.6 V VDDIO Pattern (Figure 1) VDDIO = 1.89 V 125 145 75 85 50 65 90 115 Supply Current Sleep Mode Without Input Serial Stream 3 5 2 3 IDDS IDDIOS VDD33 = 3.6 V VDDIO = 1.89 V IDDZ IDDIOZ 10 VDDIO = 3.6 V Supply Current Power Down VDD33 VDDIO PDB = L, All VDD33 = 3.6 V VDD33 LVCMOS inputs V = 3.6 V are floating or tied DDIO VDDIO VDDIO = 1.89 V to GND Submit Documentation Feedback 2 10 0.05 10 0.05 10 mA mA mA mA mA mA mA mA Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 7.6 AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) PARAMETER TEST CONDITIONS PIN/FREQ. (2) (3) MIN TYP MAX UNIT GPIO BIT RATE Forward Channel Bit Rate BR Back Channel Bit Rate See (4) (5) f = 5 to 85 MHz, GPIO[3:0] 0.25 x f Mbps >50 >75 kbps 0.3 0.4 UI 200 300 mV 800 ns CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS EW Differential Output Eye Opening Width (6) EH Differential Output Eye Height RL = 100 , Jitter Freq > f / 40 (Figure 2) (4) (5) CMLOUTP, CMLOUTN, f = 85 MHz BIST MODE tPASS BIST PASS Valid Time BISTEN = H (Figure 8) (4) (5) PASS SSCG MODE fDEV Spread Spectrum Clocking Deviation Frequency fMOD Spread Spectrum Clocking Modulation Frequency (1) (2) (3) (4) (5) (6) See Figure 14, Table 1, Table 2 (4) (5) f = 85 MHz, SSCG = ON 0.5% 2.5% 8 100 kHz The Electrical Characteristics tables list ensured specifications under the listed in Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25 C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and VOD, which are differential voltages. Specification is ensured by characterization and is not tested in production. Specification is ensured by design and is not tested in production. UI - Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35 * PCLK). The UI scales with PCLK frequency. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 11 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com 7.7 DC and AC Serial Control Bus Characteristics Over 3.3-V supply and temperature ranges unless otherwise specified. (1) PARAMETER TEST CONDITIONS VIH Input High Level SDA and SCL VIL Input Low Level Voltage SDA and SCL VHY Input Hysteresis SDA, IOL = 1.25 mA Iin SDA or SCL, VIN = VDD33 or GND SDA RiseTime - READ tF SDA Fall Time - READ tSU;DAT Setup Time -- READ tHD;DAT Holdup Time -- READ tSP Input Filter Cin Input Capacitance (1) (2) (3) MIN TYP MAX UNIT 0.7 x VDD33 VDD33 V GND 0.3 x VDD33 V > 50 VOL tR (2) (3) mV 0 0.36 V -10 10 A 430 ns 20 ns See Figure 9 560 ns See Figure 9 615 ns 50 ns SDA or SCL <5 pF SDA, RPU = 10 k, Cb 400 pF (Figure 9) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and VOD, which are differential voltages. 7.8 Timing Requirements MIN tR SDA RiseTime - READ tF SDA Fall Time - READ tSU;DAT Setup Time -- READ tHD;DAT Holdup Time -- READ tSP Input Filter 12 NOM MAX UNIT 430 ns 20 ns See Figure 9 560 ns See Figure 9 615 ns 50 ns SDA, RPU = 10 k, Cb 400 pF (Figure 9) Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 7.9 Timing Requirements for the Serial Control Bus Over 3.3-V supply and temperature ranges unless otherwise specified. MIN fSCL SCL Clock Frequency NOM MAX UNIT Standard Mode 0 100 kHz Fast Mode 0 400 kHz Standard Mode 4.7 s Fast Mode 1.3 s tLOW SCL Low Period tHIGH SCL High Period Standard Mode tHD;STA Hold time for a start or a repeated start condition (Figure 9) tSU:STA Setup time for a start or a repeated start condition (Figure 9) tHD;DAT Data Hold Time (Figure 9) tSU;DAT Data Setup Time (Figure 9) tSU;STO Setup Time for STOP Condition Standard Mode (Figure 9) Fast Mode tBUF Bus Free Time between STOP and START (Figure 9) tr SCL and SDA Rise Time (Figure 9) Standard Mode tf SCL and SDA Fall Time (Figure 9) Standard Mode 4 s 0.6 s 4 s Fast Mode 0.6 s Standard Mode 4.7 s Fast Mode 0.6 s Fast Mode Standard Mode 0 3.45 s Fast Mode 0 0.9 s Standard Mode 250 ns Fast Mode 100 ns 4 s 0.6 s Standard Mode 4.7 s Fast Mode 1.3 s 1000 ns Fast Mode 300 ns Standard Mode 300 ns Fast mode 300 ns 7.10 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER tRCP PCLK Output Period tRDC PCLK Output Duty Cycle tCLH LVCMOS Low-to-High Transition Time (Figure 3) tCHL tROS tROH LVCMOS High-to-Low Transition Time (Figure 3) Data Valid before PCLK - Setup Time SSCG = OFF (Figure 6) Data Valid after PCLK - Hold Time SSCG = OFF (Figure 6) TEST CONDITIONS MIN TYP MAX UNIT 11.76 T 200 ns 45% 50% 55% VDDIO = 1.71 to 1.89 V, CL = 12 pF 2 3 ns VDDIO = 3 to 3.6 V, CL = 12 pF 2 3 ns 2 3 ns 2 3 ns tRCP = tTCP VDDIO = 1.71 to 1.89 V, CL = 12 pF VDDIO = 3 to 3.6 V, CL = 12 pF VDDIO = 1.71 to 1.89 V, CL = 12 pF PIN/FREQ. PCLK ROUT[23:0], HS, VS, DE, PCLK, LOCK, PASS, MCLK, I2S_CLK, I2S_WC, I2S_DA, I2S_DB 2.2 ns 2.2 ns VDDIO = 1.71 to 1.89 V, CL = 12 pF 3 ns VDDIO = 3 to 3.6 V, CL = 12 pF 3 ns VDDIO = 3 to 3.6 V, CL = 12 pF Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 13 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com Switching Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Active to OFF Delay (Figure 5) (1) (2) tXZR OEN = L, OSS_SEL = H tDDLT Lock Time (Figure 5) (1) (2) (3) tDD Delay - Latency (1) (2) tDCCJ tONS tONH tSES tSEH (1) (2) (3) SSCG = OFF Cycle-to-Cycle Jitter (1) (2) MAX UNIT ROUT[23:0] 10 ns HS, VS, DE, PCLK, LOCK, PASS 15 ns MCLK, I2S_CLK, I2S_WC, I2S_DA, I2S_DB 60 ns 5 147*T ns f = 5 to <15 MHz 0.5 ns f = 15 to 85 MHz 0.2 ns I2S_CLK = 1 to 12.28MHz 2 ns VDDIO = 1.71 to 1.89 V, CL = 12 pF 50 ns VDDIO = 3 to 3.6 V, CL = 12 pF 50 ns 50 ns 50 ns 5 ns 5 ns 5 ns 5 ns VDDIO = 3 to 3.6 V, CL = 12 pF Data Tri-State after OSS_ SEL = H, Setup Time (Figure 7) (1) (2) TYP f = 5 to 85MHz VDDIO = 1.71 to 1.89 V, CL = 12 pF Data Tri-State After OEN = L SetupTime (Figure 7) (1) (2) MIN f = 5 to 85MHz SSCG = OFF Data Valid After OEN = H SetupTime (Figure 7) (1) (2) PIN/FREQ. VDDIO = 1.71 to 1.89 V, CL = 12 pF VDDIO = 3 to 3.6 V, CL = 12 pF ROUT[23:0], HS, VS, DE, PCLK, MCLK, I2S_CLK, I2S_WC, I2S_DA, I2S_DB VDDIO = 1.71 to 1.89 V, Data to Low after OSS_SEL = L CL = 12 pF Setup Time (Figure 7) (1) (2) VDDIO = 3 to 3.6 V, CL = 12 pF 40 ns Specification is ensured by characterization and is not tested in production. Specification is ensured by design and is not tested in production. tDDLT is the time required by the device to obtain lock when exiting power-down state with an active serial stream. 7.11 Timing Diagrams VDDIO PCLK GND VDDIO ROUT[n] (odd), VS, HS GND VDDIO ROUT[n] (even), DE GND Figure 1. Checker Board Data Pattern 14 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Timing Diagrams (continued) EW VOD (+) CMLOUT (Diff.) EH 0V EH VOD (-) tBIT (1 UI) Figure 2. CML Output Driver VDDIO 80% 20% GND tCLH tCHL Figure 3. LVCMOS Transition Times START BIT RIN 0 (Diff.) 1 2 STOP BIT START BIT 3 3 0 SYMBOL N 1 STOP BIT 3 3 2 SYMBOL N+1 tDD PCLK (RFB = L) ROUT[23:0], I2S[2:0], HS, VS, DE SYMBOL N-2 SYMBOL N-1 SYMBOL N Figure 4. Delay - Latency PDB 2.0V 0.8V RIN (Diff.) }v[ OE tDDLT LOCK TRI-STATE or LOW Z or L tXZR ROUT[23:0], HS, VS, DE, I2S TRI-STATE or LOW or Pulled Up PCLK (RFB = L) Z or L or PU TRI-STATE or LOW OFF IN LOCK TIME Z or L ACTIVE OFF Figure 5. PLL Lock Times and PDB Tri-State Delay Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 15 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com Timing Diagrams (continued) VDDIO PCLK w/ RFB = H 1/2 VDDIO GND ROUT[23:0], VS, HS, DE, I2S VDDIO VOHmin VOLmax tROS GND tROH Figure 6. Output Data Valid (Setup and Hold) Times With SSCG = Off PDB= H VIH OSS_SEL VIL VIH OEN VIL RIN (Diff.) }v[ OE tSEH tSES tONS tONH LOCK (HIGH) TRI-STATE PASS ACTIVE HIGH ROUT[23:0], HS, VS, DE, I2S[2:0] LOW TRI-STATE PCLK (RFB = L) LOW TRI-STATE HIGH TRI-STATE ACTIVE TRI-STATE ACTIVE LOW LOW Figure 7. Output State (Setup and Hold) Times SDA SCL S START condition, or START repeat condition P STOP condition Figure 8. BIST PASS Waveform 16 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Timing Diagrams (continued) tr tf tBUF SDA tHD;STA tSU;DAT tLOW tf tSU;STO tSP tSU;STA tHD;DAT SCL tHD;STA tHIGH tr S Sr P S Figure 9. Serial Control Bus Timing Diagram CML Serializer Data Throughput (200 mV/DIV) 7.12 Typical Characteristics 78 MHz TX Pixel Clock Input (2 V/DIV) 78 MHz RX Pixel Clock Output (2 V/DIV) Time (1.25 ns/DIV) Time (10 ns/DIV) Note: On the rising edge of each clock period, the CML driver outputs a low Stop bit, high Start bit, and 33 DC-scrambled data bits. Figure 10. Serializer CML Driver Output With 78-MHZ TX Pixel Clock Figure 11. Comparison of Deserializer LVCMOS RX PCLK Output Locked to a 78-MHz TX PCLK Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 17 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com 8 Detailed Description 8.1 Overview The DS90UB926Q-Q1 deserializer receives 35 bits of data over a single serial FPD-Link III pair operating up to 2.975-Gbps application payload. The serial stream contains an embedded clock, video control signals, and the DC-balanced video data and audio data which enhance signal quality to support AC coupling. The DS90UB926Q-Q1 deserializer attains lock to a data stream without the use of a separate reference clock source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the serializer regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers the clock and data by extracting the embedded clock information, validating then deserializing the incoming data stream. The recovered parallel LVCMOS video bus is then provided to the display. The deserializer is intended for use with the DS90UB925Q-Q1 serializer, but is also backward-compatible with DS90UR905Q or DS90UR907Q FPD-Link II serializer. 8.2 Functional Block Diagram REGULATOR SSCG CMF 24 RIN+ RIN4 CMLOUTP CMLOUTN BISTEN BISTC PDB SCL SCA IDx MODE_SEL Error Detector Timing and Control Clock and Data Recovery ROUT [23:0] HS VS DE I2S_CLK I2S_WC I2S_DA MCLK PASS PCLK LOCK DS90UB926Q-Q1 Deserializer 8.3 Feature Description 8.3.1 High-Speed Forward Channel Data Transfer The High-Speed Forward Channel (HS_FC) is composed of 35 bits of data containing DIN[23:0] or RGB[7:0] or YUV data, sync signals, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 12 shows the serial stream per PCLK cycle. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized, balanced, and scrambled. C1 C0 Figure 12. FPD-Link III Serial Stream 18 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Feature Description (continued) The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbps maximum (175 Mbps minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps minimum. 8.3.2 Low-Speed Back Channel Data Transfer The low-speed backward channel (LS_BC) of the DS90UB926Q-Q1 provides bidirectional communication between the display and host processor. The information is carried back from the Deserializer to the Serializer per serial symbol. The back channel control data is transferred over the single serial link along with the highspeed forward data, DC balance coding and embedded clock information. This architecture provides a backward path across the serial link together with a high-speed forward channel. The back channel contains the I2C, CRC, and 4 bits of standard GPIO information with 10-Mbps line rate. 8.3.3 Backward-Compatible Mode The DS90UB926Q-Q1 is also backward-compatible to DS90UR905Q and DS90UR907Q FPD Link II serializers at 15- to 65-MHz pixel clock frequencies. It receives 28 bits of data over a single serial FPD-Link II pair operating at the line rate of 420 Mbps to 1.82 Gbps. This backward-compatible mode is provided through the MODE_SEL pin (Table 9) or the configuration register (Table 11). In this mode, the minimum PCLK frequency is 15 MHz. 8.3.4 Input Equalization Gain FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces the medium-induced deterministic jitter. It equalizes up to 10 meter STP cables with 3 connection breaks at maximum serialized stream payload rate of 2.975 Gbps. 8.3.5 Common-Mode Filter Pin (CMF) The deserializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for additional noise rejection capability. A 0.1-F capacitor has to be connected to this pin to Ground. 8.3.6 Video Control Signal Filter When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following restrictions: * Normal Mode with Control Signal Filter Enabled: DE and HS -- Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 PCLK or longer. * Normal Mode with Control Signal Filter Disabled: DE and HS -- Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition pulse. * VS -- Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles. Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal can cause a visual display error. This feature allows for the chipset to validate and filter out any high-frequency noise on the control signals. See Figure 13. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 19 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com Feature Description (continued) PCLK IN HS/VS/DE IN Latency PCLK OUT HS/VS/DE OUT Pulses 1 or 2 PCLKs wide Filetered OUT Figure 13. Video Control Signal Filter Waveform 8.3.7 EMI Reduction Features 8.3.7.1 Spread Spectrum Clock Generation (SSCG) The DS90UB926Q-Q1 provides an internally generated spread-spectrum clock (SSCG) to modulate its outputs. Both clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to 2.5% (5% total) at up to 100-kHz modulations are available. This feature may be controlled by register. See Table 1, Table 2, and Table 11. Do not enable the SSCG feature if the source PCLK into the SER has a clock with spread spectrum already. Frequency fdev(max) FPCLK+ FPCLK FPCLK- fdev(min) Time 1/fmod Figure 14. SSCG Waveform Table 1. SSCG Configuration LFMODE = L (15 to 85 MHz) SSCG CONFIGURATION (0x2C) LFMODE = L (15 to 85 MHz) 20 SSC[2] SSC[1] L L SPREAD SPECTRUM OUTPUT SSC[0] Fdev (%) L L 0.9 L H 1.2 L H L 1.9 L H H 2.5 H L L 0.7 H L H 1.3 H H L 2 H H H 2.5 Submit Documentation Feedback Fmod (kHz) PCLK / 2168 PCLK / 1300 Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Table 2. SSCG Configuration LFMODE = H (5 to <15 MHz) SSCG CONFIGURATION (0x2C) LFMODE = H (5 to <15 MHz) SPREAD SPECTRUM OUTPUT SSC[2] SSC[1] SSC[0] Fdev (%) L L L 0.5 L L H 1.3 L H L 1.8 L H H 2.5 H L L 0.7 H L H 1.2 H H L 2 H H H 2.5 Fmod (kHz) PCLK / 628 PCLK / 388 8.3.8 Enhanced Progressive Turnon (EPTO) The deserializer LVCMOS parallel outputs timing are delayed. Groups of 8-bit R, G and B outputs switch in a different time. This minimizes the number of outputs switching simultaneously and helps to reduce supply noise. In addition, it spreads the noise spectrum out reducing overall EMI. 8.3.9 LVCMOS VDDIO Option The deserializer parallel bus can operate with 1.8-V or 3.3-V levels (VDDIO) for target (display) compatibility. The 1.8-V levels offers a lower noise (EMI) and also a system power savings. 8.3.10 Power Down (PDB) The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the host or through the VDDIO, where VDDIO = 3 V to 3.6 V or VDD33. To save power disable the link when the display is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after VDD33 and VDDIO have reached final levels; no external components are required. In the case of driven by the VDDIO = 3 V to 3.6 V or VDD33 directly, a 10-k resistor to the VDDIO = 3 V to 3.6 V or VDD33 , and a > 10-F capacitor to the ground are required (see Figure 24). 8.3.11 Stop Stream Sleep The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer then locks to the incoming signal and recover the data. NOTE In STOP STREAM SLEEP, the Serial Control Bus Registers values are retained. 8.3.12 Serial Link Fault Detect The serial link fault detection is able to detect any of following 7 conditions 1. cable open 2. + to - short 3. + short to GND 4. - short to GND 5. + short to battery 6. - short to battery 7. cable is linked incorrectly If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on the Serial Control Bus Register bit 0 of address 0x1C Table 11. The link errors can be monitored though Link Error Count of the Serial Control Bus Register bit [4:0] of address 0x41 Table 11. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 21 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com 8.3.13 Oscillator Output The deserializer provides an optional PCLK output when the input clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be selected. This feature is controlled by register Address 0x02, bit 5 (OSC Clock Enable). See Table 11. 8.3.14 Pixel Clock Edge Select (RFB) The RFB determines the edge that the data is strobed on. If RFB is High (1), output data is strobed on the Rising edge of the PCLK. If RFB is Low (`0'), data is strobed on the Falling edge of the PCLK. This allows for interoperability with downstream devices. The deserializer output does not need to use the same edge as the Ser input. This feature may be controlled by register. See Table 11. 8.3.15 Image Enhancement Features Several image enhancement features are provided. White balance LUTs allow the user to define and target the color temperature of the display. Adaptive Hi-FRC dithering enables the presentation of "true-color" images on an 18-bit color display. 8.3.15.1 White Balance The white balance feature enables similar display appearance when using LCDs from different vendors. It compensates for native color temperature of the display, and adjusts relative intensities of R, G, and B to maintain specified color temperature. Programmable control registers are used to define the contents of three LUTs (8-bit color value for red, green and blue) for the white balance feature. The LUTs map input RGB values to new output RGB values. There are three LUTs, one LUT for each color. Each LUT contains 256 entries, 8 bits per entry with a total size of 6144 bits (3 x 256 x 8). All entries are readable and writable. Calibrated values are loaded into registers through the I2C interface (deserializer is a slave device). This feature may also be applied to lower color depth applications such as 18-bit (666) and 16-bit (565). White balance is enabled and configured through the serial control bus register. 8.3.15.1.1 LUT Contents The user must define and load the contents of the LUT for each color (R,G, and B). Regardless of the color depth being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3 tables. Unused bits - LSBs -shall be set to 0 by the user. When 24-bit (888) input data is being driven to a 24-bit display, each LUT (R, G and B) must contain 256 unique 8-bit entries. The 8-bit white balanced data is then available at the output of the DS90UB926Q-Q1 deserializer, and driven to the display. When 18-bit (666) input data is being driven to an 18-bit display, the white balance feature may be used in one of two ways. First, simply load each LUT with 256, 8-bit entries. Each 8-bit entry is a 6-bit value (6 MSBs) with the 2 LSBs set to 00. Thus as total of 64 unique 6-bit white balance output values are available for each color (R, G, and B). The 6-bit white balanced data is available at the output of the DS90UB926Q-Q1 deserializer, and driven directly to the display. Alternatively, with 6-bit input data the user may choose to load complete 8-bit values into each LUT. This mode of operation provides the user with finer resolution at the LUT output to more closely achieve the desired white point of the calibrated display. Although 8-bit data is loaded, only 64 unique 8-bit white balance output values are available for each color (R, G, and B). The result is 8-bit white balanced data. Before driving to the output of the deserializer, the 8-bit data must be reduced to 6-bit with an FRC dithering function. To operate in this mode, the user must configure the DS90UB926Q-Q1 to enable the FRC2 function. Examples of the three types of LUT configurations described are shown in Figure 15 22 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 8.3.15.1.2 Enabling White Balance The user must load all 3 LUTs prior to enabling the white balance feature. The following sequence must be followed by the user. To initialize white balance after power-on (Table 3): 1. Load contents of all 3 LUTs . This requires a sequential loading of LUTs - first RED, second GREEN, third BLUE. 256, 8-bit entries must be loaded to each LUT. Page registers must be set to select each LUT. 2. Enable white balance By default, the LUT data may not be reloaded after initialization at power-on. An option does exist to allow LUT reloading after power-on and initial LUT loading (as described above). This option may only be used after enabling the white balance reload feature through the associated serial control bus register. In this mode the LUTs may be reloaded by the master controller through the I2C. This provides the user with the flexibility to refresh LUTs periodically , or upon system requirements to change to a new set of LUT values. The host controller loads the updated LUT values through the serial bus interface. There is no need to disable the white balance feature while reloading the LUT data. Refreshing the white balance to the new set of LUT data will be seamless - no interruption of displayed data. It is important to note that initial loading of LUT values requires that all 3 LUTs be loaded sequentially. When reloading, partial LUT updates may be made. 8-bit in / 8 bit out Gray level Entry Data Out (8-bits) 00000000b N/A N/A N/A 00000100b N/A N/A N/A 00001000b N/A N/A N/A 248 249 250 251 252 253 254 255 11111000b N/A N/A N/A 11111100b N/A N/A N/A 0 1 2 3 4 5 6 7 8 9 10 11 00000001b N/A N/A N/A 00000110b N/A N/A N/A 00001011b N/A N/A N/A 248 249 250 251 252 253 254 255 11111010b N/A N/A N/A 11111111b N/A N/A N/A 0 1 2 3 4 5 6 7 8 9 10 11 Data Out (8-bits) 11111010b 11111010b 11111011b 11111011b 11111110b 11111101b 11111101b 11111111b Data Out (8-bits) 248 249 250 251 252 253 254 255 6-bit in / 8 bit out Gray level Entry 00000000b 00000001b 00000011b 00000011b 00000110b 00000110b 00000111b 00000111b 00001000b 00001010b 00001001b 00001011b 0 1 2 3 4 5 6 7 8 9 10 11 6-bit in / 6 bit out Gray level Entry Figure 15. White Balance LUT Configurations Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 23 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com Table 3. White Balance Register Table PAGE ADD (dec) ADD (hex) REGISTER NAME BIT(s) ACCES S DEFAU LT (hex) FUNCTION RW 0x00 Page Setting DESCRIPTION 7:6 0 42 0x2A White Balance Control 5 4 RW White Balance Enable RW 0- 255 00 - FF White Balance Red LUT FF:0 2 0- 255 00 - FF White Balance Green LUT FF:0 3 0- 255 00 - FF White Balance Blue LUT FF:0 0: White Balance Disable 1: White Balance Enable 0: Reload Disable 1: Reload Enable 3:0 1 00: Configuration Registers 01: Red LUT 10: Green LUT 11: Blue LUT Reserved RW N/A Red LUT RW N/A Green LUT RW N/A Blue LUT 256 8-bit entries to be applied to the Red subpixel data 256 8-bit entries to be applied to the Green subpixel data 256 8-bit entries to be applied to the Blue subpixel data 8.3.15.2 Adaptive HI-FRC Dithering The adaptive FRC dithering feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits per subpixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use lower cost 18-bit displays. Frame Rate Control (FRC) dithering is a method to emulate "missing" colors on a lower color depth LCD display by changing the pixel color slightly with every frame. FRC is achieved by controlling on and off pixels over multiple frames (Temporal). Static dithering regulates the number of on and off pixels in a small defined pixel group (Spatial). The FRC module includes both Temporal and Spatial methods and also Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. "Hi-FRC" enables full (16,777,216) color on an 18-bit LCD panel. The "adaptive" FRC module also includes input pixel detection to apply specific Spatial dithering methods for smoother gray level transitions. When enabled, the lower LSBs of each RGB output are not active; only 18-bit data (6 bits per R,G and B) are driven to the display. This feature is enabled through the serial control bus register. Two FRC functional blocks are available, and may be independently enabled. FRC1 precedes the white balance LUT, and is intended to be used when 24-bit data is being driven to an 18-bit display with a white balance LUT that is calibrated for an 18-bit data source. The second FRC block, FRC2, follows the white balance block and is intended to be used when fine adjustment of color temperature is required on an 18-bit color display, or when a 24-bit source drives an 18-bit display with a white balance LUT calibrated for 24-bit source data. For proper operation of the FRC dithering feature, the user must provide a description of the display timing control signals. The timing mode, "sync mode" (HS, VS) or "DE only" must be specified, along with the active polarity of the timing control signals. All this information is entered to DS90UB926Q-Q1 control registers through the serial bus interface. Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit data. This allows the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is evaluated, and one of four possible algorithms is selected. The majority of incoming data sequences are supported by the default dithering algorithm. Certain incoming data patterns (black/white pixel, full on/off subpixel) require special algorithms designed to eliminate visual artifacts associated with these specific gray level transitions. Three algorithms are defined to support these critical transitions. An example of the default dithering algorithm is illustrated in Figure 16. The 1 or 0 value shown in the table describes whether the 6-bit value is increased by 1 (1) or left unchanged (0). In this case, the 3 truncated LSBs are 001. 24 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Frame = 0, Line = 0 F0L0 Pixel Index PD1 Pixel Data one Cell Value 010 R[7:2]+0, G[7:2]+1, B[7:2]+0 LSB=001 three lsb of 9 bit data (8 to 9 for Hi-Frc) PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 F0L0 010 000 000 000 000 000 010 000 F0L1 101 000 000 000 101 000 000 000 R = 4/32 F0L2 000 000 010 000 010 000 000 000 G = 4/32 F0L3 000 000 101 000 000 000 101 000 B = 4/32 F1L0 000 000 000 000 000 000 000 000 F1L1 000 111 000 000 000 111 000 000 R = 4/32 F1L2 000 000 000 000 000 000 000 000 G = 4/32 F1L3 000 000 000 111 000 000 000 111 B = 4/32 F2L0 000 000 010 000 010 000 000 000 F2L1 000 000 101 000 000 000 101 000 R = 4/32 F2L2 010 000 000 000 000 000 010 000 G = 4/32 F2L3 101 000 000 000 101 000 000 000 B = 4/32 F3L0 000 000 000 000 000 000 000 000 F3L1 000 000 000 111 000 000 000 111 R = 4/32 F3L2 000 000 000 000 000 000 000 000 G = 4/32 F3L3 000 111 000 000 000 111 000 000 B = 4/32 LSB=001 LSB = 001 Figure 16. Default FRC Algorithm See Table 4 for recommended FRC settings dependant on 18/24-bit source, 18/24-bit white balance LUT, and 18/24-bit display. Table 4. Recommended FRC settings SOURCE WHITE BALANCE LUT DISPLAY FRC1 FRC2 24-bit 24-bit 24-bit Disabled Disabled 24-bit 24-bit 18-bit Disabled Enabled 24-bit 18-bit 18-bit Enabled Disabled 18-bit 24-bit 24-bit Disabled Disabled 18-bit 24-bit 18-bit Disabled Enabled 18-bit 18-bit 18-bit Disabled Disabled 8.3.16 Internal Pattern Generation The DS90UB926Q-Q1 serializer supports the internal pattern generation feature. It allows basic testing and debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power-down mode, the test pattern will be displayed even if no parallel input is applied. If no PCLK is received, the test pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to AN-2198 Exploring the Internal Test Pattern Generation Feature of 720p FPD-Link III Devices (SNLA132). Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 25 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com 8.3.17 Built-In Self Test (BIST) An optional at-speed built-in self test (BIST) feature supports the testing of the high speed serial link and the lowspeed back channel. This is useful in the prototype stage, equipment production, in-system test, and also for system diagnostics. NOTE BIST is not available in backward-compatible mode. 8.3.17.1 BIST Configuration and Status The BIST mode is enabled at the deserializer by the pin select (Pin 44 BISTEN and Pin 16 BISTC) or configuration register (Table 11) through the deserializer. When LFMODE = 0, the pin-based configuration defaults to external PCLK or 33-MHz internal oscillator clock (OSC) frequency. In the absence of PCLK, the user can select the desired OSC frequency (default 33 MHz or 25 MHz) through the register bit. When LFMODE = 1, the pin based configuration defaults to external PCLK or 12.5MHz MHz internal oscillator clock (OSC) frequency. When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to 35 bit errors. The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the deserializer is locked or unlocked, the lock status can be read in the register. See Table 11. 8.3.17.1.1 Sample BIST Sequence See Figure 17 for the BIST mode flow diagram. 1. For the DS90UB925Q-Q1 and DS90UB926Q-Q1 FPD-Link III chipset, BIST Mode is enabled through the BISTEN pin of DS90UB926Q-Q1 FPD-Link III deserializer. The desired clock source is selected through BISTC pin. 2. The DS90UB925Q-Q1 serializer is woken up through the back channel if it is not already on. The all zero pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate. 3. To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal. 4. The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 18 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect, reducing signal condition enhancements ( Rx Equalization). 26 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Normal Step 1: DES in BIST BIST Wait Step 2: Wait, SER in BIST BIST start Step 3: DES in Normal Mode check PASS BIST stop Step 4: DES/SER in Normal Figure 17. BIST Mode Flow Diagram 8.3.17.2 Forward Channel And Back Channel Error Checking While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero pattern. The internal all-zeroes pattern goes through scrambler, DC-balancing, and so forth, and goes over the serial link to the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with all-zeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The deserializer then outputs a SSO pattern on the RGB output pins. The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in BIST mode only and keeps the record of last BIST run until cleared or enters BIST mode again. DES Outputs BISTEN (DES) Case 1 - Pass PCLK (RFB = L) ROUT[23:0] HS, VS, DE DATA (internal) PASS Prior Result PASS PASS X X X FAIL Prior Result Normal SSO Case 2 - Fail X = bit error(s) DATA (internal) BIST Test BIST Duration BIST Result Held Normal Figure 18. Bist Waveforms Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 27 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com 8.3.18 I2S Receiving In normal 24-bit RGB operation mode, the DS90UB926Q-Q1 provides up to 3-bit of I2S. They are I2S_CLK, I2S_WC and I2S_DA, as well as the Master I2S Clock (MCLK). The audio is received through the forward video frame, or can be configured to receive during video blanking periods. A jitter cleaning feature reduces I2S_CLK output jitter to +/- 2ns. 8.3.18.1 I2S Jitter Cleaning The DS90UB926Q-Q1 features a standalone PLL to clean the I2S data jitter supporting high end car audio systems. If I2S CLK frequency is less than 1MHz, this feature has to be disabled through the register bit I2S Control (0x2B) in Table 10 8.3.18.2 Secondary I2S Channel In 18-bit RGB operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio channel in additional to the 3-bit of I2S. The I2S_DB is synchronized to the I2S_CLK. To enable this synchronization feature on this bit, set the MODE_SEL (Table 9) or program through the register bit (Table 11). 8.3.18.2.1 MCLK The deserializer has an I2S Master Clock Output. It supports x1, x2, or x4 of I2S CLK Frequency. When the I2S PLL is disabled, the MCLK output is off. Table 5 below covers the range of I2S sample rates and MCLK frequencies. By default, all the MCLK output frequencies are x2 of the I2S CLK frequencies. The MCLK frequencies can also be enabled through the register bit [7:4] (I2S MCLK Output) of 0x3A shown in Table 11. To select desired MCLK frequency, write bit 7 (0x3A) = 1, then write to bit [6:4] accordingly. Table 5. Audio Interface Frequencies SAMPLE RATE (kHz) I2S DATA WORD SIZE (BITS) 32 1.024 44.1 48 1.4112 16 96 192 28 I2S CLK (MHz) 1.536 3.072 6.144 MCLK OUTPUT (MHz) REGISTER 0x3A[6:4]'b I2S_CLK x1 000 I2S_CLK x2 001 I2S_CLK x4 010 I2S_CLK x1 000 I2S_CLK x2 001 I2S_CLK x4 010 I2S_CLK x1 000 I2S_CLK x2 001 I2S_CLK x4 010 I2S_CLK x1 001 I2S_CLK x2 010 I2S_CLK x4 011 I2S_CLK x1 010 I2S_CLK x2 011 I2S_CLK x4 100 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Table 5. Audio Interface Frequencies (continued) SAMPLE RATE (kHz) I2S DATA WORD SIZE (BITS) 32 1.536 44.1 48 2.117 24 96 2.304 4.608 192 9.216 32 2.048 44.1 48 I2S CLK (MHz) 2.8224 32 96 192 3.072 6.144 12.288 MCLK OUTPUT (MHz) REGISTER 0x3A[6:4]'b I2S_CLK x1 000 I2S_CLK x2 001 I2S_CLK x4 010 I2S_CLK x1 001 I2S_CLK x2 010 I2S_CLK x4 011 I2S_CLK x1 001 I2S_CLK x2 010 I2S_CLK x4 011 I2S_CLK x1 010 I2S_CLK x2 011 I2S_CLK x4 100 I2S_CLK x1 011 I2S_CLK x2 100 I2S_CLK x4 101 I2S_CLK x1 001 I2S_CLK x2 010 I2S_CLK x4 011 I2S_CLK x1 001 I2S_CLK x2 010 I2S_CLK x4 011 I2S_CLK x1 001 I2S_CLK x2 010 I2S_CLK x4 011 I2S_CLK x1 010 I2S_CLK x2 011 I2S_CLK x4 100 I2S_CLK x1 011 I2S_CLK x2 100 I2S_CLK x4 110 8.3.19 Interrupt Pin -- Functional Description and Usage (INTB) 1. On DS90UB925Q-Q1, set register 0xC6[5] = 1 and 0xC6[0] = 1 2. DS90UB926Q-Q1 deserializer INTB_IN (pin 16) is set LOW by some downstream device. 3. DS90UB925Q-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an interrupt condition. 4. External controller detects INTB = LOW; to determine interrupt source, read ISR register . 5. A read to ISR will clear the interrupt at the DS90UB925Q-Q1, releasing INTB. 6. The external controller typically must then access the remote device to determine downstream interrupt source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the INTB_IN (pin 16) on the DS90UB926Q-Q1. The system is now ready to return to step (1) at next falling edge of INTB_IN. 8.3.20 GPIO[3:0] and GPO_REG[8:4] In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UB926Q-Q1 can be used as the general purpose IOs GPIO[3:0] in either forward channel (Outputs) or back channel (Inputs) application. GPIO[3:0] Enable Sequence Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 29 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com See Table 6 for the GPIO enable sequencing. 1. Enable the 18-bit mode either through the configuration register bit Table 11 on DS90UB925Q-Q1 only. DS90UB926Q-Q1 is automatically configured as in the 18-bit mode. 2. To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UB925Q-Q1, then write 0x05 to address 0x1F on DS90UB926Q-Q1. Table 6. GPIO Enable Sequencing Table NO. DESCRIPTION DEVICE FORWARD CHANNEL BACK CHANNEL 1 Enable 18-bit mode DS90UB925Q-Q1 0x12 = 0x04 0x12 = 0x04 DS90UB926Q-Q1 Auto Load from DS90UB925Q-Q1 Auto Load from DS90UB925Q-Q1 2 GPIO3 DS90UB925Q-Q1 0x0F = 0x03 0x0F = 0x05 DS90UB926Q-Q1 0x1F = 0x05 0x1F = 0x03 DS90UB925Q-Q1 0x0E = 0x30 0x0E = 0x50 DS90UB926Q-Q1 0x1E = 0x50 0x1E = 0x30 DS90UB925Q-Q1 0x0E = 0x03 0x0E = 0x05 3 GPIO2 4 GPIO1 5 GPIO0 DS90UB926Q-Q1 0x1E = 0x05 0x0E = 0x05 DS90UB925Q-Q1 0x0D = 0x93 0x0D = 0x95 DS90UB926Q-Q1 0x1D = 0x95 0x1D = 0x93 8.3.20.1 GPO_REG[8:4] Enable Sequence GPO_REG[8:4] are the outputs only pins. They must be programmed through the local register bits. See Table 7 for the GPO_REG enable sequencing. 1. Enable the 18-bit mode either through the configuration register bit Table 11 on DS90UB925Q-Q1 only. DS90UB926Q-Q1 is automatically configured as in the 18-bit mode. 2. To enable GPO_REG8 outputs a 1 , write 0x90 to address 0x21 on DS90UB926Q-Q1. Table 7. GPO_REG Enable Sequencing Table NO. DESCRIPTION DEVICE LOCAL ACCESS 1 Enable 18-bit mode DS90UB926Q-Q1 0x12 = 0x04 (on DS90UB925Q-Q1) 2 GPO_REG8 DS90UB926Q-Q1 0x21 = 0x90 1 0x21 = 0x10 0 3 GPO_REG7 DS90UB926Q-Q1 0x21 = 0x09 1 0x21 = 0x01 1 0x20 = 0x90 0 0x20 = 0x10 1 4 30 GPO_REG6 DS90UB926Q-Q1 LOCAL OUTPUT VALUE 5 GPO_REG5 DS90UB926Q-Q1 0x20 = 0x09 1 0x20 = 0x01 0 6 GPO_REG4 DS90UB926Q-Q1 0x1F = 0x90 1 0x1F = 0x10 0 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 8.4 Device Functional Modes 8.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL) When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW (depending on the value of the OEN setting). After the DS90UB926Q-Q1 completes its lock sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available on the parallel bus and PCLK outputs. The State of the outputs are based on the OEN and OSS_SEL setting (Table 8) or register bit (Table 11). See Figure 7. Table 8. Output States INPUTS OUTPUTS SERIAL INPUT PDB OEN OSS_SEL LOCK PASS DATA, GPIO, I2S CLK X 0 X X 1 0 X Z Z Z Z 0 L or H L L X 1 L 0 1 L or H Z Z Z Static Static 1 1 0 L L L L/OSC (Register bit enable) 1 1 1 L Previous Status L L Active 1 1 0 H L L L Active 1 1 1 H Valid Valid Valid 8.4.2 Low Frequency Optimization (LFMODE) The LFMODE is set through the register (Table 11) or MODE_SEL Pin 24 (Table 9). It controls the operating frequency of the deserializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is High, the PCLK frequency is between 5 MHz and <15 MHz. Please note when the device LFMODE is changed, a PDB reset is required. 8.4.3 Configuration Select (MODE_SEL) Configuration of the device may be done through the MODE_SEL input pin, or through the configuration register bit. A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the MODE_SEL input (VR4) and VDD33 to select one of the other 10 possible selected modes. See Figure 19 and Table 9. VDD33 R3 VR4 MODE_SEL R4 DES Figure 19. MODE_SEL Connection Diagram Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 31 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com Table 9. Configuration Select (MODE_SEL) NO. (1) (2) (3) (4) IDEAL RATIO VR4/VDD33 IDEAL VR4 (V) SUGGESTED RESISTOR R3 k (1% tolerance) SUGGESTED RESISTOR R4 k (1% tolerance) Repeater (2) LFMODE BACKWARD COMPATIBLE (3) (1) I2S CHANNEL B (18-bit Mode) (4) 1 0 0 Open 40.2 L L L L 2 0.123 0.407 115 16.2 L L L H 3 0.167 0.552 121 24.3 L H L L 4 0.227 0.748 162 47.5 L H L H 5 0.291 0.960 137 56.2 H L L L 6 0.366 1.209 107 61.9 H L L H 7 0.458 1.510 113 95.3 H H L L 8 0.542 1.790 95.3 113 H H L H 9 0.611 2.016 73.2 115 L L H L LFMODE: L = 15 to 85 MHz (Default); H = 5 to <15 MHz Repeater: L = Repeater Off (Default); H = Repeater On Backward Compatible: L = Backward Compatible Off (Default); H = Backward Compatible On to 905/907 (15 to 65 MHz) I2S Channel B: L = I2S Channel B Off, Normal 24-bit RGB Mode (Default); H = I2S Channel B On, 18-bit RGB Mode with I2S_DB Enabled. 8.4.4 Repeater Application The DS90UB925Q-Q1 and DS90UB926Q-Q1 can be configured to extend data transmission over multiple links to multiple display devices. Setting the devices into repeater mode provides a mechanism for transmitting to all receivers in the system. In a repeater application, in this document, the DS90UB925Q-Q1 is referred to as the Transmitter or transmit port (TX), and the DS90UB926Q-Q1 is referred to as the Receiver (RX). Figure 20 shows the maximum configuration supported for Repeater implementations using the DS90UB925Q-Q1 (TX) and DS90UB926Q-Q1 (RX). Two levels of Repeaters are supported with a maximum of three Transmitters per Receiver. 32 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 1:3 Repeater 1:3 Repeater TX Source TX TX RX Display TX RX Display TX RX Display TX RX Display TX RX Display TX RX Display TX RX Display TX RX Display TX RX Display RX RX TX TX 1:3 Repeater RX 1:3 Repeater RX Figure 20. Maximum Repeater Application DS90UB925Q-Q1 Transmitter I2C Master upstream Transmitter I2C I2C Slave downstream Receiver or Repeater Parallel LVCMOS DS90UB926Q-Q1 Receiver I2S Audio DS90UB925Q-Q1 Transmitter I2C Slave downstream Receiver or Repeater FPD-Link III interfaces Figure 21. 1:2 Repeater Configuration In a repeater application, the I2C interface at each TX and RX may be configured to transparently pass I2C communications upstream or downstream to any I2C device within the system. This includes a mechanism for assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 33 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com At each repeater node, the parallel LVCMOS interface fans out to up to three serializer devices, providing parallel RGB video data, HS/VS/DE control signals and, optionally, packetized audio data (transported during video blanking intervals). Alternatively, the I2S audio interface may be used to transport digital audio data between receiver and transmitters in place of packetized audio. All audio and video data is transmitted at the output of the Receiver and is received by the Transmitter.. Figure 21 provides more detailed block diagram of a 1:2 repeater configuration. 8.4.4.1 Repeater Connections The Repeater requires the following connections between the Receiver and each Transmitter for Figure 22: 1. Video Data - Connect PCLK, RGB and control signals (DE, VS, HS). 2. I2C - Connect SCL and SDA signals. Both signals should be pulled up to VDD33 with 4.7-k resistors. 3. Audio - Connect I2S_CLK, I2S_WC, and I2S_DA signals. 4. IDx pin - Each Transmitter and Receiver must have an unique I2C address. 5. MODE_SEL pin - All Transmitter and Receiver must be set into the Repeater Mode. 6. Interrupt pin- Connect DS90UB926Q-Q1 INTB_IN pin to DS90UB925Q-Q1 INTB pin. The signal must be pulled up to VDDIO. DS90UB926Q-Q1 DS90UB925Q-Q1 RGB[7:0) / ROUT[23:0] VDD33 DIN[23:0] / RGB[7:0] DE DE VS VS HS HS I2S_CLK I2S_CLK I2S_WC I2S_WC I2S_DA I2S_DA Optional MODE_SEL VDD33 MODE_SEL VDDIO INTB_IN Optional INTB VDD33 VDD33 ID[x] VDD33 SDA SDA SCL SCL ID[x] Figure 22. Repeater Connection Diagram 34 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 8.5 Programming 8.5.1 Serial Control Bus The DS90UB926Q-Q1 is configured by the use of a serial control bus that is I2C protocol compatible. . Multiple deserializer devices may share the serial control bus since 16 device addresses are supported. Device address is set through the R1 and R2 values on IDx pin. See Figure 23. The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input / Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pullup resistor to VDD33. For most applications a 4.7-k pullup resistor to VDD33 may be used. The resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low. VDD33 R1 VDD33 VR2 4.7k HOST or Salve SCL 4.7k SDA IDx R2 SER or SCL DES SDA To other Devices Figure 23. Serial Control Bus Connection The configuration pin is the IDx pin. This pin sets one of 16 possible device addresses. A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the IDx input (VR2) and VDD33 to select one of the other 16 possible addresses. See Table 10. Table 10. Serial Control Bus Addresses for IDx NO. IDEAL RATIO VR2 / VDD33 IDEAL VR2 (V) SUGGESTED RESISTOR R1 k (1% tol) SUGGESTED RESISTOR R2 k (1% tol) ADDRESS 7'b ADDRESS 8'b APPENDED 1 0 0 Open 40.2 0x2C 0x58 2 0.123 0.406 124 17.4 0x2D 0x5A 3 0.151 0.500 107 19.1 0x2E 0x5C 4 0.181 0.597 133 29.4 0x2F 0x5E 5 0.210 0.694 113 30.1 0x30 0x60 6 0.240 0.791 137 43.2 0x31 0x62 7 0.268 0.885 102 37.4 0x32 0x64 8 0.303 0.999 115 49.9 0x33 0x66 9 0.344 1.137 102 53.6 0x34 0x68 10 0.389 1.284 115 73.2 0x35 0x6A 11 0.430 1.418 115 86.6 0x36 0x6C 12 0.476 1.572 56.2 51.1 0x37 0x6E 13 0.523 1.725 93.1 102 0x38 0x70 14 0.565 1.863 82.5 107 0x39 0x72 15 0.611 2.016 73.2 115 0x3A 0x74 16 0.677 2.236 57.6 121 0x3B 0x76 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 35 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com 8.6 Register Maps Table 11. Serial Control Bus Registers ADD (dec) ADD (hex) Register Name 0 0x00 I2C Device ID 1 0x01 Reset Bit(s) Register Type Default Function (hex) 7:1 RW Device ID 7-bit address of Deserializer See Table 9 0 RW ID Setting I2C ID Setting 1: Register I2C Device ID (Overrides IDx pin) 0: Device ID is from IDx pin 7 RW Remote Auto Power Down Remote Auto Power Down 1: Power down when no forward channel link is detected 0: Do not power down when no forward channel link is detected 0x04 6:3 2 36 0x02 Configuration [0] Descriptions Reserved 2 RW BC Enable Back channel enable 1: Enable 0: Disable 1 RW Digital RESET1 Reset the entire digital block including registers This bit is self-clearing. 1: Reset 0: Normal operation 0 RW Digital RESET0 Reset the entire digital block except registers This bit is self-clearing 1: Reset 0: Normal operation 7 RW Output Enable LVCMOS Output Enable. 1: Enable 0: Disable. Tri-state Outputs 6 RW OEN and OSS_SEL Override Overrides Output Enable Pin and Output State pin 1: Enable override 0: Disable - no override 5 RW OSC Clock Enable OSC Clock Output Enable If loss of lock OSC clock is output onto PCLK 0: Disable 1: Enable 4 RW Output Sleep State Select (OSS_SEL) OSS Select to Control Output State during Lock Low Period 1: Enable 0: Disable 3 RW Backward Compatible Mode Override Mode_Sel Backward compatible Mode Override Enable. 1: Use register bit "reg_02[2]" to set BC Mode 0: Use MODE_SEL option. 2 RW Backward Compatible Mode Select Backward Compatible Mode Select to DS90UR905Q and DS90UR907Q. If Reg_02[3] = 1 1: Backward Compatible is on 0: Backward Compatible is off 1 RW LFMODE Pin Override LFMODE Pin Override Enable 1: Use register bit "reg_02[0]" to set LFMODE 0: Use LFMODE Pin 0 RW LFMODE Low Frequency Mode Select 1: PCLK = 5 to <15 MHz 0: PCLK = 15 to 85 MHz 0x00 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Register Maps (continued) Table 11. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 3 0x03 Configuration [1] Bit(s) Register Type 7 6 Default Function (hex) 0xF0 Reserved RW CRC Generator Enable 4 RW Filter Enable HS, VS, DE two clock filter When enabled, pulses less than two full PCLK cycles on the DE, HS, and VS inputs will be rejected 1: Filtering enable 0: Filtering disable 3 RW I2C Passthrough I2C Pass-Through Mode 1: Pass-Through Enabled 0: Pass-Through Disabled 2 RW Auto ACK ACK Select 1: Auto ACK enable 0: Self ACK 0 RW RRFB Pixel Clock Edge Select 1: Parallel Interface Data is strobed on the Rising Clock Edge. 0: Parallel Interface Data is strobed on the Falling Clock Edge. 7:1 RW BCC Watchdog Timer The watchdog timer allows termination of a control channel transaction, if it fails to complete within a programmed amount of time. This field sets the Bidirectional Control Channel Watchdog Timeout value in units of 2 milliseconds. This field should not be set to 0 0 RW BCC Watchdog Timer Disable Disable Bidirectional Control Channel Watchdog Timer 1: Disables BCC Watchdog Timer operation 0: Enables BCC Watchdog Timer operation" 7 RW I2C Pass Through All I2C Pass-Through All Transactions 1: Enabled 0: Disabled 6:4 RW I2C SDA Hold Time Internal I2C SDA Hold Time It configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 50 ns. 3:0 RW I2C Filter Depth I2C Glitch Filter Depth It configures the maximum width of glitch pulses on the SCL and SDA inputs that will be rejected. Units are 5 ns. 5 5 0x04 0x05 BCC Watchdog Control I2C Control [1] CRC Generator Enable (Back Channel) 1: Enable 0: Disable Reserved 1 4 Descriptions Reserved 0xFE 0x2E Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 37 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com Register Maps (continued) Table 11. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 6 0x06 I2C Control [2] Bit(s) Register Type 7 R 6 RW Default Function (hex) 0x00 Forward Channel Sequence Error Control Channel Sequence Error Detected It indicates a sequence error has been detected in forward control channel. It this bit is set, an error may have occurred in the control channel operation. Clear Sequence Error It clears the Sequence Error Detect bit This bit is not self-clearing. 5 7 8 0x07 0x08 Remote Device ID SlaveID[0] Reserved 4:3 RW SDA Output SDA Output Delay Delay This field configures output delay on the SDA output. Setting this value will increase output delay in units of 50 ns. Nominal output delay values for SCL to SDA are: 00 : 250 ns 01: 300 ns 10: 350 ns 11: 400 ns 2 RW Local Write Disable Remote Writes to Local Registers through Serializer (Does not affect remote access to I2C slaves at Deserializer) 1: Stop remote write to local device registers 0: remote write to local device registers 1 RW I2C Bus Timer Speed Speed up I2C Bus Watchdog Timer 1: Timer expires after approximately 50 ms 0: Timer expires after approximately 1 s 0 RW I2C Bus Timer Disable Disable I2C Bus Timer When the I2C Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signalling occurs for approximately 1 s, the I2C bus is assumed to be free. If SDA is low and no signaling occurs, the device will try to clear the bus by driving 9 clocks on SCL 7:1 RW Remote ID Remote ID Configures the I2C Slave ID of the remote Serializer. A value of 0 in this field disables I2C access to remote Serializer. This field is automatically configured through the Serializer Forward Channel. Software may overwrite this value, but should also set the FREEZE DEVICE ID bit to prevent overwriting by the Forward Channel. 0 RW Freeze Device ID Freeze Serializer Device ID 1: Prevent auto-loading of the Serializer Device ID from the Forward Channel. The ID will be frozen at the value written. 0: Update 7:1 RW Target Slave Device ID0 7-bit Remote Slave Device ID 0 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID0, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. 0x18 0x00 0 9 0x09 SlaveID[1] 7:1 0 38 Descriptions Reserved RW 0x00 Target Slave Device ID1 7-bit Remote Slave Device ID 1 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID1, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. Reserved Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Register Maps (continued) Table 11. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 10 0x0A SlaveID[2] Bit(s) Register Type 7:1 RW Default Function (hex) 0x00 Target Slave Device ID2 0 11 0x0B SlaveID[3] 7:1 0x0C SlaveID[4] 7:1 RW 0x00 Target Slave Device ID3 0x0D SlaveID[5] 7:1 14 0x0E SlaveID[6] 7:1 15 0x0F SlaveID[7] 7:1 16 0x10 SlaveAlias[0] 7:1 7-bit Remote Slave Device ID 3 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID3, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. Reserved RW 0x00 Target Slave Device ID4 0 13 7-bit Remote Slave Device ID 2 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID2, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. Reserved 0 12 Descriptions 7-bit Remote Slave Device ID 4 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID4, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. Reserved RW 0x00 Target Slave Device ID5 RW 0x00 Target Slave Device ID6 RW 0x00 Target Slave Device ID7 RW 0x00 ID[0] Match 0 7-bit Remote Slave Device ID 5 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID5, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. Reserved 0 7-bit Remote Slave Device ID 6 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID6, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. Reserved 0 7-bit Remote Slave Device ID 7 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer. If an I2C transaction is addressed to the Slave Alias ID7, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. Reserved 0 7-bit Remote Slave Device Alias ID 0 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID0 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 39 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com Register Maps (continued) Table 11. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 17 0x11 SlaveAlias[1] Bit(s) Register Type 7:1 RW Default Function (hex) 0x00 ID[1] Match 0 18 0x12 SlaveAlias[2] 7:1 0x13 SlaveAlias[3] 7:1 RW 0x00 ID[2] Match 0x14 SlaveAlias[4] 7:1 21 0x15 SlaveAlias[5] 7:1 22 0x16 SlaveAlias[6] 23 0x17 SlaveAlias[7] RW 0x10 ID[3] Match 0x00 ID[4] Match RW 0x00 ID[5] Match 7:1 RW 0x00 ID[6] Match 0 RW 7:1 RW 0x00 ID[7] Match 0 7-bit Remote Slave Device Alias ID 4 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID4 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved 0 40 7-bit Remote Slave Device Alias ID 3 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID3 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved RW 0 7-bit Remote Slave Device Alias ID 2 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID2 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved 0 20 7-bit Remote Slave Device Alias ID 1 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID1 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved 0 19 Descriptions 7-bit Remote Slave Device Alias ID 5 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID5 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved 7-bit Remote Slave Device Alias ID 6 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID6 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved 7-bit Remote Slave Device Alias ID 7 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Serializer. The transaction will be remapped to the address specified in the Slave ID7 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Register Maps (continued) Table 11. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 28 0x1C General Status Bit(s) Register Type 7:4 RW 3 R Default Function (hex) 0x00 Reserved I2S Locked 2 30 0x1D 0x1E GPIO0 Config GPIO2 and GPIO1 Config I2S Lock Status 0: I2S PLL controller not locked 1: I2S PLL controller locked to input I2S clock Reserved 1 29 Descriptions Reserved 0 R Lock Deserializer CDR, PLL's clock to recovered clock frequency 1: Deserializer locked to recovered clock 0: Deserializer not locked 7:4 R Rev-ID Revision ID: 1010: Production Device 3 RW GPIO0 Output Value Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled. 2 RW GPIO0 Remote Enable Remote GPIO0 Control 1: Enable GPIO control from remote Serializer. The GPIO pin will be an output, and the value is received from the remote Deserializer. 0: Disable GPIO control from remote Serializer 1 RW GPIO0 Direction Local GPIO Direction 1: Input 0: Output 0 RW GPIO0 Enable GPIO Function Enable 1: Enable GPIO operation 0: Enable normal operation 7 RW GPIO2 Output Value Local GPIO Output Value This value is output on the GPIO when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled. 6 RW GPIO2 Remote Enable Remote GPIO2 Control 1: Enable GPIO control from remote Serializer. The GPIO pin will be an output, and the value is received from the remote Deserializer. 0: Disable GPIO control from remote Serializer. 5 RW GPIO2 Direction Local GPIO Direction 1: Input 0: Output 4 RW GPIO2 Enable GPIO Function Enable 1: Enable GPIO operation 0: Enable normal operation 3 RW GPIO1 Output Value Local GPIO Output Value This value is output on the GPIO when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled. 2 RW GPIO1 Remote Enable Remote GPIO1 Control 1: Enable GPIO control from remote Serializer. The GPIO pin will be an output, and the value is received from the remote Deserializer. 0: Disable GPIO control from remote Serializer. 1 RW GPIO1 Direction Local GPIO Direction 1: Input 0: Output 0 RW GPIO1 Enable GPIO Function Enable 1: Enable GPIO operation 0: Enable normal operation 0xA0 0x00 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 41 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com Register Maps (continued) Table 11. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 31 0x1F GPO_REG4 and GPO3 Config Bit(s) Register Type 7 RW Default Function (hex) 0x00 GPO_REG4 Local GPO_REG4 Output Value Output This value is output on the GPO when the GPO function is Value enabled, the local GPO direction is Output, and remote GPO control is disabled. 6:5 32 0x20 GPO_REG6 and GPO_REG5 Config Reserved 4 RW GPO_REG4 GPO_REG4 Function Enable Enable 1: Enable GPO operation 0: Enable normal operation 3 RW GPIO3 Output Value Local GPIO Output Value This value is output on the GPIO when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled. 2 RW GPIO3 Remote Enable Remote GPIO3 Control 1: Enable GPIO control from remote Serializer. The GPIO pin will be an output, and the value is received from the remote Deserializer. 0: Disable GPIO control from remote Serializer. 1 RW GPIO3 Direction Local GPIO Direction 1: Input 0: Output 0 RW GPIO3 Enable GPIO Function Enable 1: Enable GPIO operation 0: Enable normal operation 7 RW 0x00 6:5 0x21 GPO8 and GPO7 Config 4 RW GPO_REG6 GPO_REG6 Function Enable Enable 1: Enable GPO operation 0: Enable normal operation 3 RW GPO_REG5 Local GPO_REG5 Output Value Output This value is output on the GPO when the GPO function is Value enabled, the local GPO direction is Output, and remote GPO control is disabled. 0 RW GPO_REG5 GPO_REG5 Function Enable Enable 1: Enable GPO operation 0: Enable normal operation 7 RW Reserved 6:5 0x00 GPO_REG8 Local GPO_REG8 Output Value Output This value is output on the GPO when the GPO function is Value enabled, the local GPO direction is Output, and remote GPO control is disabled. Reserved 4 RW GPO_REG8 GPO_REG8 Function Enable Enable 1: Enable GPO operation 0: Enable normal operation 3 RW GPO_REG7 Local GPO_REG7 Output Value Output This value is output on the GPO when the GPO function is Value enabled, the local GPO direction is Output, and remote GPO control is disabled. RW GPO_REG7 GPO_REG7 Function Enable Enable 1: Enable GPO operation 0: Enable normal operation 2:1 0 42 GPO_REG6 Local GPO_REG6 Output Value Output This value is output on the GPO when the GPO function is Value enabled, the local GPO direction is Output, and remote GPO control is disabled. Reserved 2:1 33 Descriptions Reserved Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Register Maps (continued) Table 11. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name Bit(s) Register Type 34 0x22 Data Path Control 7 RW 6 RW Pass RGB Setting this bit causes RGB data to be sent independent of DE. This allows operation in systems which may not use DE to frame video data or send other data when DE is deasserted. Note that setting this bit blocks packetized audio. This bit does not need to be set in DS90UB925 or in Backward Compatibility mode. 1: Pass RGB independent of DE 0: Normal operation Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set. 5 RW DE Polarity This bit indicates the polarity of the DE (Data Enable) signal. 1: DE is inverted (active low, idle high) 0: DE is positive (active high, idle low) Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set. 4 RW I2S_Gen This bit controls whether the Receiver outputs packetized Auxiliary/Audio data on the RGB video output pins. 1: Don't output packetized audio data on RGB video output pins 0: Output packetized audio on RGB video output pins. Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set. 3 RW I2S Channel 1: Set I2S Channel B Enable from reg_22[0] B Enable 0: Set I2S Channel B Enable from MODE_SEL pin Override Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set. 2 RW 18-bit Video 1: Select 18-bit video mode Select 0: Select 24-bit video mode Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set. 1 RW I2S Transport Select 0 RW I2S Channel I2S Channel B Enable B Enable 1: Enable I2S Channel B on B1 output 0: I2S Channel B disabled Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set. 7 RW 35 0x23 General Purpose Control Default Function (hex) 0x00 0x10 Descriptions Override FC 1: Disable loading of this register from the forward channel, Config keeping locally written values intact 0: Allow forward channel loading of this register Rx RGB Checksum 6:5 1: Enable I2S Data Forward Channel Frame Transport 0: Enable I2S Data Island Transport Note: this bit is automatically loaded from the remote serializer unless bit 7 of this register is set. RX RGB Checksum Enable Setting this bit enables the Receiver to validate a one-byte checksum following each video line. Checksum failures are reported in the STS register Reserved 4 R Mode_Sel Mode Select is Done 3 R LFMODE Low Frequency Mode Status 2 R Repeater Repeater Mode Status 1 R Backward Backward Compatible Mode Status 0 R I2S Channel I2S Channel B Status B Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 43 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com Register Maps (continued) Table 11. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 36 0x24 BIST Control Bit(s) 7:4 Default Function (hex) 0x08 Descriptions Reserved 3 RW BIST Pin Config BIST Configured through Pin 1: BIST configured through pin 0: BIST configured through register bit 2:1 RW BIST Clock Source BIST Clock Source 00: External Pixel Clock 01: 33 MHz Oscillator 10: Reserved 11: 25 MHz Oscillator 0 RW BIST Enable BIST Control 1: Enabled 0: Disabled 37 0x25 BIST Error 7:0 R 0x00 BIST Error Count BIST Error Count 38 0x26 SCL High Time 7:0 RW 0x83 SCL High Time I2C Master SCL High Time This field configures the high pulse width of the SCL output when the Deserializer is the Master on the local I2C bus. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL high time with the internal oscillator clock running at 26 MHz rather than the nominal 20 MHz. 39 0x27 SCL Low Time 7:0 RW 0x84 SCL Low Time I2C SCL Low Time This field configures the low pulse width of the SCL output when the De-Serializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL low time with the internal oscillator clock running at 26 MHz rather than the nominal 20 MHz. 41 0x29 FRC Control 7 RW 0x00 Timing Mode Select Select display timing mode 0: DE only Mode 1: Sync Mode (VS,HS) 6 RW VS Polarity 0: Active High 1: Active Low 5 RW HS Polarity 0: Active High 1: Active Low 4 RW DE Polarity 0: Active High 1: Active Low 3 RW FRC2 Enable 0: FRC2 Disable 1: FRC2 Enable 2 RW FRC1 Enable 0: FRC1 Disable 1: FRC1 Enable 1 RW Hi-FRC 2 Disable 0: Hi-FRC2 Enable 1: Hi-FRC2 Disable 0 RW Hi-FRC 1 Disable 0: Hi-FRC1 Enable 1: Hi-FRC1 Disable 7:6 RW Page Setting 00: Configuration Registers 01: Red LUT 10: Green LUT 11: Blue LUT 5 RW White Balance Enable 0: White Balance Disable 1: White Balance Enable 4 RW LUT Reload 0: Reload Disable Enable 1: Reload Enable 42 0x2A White Balance Control 3:0 44 Register Type 0x00 Reserved Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Register Maps (continued) Table 11. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 43 0x2B I2S Control Bit(s) Register Type 7 RW Default Function (hex) 0x00 I2S PLL 6:1 0 44 58 0x2C 0x3A SSCG Control I2S MCLK Output 0x41 Link Error Count I2S PLL Control 0: I2S PLL is on for I2S data jitter cleaning 1: I2S PLL is off. No jitter cleaning Reserved RW 7:4 I2S Clock Edge 0x00 I2S Clock Edge Select 0: I2S Data is strobed on the Rising Clock Edge 1: I2S Data is strobed on the Falling Clock Edge Reserved 3 RW SSCG Enable Enable Spread Spectrum Clock Generator 0: Disable 1: Enable 2:0 RW SSCG Selection SSCG Frequency Deviation: When LFMODE = H fdev fmod 000: 0.7 CLK/628 001: 1.3 010: 1.8 011: 2.5 100: 0.7 CLK/388 101: 1.2 110: 2 111: 2.5 When LFMODE = L fdev fmod 000: 0.9 CLK/2168 001: 1.2 010: 1.9 011: 2.5 100: 0.7 CLK/1300 101: 1.3 110: 2 111: 2.5 7 RW MCLK Override 1: Override divider select for MCLK 0: No override for MCLK divider 6:4 RW MCLK Frequency Select See Table 5 0x00 3:0 65 Descriptions Reserved 7:5 0x03 Reserved 4 RW Link Error Count Enable Enable serial link data integrity error count 1: Enable error count 0: Disable 3:0 RW Link Error Count Link error count threshold. Counter is pixel clock based. clk0, clk1 and DCA are monitored for link errors, if error count is enabled, deserializer loose lock once error count reaches threshold. If disabled deserilizer loose lock with one error. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 45 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com Register Maps (continued) Table 11. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 68 0x44 Equalization Bit(s) Register Type 7:5 RW Default Function (hex) 0x60 EQ Stage 1 Select 4 86 0x56 CML Output Reserved RW EQ Stage 2 Select EQ select value. Used if adaptive EQ is bypassed. 000 Min EQ 2nd Stage 001 010 011 100 101 110 111 Max EQ 2nd Stage 0 RW Adaptive EQ 1: Disable adaptive EQ (to write EQ select values) 0: Enable adaptive EQ 7:4 0x08 RW Reserved CMLOUT+/- 1: Disabled (Default) Enable 0: Enabled 2:0 0x64 Pattern Generator Control 7:4 Reserved RW 0x10 Pattern Generator Select 3:1 0 46 EQ select value. Used if adaptive EQ is bypassed. 000 Min EQ 1st Stage 001 010 011 100 101 110 111 Max EQ 1st Stage 3:1 3 100 Descriptions Fixed Pattern Select This field selects the pattern to output when in Fixed Pattern Mode. Scaled patterns are evenly distributed across the horizontal or vertical active regions. This field is ignored when Auto-Scrolling Mode is enabled. The following table shows the color selections in non-inverted followed by inverted color mode 0000: Reserved 0001: White/Black 0010: Black/White 0011: Red/Cyan 0100: Green/Magenta 0101: Blue/Yellow 0110: Horizontally Scaled Black to White/White to Black 0111: Horizontally Scaled Black to Red/Cyan to White 1000: Horizontally Scaled Black to Green/Magenta to White 1001: Horizontally Scaled Black to Blue/Yellow to White 1010: Vertically Scaled Black to White/White to Black 1011: Vertically Scaled Black to Red/Cyan to White 1100: Vertically Scaled Black to Green/Magenta to White 1101: Vertically Scaled Black to Blue/Yellow to White 1110: Custom color (or its inversion) configured in PGRS, PGGS, PGBS registers 1111: Reserved Reserved RW Pattern Generator Enable Pattern Generator Enable 1: Enable Pattern Generator 0: Disable Pattern Generator Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 Register Maps (continued) Table 11. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 101 0x65 Pattern Generator Configuration Bit(s) Register Type 7:5 Default Function (hex) 0x00 Descriptions Reserved 4 RW Pattern Generator 18 Bits 18-bit Mode Select 1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels of brightness and the R, G, and B outputs use the six most significant color bits. 0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of brightness. 3 RW Pattern Generator External Clock Select External Clock Source 1: Selects the external pixel clock when using internal timing. 0: Selects the internal divided clock when using internal timing This bit has no effect in external timing mode (PATGEN_TSEL = 0). 2 RW Pattern Generator Timing Select Timing Select Control 1: The Pattern Generator creates its own video timing as configured in the Pattern Generator Total Frame Size, Active Frame Size. Horizontal Sync Width, Vertical Sync Width, Horizontal Back Porch, Vertical Back Porch, and Sync Configuration registers. 0: the Pattern Generator uses external video timing from the pixel clock, Data Enable, Horizontal Sync, and Vertical Sync signals. 1 RW Pattern Generator Color Invert Enable Inverted Color Patterns 1: Invert the color output. 0: Do not invert the color output. 0 RW Pattern Generator Auto-Scroll Enable Auto-Scroll Enable: 1: The Pattern Generator will automatically move to the next enabled pattern after the number of frames specified in the Pattern Generator Frame Time (PGFT) register. 0: The Pattern Generator retains the current pattern. 102 0x66 Pattern Generator Indirect Address 7:0 RW 0x00 Indirect Address This 8-bit field sets the indirect address for accesses to indirectly-mapped registers. It should be written prior to reading or writing the Pattern Generator Indirect Data register. See AN-2198 Exploring Int Test Patt Gen Feat of 720p FPD-Link III Devices (SNLA132) 103 0x67 Pattern Generator Indirect Data 7:0 RW 0x00 Indirect Data When writing to indirect registers, this register contains the data to be written. When reading from indirect registers, this register contains the read back value. See AN-2198 Exploring Int Test Patt Gen Feat of 720p FPD-Link III Devices (SNLA132) 240 0xF0 RX ID 7:0 R 0x5F ID0 First byte ID code: _ 241 0xF1 7:0 R 0x55 ID1 Second byte of ID code: U 242 0xF2 7:0 R 0x48 ID2 Third byte of ID code, Value will be either B. 243 0xF3 7:0 R 0x39 ID3 Fourth byte of ID code: 9 244 0xF4 7:0 R 0x32 ID4 Fifth byte of ID code: 2 245 0xF5 7:0 R 0x36 ID5 Sixth byte of ID code: 6 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 47 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The DS90UB926Q-Q1, in conjunction with the DS90UB925Q-Q1, is intended for interface between a host (graphics processor) and a display. It supports an 24-bit color depth (RGB888) and high definition (720p) digital video format. The device allows to receive a three 8-bit RGB stream with a pixel rate up to 85 MHz together with three control bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192 kHz. 9.1.1 Display Application The deserializer is expected to be located close to its target device. The interconnect between the deserializer and the target device is typically in the 1-inch to 3-inch separation range. The input capacitance of the target device is expected to be in the 5- to 10-pF range. Care should be taken on the PCLK output trace as this signal is edge sensitive and strobes the data. It is also assumed that the fanout of the deserializer is up to three in the repeater mode. If additional loads need to be driven, TI recommends a logic buffer or multiplexer (mux) device. 48 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 9.2 Typical Application DS90UB926Q-Q1 3.3V 3.3V/1.8V VDDIO VDD33_A FB1 C6 FB2 C4 VDDIO VDD33_B C7 C5 VDDIO C8 CAPP12 C9 CAPR12 C13 CAPI2S PASS C10 LOCK CAPL12 C11 C12 C1 Serial FPD-Link III Interface RIN+ RINC2 CMF C3 CMLOUTP 100: VDD33_B* R5 CMLOUTN OSS_SEL OEN BISTEN BISTC / INTB_IN PDB Host Control C14 4.7k 4.7k VDD33_B VDD33_B SDA SCL R1 ID[X] R2 VDD33_B R3 MODE_SEL R4 ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 ROUT6 ROUT7 ROUT8 ROUT9 ROUT10 ROUT11 ROUT12 ROUT13 ROUT14 ROUT15 LVCMOS Parallel Video / Audio Interface ROUT16 ROUT17 ROUT18 ROUT19 ROUT20 ROUT21 ROUT22 ROUT23 HS VS DE PCLK I2S_CLK I2S_WC I2S_DA MCLK NC RES 3 DAP (GND) FB1 FB2: Impedance = 1 k: @ 100 MHz, Low DC resistance (<1:) C1 C3 = 0.1 PF (50 WV; C1, C2: 0402; C3: 0603) C4 C13 = 4.7 PF C14 =>10 PF R1 and R2 (see IDx Resistor Values Table 8) R3 and R4 (see MODE_SEL Resistor Values Table 4) R5 = 10 k: * or VDDIO = 3.3V+0.3V Figure 24. Typical Connection Diagram Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 49 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com Typical Application (continued) VDDIO VDD33 (3.3V) (1.8V or 3.3V) HOST Graphics Processor RGB Digital Display Interface VDDIO VDD33 (1.8V or 3.3V) (3.3V) R[7:0] G[7:0] B[7:0] HS VS DE PCLK DOUT+ RIN+ DOUT- RIN- 100: STP Cable DS90UB925Q Serializer PDB I2S AUDIO (STEREO) R[7:0] G[7:0] B[7:0] HS VS DE PCLK FPD-Link III 1 Pair / AC Coupled 0.1 PF 0.1 PF 3 MODE_SEL INTB SCL SDA IDx PDB OSS_SEL OEN MODE_SEL DS90UB926Q Deserializer I2S AUDIO (STEREO) MCLK SCL SDA IDx DAP LOCK PASS 3 INTB_IN RGB Display 720p 24-bit color depth DAP Figure 25. Typical Display System Diagram Figure 24 shows a typical application of the DS90UB926Q-Q1 deserializer for an 85 MHz, 24-bit color display application. Inputs use 0.1-F coupling capacitors to the line and the deserializer provides internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1-F capacitors and two 4.7F capacitors should be used for local device bypassing. Ferrite beads are placed on the power lines for effective noise suppression. Since the device in the Pin/STRAP mode, two 10-k pullup resistors are used on the parallel output bus to select the desired device features. The interface to the target display is with 3.3-V LVCMOS levels, thus the VDDIO pins are connected to the 3.3-V rail. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable. 9.2.1 Design Requirements For the typical design application, use the following as input parameters. Table 12. Design Parameters DESIGN PARAMETER EXAMPLE VALUE VDDIO 1.8 V or 3.3 V VDD33 3.3 V AC-coupling capacitor for RIN 100 nF PCLK frequency 78 MHz 9.2.2 Detailed Design Procedure 9.2.2.1 Transmission Media The DS90UB925Q-Q1 and DS90UB926Q-Q1 chipset is intended to be used in a point-to-point configuration through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer should have a differential impedance of 100 . The maximum length of cable that can be used is dependant on the quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical environment (for example, power stability, ground noise, input clock jitter, PCLK frequency, etc.) and the application environment. 50 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define the acceptable data eye-opening width and eye-opening height. A differential probe should be used to measure across the termination resistor at the CMLOUTP/N pin Figure 2. 78 MHz TX Pixel Clock Input (500 mV/DIV) Magnitude (80 mV/DIV) CML Serializer Data Throughput (200 mV/DIV) 9.2.3 Application Curves Time (100 ps/DIV) Time (2.5 ns/DIV) Figure 26. Deserializer CMLOUT Eye Diagram With 78 MHz TX Pixel Clock Figure 27. Deserializer FPD-Link III Input With 78-MHz TX Pixel Clock 10 Power Supply Recommendations 10.1 Power Up Requirements and PDB Pin When VDDIO and VDD33_X are powered separately, the VDDIO supply (1.8 V or 3.3 V) must ramp 100 s before the other supply (VDD33_X) begins to ramp. If VDDIO is tied with VDD33_X, both supplies may ramp at the same time. The VDDs (VDD33_X and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. A large capacitor on the PDB pin is required to ensure PDB arrives after all the VDDs have settled to the recommended operating voltage. When PDB pin is pulled to VDDIO = 3 V to 3.6 V or VDD33_X, TI recommends using a 10-k pullup and a > 10-F capacitor to GND to delay the PDB input signal. All inputs must not be driven until VDD33_X and VDDIO has reached its steady-state value. < 1.5 ms 1.8 V or 3.3 V VDDIO 100 s 3.3 V VDD33_X < 1.5 ms 3.3 V PDB PDB starts to ramp after all supplies have settled Figure 28. Power-Up Sequence of DS90UB926Q-Q1 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 51 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com 11 Layout 11.1 Layout Guidelines Design the circuit board layout and stack-up for the FPD-Link III devices to provide low-noise power feed to the device. Good layout practice separates high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback, and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 F to 0.1 F. Tantalum capacitors may be in the 2.2-F to 10-F range. Voltage rating of the tantalum capacitors should be at least 5x the power supply voltage being used. TI recommends surface-mount capacitors due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50-F to 100-F range and will smooth low-frequency switching noise. TI recommends connecting power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor increases the inductance of the path. TI recommends a small body size X7R chip capacitor, such as 0603 or 0402, for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs. Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 are typically recommended for CML interconnect. The closely coupled lines help to ensure that coupled noise appears as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less. Information on the WQFN style package is provided in AN-1187 Leadless Leadframe Package (LLP) (SNOA401). Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Table 13: Table 13. No Pullback WQFN Stencil Aperture Summary DEVICE PIN COUNT MKT DWG PCB I/O PCB PITCH PAD SIZE (mm) (mm) DS90UB926Q-Q1 60 NKB0060B 0.25 x 0.6 0.5 PCB DAP SIZE (mm) STENCIL I/O APERTURE (mm) STENCIL DAP APERTURE (mm) NUMBER of DAP APERTURE OPENINGS 6.3 x 6.3 0.25 x 0.8 6.3 x 6.3 1 Figure 29 shows the PCB layout example derived from the layout design of the DS90UB926QSEVB evaluation board. The graphic and layout description are used to determine both proper routing and proper solder techniques when designing the Serializer board. 52 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 11.1.1 CML Interconnect Guidelines See Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and AN-905 Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for full details. * Use 100- coupled differential pairs * Use the S/2S/3S rule in spacings - S = space between the pair - 2S = space between pairs - 3S = space to LVCMOS signal * Minimize the number of Vias * Use differential connectors when operating above 500-Mbps line speed * Maintain balance of the traces * Minimize skew within the pair Additional general guidance can be found in the LVDS Owner's Manual - available in PDF format from the TI web site at: www.ti.com/lvds. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 53 DS90UB926Q-Q1 SNLS422D - JULY 2012 - REVISED AUGUST 2017 www.ti.com 11.2 Layout Examples Length-Matched RGB Output Traces AC Capacitors NKB0060B High-Speed Traces Figure 29. DS90UB926Q-Q1 Serializer Example Layout Figure 30. 60-Pin WQFN Stencil Example of Via and Opening Placement 54 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 DS90UB926Q-Q1 www.ti.com SNLS422D - JULY 2012 - REVISED AUGUST 2017 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: * AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) * AN-905 Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035) * AN-1187 Leadless Leadframe Package (LLP) (SNOA401) * LVDS Owner's Manual (SNLA187) 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: DS90UB926Q-Q1 55 PACKAGE OPTION ADDENDUM www.ti.com 3-Aug-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) DS90UB926QSQ/NOPB ACTIVE WQFN NKB 60 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB926QSQ DS90UB926QSQE/NOPB ACTIVE WQFN NKB 60 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB926QSQ DS90UB926QSQX/NOPB ACTIVE WQFN NKB 60 2000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB926QSQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 3-Aug-2017 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS90UB926QSQ/NOPB WQFN NKB 60 DS90UB926QSQE/NOPB WQFN NKB DS90UB926QSQX/NOPB WQFN NKB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 60 250 178.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 60 2000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90UB926QSQ/NOPB WQFN NKB 60 1000 367.0 367.0 38.0 DS90UB926QSQE/NOPB WQFN NKB 60 250 210.0 185.0 35.0 DS90UB926QSQX/NOPB WQFN NKB 60 2000 367.0 367.0 38.0 Pack Materials-Page 2 PACKAGE OUTLINE NKB0060B VQFN - 0.8 mm max height SCALE 1.500 PLASTIC QUAD FLATPACK - NO LEAD 9.1 8.9 B A PIN 1 INDEX AREA 9.1 8.9 0.8 0.7 C SEATING PLANE 0.05 0.00 0.08 C 2X 7 6.3 0.1 EXPOSED THERMAL PAD SYMM 16 15 31 SYMM 61 2X 7 1 56X 0.5 PIN 1 ID (0.1) TYP 30 45 60 46 0.7 60X 0.5 60X 0.3 0.2 0.1 0.05 C A B 4214995/A 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT NKB0060B VQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 6.3) SYMM 60X (0.8) 46 60 SEE SOLDER MASK DETAIL 60X (0.25) 1 45 56X (0.5) (1.1) TYP (1.2) TYP (R0.05) TYP ( 0.2) TYP VIA SYMM 61 (0.6) TYP 15 (8.6) 31 16 30 (0.6) TYP (1.2) TYP (1.1) TYP (8.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 8X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND METAL UNDER SOLDER MASK METAL EDGE EXPOSED METAL SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4214995/A 03/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN NKB0060B VQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD 25X ( 1) (1.2) TYP 60X (0.8) 60 46 60X (0.25) 1 45 56X (0.5) (R0.05) TYP (1.2) TYP 61 SYMM (8.6) 15 31 30 16 SYMM (8.6) SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 8X EXPOSED PAD 61 63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE 4214995/A 03/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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