INTEGRATED CIRCUITS 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA + 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33 MHz) Product specification Supersedes data of 1998 Jun 04 IC20 Data Handbook 1999 Apr 01 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33 MHz) DESCRIPTION FEATURES * 80C51 Central Processing Unit * Speed up to 33MHz * Full static operation * Operating voltage range: 2.7V to 5.5V @ 16MHz * Security bits: Three different Single-Chip 8-Bit Microcontroller families are presented in this datasheet: * 80C32/8XC52/8XC54/8XC58 * 80C51FA/8XC51FA/8XC51FB/8XC51FC * 80C51RA+/8XC51RA+/8XC51RB+/8XC51RC+/8XC51RD+ For applications requiring 4K ROM/EPROM, see the 8XC51/80C31 8-bit CMOS (low voltage, low power, and high speed) microcontroller families datasheet. - ROM - 2 bits - OTP-EPROM - 3 bits * Encryption array - 64 bytes * RAM expandable to 64K bytes * 4 level priority interrupt * 6 or7 interrupt sources, depending on device * Four 8-bit I/O ports * Full-duplex enhanced UART All the families are Single-Chip 8-Bit Microcontrollers manufactured in advanced CMOS process and are derivatives of the 80C51 microcontroller family. All the devices have the same instruction set as the 80C51. These devices provide architectural enhancements that make them applicable in a variety of applications for general control systems. ROM/EPROM Memory Size (X by 8) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ RAM Size (X by 8) Programmable Timer Counter (PCA) Hardware Watch Dog Timer - Framing error detection - Automatic address recognition 80C31/8XC51 0K/4K 128 No * Power control modes No - Clock can be stopped and resumed 80C32/8XC52/54/58 0K/8K/16K/32K - Idle mode 256 No No - Power down mode * Programmable clock out * Second DPTR register * Asynchronous port reset * Low EMI (inhibit ALE) 80C51FA/8XC51FA/FB/FC 0K/8K/16K/32K 256 Yes No 512 Yes Yes 1024 Yes Yes 80C51RA+/8XC51RA+/RB+/RC+ 0K/8K/16K/32K 8XC51RD+ 64K The ROMless devices, 80C32, 80C51FA, and 80C51RA+ can address up to 64K of external memory. All the devices have four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. For systems that require extra memory capability up to 64k bytes, each can be expanded using standard TTL-compatible memories and logic. Its added features make it an even more powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multiprocessor communications. 1999 Apr 01 2 853-2068 21142 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33 MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ BLOCK DIAGRAM P0.0-P0.7 P2.0-P2.7 PORT 0 DRIVERS PORT 2 DRIVERS VCC VSS RAM ADDR REGISTER PORT 0 LATCH RAM PORT 2 LATCH ROM/EPROM 8 B REGISTER STACK POINTER ACC PROGRAM ADDRESS REGISTER TMP1 TMP2 BUFFER ALU SFRs TIMERS PSW PC INCREMENTER P.C.A. (FA & RA+ only) 8 16 PSEN ALE/PROG EAVPP TIMING AND CONTROL RST INSTRUCTION REGISTER PROGRAM COUNTER PD DPTR'S MULTIPLE PORT 1 LATCH PORT 3 LATCH PORT 1 DRIVERS PORT 3 DRIVERS P1.0-P1.7 P3.0-P3.7 OSCILLATOR XTAL1 XTAL2 SU00831B 1999 Apr 01 3 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33 MHz) LOGIC SYMBOL 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS VCC 6 VSS XTAL1 PORT 0 DATA BUS LCC 17 PORT 1 RST EA/VPP Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PORT 2 ADDRESS BUS SU00830 PIN CONFIGURATIONS 39 P0.0/AD0 ECI/P1.2 3 38 P0.1/AD1 CEX0/P1.3 4 37 P0.2/AD2 CEX1/P1.4 5 36 P0.3/AD3 CEX2/P1.5 6 35 P0.4/AD4 CEX3/P1.6 7 34 P0.5/AD5 CEX4/P1.7 8 33 P0.6/AD6 RST 9 32 P0.7/AD7 TxD/P3.1 11 DUAL IN-LINE PACKAGE INT1/P3.3 13 28 P2.7/A15 T0/P3.4 14 27 P2.6/A14 T1/P3.5 15 26 P2.5/A13 WR/P3.6 16 25 P2.4/A12 RD/P3.7 17 24 P2.3/A11 XTAL2 18 23 P2.2/A10 XTAL1 19 22 P2.1/A9 VSS 20 21 P2.0/A8 Function P2.7/A15 PSEN ALE/PROG NIC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC SU00023 34 33 PQFP 11 23 12 30 ALE/PROG 29 PSEN Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 31 EA/VPP INT0/P3.2 12 Function P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 44 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 * NO INTERNAL CONNECTION SU00021 1999 Apr 01 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PLASTIC QUAD FLAT PACK PIN FUNCTIONS 40 VCC T2EX/P1.1 2 Function NIC* P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 28 * NO INTERNAL CONNECTION DUAL IN-LINE PACKAGE PIN FUNCTIONS T2/P1.0 1 29 18 ALE/PROG PORT 3 SECONDARY FUNCTIONS PSEN 39 ADDRESS AND T2 T2EX RxD/P3.0 10 40 7 XTAL2 RxD TxD INT0 INT1 T0 T1 WR RD 1 4 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 22 Function VSS NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG NIC* EA/VPP P0.7/AD7 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC NIC* P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 SU00024 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33 MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ PIN DESCRIPTIONS PIN NUMBER MNEMONIC DIP LCC QFP TYPE VSS 20 22 16 I Ground: 0V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. 39-32 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and received code bytes during EPROM programming. External pull-ups are required during program verification. 1-8 2-9 40-44, 1-3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the low-order address byte during program memory verification. 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 40 41 42 43 44 1 2 3 I/O I I I/O I/O I/O I/O I/O P2.0-P2.7 21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive the high order address bits during EPROM programming and verification. P3.0-P3.7 10-17 11, 13-19 5, 7-13 I/O 10 11 12 13 14 15 16 17 11 13 14 15 16 17 18 19 5 7 8 9 10 11 12 13 I O I I I I O O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. ALE/PROG 30 33 27 O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. P0.0-0.7 P1.0-P1.7 1999 Apr 01 NAME AND FUNCTION Alternate functions for 8XC51FX and 8XC51RX+ Port 1 include: T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out) T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control ECI (P1.2): External Clock Input to the PCA CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 5 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33 MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ PIN DESCRIPTIONS (Continued) PIN NUMBER MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA/VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations starting with 0000H. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 8k Devices (IFFFH), 16k Devices (3FFFH) or 32k Devices (7FFFH). Since the RD+ has 64k Internal Memory, the RD+ will execute only from internal memory when EA is held high. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. If security bit 1 is programmed, EA will be internally latched on Reset. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS - 0.5V, respectively. 1999 Apr 01 6 MEMORY SIZE 16K x 8 MEMORY SIZE 32K x 8 7 P80C52SBPN P80C54SBPN P80C58SBPN OTP P87C52SBPN P87C54SBPN P87C58SBPN ROM P80C52SBAA P80C54SBAA P80C58SBAA OTP P87C52SBAA P87C54SBAA P87C58SBAA ROM P80C52SBBB P80C54SBBB P80C58SBBB OTP P87C52SBBB P87C54SBBB P87C58SBBB ROM P80C52SFP N P80C54SFP N P80C58SFP N OTP P87C52SFP N P87C54SFP N P87C58SFP N ROM P80C52SFA A P80C54SFA A P80C58SFA A OTP P87C52SFA A P87C54SFA A P87C58SFA A ROM P80C52SFB B P80C54SFB B P80C58SFB B OTP P87C52SFB B P87C54SFB B P87C58SFB B ROM P80C52UBAA P80C54UBAA P80C58UBAA OTP P87C52UBAA P87C54UBAA P87C58UBAA ROM P80C52UBPN P80C54UBPN P80C58UBPN OTP P87C52UBPN P87C54UBPN P87C58UBPN ROM P80C52UBBB P80C54UBBB P80C58UBBB OTP P87C52UBBB P87C54UBBB P87C58UBBB ROM P80C52UFA A P80C54UFA A P80C58UFA A OTP P87C52UFA A P87C54UFA A P87C58UFA A ROM P80C52UFPN P80C54UFPN P80C58UFPN OTP P87C52UFPN P87C54UFPN P87C58UFPN ROM P80C52UFBB P80C54UFBB P80C58UFBB OTP P87C52UFBB P87C54UFBB P87C58UFBB VOLTAGE RANGE FREQ. (MHz) DWG. # P80C32SBPN line Package 0 to +70 +70, Plastic Dual In In-line 2 7V to 5.5V 5 5V 2.7V 0 to 16 SOT129 1 SOT129-1 P80C32SBAA 0 to +70, +70 Plastic Leaded Chip Carrier 2 7V to 5.5V 2.7V 5 5V 0 to 16 SOT187 2 SOT187-2 P80C32SBBB +70 Plastic Quad Flat Pack 0 to +70, 2 7V to 5.5V 5 5V 2.7V 0 to 16 SOT307 2 SOT307-2 P80C32SFP N -40 40 to +85 +85, Plastic Dual In In-line line Package 2 7V to 5.5V 2.7V 5 5V 0 to 16 SOT129 1 SOT129-1 P80C32SFA A 40 to +85, +85 Plastic Leaded Chip Carrier -40 2 7V to 5.5V 5 5V 2.7V 0 to 16 SOT187 2 SOT187-2 P80C32SFB B -40 40 to +85 +85, Plastic Quad Flat Pack 2 7V to 5.5V 2.7V 5 5V 0 to 16 SOT307 2 SOT307-2 P80C32UBAA +70 Plastic Leaded Chip Carrier 0 to +70, 5V 0 to 33 SOT187 2 SOT187-2 P80C32UBPN 0 to +70 +70, Plastic Dual In In-line line Package 5V 0 to 33 SOT129 1 SOT129-1 P80C32UBBB +70 Plastic Quad Flat Pack 0 to +70, 5V 0 to 33 SOT307 2 SOT307-2 P80C32UFA A -40 40 to +85, +85 Plastic Leaded Chip Carrier 5V 0 to 33 SOT187 2 SOT187-2 P80C32UFPN 40 to +85 line Package -40 +85, Plastic Dual In In-line 5V 0 to 33 SOT129 1 SOT129-1 P80C32UFBB -40 40 to +85 +85, Plastic Quad Flat Pack 5V 0 to 33 SOT307 2 SOT307-2 Note: For Multi Time Programmable devices, See P89C51RX+ Flash datasheet. Product specification 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ ROM TEMPERATURE RANGE C AND PACKAGE ROMless Philips Semiconductors MEMORY SIZE 8K x 8 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 1999 Apr 01 8XC52/54/58 AND 80C32 ORDERING INFORMATION MEMORY SIZE 32K x 8 ROM P83C51FA-4N P83C51FB-4N P83C51FC-4N OTP P87C51FA-4N P87C51FB-4N P87C51FC-4N ROM P83C51FA-4A P83C51FB-4A P83C51FC-4A OTP P87C51FA-4A P87C51FB-4A P87C51FC-4A ROM P83C51FA-4B P83C51FB-4B P83C51FC-4B OTP P87C51FA-4B P87C51FB-4B P87C51FC-4B ROM P83C51FA-5N P83C51FB-5N P83C51FC-5N OTP P87C51FA-5N P87C51FB-5N P87C51FC-5N ROM P83C51FA-5A P83C51FB-5A P83C51FC-5A OTP P87C51FA-5A P87C51FB-5A P87C51FC-5A ROM P83C51FA-5B P83C51FB-5B P83C51FC-5B OTP P87C51FA-5B P87C51FB-5B P87C51FC-5B ROM P83C51FA-IN P83C51FB-IN P83C51FC-IN OTP P87C51FA-IN P87C51FB-IN P87C51FC-IN ROM P83C51FA-IA P83C51FB-IA P83C51FC-IA OTP P87C51FA-IA P87C51FB-IA P87C51FC-IA ROM P83C51FA-IB P83C51FB-IB P83C51FC-IB OTP P87C51FA-IB P87C51FB-IB P87C51FC-IB ROM P83C51FA-JN P83C51FB-JN P83C51FC-JN OTP P87C51FA-JN P87C51FB-JN P87C51FC-JN ROM P83C51FA-JA P83C51FB-JA P83C51FC-JA OTP P87C51FA-JA P87C51FB-JA P87C51FC-JA ROM P83C51FA-JB P83C51FB-JB P83C51FC-JB OTP P87C51FA-JB P87C51FB-JB P87C51FC-JB ROMless TEMPERATURE RANGE C AND PACKAGE VOLTAGE RANGE FREQ. (MHz) DWG. # P80C51FA 4N P80C51FA-4N Pin Plastic Dual In line Pkg 0 to +70 +70, 40 40-Pin In-line Pkg. 2 7V to 5.5V 5 5V 2.7V 0 to 16 SOT129 1 SOT129-1 P80C51FA 4A P80C51FA-4A 0 to +70 +70, 44 44-Pin Pin Plastic Leaded Chip Carrier 2 7V to 5.5V 2.7V 5 5V 0 to 16 SOT187 2 SOT187-2 P80C51FA 4B P80C51FA-4B Pin Plastic Quad Flat Pack 0 to +70 +70, 44 44-Pin 2 7V to 5.5V 5 5V 2.7V 0 to 16 SOT307 2 SOT307-2 P80C51FA 5N P80C51FA-5N -40 40 to +85, +85 40-Pin 40 Pin Plastic Dual In-line In line Pkg. Pkg 2 7V to 5.5V 2.7V 5 5V 0 to 16 SOT129 1 SOT129-1 P80C51FA 5A P80C51FA-5A 40 to +85 Pin Plastic Leaded Chip Carrier -40 +85, 44 44-Pin 2 7V to 5.5V 5 5V 2.7V 0 to 16 SOT187 2 SOT187-2 P80C51FA 5B P80C51FA-5B -40 40 to +85 +85, 44 44-Pin Pin Plastic Quad Flat Pack 2 7V to 5.5V 2.7V 5 5V 0 to 16 SOT307 2 SOT307-2 P80C51FA IN P80C51FA-IN Pin Plastic Dual In line Pkg 0 to +70 +70, 40 40-Pin In-line Pkg. 5V 0 to 33 SOT129 1 SOT129-1 P80C51FA IA P80C51FA-IA 0 to +70 +70, 44 44-Pin Pin Plastic Leaded Chip Carrier 5V 0 to 33 SOT187 2 SOT187-2 P80C51FA IB P80C51FA-IB 0 to +70 +70, 44 44-Pin Pin Plastic Quad Flat Pack 5V 0 to 33 SOT307 2 SOT307-2 P80C51FA JN P80C51FA-JN -40 40 to +85, +85 40-Pin 40 Pin Plastic Dual In-line In line Pkg. Pkg 5V 0 to 33 SOT129 1 SOT129-1 P80C51FA JA P80C51FA-JA -40 40 to +85 +85, 44 44-Pin Pin Plastic Leaded Chip Carrier 5V 0 to 33 SOT187 2 SOT187-2 P80C51FA JB P80C51FA-JB -40 40 to +85 +85, 44 44-Pin Pin Plastic Quad Flat Pack 5V 0 to 33 SOT307 2 SOT307-2 Note: For Multi Time Programmable devices, See P89C51RX+ Flash datasheet. Product specification 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ MEMORY SIZE 16K x 8 Philips Semiconductors 8 MEMORY SIZE 8K x 8 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 1999 Apr 01 8XC51FA/FB/FC AND 80C51FA ORDERING INFORMATION MEMORY SIZE 32K x 8 MEMORY SIZE 64K x 8 ROM P83C51RA+4N P83C51RB+4N P83C51RC+4N P83C51RD+4N OTP P87C51RA+4N P87C51RB+4N P87C51RC+4N P87C51RD+4N ROM P83C51RA+4A P83C51RB+4A P83C51RC+4A P83C51RD+4A OTP P87C51RA+4A P87C51RB+4A P87C51RC+4A P87C51RD+4A ROM P83C51RA+4B P83C51RB+4B P83C51RC+4B P83C51RD+4B OTP P87C51RA+4B P87C51RB+4B P87C51RC+4B P87C51RD+4B ROM P83C51RA+5N P83C51RB+5N P83C51RC+5N P83C51RD+5N OTP P87C51RA+5N P87C51RB+5N P87C51RC+5N P87C51RD+5N ROM P83C51RA+5A P83C51RB+5A P83C51RC+5A P83C51RD+5A OTP P87C51RA+5A P87C51RB+5A P87C51RC+5A P87C51RD+5A ROM P83C51RA+5B P83C51RB+5B P83C51RC+5B P83C51RD+5B OTP P87C51RA+5B P87C51RB+5B P87C51RC+5B P87C51RD+5B ROM P83C51RA+IN P83C51RB+IN P83C51RC+IN P83C51RD+IN OTP P87C51RA+IN P87C51RB+IN P87C51RC+IN P87C51RD+IN ROM P83C51RA+IA P83C51RB+IA P83C51RC+IA P83C51RD+IA OTP P87C51RA+IA P87C51RB+IA P87C51RC+IA P87C51RD+IA ROM P83C51RA+IB P83C51RB+IB P83C51RC+IB P83C51RD+IB OTP P87C51RA+IB P87C51RB+IB P87C51RC+IB P87C51RD+IB ROM P83C51RA+JN P83C51RB+JN P83C51RC+JN P83C51RD+JN OTP P87C51RA+JN P87C51RB+JN P87C51RC+JN P87C51RD+JN ROM P83C51RA+JA P83C51RB+JA P83C51RC+JA P83C51RD+JA OTP P87C51RA+JA P87C51RB+JA P87C51RC+JA P87C51RD+JA ROM P83C51RA+JB P83C51RB+JB P83C51RC+JB P83C51RD+JB OTP P87C51RA+JB P87C51RB+JB P87C51RC+JB P87C51RD+JB Note: For Multi Time Programmable devices, See P89C51RX+ Flash datasheet. ROMless TEMPERATURE RANGE C AND PACKAGE VOLTAGE RANGE FREQ. (MHz) DWG. # P80C51RA+4N 0 to +70,, 40-Pin Plastic Dual In-line Pkg. 2 7V to 5.5V 2.7V 5 5V 0 to 16 SOT129 1 SOT129-1 P80C51RA+4A 0 to +70,, 44-Pin Plastic Leaded Chip Carrier 2 7V to 5.5V 2.7V 5 5V 0 to 16 SOT187 2 SOT187-2 P80C51RA+4B 0 to +70,, 44-Pin Plastic Quad Flat Pack 2 7V to 5.5V 2.7V 5 5V 0 to 16 SOT307 2 SOT307-2 P80C51RA+5N -40 to +85,, 40-Pin Plastic Dual In-line Pkg. 2 7V to 5.5V 2.7V 5 5V 0 to 16 SOT129 1 SOT129-1 P80C51RA+5A -40 to +85,, 44-Pin Plastic Leaded Chip Carrier 2 7V to 5.5V 2.7V 5 5V 0 to 16 SOT187 2 SOT187-2 P80C51RA+5B -40 to +85,, 44-Pin Plastic Quad Flat Pack 2 7V to 5.5V 2.7V 5 5V 0 to 16 SOT307 2 SOT307-2 P80C51RA+IN 0 to +70,, 40-Pin Plastic Dual In-line Pkg. 5V 0 to 33 SOT129 1 SOT129-1 P80C51RA+IA 0 to +70,, 44-Pin Plastic Leaded Chip Carrier 5V 0 to 33 SOT187 2 SOT187-2 P80C51RA+IB 0 to +70,, 44-Pin Plastic Quad Flat Pack 5V 0 to 33 SOT307 2 SOT307-2 P80C51RA+JN -40 to +85,, 40-Pin Plastic Dual In-line Pkg. 5V 0 to 33 SOT129 1 SOT129-1 P80C51RA+JA -40 to +85,, 44-Pin Plastic Leaded Chip Carrier 5V 0 to 33 SOT187 2 SOT187-2 P80C51RA+JB -40 to +85,, 44-Pin Plastic Quad Flat Pack 5V 0 to 33 SOT307-2 Product specification 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ MEMORY SIZE 16K x 8 Philips Semiconductors 9 MEMORY SIZE 8K x 8 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 1999 Apr 01 87C51RA+/RB+/RC+/RD+ AND 80C51RA+ ORDERING INFORMATION Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) Table 1. SYMBOL 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 8XC52/54/58/80C32 Special Function Registers DESCRIPTION DIRECT ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB RESET VALUE ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H AUXR# Auxiliary 8EH - - - - - - - AO xxxxxxx0B AUXR1# Auxiliary 1 A2H - - - LPEP3 GF3 0 - DPS xxx0xxx0B B* DPTR: DPH DPL B register Data Pointer (2 bytes) Data Pointer High Data Pointer Low F0H F7 F6 F5 F4 F3 F2 F1 F0 IE* Interrupt Enable A8H IP* IPH# P0* P1* P2* Interrupt Priority Interrupt Priority High Port 0 Port 1 Port 2 83H 82H B8H B7H 80H 90H A0H 00H 00H 00H AF AE AD AC AB AA A9 A8 EA - ET2 ES ET1 EX1 ET0 EX0 BF BE BD BC BB BA B9 B8 - - PT2 PS PT1 PX1 PT0 PX0 B7 B6 B5 B4 B3 B2 B1 B0 - - PT2H PSH PT1H PX1H PT0H PX0H 87 86 85 84 83 82 81 80 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 97 96 95 94 93 92 91 90 - - - - - - T2EX T2 A7 A6 A5 A4 A3 A2 A1 A0 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 B7 B6 B5 B4 B3 B2 B1 B0 0x000000B xx000000B xx000000B FFH FFH FFH P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TxD RxD FFH PCON#1 Power Control 87H SMOD1 SMOD0 - POF2 GF1 GF0 PD IDL 00xx0000B D7 D6 D5 D4 D3 D2 D1 D0 CY AC F0 RS1 RS0 OV - P PSW* Program Status Word D0H RCAP2H# RCAP2L# Timer 2 Capture High Timer 2 Capture Low CBH CAH 00H 00H SADDR# SADEN# Slave Address Slave Address Mask A9H B9H 00H 00H SBUF Serial Data Buffer 99H SCON* Serial Control 98H SP Stack Pointer 81H xxxxxxxxB 9F 9E 9D 9C 9B 9A 99 98 SM0/FE SM1 SM2 REN TB8 RB8 TI RI 8F 8E 8D 8C 8B 8A 89 88 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H 07H TCON* Timer Control 88H TF1 CF CE CD CC CB CA C9 C8 T2CON* Timer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 T2MOD# TH0 TH1 TH2# TL0 TL1 TL2# Timer 2 Mode Control Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 C9H 8CH 8DH CDH 8AH 8BH CCH - - - - - - T2OE DCEN C/T M1 M0 GATE C/T M1 M0 TMOD Timer Mode 89H GATE * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits. 1. Reset value depends on reset source. 2. Bit will not be affected by Reset. 3. LPEP - Low Power OTP-EPROM only operation. 1999 Apr 01 000000x0B 10 00H 00H xxxxxx00B 00H 00H 00H 00H 00H 00H 00H Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) Table 2. SYMBOL 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 8XC51FA/FB/FC, 8XC51RA+/RB+/RC+/RD+ Special Function Registers DESCRIPTION DIRECT ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB RESET VALUE ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H AUXR# Auxiliary 8EH - - - - - - EXTRAM (RX+ only) AO xxxxxx00B AUXR1# Auxiliary 1 A2H - - - LPEP3 GF3 0 - DPS xxx0xxx0B B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 CCAP0H# CCAP1H# CCAP2H# CCAP3H# CCAP4H# CCAP0L# CCAP1L# CCAP2L# CCAP3L# CCAP4L# Module 0 Capture High Module 1 Capture High Module 2 Capture High Module 3 Capture High Module 4 Capture High Module 0 Capture Low Module 1 Capture Low Module 2 Capture Low Module 3 Capture Low Module 4 Capture Low FAH FBH FCH FDH FEH EAH EBH ECH EDH EEH CCAPM0# Module 0 Mode DAH - ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM1# Module 1 Mode DBH - ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM2# Module 2 Mode DCH - ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM3# Module 3 Mode DDH - ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM4# Module 4 Mode DEH - ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B DF DE DD DC DB DA D9 D8 00H xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB CCON*# CH# CL# PCA Counter Control PCA Counter High PCA Counter Low D8H F9H E9H CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 00x00000B 00H 00H CMOD# PCA Counter Mode D9H CIDL WDTE - - - CPS1 CPS0 ECF 00xxx000B DPTR: DPH DPL Data Pointer (2 bytes) Data Pointer High Data Pointer Low 83H 82H IE* Interrupt Enable A8H 00H 00H AF AE AD AC AB AA A9 A8 EA EC BF BE ET2 ES ET1 EX1 ET0 EX0 BD BC BB BA B9 B8 - PPC PT2 PS PT1 PX1 PT0 PX0 00H IP* Interrupt Priority B8H B7 B6 B5 B4 B3 B2 B1 B0 IPH# Interrupt Priority High B7H - PPCH PT2H PSH PT1H PX1H PT0H PX0H 87 86 85 84 83 82 81 80 P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 97 96 95 94 93 92 91 90 P1* Port 1 90H CEX4 CEX3 CEX2 CEX1 CEX0 ECI T2EX T2 A7 A6 A5 A4 A3 A2 A1 A0 P2* Port 2 A0H AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 B7 B6 B5 B4 B3 B2 B1 B0 RD WR T1 T0 INT1 INT0 TxD RxD FFH SMOD0 - POF2 GF1 GF0 PD IDL 00xx0000B P3* Port 3 B0H PCON#1 Power Control 87H SMOD1 * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits. 1. Reset value depends on reset source. 2. Bit will not be affected by Reset. 3. LPEP - Low Power OTP-EPROM only operation. 1999 Apr 01 11 x0000000B x0000000B FFH FFH FFH Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) Table 2. 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 8XC51FA/FB/FC, 8XC51RA+/RB+/RC+/RD+ Special Function Registers (Continued) DESCRIPTION DIRECT ADDRESS PSW* Program Status Word D0H RACAP2H# RACAP2L# Timer 2 Capture High Timer 2 Capture Low CBH CAH 00H 00H SADDR# SADEN# Slave Address Slave Address Mask A9H B9H 00H 00H SBUF Serial Data Buffer 99H SYMBOL BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 CY AC F0 RS1 RS0 OV - P RESET VALUE 000000x0B xxxxxxxxB 9F 9E 9D 9C 9B 9A 99 98 SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON* Serial Control 98H SP Stack Pointer 81H 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 CF CE CD CC CB CA C9 C8 T2CON* Timer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 T2MOD# Timer 2 Mode Control C9H - - - - - - T2OE DCEN TH0 TH1 TH2# TL0 TL1 TL2# Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 8CH 8DH CDH 8AH 8BH CCH TMOD Timer Mode 89H 00H 07H 00H 00H xxxxxx00B 00H 00H 00H 00H 00H 00H GATE C/T M1 M0 GATE C/T M1 M0 00H WDTRST HDW Watchdog 0A6H Timer Reset (RX+ only) * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits. OSCILLATOR CHARACTERISTICS RESET XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above VIH1 (min.) is applied to RESET. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. 1999 Apr 01 12 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) LOW POWER MODES 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ POWER OFF FLAG The Power Off Flag (POF) is set by on-chip circuitry when the VCC level on the 8XC51FX/8XC51RX+ rises from 0 to 5V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The VCC level must remain above 3V for the POF to remain unaffected by the VCC level. Stop Clock Mode The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested. Design Consideration * When the idle mode is terminated by a hardware reset, the device Idle Mode normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. In the idle mode (see Table 3), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. ONCE Mode The ONCE ("On-Circuit Emulation") Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: Power-Down Mode To save even more power, a Power Down mode (see Table 3) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2.0V and care must be taken to return VCC to the minimum specified operating voltages before the Power Down Mode is terminated. 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. Either a hardware reset or external interrupt can be used to exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. Programmable Clock-Out A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). 1. to input the external clock for Timer/Counter 2, or 2. to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a 16MHz operating frequency. With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: LPEP Oscillator Frequency 4 (65536 RCAP2H, RCAP2L) The LPEP bit (AUXR.4), only needs to be set for applications operating at VCC less than 4V. Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same. Table 3. External Pin Status During Idle and Power-Down Mode PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 Idle MODE Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 0 Float Data Data Data 1999 Apr 01 13 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Figure 3). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. TIMER 2 OPERATION Timer 2 Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2* in the special function register T2CON (see Figure 1). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 4. Figure 4 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means. Capture Mode In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2* in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure 2. (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/12 pulses.) If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1, which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. Auto-Reload Mode (Up or Down Counter) The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation. In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter [C/T2* in T2CON]) then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see (MSB) TF2 (LSB) EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 Symbol Position Name and Significance TF2 T2CON.7 EXF2 T2CON.6 RCLK T2CON.5 TCLK T2CON.4 EXEN2 T2CON.3 TR2 C/T2 T2CON.2 T2CON.1 CP/RL2 T2CON.0 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/stop control for Timer 2. A logic 1 starts the timer. Timer or counter select. (Timer 2) 0 = Internal timer (OSC/12) 1 = External event counter (falling edge triggered). Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. SU00728 Figure 1. Timer/Counter 2 (T2CON) Control Register 1999 Apr 01 14 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Table 4. Timer 2 Operating Modes RCLK + TCLK CP/RL2 TR2 0 0 1 16-bit Auto-reload 0 1 1 16-bit Capture 1 X 1 Baud rate generator X X 0 (off) OSC MODE / 12 C/T2 = 0 TL2 (8-bits) TH2 (8-bits) TF2 C/T2 = 1 T2 Pin Control TR2 Capture Transition Detector Timer 2 Interrupt RCAP2L RCAP2H T2EX Pin EXF2 Control EXEN2 SU00066 Figure 2. Timer 2 in Capture Mode T2MOD Address = 0C9H Reset Value = XXXX XX00B Not Bit Addressable Bit * -- -- -- -- -- -- T2OE DCEN 7 6 5 4 3 2 1 0 Symbol Function -- Not implemented, reserved for future use.* T2OE Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU00729 Figure 3. Timer 2 Mode (T2MOD) Control Register 1999 Apr 01 15 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ / 12 OSC C/T2 = 0 TL2 (8-BITS) TH2 (8-BITS) C/T2 = 1 T2 PIN CONTROL TR2 RELOAD TRANSITION DETECTOR RCAP2L RCAP2H TF2 TIMER 2 INTERRUPT T2EX PIN EXF2 CONTROL SU00067 EXEN2 Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0) (DOWN COUNTING RELOAD VALUE) FFH FFH TOGGLE EXF2 OSC /12 C/T2 = 0 OVERFLOW TL2 T2 PIN TH2 TF2 INTERRUPT C/T2 = 1 CONTROL TR2 COUNT DIRECTION 1 = UP 0 = DOWN RCAP2L RCAP2H (UP COUNTING RELOAD VALUE) Figure 5. Timer 2 Auto Reload Mode (DCEN = 1) 1999 Apr 01 16 T2EX PIN SU00730 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Timer 1 Overflow /2 NOTE: OSC. Freq. is divided by 2, not 12. "0" /2 OSC "1" C/T2 = 0 SMOD TL2 (8-bits) "1" TH2 (8-bits) "0" RCLK C/T2 = 1 T2 Pin Control / 16 "1" TR2 Reload Transition Detector RCAP2L T2EX Pin EXF2 RCAP2H RX Clock "0" TCLK / 16 TX Clock Timer 2 Interrupt Control EXEN2 Note availability of additional external interrupt. SU00068 Figure 6. Timer 2 in Baud Rate Generator Mode Table 5. The baud rates in modes 1 and 3 are determined by Timer 2's overflow rate given below: Timer 2 Generated Commonly Used Baud Rates Modes 1 and 3 Baud Rates + Timer 2 Overflow Rate 16 Timer 2 Ba d Rate Baud Osc Freq 375K 9.6K 2.8K 2.4K 1.2K 300 110 300 110 12MHz 12MHz 12MHz 12MHz 12MHz 12MHz 12MHz 6MHz 6MHz RCAP2H RCAP2L FF FF FF FF FE FB F2 FD F9 FF D9 B2 64 C8 1E AF 8F 57 The timer can be configured for either "timer" or "counter" operation. In many applications, it is configured for "timer" operation (C/T2*=0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Usually, as a timer it would increment every machine cycle (i.e., 1/12 the oscillator frequency). As a baud rate generator, it increments every state time (i.e., 1/2 the oscillator frequency). Thus the baud rate formula is as follows: Modes 1 and 3 Baud Rates = Oscillator Frequency [32 [65536 * (RCAP2H, RCAP2L)]] Baud Rate Generator Mode Where: (RCAP2H, RCAP2L)= The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Bits TCLK and/or RCLK in T2CON (Table 5) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit baud rate generator. When TCLK= 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates - one generated by Timer 1, the other by Timer 2. The Timer 2 as a baud rate generator mode shown in Figure 6, is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed. Figure 6 shows the Timer 2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode,in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. 1999 Apr 01 17 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ If Timer 2 is being clocked internally , the baud rate is: When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is incremented every state time (osc/2) or asynchronously from pin T2; under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Baud Rate + [32 f OSC [65536 * (RCAP2H, RCAP2L)]] Where fOSC= Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as: Table 5 shows commonly used baud rates and how they can be obtained from Timer 2. RCAP2H, RCAP2L + 65536 * 32 f OSC Baud Rate Summary Of Baud Rate Equations Timer/Counter 2 Set-up Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is: Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. See Table 6 for set-up of Timer 2 as a timer. Also see Table 7 for set-up of Timer 2 as a counter. Baud Rate + Timer 2 Overflow Rate 16 Table 6. Timer 2 as a Timer T2CON MODE INTERNAL CONTROL (Note 1) EXTERNAL CONTROL (Note 2) 16-bit Auto-Reload 00H 08H 16-bit Capture 01H 09H Baud rate generator receive and transmit same baud rate 34H 36H Receive only 24H 26H Transmit only 14H 16H Table 7. Timer 2 as a Counter TMOD MODE INTERNAL CONTROL (Note 1) EXTERNAL CONTROL (Note 2) 16-bit 02H 0AH Auto-Reload 03H 0BH NOTES: 1. Capture/reload occurs only on timer/counter overflow. 2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode. 1999 Apr 01 18 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) Slave 1 Enhanced UART The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 UART. Slave 0 SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 Slave 1 SADDR = SADEN = Given = 1110 0000 1111 1010 1110 0X0X Slave 2 SADDR = SADEN = Given = 1110 0000 1111 1100 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don't-cares. In most cases, interpreting the don't-cares as ones, the broadcast address will be FF hexadecimal. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are "don't care". The SADEN mask can be logically ANDed with the SADDR to create the "Given" address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: 1999 Apr 01 1100 0000 1111 1110 1100 000X In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the "Given" address or the "Broadcast" address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 9. SADDR = SADEN = Given = SADDR = SADEN = Given = In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 8. Slave 0 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all "don't cares" as well as a Broadcast address of all "don't cares". This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. 1100 0000 1111 1101 1100 00X0 19 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ SCON Address = 98H Reset Value = 0000 0000B Bit Addressable SM0/FE Bit: SM1 7 6 (SMOD0 = 0/1)* SM2 REN TB8 RB8 Tl Rl 5 4 3 2 1 0 Symbol Function FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. SM0 Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) SM1 Serial Port Mode Bit 1 SM0 SM1 Mode 0 0 1 1 0 1 0 1 0 1 2 3 Description Baud Rate** shift register 8-bit UART 9-bit UART 9-bit UART fOSC/12 variable fOSC/64 or fOSC/32 variable SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Tl Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Rl Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. NOTE: *SMOD0 is located at PCON6. **fOSC = oscillator frequency SU00043 Figure 7. SCON: Serial Port Control Register 1999 Apr 01 20 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) D0 D1 D2 D3 D4 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ D5 D6 D7 D8 DATA BYTE START BIT ONLY IN MODE 2, 3 STOP BIT SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL SM0 / FE SM1 SM2 REN SMOD1 SMOD0 - POF TB8 GF1 RB8 TI GF0 PD RI SCON (98H) IDL PCON (87H) 0 : SCON.7 = SM0 1 : SCON.7 = FE SU01191 Figure 8. UART Framing Error Detection D0 D1 D2 D3 D4 SM0 SM1 1 1 1 0 D5 SM2 1 D6 D7 D8 REN TB8 RB8 1 X TI RI SCON (98H) RECEIVED ADDRESS D0 TO D7 COMPARATOR PROGRAMMED ADDRESS IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND "RECEIVED ADDRESS" = "PROGRAMMED ADDRESS" - WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES - WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. SU00045 Figure 9. UART Multiprocessor Communication, Automatic Address Recognition 1999 Apr 01 21 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ The priority scheme for servicing the interrupts is the same as that for the 80C51, except there are four interrupt levels rather than two as on the 80C51. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed. Interrupt Priority Structure The 8XC51FA/FB/FC and 8XC51RA+/RB+/RC+/RD+ have a 7-source four-level interrupt structure (see Table 8). The 80C52/54/58 and 80C32 only have a 6-source four-level interrupt structure because these devices do not have a PCA. There are 3 SFRs associated with the four-level interrupt. They are the IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt Priority High) register makes the four-level interrupt structure possible. The IPH is located at SFR address B7H. The structure of the IPH register and a description of its bits is shown in Figure 12. The function of the IPH SFR is simple and when combined with the IP SFR determines the priority of each interrupt. The priority of each interrupt is determined as shown in the following table: PRIORITY BITS INTERRUPT PRIORITY LEVEL IPH.x IP.x 0 0 Level 0 (lowest priority) 0 1 Level 1 1 0 Level 2 1 1 Level 3 (highest priority) Table 8. Interrupt Table SOURCE POLLING PRIORITY REQUEST BITS HARDWARE CLEAR? N (L)1 Y (T)2 VECTOR ADDRESS X0 1 IE0 T0 2 TF0 Y 03H X1 3 IE1 N (L) Y (T) 13 T1 4 TF1 Y 1B PCA 5 CF, CCFn n = 0-4 N 33 SP 6 RI, TI N 23 T2 7 TF2, EXF2 N 2B 0B NOTES: 1. L = Level activated 2. T = Transition activated IE (0A8H) 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables it. BIT IE.7 SYMBOL EA IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 EC ET2 ES ET1 EX1 ET0 EX0 FUNCTION Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually enabled or disabled by setting or clearing its enable bit. PCA interrupt enable bit for FX and RX+ only - otherwise it is not implemented. Timer 2 interrupt enable bit. Serial Port interrupt enable bit. Timer 1 interrupt enable bit. External interrupt 1 enable bit. Timer 0 interrupt enable bit. External interrupt 0 enable bit. SU00840 Figure 10. IE Registers 1999 Apr 01 22 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) IP (0B8H) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 7 6 5 4 3 2 1 0 -- PPC PT2 PS PT1 PX1 PT0 PX0 Priority Bit = 1 assigns high priority Priority Bit = 0 assigns low priority BIT IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 SYMBOL -- PPC PT2 PS PT1 PX1 PT0 PX0 FUNCTION Not implemented, reserved for future use. PCA interrupt priority bit for FX and RX+ only, otherwise it is not implemented. Timer 2 interrupt priority bit. Serial Port interrupt priority bit. Timer 1 interrupt priority bit. External interrupt 1 priority bit. Timer 0 interrupt priority bit. External interrupt 0 priority bit. SU00841 Figure 11. IP Registers IPH (B7H) 7 6 5 4 3 2 1 0 -- PPCH PT2H PSH PT1H PX1H PT0H PX0H Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority BIT IPH.7 IPH.6 IPH.5 IPH.4 IPH.3 IPH.2 IPH.1 IPH.0 SYMBOL -- PPCH PT2H PSH PT1H PX1H PT0H PX0H FUNCTION Not implemented, reserved for future use. PCA interrupt priority bit high for FX and RX+ only, otherwise it is not implemented. Timer 2 interrupt priority bit high. Serial Port interrupt priority bit high. Timer 1 interrupt priority bit high. External interrupt 1 priority bit high. Timer 0 interrupt priority bit high. External interrupt 0 priority bit high. SU00881 Figure 12. IPH Registers 1999 Apr 01 23 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ be quickly toggled simply by executing an INC DPTR instruction without affecting the GF3 or LPEP bits. Reduced EMI Mode The AO bit (AUXR.0) in the AUXR register when set disables the ALE output. Reduced EMI Mode DPS AUXR (8EH) 7 6 5 4 3 2 1 0 - - - - - - EXTRAM AO AUXR.1 AUXR.0 EXTRAM AO BIT0 AUXR1 DPTR1 DPTR0 DPH (83H) (RX+ only) Turns off ALE output. DPL (82H) EXTERNAL DATA MEMORY SU00745A Dual DPTR Figure 13. The dual DPTR structure (see Figure 13) is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them. DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: * New Register Name: AUXR1# * SFR Address: A2H * Reset Value: xxxx00x0B 7 6 5 4 3 2 1 0 - - - LPEP GF3 0 - DPS Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPS DPTR0 0 DPTR1 1 Increments the data pointer by 1 MOV DPTR, #data16 Loads the DPTR with a 16-bit constant MOV A, @ A+DPTR Move code byte relative to DPTR to ACC MOVX A, @ DPTR Move external RAM (16-bit address) to ACC MOVX @ DPTR , A Move ACC to external RAM (16-bit address) JMP @ A + DPTR Jump indirect relative to DPTR The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details. The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. The GF3 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to 1999 Apr 01 INC DPTR 24 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) ECF bit in the CMOD register is set, The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. The PCA interrupt system shown in Figure 16. Programmable Counter Array (PCA) (8XC51FX and 8XC51RX+ only) The Programmable Counter Array available on the 8XC51FX and 8XC51RX+ is a special 16-bit Timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. Each module has a pin associated with it in port 1. Module 0 is connected to P1.3(CEX0), module 1 to P1.4(CEX1), etc. The basic PCA configuration is shown in Figure 14. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (see Figure 19). The registers contain the bits that control the mode that each module will operate in. The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register. The PCA timer is a common time base for all five modules and can be programmed to run at: 1/12 the oscillator frequency, 1/4 the oscillator frequency, the Timer 0 overflow, or the input on the ECI pin (P1.2). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR as follows (see Figure 17): CPS1 CPS0 PCA Timer Count Source 0 0 1/12 oscillator frequency 0 1 1/4 oscillator frequency 1 0 Timer 0 overflow 1 1 External Input at ECI pin The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Figure 20 shows the CCAPMn settings for the various PCA functions. In the CMOD SFR are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during idle mode, WDTE which enables or disables the watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. These functions are shown in Figure 15. The watchdog timer function is implemented in module 4 (see Figure 24). There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output. The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (refer to Figure 18). To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the 16 BITS MODULE 0 P1.3/CEX0 MODULE 1 P1.4/CEX1 MODULE 2 P1.5/CEX2 MODULE 3 P1.6/CEX3 MODULE 4 P1.7/CEX4 16 BITS PCA TIMER/COUNTER TIME BASE FOR PCA MODULES MODULE FUNCTIONS: 16-BIT CAPTURE 16-BIT TIMER 16-BIT HIGH SPEED OUTPUT 8-BIT PWM WATCHDOG TIMER (MODULE 4 ONLY) SU00032 Figure 14. Programmable Counter Array (PCA) 1999 Apr 01 25 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) TO PCA MODULES OSC/12 OVERFLOW OSC/4 CH INTERRUPT CL 16-BIT UP COUNTER TIMER 0 OVERFLOW EXTERNAL INPUT (P1.2/ECI) 00 01 10 11 DECODE IDLE CIDL CF WDTE -- -- -- CPS1 CPS0 ECF CMOD (D9H) CR -- CCF4 CCF3 CCF2 CCF1 CCF0 CCON (D8H) SU00033 Figure 15. PCA Timer/Counter CF CR -- CCF4 CCF3 CCF2 CCF1 CCF0 CCON (D8H) PCA TIMER/COUNTER MODULE 0 IE.6 EC IE.7 EA TO INTERRUPT PRIORITY DECODER MODULE 1 MODULE 2 MODULE 3 MODULE 4 CMOD.0 ECF CCAPMn.0 ECCFn SU00034 Figure 16. PCA Interrupt System 1999 Apr 01 26 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) CMOD Address = OD9H Reset Value = 00XX X000B CIDL WDTE - - - CPS1 7 6 5 4 3 2 Bit: CPS0 1 ECF 0 Symbol Function CIDL Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. - Not implemented, reserved for future use.* CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0. CPS1 CPS0 Selected PCA Input** 0 0 1 1 ECF 0 1 0 1 Internal clock, fOSC / 12 Internal clock, fOSC / 4 Timer 0 overflow External clock at ECI/P1.2 pin (max. rate = fOSC / 8) 0 1 2 3 PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF. NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. ** fOSC = oscillator frequency SU00035 Figure 17. CMOD: PCA Counter Mode Register CCON Address = OD8H Reset Value = 00X0 0000B Bit Addressable Bit: CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 7 6 5 4 3 2 1 0 Symbol Function CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. - Not implemented, reserved for future use*. CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU00036 Figure 18. CCON: PCA Counter Control Register 1999 Apr 01 27 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) CCAPMn Address CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 0DAH 0DBH 0DCH 0DDH 0DEH Reset Value = X000 0000B Not Bit Addressable Bit: - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn 7 6 5 4 3 2 1 0 Symbol Function - ECOMn CAPPn CAPNn MATn Not implemented, reserved for future use*. Enable Comparator. ECOMn = 1 enables the comparator function. Capture Positive, CAPPn = 1 enables positive edge capture. Capture Negative, CAPNn = 1 enables negative edge capture. Match. When MATn = 1, a match of the PCA counter with this module's compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture register causes the CEXn pin to toggle. Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. TOGn PWMn ECCFn NOTE: *User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU00037 Figure 19. CCAPMn: PCA Modules Compare/Capture Registers - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn X 0 0 0 0 0 0 0 No operation X X 1 0 0 0 0 X 16-bit capture by a positive-edge trigger on CEXn X X 0 1 0 0 0 X 16-bit capture by a negative trigger on CEXn X X 1 1 0 0 0 X 16-bit capture by a transition on CEXn X 1 0 0 1 0 0 X 16-bit Software Timer X 1 0 0 1 1 0 X 16-bit High Speed Output X 1 0 0 0 0 1 0 8-bit PWM X 1 0 0 1 X 0 X Watchdog Timer MODULE FUNCTION Figure 20. PCA Module Modes (CCAPMn Register) PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. Refer to Figure 21. High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (see Figure 23). Pulse Width Modulator Mode All of the PCA modules can be used as PWM outputs. Figure 24 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 22). 1999 Apr 01 28 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) CF CR -- CCF4 CCF3 CCF2 CCF1 CCON (D8H) CCF0 PCA INTERRUPT (TO CCFn) PCA TIMER/COUNTER CH CL CCAPnH CCAPnL CAPTURE CEXn -- ECOMn CAPPn CAPNn MATn TOGn PWMn 0 0 0 0 ECCFn CCAPMn, n= 0 to 4 (DAH - DEH) SU00749 Figure 21. PCA Capture Mode CF WRITE TO CCAPnH -- CCF4 CCF3 CCF2 CCF1 CCF0 CCON (D8H) RESET CCAPnH WRITE TO CCAPnL 0 CR PCA INTERRUPT CCAPnL (TO CCFn) 1 ENABLE MATCH 16-BIT COMPARATOR CH CL PCA TIMER/COUNTER -- ECOMn CAPPn CAPNn 0 0 MATn TOGn PWMn 0 0 ECCFn CCAPMn, n= 0 to 4 (DAH - DEH) SU00750 Figure 22. PCA Compare Mode 1999 Apr 01 29 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) CF WRITE TO CCAPnH CR CCF4 CCF3 CCF2 CCF1 CCON (D8H) CCF0 RESET CCAPnH WRITE TO CCAPnL 0 -- PCA INTERRUPT CCAPnL (TO CCFn) 1 MATCH ENABLE 16-BIT COMPARATOR TOGGLE CH CEXn CL PCA TIMER/COUNTER -- ECOMn CAPPn CAPNn 0 0 MATn TOGn PWMn 1 CCAPMn, n: 0..4 (DAH - DEH) ECCFn 0 SU00751 Figure 23. PCA High Speed Output Mode CCAPnH CCAPnL 0 CL < CCAPnL ENABLE 8-BIT COMPARATOR CEXn CL >= CCAPnL 1 CL OVERFLOW PCA TIMER/COUNTER -- ECOMn CAPPn CAPNn MATn TOGn 0 0 0 0 PWMn ECCFn CCAPMn, n: 0..4 (DAH - DEH) 0 SU00752 Figure 24. PCA PWM Mode 1999 Apr 01 30 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) CIDL WRITE TO CCAP4H -- -- -- CPS1 CPS0 ECF CMOD (D9H) RESET CCAP4H WRITE TO CCAP4L 0 WDTE CCAP4L MODULE 4 1 ENABLE MATCH RESET 16-BIT COMPARATOR CH CL PCA TIMER/COUNTER -- ECOMn CAPPn CAPNn MATn 0 0 1 TOGn X PWMn ECCFn 0 X CCAPM4 (DEH) SU00832 Figure 25. PCA Watchdog Timer m(Module 4 only) PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. Figure 25 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. Figure 26 shows the code for initializing the watchdog timer. Module 4 can be configured in either compare mode, and the WDTE bit in CMOD must also be set. The user's software then must periodically change (CCAP4H,CCAP4L) to keep a match from occurring with the PCA timer (CH,CL). This code is given in the WATCHDOG routine in Figure 26. In order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the PCA timer, This routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine from the main program within 216 count of the PCA timer. 2. periodically change the PCA timer value so it will never match the compare values, or 3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. 1999 Apr 01 31 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51FX and 8XC51RX+ ONLY) INIT_WATCHDOG: MOV CCAPM4, #4CH MOV CCAP4L, #0FFH MOV CCAP4H, #0FFH ORL CMOD, #40H ; ; ; ; ; ; ; ; Module 4 in compare mode Write to low byte first Before PCA timer counts up to FFFF Hex, these compare values must be changed Set the WDTE bit to enable the watchdog timer without changing the other bits in CMOD ; ;******************************************************************** ; ; Main program goes here, but CALL WATCHDOG periodically. ; ;******************************************************************** ; WATCHDOG: CLR EA ; Hold off interrupts MOV CCAP4L, #00 ; Next compare value is within MOV CCAP4H, CH ; 255 counts of the current PCA SETB EA ; timer value RET Figure 26. PCA Watchdog Timer Initialization Code 1999 Apr 01 32 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51RX+ ONLY) Expanded Data RAM Addressing (8XC51RX+ ONLY) For example: The 8XC51RX+ have internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes Special Function Register (SFR), and 256 bytes (768 for RD+) expanded RAM (EXTRAM). where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). The EXTRAM can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory is physically located on-chip, logically occupies the first 256-bytes (768 for RD+) of external data memory. MOV @R0,#data The four segments are: 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. With EXTRAM = 0, the EXTRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to EXTRAM will not affect ports P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during external addressing. For example, with EXTRAM = 0, 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only. 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only. MOVX @R0,#data 4. The 256-bytes (768 for RD+) expanded RAM ((EXTRAM (256-bytes) 00H-FFH)) and ((EXTRAM (768-bytes for RD+) 00H - 2FFH)) are indirectly accessed by move external instruction, MOVX, and with the EXTRAM bit cleared, see Figure 27. where R0 contains 0A0H, access the EXTRAM at address 0A0H rather than external memory. An access to external data memory locations higher than FFH (2FF for RD+) (i.e., 0100H to FFFFH) will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals. Refer to Figure 28. The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an 8-bit address multiplexed with data on Port 0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a 16-bit address. Port 2 outputs the high-order eight address bits (the contents of DPH) while Port 0 multiplexes the low-order eight address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will generate either read or write signals on P3.6 (#WR) and P3.7 (#RD). When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For example: MOV 0A0H,#data The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the EXTRAM. accesses the SFR at location 0A0H (which is P2). Instructions that use indirect addressing access the Upper 128 bytes of data RAM. AUXR Address = 8EH Reset Value = xxxx xx00B Not Bit Addressable -- -- -- -- -- -- EXTRAM AO 7 6 5 4 3 2 1 0 Bit: Symbol Function AO Disable/Enable ALE AO Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency. 1 ALE is active only during a MOVX or MOVC instruction. EXTRAM Internal/External RAM access using MOVX @Ri/@DPTR EXTRAM Operating Mode 0 Internal ERAM (00H-FFH) (00H-2FFH for RD+) access using MOVX @Ri/@DPTR 1 External data memory access. -- Not implemented, reserved for future use*. NOTE: *User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU01003 Figure 27. AUXR: Auxiliary Register (RX+ only) 1999 Apr 01 33 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ (8XC51RX+ ONLY) EEEEE EEEEE EEEEE EEEEE EEEEE 2FF (RD TO RD+) FF FF FF UPPER 128 BYTES INTERNAL RAM ERAM 256 BYTES 80 FFFF SPECIAL FUNCTION REGISTER EXTERNAL DATA MEMORY 80 LOWER 128 BYTES INTERNAL RAM 300 (RD+ only) 00 00 00 0100 0000 SU00834 Figure 28. Internal and External Data Memory Address Space with EXTRAM = 0 In applications using the Hardware Watchdog Timer of the P8xC51RD+, a series resistor (1K 20%) needs to be included between the reset pin and any external components. Without this resistor the watchdog timer will not function. HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT FOR 89C51RC+/RD+) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output reset HIGH pulse at the RST-pin. Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When using the WDT, a 1Kohm resistor must be inserted between RST of the device and the Power On Reset circuitry. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT, the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the reset pin. The RESET pulse duration is 98 x TOSC, where TOSC = 1/fOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. 1999 Apr 01 34 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER Operating temperature under bias Storage temperature range RATING UNIT 0 to +70 or -40 to +85 C -65 to +150 C 0 to +13.0 V Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS -0.5 to +6.5 V 15 mA Maximum IOL per I/O pin Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. AC ELECTRICAL CHARACTERISTICS Tamb = 0C to +70C or -40C to +85C CLOCK FREQUENCY RANGE -f SYMBOL 1/tCLCL 1999 Apr 01 FIGURE 33 PARAMETER Oscillator frequency Speed versions : 4:5:S (16MHz) I:J:U (33MHz) 35 MIN MAX 0 0 16 33 UNIT MHz MHz Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ DC ELECTRICAL CHARACTERISTICS Tamb = 0C to +70C or -40C to +85C, VCC = 2.7V to 5.5V, VSS = 0V (16MHz devices) SYMBOL VIL Input low voltage VIH Input high voltage (ports 0, 1, 2, 3, EA) VIH1 Input high voltage, XTAL1, RST MIN 4.0V < VCC < 5.5V -0.5 2.7V<VCC< 4.0V VOL Output low voltage, ports 1, 2 8 VCC = 2.7V IOL = 1.6mA2 VOL1 Output low voltage, port 0, ALE, PSEN8, 7 VCC = 2.7V IOL = 3.2mA2 VOH O voltage ports 1, 1 2, 2 3 Output high voltage, LIMITS TEST CONDITIONS PARAMETER 3 TYP1 MAX UNIT 0.2VCC-0.1 V -0.5 0.7 V 0.2VCC+0.9 VCC+0.5 V 0.7VCC VCC+0.5 V 0.4 V 0.4 V VCC = 2.7V IOH = -20A VCC - 0.7 V VCC = 4.5V IOH = -30A VCC - 0.7 V VCC = 2.7V IOH = -3.2mA VCC - 0.7 V -1 VOH1 Output high voltage (port 0 in external bus mode), ALE9, PSEN3 IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4V -50 A ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0V See note 4 -650 A ILI Input leakage current, port 0 0.45 < VIN < VCC - 0.3 10 A ICC Power supply current (see Figure 36): Active mode @ 16MHz (all except 8XC51RD+) 87C51RD+ Idle mode @ 16MHz Power-down mode or clock stopped (see Figure 40 f conditions) for diti ) 15 16 4 50 75 mA mA mA A A 225 k RRST See note 5 Tamb = 0C to 70C Tamb = -40C to +85C Internal reset pull-down resistor 3 40 capacitance10 CIO Pin (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC-0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. See Figures 37 through 40 for ICC test conditions, and Figure 36 for ICC vs Freq. Active mode: ICC = (0.9 x FREQ. + 1.1)mA for all devices except 8XC51RD+; 8XC51RD+ ICC = (0.9 x Freq +2.1) mA Idle mode: ICC = (0.18 x FREQ. +1.01)mA 6. This value applies to Tamb = 0C to +70C. For Tamb = -40C to +85C, ITL = -750A. 7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA (*NOTE: This is 85C specification.) 26mA Maximum IOL per 8-bit port: Maximum total IOL for all outputs: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA is 25pF). 1999 Apr 01 36 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ DC ELECTRICAL CHARACTERISTICS Tamb = 0C to +70C or -40C to +85C, 33MHz devices; 5V 10%; VSS = 0V SYMBOL TEST CONDITIONS PARAMETER VIL Input low voltage VIH Input high voltage (ports 0, 1, 2, 3, EA) VIH1 Input high voltage, XTAL1, RST VOL Output low voltage, ports 1, 2, 3 8 VOL1 MIN TYP1 UNIT MAX -0.5 0.2VCC-0.1 V 0.2VCC+0.9 VCC+0.5 V 0.7VCC VCC+0.5 V VCC = 4.5V IOL = 1.6mA2 0.4 V Output low voltage, port 0, ALE, PSEN 7, 8 VCC = 4.5V IOL = 3.2mA2 0.4 V VOH Output high voltage, ports 1, 2, 3 3 VCC = 4.5V IOH = -30A VCC - 0.7 V VOH1 Output high voltage (port 0 in external bus mode), ALE9, PSEN3 VCC = 4.5V IOH = -3.2mA VCC - 0.7 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4V -1 ITL Logical 1-to-0 transition current, ports 1, 2, 36 ILI Input leakage current, port 0 ICC Power supply current (see Figure 36): Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped (see Figure 40 for ( Fi f conditions) diti ) RRST CIO 4.5V < VCC < 5.5V LIMITS -50 A VIN = 2.0V See note 4 -650 A 0.45 < VIN < VCC - 0.3 10 A 50 75 A A 225 k 15 pF See note 5 Tamb = 0C to 70C Tamb = -40C to +85C Internal reset pull-down resistor Pin capacitance10 3 40 (except EA) NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC-0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. See Figures 37 through 40 for ICC test conditions and Figure 36 for ICC vs Freq. Active mode: ICC(MAX) = (0.9 x FREQ. + 1.1)mA. for all devices except 8XC51RD+; 8XC51RD+ ICC = (0.9 x Freq +2.1) mA Idle mode: ICC(MAX) = (0.18 x FREQ. +1.0)mA 6. This value applies to Tamb = 0C to +70C. For Tamb = -40C to +85C, ITL = -750A. 7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA (*NOTE: This is 85C specification.) Maximum IOL per port pin: Maximum IOL per 8-bit port: 26mA 71mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA is 25pF). 1999 Apr 01 37 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ AC ELECTRICAL CHARACTERISTICS Tamb = 0C to +70C or -40C to +85C, VCC = +2.7V to +5.5V, VSS = 0V1, 2, 3 16MHz CLOCK SYMBOL FIGURE 1/tCLCL 29 PARAMETER MIN MAX Oscillator frequency5 Speed versions : 4; 5;S VARIABLE CLOCK MIN MAX UNIT 3.5 16 MHz tLHLL 29 ALE pulse width 85 2tCLCL-40 ns tAVLL 29 Address valid to ALE low 22 tCLCL-40 ns tLLAX 29 Address hold after ALE low 32 tLLIV 29 ALE low to valid instruction in tLLPL 29 ALE low to PSEN low 32 tPLPH 29 PSEN pulse width 142 tPLIV 29 PSEN low to valid instruction in tPXIX 29 Input instruction hold after PSEN tPXIZ 29 Input instruction float after PSEN 37 tCLCL-25 ns 29 Address to valid instruction in 207 5tCLCL-105 ns 29 PSEN low to address float 10 10 ns tAVIV 5 tPLAZ tCLCL-30 150 ns 4tCLCL-100 tCLCL-30 ns 3tCLCL-45 82 0 ns ns 3tCLCL-105 0 ns ns Data Memory tRLRH 30, 31 RD pulse width 275 6tCLCL-100 ns tWLWH 30, 31 WR pulse width 275 6tCLCL-100 ns tRLDV 30, 31 RD low to valid data in tRHDX 30, 31 Data hold after RD tRHDZ 30, 31 Data float after RD 65 2tCLCL-60 ns tLLDV 30, 31 ALE low to valid data in 350 8tCLCL-150 ns tAVDV 30, 31 Address to valid data in 397 9tCLCL-165 ns tLLWL 30, 31 ALE low to RD or WR low 137 3tCLCL+50 ns tAVWL 30, 31 Address valid to WR low or RD low 122 4tCLCL-130 ns tQVWX 30, 31 Data valid to WR transition 13 tCLCL-50 ns tWHQX 30, 31 Data hold after WR 13 tCLCL-50 ns tQVWH 31 Data valid to WR high 287 7tCLCL-150 ns tRLAZ 30, 31 RD low to address float tWHLH 30, 31 RD or WR high to ALE high 23 147 0 5tCLCL-165 0 239 3tCLCL-50 0 103 tCLCL-40 ns ns 0 ns tCLCL+40 ns External Clock tCHCX 33 High time 20 20 tCLCL-tCLCX ns tCLCX 33 Low time 20 20 tCLCL-tCHCX ns tCLCH 33 Rise time 20 20 ns tCHCL 33 Fall time 20 20 ns tXLXL 32 Serial port clock cycle time 750 12tCLCL ns tQVXH 32 Output data setup to clock rising edge 492 10tCLCL-133 ns tXHQX 32 Output data hold after clock rising edge 8 2tCLCL-117 ns tXHDX 32 Input data hold after clock rising edge 0 0 ns Shift Register tXHDV 32 Clock rising edge to input data valid 492 10tCLCL-133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interface. 5. Parts are guaranteed to operate down to 0Hz. 1999 Apr 01 38 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ AC ELECTRICAL CHARACTERISTICS Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%, VSS = 0V1, 2, 3 SYMBOL FIGURE PARAMETER VARIABLE CLOCK4 33MHz CLOCK MIN MIN MAX MAX UNIT tLHLL 29 ALE pulse width 2tCLCL-40 21 ns tAVLL 29 Address valid to ALE low tCLCL-25 5 ns tLLAX 29 Address hold after ALE low tCLCL-25 tLLIV 29 ALE low to valid instruction in tLLPL 29 ALE low to PSEN low tCLCL-25 5 ns tPLPH 29 PSEN pulse width 3tCLCL-45 45 ns tPLIV 29 PSEN low to valid instruction in tPXIX 29 Input instruction hold after PSEN tPXIZ 29 Input instruction float after PSEN tCLCL-25 5 ns tAVIV 29 Address to valid instruction in 5tCLCL-80 70 ns tPLAZ 29 PSEN low to address float 10 10 ns ns 4tCLCL-65 55 3tCLCL-60 0 30 0 ns ns ns Data Memory tRLRH 30, 31 RD pulse width 6tCLCL-100 82 tWLWH 30, 31 WR pulse width 6tCLCL-100 tRLDV 30, 31 RD low to valid data in tRHDX 30, 31 Data hold after RD tRHDZ 30, 31 Data float after RD 2tCLCL-28 32 ns tLLDV 30, 31 ALE low to valid data in 8tCLCL-150 90 ns tAVDV 30, 31 Address to valid data in 9tCLCL-165 105 ns tLLWL 30, 31 ALE low to RD or WR low 3tCLCL-50 140 ns tAVWL 30, 31 Address valid to WR low or RD low 4tCLCL-75 45 ns tQVWX 30, 31 Data valid to WR transition tCLCL-30 0 ns tWHQX 30, 31 Data hold after WR tCLCL-25 5 ns 82 5tCLCL-90 0 tQVWH 31 tRLAZ 30, 31 Data valid to WR high RD low to address float tWHLH 30, 31 RD or WR high to ALE high tCLCL-25 ns ns 60 0 3tCLCL+50 7tCLCL-130 40 ns 80 0 tCLCL+25 5 ns ns 0 ns 55 ns External Clock tCHCX 33 High time 0.38tCLCL tCLCL-tCLCX ns tCLCX 33 Low time 0.38tCLCL tCLCL-tCHCX ns tCLCH 33 Rise time 5 ns tCHCL 33 Fall time 5 ns tXLXL 32 Serial port clock cycle time tQVXH 32 tXHQX 32 tXHDX 32 Input data hold after clock rising edge Shift Register 12tCLCL 360 ns Output data setup to clock rising edge 10tCLCL-133 167 ns Output data hold after clock rising edge 2tCLCL-80 0 ns 0 ns tXHDV 32 Clock rising edge to input data valid 10tCLCL-133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. For frequencies equal or less than 16MHz, see 16MHz "AC Electrical Characteristics", page 38. 5. Parts are guaranteed to operate down to 0Hz. 1999 Apr 01 39 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ EXPLANATION OF THE AC SYMBOLS P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low. Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE tLHLL ALE tAVLL tLLPL tPLPH tLLIV tPLIV PSEN tLLAX INSTR IN A0-A7 PORT 0 tPXIZ tPLAZ tPXIX A0-A7 tAVIV PORT 2 A0-A15 A8-A15 SU00006 Figure 29. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL tRLRH RD tAVLL tLLAX tRLAZ PORT 0 tRHDZ tRLDV tRHDX A0-A7 FROM RI OR DPL DATA IN A0-A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0-P2.7 OR A8-A15 FROM DPF A0-A15 FROM PCH SU00025 Figure 30. External Data Memory Read Cycle 1999 Apr 01 40 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ ALE tWHLH PSEN tWLWH tLLWL WR tLLAX tAVLL tWHQX tQVWX tQVWH A0-A7 FROM RI OR DPL PORT 0 DATA OUT A0-A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0-P2.7 OR A8-A15 FROM DPF A0-A15 FROM PCH SU00026 Figure 31. External Data Memory Write Cycle INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE tXLXL CLOCK tXHQX tQVXH OUTPUT DATA 0 1 2 WRITE TO SBUF 3 4 5 6 7 tXHDX tXHDV SET TI INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID CLEAR RI SET RI SU00027 Figure 32. Shift Register Mode Timing VCC-0.5 0.45V 0.7VCC 0.2VCC-0.1 tCHCL tCHCX tCLCH tCLCX tCLCL SU00009 Figure 33. External Clock Drive 1999 Apr 01 41 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) VCC-0.5 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ VLOAD+0.1V 0.2VCC+0.9 TIMING REFERENCE POINTS VLOAD 0.45V 0.2VCC-0.1 VLOAD-0.1V SU00717 SU00718 Figure 34. AC Testing Input/Output Figure 35. Float Waveform 35 30 ICC(mA) 25 MAX ACTIVE MODE (EXCEPT 8XC51RD+) ICCMAX ACTIVE MODE (8XC51RD+) ICCMAX = 0.9 X FREQ + 2.1 15 ICCMAX = 0.9 X FREQ. + 1.1 TYP ACTIVE MODE 10 MAX IDLE MODE 5 TYP IDLE MODE 4 8 12 16 20 24 28 32 36 FREQ AT XTAL1 (MHz) SU00837A Figure 36. ICC vs. FREQ Valid only within frequency specifications of the device under test 1999 Apr 01 VOL+0.1V NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA. NOTE: AC inputs during testing are driven at VCC -0.5 for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'. 20 VOH-0.1V 42 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ VCC VCC ICC ICC VCC VCC VCC VCC RST RST P0 P0 EA EA (NC) XTAL2 (NC) XTAL2 CLOCK SIGNAL XTAL1 CLOCK SIGNAL XTAL1 VSS VSS SU00719 SU00720 Figure 37. ICC Test Condition, Active Mode All other pins are disconnected VCC-0.5 Figure 38. ICC Test Condition, Idle Mode All other pins are disconnected 0.7VCC 0.2VCC-0.1 0.45V tCHCL tCHCX tCLCH tCLCX tCLCL SU00009 Figure 39. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns VCC ICC VCC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS SU00016 Figure 40. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2V to 5.5V 1999 Apr 01 VCC 43 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 43. The other pins are held at the `Verify Code Data' levels indicated in Table 9. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. EPROM CHARACTERISTICS All these devices can be programmed by using a modified Improved Quick-Pulse Programming algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. If the 64 byte encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. The family contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as being manufactured by Philips. Table 9 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 41 and 42. Figure 43 shows the circuit configuration for normal program memory verification. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = 97H indicates 87C52 BBH indicates 87C54 BDH indicates 87C58 B1H indicates 87C51FA B2H indicates 87C51FB B3H indicates 87C51FC CAH indicates 87C51RA+ CBH indicates 87C51RB+ CCH indicates 87C51RC+ CDH indicates 87C51RD+ (060H) = NA Quick-Pulse Programming The setup for microcontroller quick-pulse programming is shown in Figure 41. Note that the device is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 41. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 9 are held at the `Program Code Data' levels indicated in Table 9. The ALE/PROG is pulsed low 5 times as shown in Figure 42. Program/Verify Algorithms To program the encryption table, repeat the 5 pulse programming sequence for addresses 0 through 1FH, using the `Pgm Encryption Table' levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. Any algorithm in agreement with the conditions listed in Table 9, and which satisfies the timing specifications, is suitable. Security Bits With none of the security bits programmed the code in the program memory can be verified. If the encryption table is programmed, the code will be encrypted when verified. When only security bit 1 (see Table 10) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory, EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. To program the security bits, repeat the 5 pulse programming sequence using the `Pgm Security Bit' levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bits can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot. Encryption Array Program Verification If security bits 2 and 3 have not been programmed, the on-chip program memory can be read out for program verification. The 64 bytes of encryption array are initially unprogrammed (all 1s). Trademark phrase of Intel Corporation. 1999 Apr 01 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ 44 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Table 9. EPROM Programming Modes RST PSEN ALE/PROG EA/VPP P2.7 P2.6 P3.7 P3.6 Read signature MODE 1 0 1 1 0 0 0 0 Program code data 1 0 0* VPP 1 0 1 1 Verify code data 1 0 1 1 0 0 1 1 Pgm encryption table 1 0 0* VPP 1 0 1 0 Pgm security bit 1 1 0 0* VPP 1 1 1 1 Pgm security bit 2 1 0 0* VPP 1 1 0 0 Pgm security bit 3 1 0 0* VPP 0 1 0 1 NOTES: 1. `0' = Valid low for that pin, `1' = valid high for that pin. 2. VPP = 12.75V 0.25V. 3. VCC = 5V10% during programming and verification. * ALE/PROG receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while VPP is held at 12.75V. Each programming pulse is low for 100s (10s) and high for a minimum of 10s. Table 10. Program Security Bits for EPROM Devices PROGRAM LOCK BITS1, 2 SB1 SB2 SB3 PROTECTION DESCRIPTION 1 U U U No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled. 3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, external execution is disabled. NOTES: 1. P - programmed. U - unprogrammed. 2. Any other combination of the security bits is not defined. 1999 Apr 01 45 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ +5V A0-A7 VCC P1 P0 1 RST 1 P3.6 EA/VPP 1 P3.7 ALE/PROG OTP XTAL2 4-6MHz XTAL1 PGM DATA +12.75V 5 PULSES TO GROUND PSEN 0 P2.7 1 P2.6 0 A8-A13 P2.0-P2.5 VSS A8-A15 are programming addresses (not external memory addresses per device pin out) P3.4 A14 P3.5 A15 (RD+ ONLY) SU00838A Figure 41. Programming Configuration 5 PULSES 1 ALE/PROG: 0 1 2 3 4 5 SEE EXPLODED VIEW BELOW tGHGL = 10s MIN tGLGH = 100s10s 1 ALE/PROG: 1 0 SU00875 Figure 42. PROG Waveform +5V VCC A0-A7 P0 P1 1 RST 1 P3.6 1 P3.7 OTP XTAL2 4-6MHz XTAL1 EA/VPP 1 ALE/PROG 1 PSEN 0 P2.7 0 ENABLE P2.6 0 P2.0-P2.5 VSS P3.4 A8-A15 are programming addresses (not external memory addresses per device pin out) P3.5 A8-A13 A14 A15 (RD+ ONLY) SU00870 Figure 43. Program Verification 1999 Apr 01 PGM DATA 46 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Tamb = 21C to +27C, VCC = 5V10%, VSS = 0V (See Figure 44) SYMBOL PARAMETER MIN MAX UNIT 12.5 13.0 V 50 1 mA 6 MHz VPP Programming supply voltage IPP Programming supply current 1/tCLCL Oscillator frequency tAVGL Address setup to PROG low 48tCLCL tGHAX Address hold after PROG 48tCLCL tDVGL Data setup to PROG low 48tCLCL tGHDX Data hold after PROG 48tCLCL tEHSH P2.7 (ENABLE) high to VPP 48tCLCL tSHGL VPP setup to PROG low 10 s tGHSL VPP hold after PROG 10 s tGLGH PROG width 90 tAVQV Address to data valid 48tCLCL tELQZ ENABLE low to data valid 48tCLCL tEHQZ Data float after ENABLE 0 tGHGL PROG high to PROG low 10 4 110 s 48tCLCL s NOTE: 1. Not tested. PROGRAMMING* VERIFICATION* P1.0-P1.7 P2.0-P2.5 P3.4 (A0 - A14) ADDRESS ADDRESS PORT 0 P0.0 - P0.7 (D0 - D7) DATA IN tAVQV DATA OUT tDVGL tAVGL tGHDX tGHAX ALE/PROG tGLGH tSHGL tGHGL tGHSL LOGIC 1 LOGIC 1 EA/VPP LOGIC 0 tEHSH tELQV tEHQZ P2.7 ** SU00871 NOTES: * FOR PROGRAMMING CONFIGURATION SEE FIGURE 41. FOR VERIFICATION CONDITIONS SEE FIGURE 43. ** SEE TABLE 9. Figure 44. EPROM Programming and Verification 1999 Apr 01 47 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ MASK ROM DEVICES internal memory, EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. Security Bits With none of the security bits programmed the code in the program memory can be verified. If the encryption table is programmed, the code will be encrypted when verified. When only security bit 1 (see Table 11) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the Encryption Array 64 bytes of encryption array are initially unprogrammed (all 1s). Table 11. Program Security Bits PROGRAM LOCK BITS1, 2 SB1 SB2 PROTECTION DESCRIPTION 1 U U No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) 2 P U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled. NOTES: 1. P - programmed. U - unprogrammed. 2. Any other combination of the security bits is not defined. ROM CODE SUBMISSION FOR 8K ROM DEVICES (80C52, 83C51FA, AND 83C51RA+) When submitting ROM code for the 8k ROM devices, the following must be specified: 1. 8k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to 1FFFH DATA 7:0 User ROM Data 2000H to 203FH KEY 7:0 ROM Encryption Key FFH = no encryption 2040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 2040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: Enabled Disabled Security Bit #2: Enabled Disabled Encryption: No Yes 1999 Apr 01 If Yes, must send key file. 48 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ ROM CODE SUBMISSION FOR 16K ROM DEVICES (80C54, 83C51FB AND 83C51RB+) When submitting ROM code for the 16K ROM devices, the following must be specified: 1. 16k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to 3FFFH DATA 7:0 User ROM Data 4000H to 403FH KEY 7:0 ROM Encryption Key FFH = no encryption 4040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 4040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: Enabled Disabled Security Bit #2: Enabled Disabled Encryption: No Yes 1999 Apr 01 If Yes, must send key file. 49 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ ROM CODE SUBMISSION FOR 32K ROM DEVICES (80C58, 83C51FC, AND 83C51RC+) When submitting ROM code for the 32K ROM devices, the following must be specified: 1. 32k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to 7FFFH DATA 7:0 User ROM Data 8000H to 803FH KEY 7:0 ROM Encryption Key FFH = no encryption 8040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 8040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: Enabled Disabled Security Bit #2: Enabled Disabled Encryption: No Yes 1999 Apr 01 If Yes, must send key file. 50 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ ROM CODE SUBMISSION FOR 64K ROM DEVICE (83C51RD+) When submitting ROM code for the 64K ROM devices, the following must be specified: 1. 64k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to FFFFH DATA 7:0 User ROM Data 10000H to 1003FH KEY 7:0 ROM Encryption Key FFH = no encryption 10040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 10040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: Enabled Disabled Security Bit #2: Enabled Disabled Encryption: No Yes 1999 Apr 01 If Yes, must send key file. 51 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm 1999 Apr 01 52 SOT307-2 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) PLCC44: plastic leaded chip carrier; 44 leads 1999 Apr 01 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ SOT187-2 53 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) DIP40: plastic dual in-line package; 40 leads (600 mil) 1999 Apr 01 54 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ SOT129-1 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) NOTES 1999 Apr 01 55 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless, low voltage (2.7V-5.5V), low power, high speed (33MHz) 8XC52/54/58/80C32 8XC51FA/FB/FC/80C51FA 8XC51RA+/RB+/RC+/RD+/80C51RA+ Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Date of release: 04-99 Document order number: 1999 Apr 01 56 9397 750 05509