SMD Packages - Infineon Technologies

Special Subject Book January 2000

SMD Packages

Never stop thinking

Thermal Resistance

Theory and Practice

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The information herein is given to describe

certain components and shall not be

considered as warranted characteristics.

Terms of delivery and rights to technical

change reserved.

We hereby disclaim any and all warranties,

including but not limited to warranties of

non-infringement, regarding circuits,

descriptions and charts stated herein.

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manufacturer.

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delivery terms and conditions and prices

please contact your nearest Infineon

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Due to technical requirements components

may contain dangerous substances.

For information on the types in question

please contact your nearest Infineon

Technologies Office.

Infineon Technologies Components may

only be used in life-support devices or

systems with the express written approval

of Infineon Technologies, if a failure of such

components can reasonably be expected to

cause the failure of that life-support device

or system, or to affect the safety or

effectiveness of that device or system.

Life support devices or systems are

intended to be implanted in the human

body, or to support and/or maintain and

sustain and/or protect human life. If they

fail, it is reasonable to assume that the

health of the user or other persons may be

endangered.

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

SMD-Package Properties for Power Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Using a Printed Circuit Board as a Heat Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Static Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Dynamic Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Finite Element Method (FEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Determining the Static Heat Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Measuring the Rthj-a in the Real Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Determining the Dynamic Heat Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Package and Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Thermal Resistance - Theory and Practice

Contents

InfineonTechnologies AG

Infineon Technologies AG4

Thermal Resistance - Theory and Practice

Power-SMD applications or

what’s the size of the heat sink ?

More and more frequently,

modern SMD-component users

(Surface Mounted Devices) ask

the question, “What’s the size of

the heat sink ?”

The reason: The trend from

through-hole packages to

low-cost SMD-applications is

marked by the improvement of

chip technologies.

„Silicon instead of heat sink“ is

therefore possible in many cases.

The printed circuit board (PCB)

itself becomes the heat sink. As

many applications today use

PCBs assembled with SMD-

technology, the emphasis is on

Power-ICs in SMD packages

mounted on single-sided PCBs

laminated on one side.

Pricing pressure demands simple

processes and lowest-cost

solutions. This report describes a

solution.

Introduction

Infineon Technologies AG 5

1.27

1.45

-0.2

8.75

-0.2

14 8

1.75 max.

0.2

±0.2

0.35 x 45˚

-0.2

0.1

-0.1

0.4

+0.8

Index Marking

P-DSO-14-4P-TO252-3-1

+0.15

0.35

0.2 14x

0.19

+0.06

8 max.

Package

Footprint / Dimensions

Dimensions in mm

1.27P-DSO-14-4

5.69

1.31

0.65

5.4

±0.1

-0.10

6.5

All metal surfaces thin plated,

except area of cut.

+0.15

±0.5

9.9

6.22

-0.2

±0.1

±0.15

0.8

0.15

±0.1

max

per side 0.75

2.28

4.57

+0.08

-0.04

0.9

2.3

-0.10

+0.05

min0.51

±0.1

+0.08

-0.04

0.5

0...0.15

BA0.25

0.1

(4.17)

5.8

6.4

2.2

10.6

5.76

1.2

Figure 1 Heat Sink - vs. Thermal Enhanced Package Types

SMD-Package Properties for

Power Applications

There are two basic groups of

packages:

Heat Sink packages are the first

group.The heat sink (chip carrier -

lead frame) is soldered directly to

the PCB. The thermal resistance

of this packages between chip

and heat sink is called Rthj-c

(junction-case) and has low

values.

Thermal Enhanced Leadframes

constitute the second group of

packages. Metal bridges are

connected between the chip

carrier (lead frame) and the pins.

From the outside, this package

looks identical to standard

components because the plastic

molding compound conceals

these details. Figure 1 shows

both types of packages with the

examples P-TO252-3-1 (D-Pack)

and P-DSO-14-4 (3 center pins

each per side of the cooling path).

The internal structure is described

in more detail in this report and

can be seen in Figure 11.

Infineon Technologies AG6

Thermal Resistance - Theory and Practice

Using a printed circuit board

as a heat sink ?

How do I calculate that ?

How big does my heat sink

need to be ?

Which size do we need ?

In earlier fabrications, a solid heat

sink was either screwed or

clamped to the power package. It

was easy to calculate the thermal

resistance from the geometry of

the heat sink.

In SMD-technology, this

calculation is much more difficult

because the heat path must be

evaluated: chip (junction) - lead

frame - case or pin - footprint -

PCB materials (basic material,

thickness of the laminate) - PCB

volume - surroundings.

As the layout of the PCB is a main

contributor to the result, a new

technique must be applied. The

Appendix proivdes thermal data for

all packages listed in Table 1.

Let us start with some

theoretical considerations:

Static Properties

To facilitate discussion of the

static properties of a Power IC

(PIC), the internal structure of a

PIC and its method of mounting

on a PCB or heat sink is

illustrated in Figure 2. The PIC

consists of a chip mounted on a

chip carrier or lead frame, and

held by solder or bonding

adhesive. The lead frame consists

of a high-conductivity material

such as copper, and can have a

Table 1 The Most Important

SMD-Packages

Package Heat Sink / Pin

P-DSO-8-1 –

P-DSO-14-4 Pin 3-5; 10-12

P-DSO-16-1 –

P-DSO-20-1 –

P-DSO-20-6 Pin 4-7; 14-17

P-DSO-24-3 Pin 5-8; 17-20

P-DSO-28-6 Pin 6-9; 20-23

P-DSO-20-10 Tab

P-DSO-36-10 Tab

P-TO252-3-1 (D-Pack)

SCT-595-5-1 Pin 2; 5

SOT-223-4-2 Tab or Pin 4

P-TO263-5-1 Tab

Tab

Infineon Technologies AG 7

thickness of several millimeters.

The associated static equivalent

circuit is shown in Figure 3. The

following analogies with electrical

quantities have been used:

CThe power dissipation PV

occurring close to the chip

surface is symbolized by a

current source.

CThe thermal resistances are

represented by ohmic

resistors. The “resistance”

network is essentially a serial

connection to the ambient

temperature. As a first

approximation, the parallel-

connected thermal resistance

of the molding (broken lines)

can be neglected in power

packages.

CThe ambient temperature is

represented by a voltage

source.

In accordance with the analogy,

the thermal current PV= Q/tcan

now be calculated from the

“thermic Ohm’s law”

V= I•Ras Tj- Ta= PV•Rthj-a.

For the purpose of discussing the

application as a whole, the

function PV= ƒ(Ta) is of practical

interest. One obtains:

PV= - Ta/ Rthj-a + Tj/ Rthj-a.

This is a descending straight line

of gradient -1 / Rthj-a with its zero

at Tj.

Figure 2 Internal Structure of

a PIC and Method of

Mounting on

a Heat Sink

Chip (Die)

Molding compound

(Molding)

Heat sink or PCB

(Heat sink)

Chip adhesive / Lot

(Die bond)

Chip carrier

(Leadframe)

Solder

PVTjTa

Die

bond

Die Lead-

frame Solder Heat

sink

Rth

Molding

Rth Rth

Rthj-c

Rthj-a

Rth

Application

Rth Rth Rth

Figure 3 Static Equivalent

Circuit for the

Structure

shown in Figure 2

Infineon Technologies AG8

Thermal Resistance - Theory and Practice

In Figure 4, this function is

shown for the P-DSO-14-4 Pack-

age (Thermal Enhanced Power

Package) mounted on the

standard application board. From

this function, the user can derive

the permissible power dissipation

directly for any ambient

temperature. At Ta= 85 °C, for

example, the permissible

dissipation is approxi-

mately

0.7 W. The exact value can

calculated from the equation

PV= (Tj- Tamax) / Rthj-a =

65 K / 92 K/W = 0.7 W.

It should be noted that in the data

sheets of the PICs the power

dissipation is given as a function

of the package (case) tempera-

ture TC, because the application-

specific thermal resistances are

not known to the manufacturer.

This function, like the previous

one, is a descending straight line.

The slope now has the value

1 / Rthj-c. The zero remains at Tj.

As an example, this function is

presented in Figure 5 for the

P-TO252-3-1 Package.

The new P-TO252-3-1 package

has a thermal resistance of max.

4 K/W and is unique in the small

size of its base area when com-

pared with packages of equivalent

performance (PCB board area). At

approximately 30 °C, the permis-

sible power dissipation is 30 W.

Higher power dissipation is

prevented by intervention of the

chip-internal current limiters. For

this reason, the value for power

dissipation at lower temperatures

remains constant. Figure 5 Permissible Power Dissipation of

the P-TO252-3-1 as a Function of

the Package (Case) Temperature

Figure 4 Permissible Power Dissipation of the

P-DSO-14-4 Package Mounted on a

PCB with 300 mm² Cooling Area, as

a Function of Ambient Temperature

0TC

˚C150100500

Rthj-c = 4 K/W

W ≈ 1.63 W

150 ˚C100500

0.54

1.08

1.63

∆PV = 1 W

∆T = 92 ˚C

Parameter: Tjmax = 150 ˚C

Rthj-a = 92 K/W

Tamax = 85 ˚C

Tamax

Rthj-a

PVO = 150

Infineon Technologies AG 9

Dynamic Properties

As mentioned earlier, the thermal

behavior of PICs changes when

dynamic phenomena are

considered (pulse power

operation). This behavior can be

described in terms of thermal

capacity Cth, which is directly

proportional to the relevant

volume V(in cm³), to the density

ρ(in g/cm³) of the material and to

a proportionality factor of the

specific heat cin Ws/g •K.

The applicable equation is:

Cth = c •ρ•V= m•c

This means: The thermal capacity

of a body of mass m= ρ•V

corresponds to the quantity of heat

needed to heat the body by 1 °C.

To calculate the temperature

change ∆Tit is necessary to use

the quantity-of-charge equation

for a capacitance C.

The equation is:

V•C= I •t= Q

By analogy, the quantity-of-heat

equation is:

∆T•Cth = P •t= Q

This means: Just as the current

I= Q/trepresents a transport of

charge per unit of time, the

power dissipation Prepresents

the transport of thermal energy

per unit of time. Consequently:

∆T=

The equivalent circuit of the

P-TO263-7-3 power package, with

the thermal capacities added, is

shown in Figure 6. The thermal

capacities calculated from the

material and the volume are

shown in parallel with the thermal

resistances.

When calculating the components

of a network it is necessary to

know the thickness d, the cross-

sectional area Aand the thermal

conductivity Lin W/m •K, in order

to obtain the appropriate thermal

resistance Rth. The formula is:

Rth =

]

[

L•A

P •t

Cth

Figure 6 Thermal Equivalent

Circuit of the

P-TO263-7-3 Package

(Simplified)

3 mWs/K 300 mWs/K

0.24 K/W0.48 K/W

Heat sink

RthD RthHS

τHS = 70 msτD = 1.5 ms

CthD

PVTcase

Die

CthHS =

Infineon Technologies AG10

Thermal Resistance - Theory and Practice

8˚ max.

BA0.25

0.1 Typical

9.8 ±0.15

±0.2

8.51)

81)

(15)

±0.2

9.25 ±0.3

0...0.15

7x0.6 ±0.1

±0.1

1.27 4.4 Footprint

0.5

±0.1

±0.3

2.7

4.7±0.5

0.05

0.1

All metal surfaces tin plated, except area of cut.

±0.3

1.3

2.4

6x1.27

8.42

10.8

9.4

16.15

4.6

0.47

0.8

To calculate the thermal capacity

Cth, it is necessary to know the

volume V= d•A, the specific

weight ρin g/cm3 and the speci-

fic thermal capacity cin Ws/g •K.

The thermal capacity Cth is

calculated from:

Cth = m•c(Ws/T).

The package dimensions are

shown in Figure 7.

Table 2 lists all the important

parametric data of the

P-TO263-7-3 package.

Figure 7 Outline Drawing of the P-TO263-7-3 Power Package

Table 2 Parametric Data of the P-TO263-7-3

AHS

Area (effective area of 64 mm²)

dHS

Thickness

LCu

Thermal conductivity of cooper

RthHS

Thermal resistance of heat slug ρCu

Specific weight of cooper

mHS

Mass of heat slug

cCu

Spec, thermal capacity of Cu

CthHS

Thermal capacity of heat slug τHS

Thermal time constant of heat slug

Symbol

1.27

384

0.24

8.93

0.8

0.385

310

Value

mm²

W/m

•

K/W

g/cm³

Ws/g

•

mWs/K

Dimension

Parameters for the Heat Slug

Area

Thickness

LSi

Thermal conductivity of silicon

RthD

Thermal resistance of chip ρSi

Specific weight of silicon

Mass of chip

cSi

Spec, thermal capacity of Si

CthD

Thermal capacity of chip τD

Thermal time constant of chip

Symbol

360

150

0.48

2.33

4.2

approx. 0.7

approx. 3

approx. 1.5

Value

mm²

µm

W/m

•

K/W

g/cm³

Ws/g

•

mWs/K

Dimension

Parameters for the Chip

Infineon Technologies AG 11

The die bond and molding

components have been omitted

from this discussion because they

do not significantly influence the

calculation of Rthj-c.

For reference, these data are

listed here:

CRthDB = 0.01 to 0.1 K/W;

CCthDB = 0.1 to 0.5 mWs/K;

DB = 1 to 50 ms;

CRthM = 100 K/W;

CCthM = 0.64 Ws/K and

M= 64 s.

(Die Bond = index: DB;

molding = index: M)

The time constance of the die

bond is smaller than that of the

chip by two orders of magnitude

and can, thus, be neglected.

The thermal resistance RthM of

the molding is even three orders

of magnitude bigger than that of

the chip and that of the heat slug,

and, being in parallel, can be

neglected also.

Pulse operation and the associat-

ed chip temperature responses

also deserve examination.

In accordance with the analogy to

electrical systems, the chip tem-

perature response can be viewed

like a voltage increase across an

RC section which is being fed by

a current pulse generator.

The following relationship applies:

V(t) = R•I•(1 - et/R • C)

and for the increase in tempera-

ture:

T(t) = Rth •P•(1 - et/Rth • Cth)

This heating-up and cooling-down

process is presented qualitatively

in Figure 8 (valid for tp>> 2 ms

only).

The chip temperature goes up

and down between Tmin and Tmax.

The variation depends on the

magnitude of the power pulse

and its duty cycle.

Figure 8 Chip Temperature Tj

vs. Time, for Periodic

Pulse Operation

Tmax

Tmin

Tavg

Infineon Technologies AG12

Thermal Resistance - Theory and Practice

This junction temperature

transients can be represented in

the form of a function if the

dynamic thermal impedance

Zth = (Tmax - Tmin) / PV

is shown versus pulse width tpfor

different duty cycles (duty cycle =

DC = tp/T) (Figure 9).

A special case of this representa-

tion is the dynamic thermal

impedance in single-pulse

operation (DC = 0). Figure 10

shows the thermal impedance in

single-pulse operation for the

medium-power package

P-DSO-14-4 for three different

cooling areas on the PCB.

This function clearly shows the

regions of dominance of the

various time constants of the

chip, the lead frame, and the

PCB.

The chip time constant tDlies in

the millisecond range, whereas

the lead frame dominates in the

range of several 100 ms and the

PCB in the 100-second range.

single pulse

0.50

D =

0.20

0.10

0.05

0.02

0.01

10 -4 -7

Zthj-c

10-6 10-5 10-4 10-3 10-2 10-1 s 100

-3

-2

-1

K/W

Figure 9 Dynamic Thermal

Impedance Zthj-c of a

P-TO263-7-3 Package

-3

100

120

-2

-1

600 mm

300 mm

Footprint

thj-a

K/W

Figure 10 Thermal Impedance of the

P-DSO-14-4 Package for

Single-Pulse Operation

Infineon Technologies AG 13

Finite Element Method (FEM)

The steps of the Finite Element

Method (FEM) are explained

below and one example is

provided per group.

The geometric data of the

package is entered into the FEM

model to calculate the thermal

resistance. This avoids time-

consuming measurements.

Figure 11 shows an implemented

model.

Figure 11

P-TO252-3-1 P-DSO-14-4

FEM Model of Heat Sink and

Thermal Enhanced Package

Infineon Technologies AG14

Thermal Resistance - Theory and Practice

Figure 12

The temperatures of the

individual components (chip, die-

pad, molding compound, and

leadframe) can be viewed

individually or in combination

(Figure 12).

Chip with two active areas (dice only) Mold compound without cooling

tab,chip and lead frame

P-TO252-3-1 without mold compound

with

= 3 W for determining the

Rthj-c

Chip and lead frame of the

SOT223-4-2 package on a PCB

with heat sink

Lead frame of the SCT595-5-1 on a

PCB with heat sink

SOT223-4-2 on a PCB with 6 cm²

heat sink; Rthj-a ~ 70 K/W is calculated

at PV= 0.5 W

FEM Analysis Possibilities

Infineon Technologies AG 15

Three different PCBs have been

created for each package model.

They differ in the size of the

copper laminated area A (heat

sink) which is linked to the heat

dissipating parts of the case (die-

pad in the P-TO252-3-1 or center

pins in the P-DSO-14) (Figure 13).

1 1

P-DSO-14-4

123

6 cm² 3 cm² Footprint only

P-DSO-14-4P-DSO-14-4

Application-Board for

Measurement

-P-DSO-14-4 LP 1.0

Application-Board for

Measurement

-P-TO252-3-1 LP 1.1

-16-1

a/2 0.375

0.67

P-TO252-3-1

1IQ 1

P-TO252-3-1

I Q

P-TO252-3-1

1I Q

123

Footprint only

6 cm² 3 cm²

a/2

Figure 13 PCB-Layout for FEM-Simulation

P-DSO-14-4 and P-TO252-3-1

Infineon Technologies AG16

Thermal Resistance - Theory and Practice

Determining the Static Heat

Resistance

The FEM simulation calculates

the thermal static resistance Rthj-a

(junction-ambient) and the Rthj-c

(junction-case) for packages with

enhanced die-pad or Rthj-pin

(junction to a defined pin) for

thermal enhanced P-DSO

packages without die-pad. This

value depends only slightly on the

active chip area. It is sufficient to

simulate just one medium-sized

chip (>2 mm²).

If the static thermal resistance

Rthj-a is applied versus the PCB

heat sink area, a very important

function is obtained for the

application of the component. By

estimating the heat sink area in a

real application, the user can

easily determine the expected

Rthj-a, especially as the simulated

values are calculated in still air.

Therefore, they represent the

“worst case“. In real applications

the values for the heat resistance

are much lower. At an air stream

of 500 lin ft/min (linear feet per

minute) the Rthj-a of the

P-DSO-14-4 for example is up to

15 % lower (Figure 15).

thj-pin

= 31.7 K/W

thj-a

100

K/W

120

100 200 300 400 500 600mm

0 100 200 300 400 500 mm

600

thj-a

100

120

K/W

160

thj-c

= 1.8 K/W

P-DSO-14-4 P-TO252-3-1

112

143.9

54.7

Figure 14 Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A at zero airflow

Airspeed Airspeed

thj-a

100

110

K/W

120

100 200 300 400 600m/min m/min0 50 100 150 200

100

120

140

160

thj-a

K/W

P-DSO-14-4 P-TO252-3-1

Footprint only

= 300 mm

= 600 mm

Footprint only

= 300 mm

= 600 mm

Figure 15 Thermal Resistance Junction to Ambient Rthj-a vs.

Airspeed for the P-DSO-14-4 and P-TO252-3-1 Packages

Infineon Technologies AG 17

Measuring the Rthj-a in a

Real Application:

Using the measurement described

below the real thermal resistance

can be determined.

To determine the actual Rthj-a the

temperature difference between

chip temperature Tj and ambient

temperature Tais required. The

equation Rthj-a = applies.

The power loss PVand the ambient

temperature Tacan be determined

easily in a temperature chamber or

calculated.

To measure the chip temperature

(Tj) requires a little trick:

A temperature sensor is required

on the chip which can also be read

during operation. In many products

a substrate diode can be used at

an output (Status, Reset, etc.) to

measure the chip temperature.

To do this, the forward voltage VF

of the diode is measured at load

independent current as a

calibration curve. Due to the

characteristic temperature behavior

of the forward voltage - it has a

negative temperature coefficient of

approx. -2 mV/K - the relevant chip

temperature can be determined.

The calibration curve is measured

in the temperature chamber with

airflow. The power loss should be

kept as low as possible to ensure

the chip temperature remains

equal to the ambient temperature.

For the voltage regulator

TLE 4269 GM (P-DSO-14-4 Package)

a calibration curve (measured at

the diode at the reset output, pin 7).

RO is illustrated in Figure 16.

Figure 17 shows the

corresponding measuring circuit.

Tj-Ta

Figure 16 Calibration Curve TLE 4269 GM for IRO = -500 µA

(current drawn from Pin 7; RO)

100

200

300

400

500

600

700

50 100 150

˚C

Infineon Technologies AG18

Thermal Resistance - Theory and Practice

The Rthj-a of any application can be

determined by measuring the

forward voltage of an output with

substrate diode during operation

(Figure 17).

When the switch S1 is closed and

the output voltage VQ= 5 V, the

output current is A.

The power loss PV= (VI- VQ) •IQ

in the chip of the voltage

regulator is now 1 W. Now,

change the ambient temperature

Taand measure the respective

forward voltage VFof the diode.

The appropriate Tjfor every VF

value can be read from the

calibration curve VF= ƒ(Tj).

The exact heat resistance of the

real application is calculated with

this values in the formula

Rthj-a =

Parameters such as air flow can

be changed without affecting the

measuring accuracy.

Tj-Ta

Figure 17 Measuring Circuit

with TLE 4269GM

100 k

Ω

Substrat

diode

of T

TLE 4269 GM

Power

P-DSO-14-4

= 12 V

~ 0.7 V

~ 500

–

Ω

3-5; 10-12

50 V

20 k

Ω

1. Measurement of function VF =

(Ta):

S1 open; we get IQ = 0 mA

and PV = VI * II ~ 0 mW

Ta ~ Tj

2. Measurement of thermal resistance junction to ambient Rthj-a:

S1 closed; we get IQ = VQ / RQ

and PV = (VI - VQ) * IQ ~ 1 W

Tj then can be found by measuring VF at given Ta from function VF vs. Ta

then we get Rthj-a = (Ta - Tj) / 1 W

= Power losses

= Ambient temperature

= Junction temperature

Infineon Technologies AG 19

Determining the Dynamic

Heat Resistance

The FEM analysis is used also for

dynamic processes.

As described above, the dynamic

thermal impedance is defined as

the ratio of the temperature

difference ∆T= Tj- Ta(chip tem-

perature - start temperature) after

the time tpto the power loss.

If a transient FEM simulation is

performed, it is easy to obtain the

graph Zthj-a = ƒ(tp) (dynamic

thermal impedance as a function

of the pulse width tp).

For the P-TO252-3-1 (D-Pack) and

the P-DSO-14-4 the thermal

impedances for the above-

mentioned PCB configurations are

specified (Figure 18).

The peak temperatures can be

calculated easily from these

curves:

– P-TO252-3-1 (D-Pack)

– 3 cm² heat sink

– Power loss PV= 10 W

– Pulse width tp= 200 ms

– Ambient temperature

Ta= 85 °C.

From the middle curve (Figure 18),

the Zthj-a of approximately 3.5 K/W

at tp= 200 ms gives a tem

pera-

ture rise ∆T= PVx Zthj-a of 35 K

and finally a peak temperature

Tjmax of 85 °C+35 °C = 120 °C.

Figure 18 Thermal Impedance

Junction to Ambient

Zthj-a vs. Single

Pulse Time tp

thj-a

-3

-2

-1

120

K/W

100

Footprint

300 mm

600 mm

P-DSO-14-4 P-TO252-3-1

thj-a

600 mm

300 mm

160

K/W

120

100

Footprint

-3

-2

-1

Infineon Technologies AG20

Thermal Resistance - Theory and Practice

For each case listed in Table 1,

a „Package and Thermal

Information“ data sheet is

provided in the appendix.Each

data sheet shows the footprint

and case dimensions. The various

versions of the PCBs used for the

simulation are shown. It shows

the heat distribution diagrams and

the result diagrams of the FEM

simulation. The left side shows

the diagram of the static thermal

resistance Rthj-a depending on the

PCB heat sink area A. It includes

the related thermal resistance

Rthj-c (junction-case) or Rthj-pin.

On the right side is the diagram

for the dynamic heat resistance

Zthj-a, with three graphs for the

various PCB heat sinks depending

on the single pulse duration tp.

This information is a valuable aid

for SMD Power applications. It is

intentionally limited to PCBs

laminated on one side because it

represents the cost optimum. For

double sided PCBs or multilayers

a simple attempt with

conductance cross sections can

be made to determine the change

in the PCB thermal resistance

(compare

thermal data sheet of

P-DSO-20-10

with P-DSO-36-10 in

the appendix).

The PCBs are usually installed in

closed plastic cases. The most

favorable heat path then usually

forms at plug contacts to the

cables because a supply wire

with an adequate cross section is

ideal as a heat conductor.

The future of chip placement

requires mechatronic solutions

where the PCB can be replaced

by chip-connector-supply wire

configurations.

Summary

Infineon Technologies AG 21

P-DSO-8-1 22

P-DSO-14-4 23

P-DSO-16-1 24

P-DSO-20-1 25

P-DSO-20-6 26

P-DSO-24-3 27

P-DSO-28-6 28

P-DSO-20-10 29

P-DSO-36-10 30

SCT595-5-1 31

SOT223-4-2 32

P-TO252-3-1 33

P-TO263-5-1 34

Package and Thermal Information

Appendix

Infineon Technologies AG22

111

123

P-DSO-8-1

6 cm² 3 cm² Footprint only

P-DSO-8-1 P-DSO-8-1

a/2

0.375

0.67

0.375

a/2

FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 600 mm²; a = 17.32 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 300 mm²; a = 12.247 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

Footprint only

1.27

0.2

1.75 max.

-0.1

-0.2

±0.2

0.19

+0.06

0.1 0.4

+0.8

0.35 x 45˚

Index Marking

+0.15

0.35

0.2 8x

-0.2

1.45

8 max.

Package

Reflow soldering

1.27P-DSO-8-1

5.69

1.31

0.65

Dimensions in mm

100

thj-a

100 200 300 400 500 600mm

thj-a

-3

-2

-1

K/W

110

120

130

140

150

160

170

190

100

120

140

160

200

600 mm

300 mm

Footprint

164

185

142

thj-pin2

= 71.8 K/W

Footprint/Dimensions

PC-Board

Finite Element Method

Diagrams

P-DSO-8-1

Infineon Technologies AG22

A = 600 mm²; Ta= 298 K; Tmax = 369 K

FEM Simulation (chip area ≥2 mm²; Pv= 0.5 W; zero airflow)

Application-Boards for Rth - Measurement

Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A(zero airflow)

Thermal Impedance Junction to Ambient Zthj-a vs.

Single Pulse Time tp(zero airflow)

A = 300 mm²; Ta= 298 K; Tmax = 380 K Footprint only; Ta= 298 K; Tmax = 390 K

Infineon Technologies AG 23

1 1

P-DSO-14-4

1 2 3

6 cm² 3 cm² Footprint only

P-DSO-14-4P-DSO-14-4

FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 600 mm²; a = 17.32 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 300 mm²; a = 12.247 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

Footprint only

-16-1

a/2 0.375

0.67

1.27

1.45

-0.2

1 7

8.75

-0.2

14 8

1.75 max.

0.2

±0.2

0.35 x 45˚

-0.2

0.1

-0.1

0.4 GND GND

+0.8

Index Marking

+0.15

0.35

0.2 14x

0.19

+0.06

8 max.

Package

1.27P-DSO-14-4

5.69

1.31

0.65

Reflow soldering Dimensions in mm

thj-a

120

K/W

100 Footprint

300 mm

600 mm

thj-pin4

= 31.7 K/W

112

thj-a

100

K/W

120

100 200 300 400 500 600mm

-3

-2

-1

Package and Thermal Information

Footprint/Dimensions

P-DSO-14-4

PC-Board

Finite Element Method

Diagrams

Infineon Technologies AG 23

A = 600 mm²; Ta= 298.1 K; Tmax = 377.7 K

FEM Simulation (chip area ≥2 mm²; Pv= 1 W; zero airflow)

Application-Boards for Rth - Measurement

Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A(zero airflow)

Thermal Impedance Junction to Ambient Zthj-a vs.

Single Pulse Time tp(zero airflow)

Footprint only; Ta= 298 K; Tmax = 410.1 KA = 300 mm²; Ta= 298 K; Tmax = 389.8 K

Infineon Technologies AG24

P-DSO-14-4

Footprint only

FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

Footprint only

-16-1

Package

Reflow soldering

1.27P-DSO-16-1

5.69

1.31

0.65

1.27

1.45

-0.2

16 9

1.75 max.

0.2

±0.2

0.35 x 45˚

-0.2

0.1

-0.1

0.4

+0.8

Index Marking

+0.15

0.35

0.2 16x

0.19

+0.06

8 max.

Dimensions in mm

thj-pin4

= 48.2 K/W

thj-a

Footprint

100

110

K/W

130 121

100

K/W

140

100 200 300 400 500 600mm

-3

-2

-1

Infineon Technologies AG24

Footprint/Dimensions

PC-Board

Finite Element Method

Diagrams

P-DSO-16-1

Footprint only; Ta= 298 K; Tmax = 419.1 K

FEM Simulation (chip area ≥2 mm²; Pv= 1 W; zero airflow)

Application-Board for Rth - Measurement

Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A(zero airflow)

Thermal Impedance Junction to Ambient Zthj-a vs.

Single Pulse Time tp(zero airflow)

Infineon Technologies AG 25

FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

Footprint only

P-DSO-20-1

-24-3

-28-6

-20-6

Package

1.27P-DSO-20-1

9.73

1.67

0.65

Reflow soldering

1 10

1120

Index Marking

2.65 max.

0.1

0.2

-0.1

2.45

-0.2

+0.15

0.35

1.27

0.2 20x

-0.2

7.6

0.35 x 45˚

0.23

+0.8

10.3

0.4

12.8

-0.21)

+0.09

±0.3

8˚max.

Dimensions in mm

thj-pin5

= 43.6 K/W

thj-a

100

K/W

120

thj-a

K/W

120

Footprint

109

100 200 300 400 500 600mm

-3

-2

-1

Package and Thermal Information

Infineon Technologies AG 25

Footprint/Dimensions

P-DSO-20-1

PC-Board

Finite Element Method

Diagrams

Footprint only; Ta= 298 K; Tmax = 407 K

FEM Simulation (chip area ≥2 mm²; Pv= 1 W; zero airflow)

Application-Board for Rth - Measurement

Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A(zero airflow)

Thermal Impedance Junction to Ambient Zthj-a vs.

Single Pulse Time tp(zero airflow)

FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 600 mm²; a = 17.32 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 300 mm²; a = 12.247 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

Footprint only

1 1 1

1 3

a/2

6 cm² Footprint only

P-DSO-20-6

-24-3

-28-6

3 cm²

P-DSO-20-1

-24-3

-28-6

-20-6

-28-6

-24-3

P-DSO-20-6

a/2

0.3

a0.375 0.375

0.3

GND GND

Package

1.27P-DSO-20-6

9.73

1.67

0.65

Reflow soldering

1 10

1120

Index Marking

2.65 max.

0.1

0.2

-0.1

2.45

-0.2

+0.15

0.35

1.27

0.2 20x

-0.2

7.6

0.35 x 45˚

0.23

+0.8

10.3

0.4

12.8

-0.21)

+0.09

±0.3

8˚max.

Dimensions in mm

thj-pin5

= 22.9 K/W

thj-a

K/W

120

K/W

110 100

81 600 mm

300 mm

Footprint

100 200 300 400 500 600mm

-3

-2

-1

Infineon Technologies AG26

Footprint/Dimensions

PC-Board

Finite Element Method

Diagrams

P-DSO-20-6

A = 600 mm²; Ta= 298 K; Tmax = 372 K

FEM Simulation (chip area ≥2 mm²; Pv= 1 W; zero airflow)

Application-Boards for Rth - Measurement

Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A(zero airflow)

Thermal Impedance Junction to Ambient Zthj-a vs.

Single Pulse Time tp(zero airflow)

A = 300 mm²; Ta= 298 K; Tmax = 379 K Footprint only; Ta= 298 K; Tmax = 397 K

FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 600 mm²; a = 17.32 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 300 mm²; a = 12.247 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

Footprint only

1 1 1

1 3

a/2

6 cm² Footprint only

P-DSO-20-6

-24-3

-28-6

3 cm²

P-DSO-20-1

-24-3

-28-6

-20-6

-28-6

-24-3

P-DSO-20-6

a/2

0.3

a0.375 0.375

0.3

Package

Reflow soldering

1.27P-DSO-24-3

9.73

1.67

0.65

15.6-0.4

24 13

1 12

Index Marking

0.35+0.15 0.2 24x

-0.2

2.65 max.

0.1

0.2 -0.1

2.45

-0.2

7.6

0.35 x 45˚

0.23

+0.09

10.3

GND GND

0.4 +0.8

1.27

2) ±0.3

8˚max.

Dimensions in mm

thj-a

K/W

76.4

67.4

60.5

K/W

thj-pin6

= 20.5 K/W

600 mm

300 mm

Footprint

100 200 300 400 500 600mm

-3

-2

-1

Infineon Technologies AG 27

A = 600 mm²; Ta= 298 K; Tmax = 358 K

FEM Simulation (chip area ≥2 mm²; Pv= 1 W; zero airflow)

Application-Boards for Rth - Measurement

Package and Thermal Information

Footprint/Dimensions

P-DSO-24-3

PC-Board

Finite Element Method

Diagrams

Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A(zero airflow)

Thermal Impedance Junction to Ambient Zthj-a vs.

Single Pulse Time tp(zero airflow)

A = 300 mm²; Ta= 298 K; Tmax = 365 K Footprint only; Ta= 298 K; Tmax = 374 K

FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 600 mm²; a = 17.32 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 300 mm²; a = 12.247 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

Footprint only

1 1 1

1 3

a/2

6 cm² Footprint only

P-DSO-20-6

-24-3

-28-6

3 cm²

P-DSO-20-1

-24-3

-28-6

-20-6

-28-6

-24-3

P-DSO-20-6

a/2

0.3

a0.375 0.375

0.3

Package

1.27P-DSO-28-6

9.73

1.67

0.65

Reflow soldering

1 14

1528

18.1-0.4

Index Marking

2.45

-0.1

0.2

2.65 max.

-0.2

0.1

0.2 28x

8˚max.

+0.09

0.23

7.6 1)

-0.2

0.35 x 45˚

10.3

+0.8

±0.3

0.4

1.27

+0.15

0.35 2)

GND GND

Dimensions in mm

thj-pin7

= 20.1 K/W

thj-a

K/W

600 mm

300 mm

Footprint

61.4

100 200 300 400 500 600mm

-3

-2

-1

Infineon Technologies AG28

Footprint/Dimensions

PC-Board

Finite Element Method

Diagrams

P-DSO-28-6

A = 600 mm²; Ta= 298 K; Tmax = 349 K

FEM Simulation (chip area ≥2 mm²; Pv= 1 W; zero airflow)

Application-Boards for Rth - Measurement

Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A(zero airflow)

Thermal Impedance Junction to Ambient Zthj-a vs.

Single Pulse Time tp(zero airflow)

Footprint only; Ta= 298 K; Tmax = 359 KA = 300 mm²; Ta= 298 K; Tmax = 354 K

Infineon Technologies AG 29

11 1

1 3

6 cm² Footprint only

3 cm²

P-DSO-20-10P-DSO-20-10P-DSO-20-10

0.375

a/2

0.3

a/2

0.375

0.3

FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 600 mm²; a = 17.32 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 300 mm²; a = 12.247 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

Footprint only

Package

1.27P-DSO-20-10

13.48

1.83

0.68

Reflow soldering

+0.07

-0.02

-0.3

1.2 2.8

1.3

0.25

20x0.25 M

Heatsink

0.95

14.2

+0.15

Index

Marking

15.9

101

0.1

+0.13

0.4

1.27

3.5 max.

6.3

3.25

20 11

±0.15

±0.1

±0.15

1 x 45˚

±0.3

5˚±3˚

±0.15

15.74 ±0.1

1) B

0.25 MB

(Heatsink)

GND

Dimensions in mm

thj-c

= 2.4 K/W

thj-a

600 mm

300mm

Footprint

60 K/W

K/W

100 200 300 400 500 600mm

-3

-2

-1

A = 600 mm²; Ta= 298 K; Tmax = 406 K

FEM Simulation (chip area ≥2 mm²; Pv= 3 W; zero airflow)

Application-Boards for Rth - Measurement

Package and Thermal Information

Footprint/Dimensions

P-DSO-20-10

PC-Board

Finite Element Method

Diagrams

Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A(zero airflow)

Thermal Impedance Junction to Ambient Zthj-a vs.

Single Pulse Time tp(zero airflow)

Footprint only; Ta= 298 K; Tmax = 463 KA = 300 mm²; Ta= 298 K; Tmax = 421 K

Infineon Technologies AG30

P-DSO-36-10 P-DSO-36-10

FR4; 47

1.5 mm; 70 µ Cu

A = 600 mm²; 24.5 x 24.5 mm FR4; 47

1.5 mm; 70 µ Cu

A = 300 mm²; 16 x 19 mm

Package

Reflow soldering

0.65P-DSO-36-10

13.48

1.83

0.45

+0.07

-0.02

±0.1

1.1 2.8

1.3

0.25

36x0.25

Heatsink

0.95

14.2

+0.1

Index

Marking

15.9

181

0.1

+0.13

0.25

0.65

3.5 max.

6.3

3.25

36 19

±0.15

±0.1

±0.15

1 x 45˚

±0.3

5˚

±3˚

±0.15

15.74 ±0.1

1) B

0.25 B

(Heatsink)

GND

Dimensions in mm

Rthj-c = 2 K/W

Rthj-a

K/W

36.8

28.6

Zthj-a

100 200 300 400 500 600mm

-3

-2

-1

K/W

600 mm2

300 mm2

Infineon Technologies AG30

Footprint/Dimensions

PC-Board

Finite Element Method

Diagrams

P-DSO-36-10

A = 600 mm²; Ta= 298 K; Tmax = 398 K A = 300 mm²; Ta= 298 K; Tmax = 427 K

FEM Simulation (chip area ≥2 mm²; Pv= 3.5 W; zero airflow)

Application-Boards for Rth - Measurement

Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A(zero airflow)

Thermal Impedance Junction to Ambient Zthj-a vs.

Single Pulse Time tp(zero airflow)

Infineon Technologies AG 31

1 1 1

1 3

6 cm² Footprint only

3 cm²

SCT595

INH

I Q

GND

SCT595 SCT595

a0.375

0.3a/2

0.375

0.3

a/2

FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 600 mm²; a = 17.32 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 300 mm²; a = 12.247 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

Footprint only

Reflow soldering

acc. to

+0.2

1.9

0.6

-0.05

+0.1

-0.05

0.3

0.25

1.1 max

2.6 max

10˚max

0.1 max

0.20

2.9

±0.2

1.6

±0.1

DIN 6784

(2.2)

(0.3)

1.2

-0.05

+0.1

321

0.95

-0.06

+0.1

0.15

10˚max

0.95

1.9

0.5

2.9

1.4

0.8

GND

Dimensions in mm

thj-pin5

= 25.9 K/W

thj-a

600 mm

300 mm

100

120

140

160

K/W

200

Footprint

100

120

140

160

K/W

200

178.7

98.5 87

100 200 300 400 500 600mm

-3

-2

-1

Package and Thermal Information

Infineon Technologies AG 31

Footprint/Dimensions

SCT595-5-1

PC-Board

Finite Element Method

Diagrams

A = 600 mm²; Ta= 298 K; Tmax = 315 K

FEM Simulation (chip area ≥2 mm²; Pv= 0.2 W; zero airflow)

Application-Boards for Rth - Measurement

Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A(zero airflow)

Thermal Impedance Junction to Ambient Zthj-a vs.

Single Pulse Time tp(zero airflow)

A = 300 mm²; Ta= 298 K; Tmax = 318 K Footprint only; Ta= 298 K; Tmax = 334 K

Infineon Technologies AG32

1 1 1

6 cm² Footprint only

3 cm²

SOT223SOT223SOT223

III

Q GND Q GND Q GND

a/2

0.3

a/2

0.3

FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 600 mm²; a = 24.49 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 300 mm²; a = 17.32 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

Footprint only

GND

Reflow soldering

±0.1

±0.2

±0.1

0.7

6.5

acc. to

+0.2

DIN 6784

1.6

±0.1

15˚max

±0.04

0.28

±0.3

±0.2

3.5

0.5

0.1 max

min

0.25

2.3

4.6

0.25

3.5

1.4

1.1 1.2

1.4 4.8

Dimensions in mm

thj-a

100

120

140

K/W

180

100

120

140

K/W

180

thj-pin4

= 16.5 K/W

600 mm

300 mm

Footprint

164.3

81.2 68

100 200 300 400 500 600mm

-3

-2

-1

Infineon Technologies AG32

Footprint/Dimensions

PC-Board

Finite Element Method

Diagrams

SOT223-4-2

A = 600 mm²; Ta= 298 K; Tmax = 332 K

FEM Simulation (chip area ≥2 mm²; Pv= 0.5 W; zero airflow)

Application-Boards for Rth - Measurement

Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A(zero airflow)

Thermal Impedance Junction to Ambient Zthj-a vs.

Single Pulse Time tp(zero airflow)

A = 300 mm²; Ta= 298 K; Tmax = 339 K Footprint only; Ta= 298 K; Tmax = 380 K

Infineon Technologies AG 33

P-TO252-3-1

1I Q 1

P-TO252-3-1

I Q

P-TO252-3-1

1I Q

1 2 3

Footprint only

6 cm² 3 cm²

a/2

FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 600 mm²; a = 24.49 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 300 mm²; a = 17.32 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

Footprint only

5.4

±0.1

1 3

-0.10

6.5

+0.15

±0.5

9.9

6.22

-0.2

±0.1

±0.15

0.8

0.15

±0.1

max

per side 0.75

2.28

4.57

+0.08

-0.04

0.9

2.3

-0.10

+0.05

min0.51

±0.1

+0.08

-0.04

0.5

0...0.15

BA0.25

0.1

(4.17)

Reflow soldering

5.8

6.4

2.2

10.6

5.76

1.2

GND

Dimensions in mm

thj-c

= 1.8 K/W

thj-a

600 mm

300 mm

160

K/W

120

100

120

K/W

160

Footprint

143.9

54.7

100 200 300 400 500 600mm

-3

-2

-1

Package and Thermal Information

Infineon Technologies AG 33

Footprint/Dimensions

P-TO252-3-1

PC-Board

Finite Element Method

Diagrams

A = 600 mm²; Ta= 298 K; Tmax = 353 K

FEM Simulation (chip area ≥2 mm²; Pv= 1 W; zero airflow)

Application-Boards for Rth - Measurement

Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A(zero airflow)

Thermal Impedance Junction to Ambient Zthj-a vs.

Single Pulse Time tp(zero airflow)

Footprint only; Ta= 298 K; Tmax = 442 KA = 300 mm²; Ta= 298 K; Tmax = 376 K

Infineon Technologies AG34

P-TO263-5-1

1 1 1

1 2 3

Footprint only6 cm² 3 cm²

P-TO263-5-1 P-TO263-5-1

a/2

FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 600 mm²; a = 24.49 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

A = 300 mm²; a = 17.32 mm FR4; 80

1.5 mm; 35 µ Cu, 5 µ Sn

Footprint only

Reflow soldering

8˚max.

BA0.25

0.1

±0.2

8.5

(15)

±0.2

9.25

±0.3

5x0.8

±0.1

1 5

±0.1

1.27

0.5

±0.1

±0.3

2.7

4.7

±0.5

0.05

GND

4x1.7

±0.1

4.4

±0.1

0.1

2.4

±0.1

7.9

1.1

0.6

10.8

9.4 16.15 4.6

Dimensions in mm

thj-c

= 1.3 K/W

thj-a

600 mm

300 mm

Footprint

K/W

85 90

K/W

78.4

52.4

100 200 300 400 500 600mm

-3

-2

-1

Infineon Technologies AG34

Footprint/Dimensions

PC-Board

Finite Element Method

Diagrams

P-TO263-5-1

A = 600 mm²; Ta= 298 K; Tmax = 417 K

FEM Simulation (chip area ≥2 mm²; Pv= 3 W; zero airflow)

Application-Boards for Rth - Measurement

Thermal Resistance Junction to Ambient Rthj-a vs.

PCB Heat Sink Area A(zero airflow)

Thermal Impedance Junction to Ambient Zthj-a vs.

Single Pulse Time tp(zero airflow)

A = 300 mm²; Ta= 298 K; Tmax = 455 K Footprint only; Ta= 298 K; Tmax = 533 K

Infineon Technologies AG’s sales offices worldwide –

partly represented by Siemens AG

Siemens AG Österreich

Erdberger Lände 26

A-1031 Wien

T(+43) 1-17 07-3 56 11

Fax (+43) 1-17 07-5 59 73

AUS

Siemens Ltd.

885 Mountain Highway

Bayswater, Victoria 3153

T(+61) 3-97 21 21 11

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Benelux

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Semiconductores

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CDN

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Halbleiter Distribution

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Dpto. Componentes

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T(+34) 91-5 14 71 51

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39/47, Bd. Ornano

F-93527 Saint-Denis CEDEX 2

T(+33) 1-49 22 31 00

Fax (+33) 1-49 22 28 01

FIN

Siemens Components

Scandinavia

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FIN-02601 Espoo (Helsinki)

T(+3 58) 10-5 11 51 51

Fax (+3 58) 10-5 11 24 95

Email:

scs@components.siemens.se

Infineon Technologies

Siemens House

Oldbury

GB-Bracknell, Berkshire

RG 12 8FZ

T(+44) 13 44-39 66 18

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Lajos u. 103

H-1036 Budapest

T(+36) 1-4 57 16 90

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Infineon Technologies

Hong Kong Ltd.

Suite 302, Level 3,

Festival Walk,

80 Tat Chee Avenue,

Yam Yat Tsuen,

Kowloon Tong

Hong Kong

T(+8 52) 28 32 05 00

Fax (+8 52) 28 27 97 62

Siemens S.p.A.

Semiconductor Sales

Via Piero e Alberto Pirelli, 10

I-20126 Milano

T(+39) 02-66 76 -1

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IND

Siemens Ltd.

Components Division

No. 84 Keonics Electronic City

Hosur Road

Bangalore 561 229

T(+91) 80-8 52 11 22

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Mumbai 400 018

T(+91) 22-4 96 21 99

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IRL

Siemens Ltd.

Electronic Components Division

8, Raglan Road

IRL-Dublin 4

T(+3 53) 1-2 16 23 42

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Nisko Ltd.

2A,Habarzel St.

P.O. Box 58151

61580 Tel Aviv – Isreal

T(+9 72) 3-7 65 73 00

Fax (+9 72) 3-7 65 73 33

Siemens Components K.K.

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3-20-14, Higashi-Gotanda,

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Tokyo

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Fax (+81) 3-54 49 64 01

MAL

Infineon Technologies AG

Sdn Bhd

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11900 Penang

T(+60) 4-6 44 99 75

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Scandinavia

Østre Aker vei 24

Postboks 10, Veitvet

N-0518 Oslo

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Fax (+47) 22-68 49 13

Email:

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Benelux

Postbus 16068

NL-2500 BB Den Haag

T(+31) 70-3 33 20 65

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Email: components@siemens.nl

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300 Great South Road

Greenland

Auckland

T(+64) 9-5 20 30 33

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an Componentes Electronicos

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Alfragide

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Co.Ltd.

PO Box 1129, Islamabad 44000

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Islamabad

T(+92) 51-21 22 00

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PL-03-821 Warszawa

T(+48) 22-8 70 91 50

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ROK

Siemens Ltd.

Asia Tower, 10th Floor

726 Yeoksam-dong, Kang-nam Ku

CPO Box 3001

Seoul 135-080

T(+82) 2-5 27 77 00

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RUS

INTECH electronics

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RUS-125 445 Moskva

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T (+46) 8-7 03 35 00

Fax (+46) 8-7 03 35 01

Email:

scs@components.siemens.se

Infineon Technologies

Asia Pacific Pte. Ltd.

Taiwan Branch

10F, No. 136 Nan King East Road

Section 23, Taipei

T(+8 86) 2-27 73 66 06

Fax (+8 86) 2-27 71 20 76

SGP

Infineon Technologies Asia

Pacific, Pte. Ltd.

168 Kallang Way

Singapore 349 253

T(+65) 8 40 06 10

Fax (+65) 7 42 62 39

USA

Infineon Technologies

Corporation

1730 North First Street

San Jose, CA 95112

T(+1) 4 08-5 01 60 00

Fax (+1) 4 08-5 01 24 24

Siemens Components, Inc.

Optoelectronics Division

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T(+1) 4 08-2 57 79 10

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Special Products Division

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T(+1) 7 32-9 06 43 00

Fax (+1) 7 32-6 32 28 30

VRC

Infineon Technologies

Hong Kong Ltd.

Beijing Office

Room 2106, Building A

Vantone New World Plaza

No. 2 Fu Cheng Men Wai Da Jie

100037 Beijing

T(+86) 10-68 57 90 -06, -07

Fax (+86) 10-68 57 90 08

Infineon Technologies

Hong Kong Ltd.

Chengdu Office

Room 14J1, Jinyang Mansion

58 Tidu Street

Chengdu,

Sichuan Province 610 016

T(+86) 28-6 61 54 46 / 79 51

Fax (+86) 28-6 61 01 59

Infineon Technologies

Hong Kong Ltd.

Shanghai Office

Room 1101, Lucky Target Square

No. 500 Chengdu Road North

Shanghai 200003

T(+86) 21-63 61 26 18/19

Fax (+86) 21-63 61 11 67

Infineon Technologies

Hong Kong Ltd.

Shenzhen Office

Room 1502, Block A

Tian An International Building

Renim South Road

Shenzhen 518 005

T(+86) 7 55-2 28 91 04

Fax (+86) 7 55-2 28 02 17

Siemens Ltd.

Components Division

P.O.B. 3438

Halfway House 1685

T(+27) 11-6 52 -27 02

Fax (+27) 11-6 52 20 42

06.10.99

Internet-address: http://www.infineon.com

Qualität hat für uns eine

umfassende Bedeutung.

Wir wollen allen Ihren

Ansprüchen in der

bestmöglichen Weise

gerecht werden. Es geht

uns also nicht nur um die

Produktqualität – unsere

Anstrengungen

gelten gleichermaßen der

Lieferqualität und Logistik,

dem Service und Support

sowie allen sonstigen

Beratungs- und Betreuungs-

leistungen.

Dazu gehört eine bestimmte

Geisteshaltung unserer

Mitarbeiter. Total Quality

im Denken und Handeln

gegenüber Kollegen,

Lieferanten und Ihnen,

unserem Kunden. Unsere

Leitlinie ist, jede Aufgabe

mit „Null Fehlern“ zu

lösen – in offener

Sichtweise auch über den

eigenen Arbeitsplatz

hinaus – und uns ständig

zu verbessern.

Unternehmensweit

orientieren wir uns dabei

auch an „top“ (Time

Optimized Processes), um

Ihnen durch größere

Schnelligkeit den

entscheidenden

Wettbewerbsvorsprung

zu verschaffen.

Geben Sie uns die Chance,

hohe Leistung durch

umfassende Qualität zu

beweisen.

Wir werden Sie überzeugen.

Quality takes on an all-

encompassing significance

at Semiconductor Group.

For us it means living up

to each and every one of

your demands in the best

possible way. So we are

not only concerned with

product quality. We direct

our efforts equally at

quality of supply and

logistics, service and

support, as well as all the

other ways in which we

advise and attend to you.

Part of this is the very

special attitude of our

staff. Total Quality in

thought and deed,

towards co-workers,

suppliers and you, our

customer. Our guideline is

“do everything with zero

defects”, in an open

manner that is

demonstrated beyond

your immediate

workplace, and to

constantly improve.

Throughout the

corporation we also think

in terms of

Time Optimized Processes

(top), greater speed on

our part to give you that

decisive competitive edge.

Give us the chance to

prove the best of

performance through the

best of quality – you will

be convinced.

Total Quality Management

Published by Infineon Technologies AG

Ordering No. B112-H7482-G1-X-7600

Printed in Germany

TB 01005. NB