FN8222 Rev 4.00 Page 1 of 12
Jan 11, 2019
FN8222
Rev 4.00
Jan 11, 2019
X9C102, X9C103, X9C104, X9C503
Digitally Controlled Potentiometer (XDCP™)
DATASHEET
The X9C102, X9C103, X9C104, X9C503 are digitally
controlled (XDCP) potentiometers. The device consists of a
resistor array, wiper switches, a control section, and
nonvolatile memory. The wiper position is controlled by a
three-wire interface.
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in non-volatile
memory and then be recalled upon a subsequent power-up
operation.
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications ranging from control to signal processing to
parameter adjustment.
Pinout
X9C102, X9C103, X9C104, X9C503
(8 LD SOIC, 8 LD PDIP)
TOP VIEW
Features
• Solid-State Potentiometer
• Three-Wire Serial Interface
• 100 Wiper Tap Points
- Wiper Position Stored in Non-volatile Memory and
Recalled on Power-up
• 99 Resistive Elements
- Temperature Compensated
- End-to-End Resistance, ±20%
- Terminal Voltages, ±5V
• Low Power CMOS
-V
CC = 5V
- Active Current, 3mA max.
- Standby Current, 750µA max.
• High Reliability
- Endurance, 100,000 Data Changes per Bit
- Register Data Retention, 100 years
• X9C102 = 1k
• X9C103 = 10k
• X9C503 = 50k
• X9C104 = 100k
• Packages
- 8 Ld SOIC
- 8 Ld PDIP
• Pb-Free Available (RoHS Compliant)
Block Diagram
VCC
CS
VL/RL
VW/RW
INC
U/D
VH/RH
VSS
1
2
3
4
8
7
6
5
7-BIT
UP/DOWN
COUNTER
7-BIT
NON-VOLATILE
MEMORY
STORE AND
RECALL
CONTROL
CIRCUITRY
ONE
OF
HUNDRED
DECODER RESISTOR
ARRAY
RL/VL
RW/VW
RH/VH
U/D
INC
CS
TRANSFER
VCC
ONE-
GATES
99
98
97
96
2
1
0
GND
UP/DOWN
(INC)INCREMENT
DEVICE
(U/D)
(CS)
VCC (SUPPLY VOLTAGE)
VSS (GROUND)
CONTROL
AND
MEMORY
GENERAL
VH/RH
RW/VW
VL/RL
SELECT
DETAILED
X9C102, X9C103, X9C104, X9C503
FN8222 Rev 4.00 Page 2 of 12
Jan 11, 2019
Ordering Information
PART
NUMBER
PART
MARKING
RTOTAL
(k)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PACKAGE
DWG. #
X9C102PZ (Notes 2, 3) X9C102P Z 1 0 to +70 8 Ld PDIP MDP0031
X9C102PIZ (Notes 2, 3) X9C102P ZI -40 to +85 8 Ld PDIP MDP0031
X9C102SZ (Notes 1, 2) X9C102S Z 0 to +70 8 Ld SOIC M8.15E
X9C102SIZ (Notes 1, 2) X9C102S ZI -40 to +85 8 Ld SOIC M8.15E
X9C103PZ (Notes 2, 3) X9C103P Z 10 0 to +70 8 Ld PDIP MDP0031
X9C103PIZ (Notes 2, 3) X9C103P ZI -40 to +85 8 Ld PDIP MDP0031
X9C103SZ (Notes 1, 2) X9C103S Z 0 to +70 8 Ld SOIC M8.15
X9C103SIZ (Notes 1, 2) X9C103S ZI -40 to +85 8 Ld SOIC M8.15
X9C503PZ (Notes 2, 3) X9C503P Z 50 0 to +70 8 Ld PDIP MDP0031
X9C503PIZ (Notes 2, 3) X9C503P ZI -40 to +85 8 Ld PDIP MDP0031
X9C503SZ (Notes 1, 2) X9C503S Z 0 to +70 8 Ld SOIC M8.15E
X9C503SIZ (Notes 1, 2) X9C503S ZI -40 to +85 8 Ld SOIC M8.15E
X9C104PIZ (Notes 2, 3) X9C104P ZI 100 -40 to +85 8 Ld PDIP MDP0031
X9C104SZ (Notes 1, 2) X9C104S Z 0 to +70 8 Ld SOIC M8.15E
X9C104SIZ (Notes 1, 2) X9C104S ZI -40 to +85 8 Ld SOIC M8.15E
NOTES:
1. Add “T1” suffix for tape and reel. See TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
X9C102, X9C103, X9C104, X9C503
FN8222 Rev 4.00 Page 3 of 12
Jan 11, 2019
Pin Descriptions
PIN
NUMBER PIN NAME DESCRIPTION
1INC
INCREMENT The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or
decrement the counter in the direction indicated by the logic level on the U/D input.
2U/D
UP/DOWN The U/D input controls the direction of the wiper movement and whether the counter is incremented or
decremented.
3V
H/RHVH/RH The high (VH/RH) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of
a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL
references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and
not the voltage potential on the terminal.
4V
SS VSS
5V
W/RWVW/RW VW/RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The
position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically
40.
6R
L/VLRL/VL The low (VL/RL) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of a
mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL
references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and
not the voltage potential on the terminal.
7CS
CS The device is selected when the CS input is LOW. The current counter value is stored in non-volatile memory when
CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9C102, X9C103,
X9C104, X9C503 device will be placed in the low power standby mode until the device is selected once again.
8V
CC VCC
X9C102, X9C103, X9C104, X9C503
FN8222 Rev 4.00 Page 4 of 12
Jan 11, 2019
Absolute Maximum Ratings Thermal Information
Voltage on CS, INC, U/D and VCC with Respect to VSS . -1V to +7V
Voltage on VH/RH and VL/RL Referenced to VSS . . . . . . . -8V to +8V
V = |VH/RH - VL/RL|
X9C102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V
X9C103, X9C104, and X9C503 . . . . . . . . . . . . . . . . . . . . . . . .10V
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8mA
Power Rating
X9C102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mW
X9C103 X0C104, and X9C503 . . . . . . . . . . . . . . . . . . . . . .10mW
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . -65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TB493
*Pb-free PDIPs can be used for through-hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Recommended Operating Conditions
Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial Temperature Range . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage Range (VCC) . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications Over recommended operating conditions unless otherwise stated.
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
UNITMIN
TYP
(Note 7) MAX
POTENTIOMETER CHARACTERISTICS
RTOTAL End-to-End Resistance Variation -20 +20 %
VVH/RH VH Terminal Voltage -5 +5 V
VVL/RL VL Terminal Voltage -5 +5 V
IWWiper Current -4.4 4.4 mA
RWWiper Resistance Wiper Current = ±1mA 40 100
Resistor Noise (Note 8) Ref 1kHz -120 dBV
Charge Pump Noise (Note 8) @ 850kHz 20 mVRMS
Resolution 1%
Absolute Linearity (Note 4) VW(n)(actual) - VW(n)(EXPECTED) -1 +1 MI (Note 6)
Relative Linearity (Note 5) VW(n + 1)(ACTUAL) - [VW(n) + MI] -0.2 +0.2 MI (Note 6)
RTOTAL Temperature Coefficient X9C103, X9C503, X9C104 ±300 (Note 8) ppm/°C
RTOTAL Temperature Coefficient X9C102 ±600 (Note 8) ppm/°C
Ratiometric Temperature Coefficient ±20 ppm/°C
CH/CL/CW
(Note 8)
Potentiometer Capacitances See “Circuit #3 SPICE Macro
Model” on page 5.
10/10/25 pF
DC OPERATING CHARACTERISTICS
ICC VCC Active Current CS = VIL, U/D = VIL or VIH and
INC = 0.4V to 2.4V at Max tCYC
13mA
ISB Standby Supply Current CS = VCC - 0.3V, U/D and
INC =V
SS or VCC -0.3V
200 750 µA
ILI CS, INC, U/D Input Leakage Current VIN = VSS to VCC ±10 µA
VIH CS, INC, U/D input HIGH Voltage 2 V
VIL CS, INC, U/D input LOW Voltage 0.8 V
CIN CS, INC, U/D Input Capacitance (Note 8) VCC = 5V, VIN = VSS, TA= +25°C,
f = 1MHz
10 pF
X9C102, X9C103, X9C104, X9C503
FN8222 Rev 4.00 Page 5 of 12
Jan 11, 2019
Power-up and Down Requirements
At all times, voltages on the potentiometer pins must be less
than ±VCC. The recall of the wiper position from non-volatile
memory is not in effect until the VCC supply reaches its final
value. The VCC ramp rate specification is always in effect.
AC OPERATION CHARACTERISTICS
tCl CS to INC Setup 100 ns
tlD INC HIGH to U/D Change 100 ns
tDI U/D to INC Setup 2.9 µs
tlL INC LOW Period 1 µs
tlH INC HIGH Period 1 µs
tlC INC Inactive to CS Inactive 1 µs
tCPH CS Deselect Time (STORE) 20 ms
tCPH CS Deselect Time (NO STORE) 100 ns
tIW (5) INC to VW/RW Change 100 µs
tCYC INC Cycle Time 2 µs
tCYC INC Input Rise and Fall Time 500 µs
tR, tFPower-up to Wiper Stable (Note 8) 500 µs
tPU VCC Power-up Rate (Note 8) 0.2 50 V/ms
NOTES:
4. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage = [VW(n)(actual) - VW(n)(expected )] = ±1 MI Maximum.
5. Relative linearity is a measure of the error in step size between taps = VW(n + 1) - [VW(n) + MI] = +0.2 MI.
6. 1 MI = Minimum Increment = RTOT/99.
7. Typical values are for TA = +25°C and nominal supply voltage.
8. This parameter is not 100% tested.
Electrical Specifications Over recommended operating conditions unless otherwise stated. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
UNITMIN
TYP
(Note 7) MAX
Test Circuit #1
TEST POINT
Vw/RW
VR/RH
VL/RL
VS
Test Circuit #2
FORCE
VL/RL
VW/Rw
VH/RH
TEST POINT
CURRENT
Circuit #3 SPICE Macro Model
CW
RTOTAL
RLRH
CL
RW
10pF
CL
10pF
25pF
Endurance and Data Retention
PARAMETER MIN UNIT
Medium Endurance 100,000 Data changes per bit
per register
Data Retention 100 years
AC Conditions of Test
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 10ns
Input Reference Levels 1.5V
X9C102, X9C103, X9C104, X9C503
FN8222 Rev 4.00 Page 6 of 12
Jan 11, 2019
AC Timing Diagram
Pin Descriptions
RH/VH and RL/VL
The high (VH/RH) and low (VL/RL) terminals of the ISLX9C102,
X9C103, X9C104, X9C503 are equivalent to the fixed
terminals of a mechanical potentiometer. The minimum voltage
is -5V and the maximum is +5V. The terminology of VH/RH and
VL/RL references the relative position of the terminal in relation
to wiper movement direction selected by the U/D input and not
the voltage potential on the terminal.
RW/VW
VW/RW is the wiper terminal, and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs. The
wiper terminal series resistance is typically 40.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the counter
in the direction indicated by the logic level on the U/D input.
Chip Select (CS)
The device is selected when the CS input is LOW. The current
counter value is stored in non-volatile memory when CS is
returned HIGH while the INC input is also HIGH. After the store
operation is complete the ISLX9C102, X9C103, X9C104,
X9C503 device will be placed in the low power standby mode
until the device is selected once again.
Principles of Operation
There are three sections of the X9C102, X9C103, ISL9C104
and ISL9C503: the input control, counter and decode section;
the non-volatile memory; and the resistor array. The input control
section operates just like an up/down counter. The output of this
counter is decoded to turn on a single electronic switch
connecting a point on the resistor array to the wiper output.
Under the proper conditions, the contents of the counter can be
stored in non-volatile memory and retained for future use. The
resistor array is comprised of 99 individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap
positions. If the wiper is moved several positions, multiple taps
are connected to the wiper for tIW (INC to VW/RW change). The
RTOTAL value for the device can temporarily be reduced by a
significant amount if the wiper is moved several positions.
When the device is powered-down, the last wiper position
stored will be maintained in the non-volatile memory. When
power is restored, the contents of the memory are recalled and
the wiper is reset to the value last stored.
The internal charge pump allows a wide range of voltages
(from -5V to 5V) applied to XDCP terminals yet given a
convenience of single power supply. The typical charge pump
noise of 20mV at 850kHz should be taken in consideration
when designing an application circuit.
CS
INC
U/D
VW
tCI tIL tIH
tCYC
tID tDI
tIW
MI
tIC tCPH
tFtR
10%
90% 90%
(NOTE)
NOTE: MI REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE VW OUTPUT DUE TO A CHANGE IN THE WIPER POSITION.
X9C102, X9C103, X9C104, X9C503
FN8222 Rev 4.00 Page 7 of 12
Jan 11, 2019
Instructions and Programming
The INC, U/D and CS inputs control the movement of the wiper
along the resistor array. With CS set LOW, the device is selected
and enabled to respond to the U/D and INC inputs. HIGH to
LOW transitions on INC will increment or decrement (depending
on the state of the U/D input) a 7-bit counter. The output of this
counter is decoded to select one of one-hundred wiper positions
along the resistive array.
The value of the counter is stored in non-volatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
The system may select the X9Cxxx, move the wiper and
deselect the device without having to store the latest wiper
position in non-volatile memory. After the wiper movement is
performed as previously described and once the new position
is reached, the system must keep INC LOW while taking CS
HIGH. The new wiper position will be maintained until changed
by the system or until a power-down/up cycle recalled the
previously stored data.
This procedure allows the system to always power-up to a pre-
set value stored in non-volatile memory; then during system
operation, minor adjustments could be made. The adjustments
might be based on user preference, i.e.: system parameter
changes due to temperature drift, etc.
The state of U/D may be changed while CS remains LOW. This
allows the host system to enable the device and then move the
wiper up and down until the proper trim is attained.
Symbol Table
Performance Characteristics
Contact the factory for more information.
Applications Information
Electronic digitally controlled (XCDP) potentiometers provide
three powerful application advantages:
1. The variability and reliability of a solid-state potentiometer.
2. The flexibility of computer-based digital controls.
3. The retentivity of non-volatile memory used for the storage
of multiple potentiometer settings or data.
Mode Selection
CS INC U/D MODE
L H Wiper Up
L L Wiper Down
H X Store Wiper Position
H X X Standby Current
L X No Store, Return to Standby
L H Wiper Up (not recommended)
L L Wiper Down (not recommended)
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X9C102, X9C103, X9C104, X9C503
FN8222 Rev 4.00 Page 8 of 12
Jan 11, 2019
Basic Configurations of Electronic Potentiometers
Basic Circuits
VRVR
I
THREE TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER TWO TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
VH/RH
VL/RL
VW/RW
CASCADING TECHNIQUESBUFFERED REFERENCE VOLTAGE
–
+
+5V
R1
+V
-5V
VW
VREF VOUT
OP-07
VW/RW
VW/RW
+V
+V +V
X
(a) (b)
VOUT = VW/RW
NONINVERTING AMPLIFIER
VO = (1+R2/R1)VS
VOLTAGE REGULATOR
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
OFFSET VOLTAGE ADJUSTMENT
+
–
VS
VO
R2
R1
100k
10k10k
10k
-12V+12V
TL072
COMPARATOR WITH HYSTERESIS
VUL = {R1/(R1 + R2)} VO(MAX)
VLL = {R1/(R1 + R2)} VO(MIN)
+
–
VS
VO
R2
R1
LM308A
+5V
-5V
+
–
VS
VO
R2
R1
}
}
LT311A
(FOR ADDITIONAL CIRCUITS SEE AN1145)
Revision History
Rev. Date Description
4.00 Jan 11, 2019 Updated Ordering Information table to remove Obsolete and Retired parts.
Added Revision History.
Updated PODs for X9C102, X9C104, and X9C503 SOICs from: MDP0027 to: M8.15E and X9C103 SOIC from:
MDP0027 to: M8.15, to include the Land Pattern design and convert dimensions from table to graphics.
Updated Intersil disclaimer to Renesas disclaimer.
X9C102, X9C103, X9C104, X9C503
FN8222 Rev 4.00 Page 9 of 12
Jan 11, 2019
Package Outline Drawings
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
TOP VIEW
INDEX
AREA
123
-C-
SEATING PLANE
x 45°
NOTES:
9. Dimensioning and tolerancing per ANSI Y14.5M-1994.
10. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
11. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
12. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
13. Terminal numbers are shown for reference only.
14. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
15. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
16. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
SIDE VIEW “A
SIDE VIEW “B”
1.27 (0.050)
6.20 (0.244)
5.80 (0.228)
4.00 (0.157)
3.80 (0.150)
0.50 (0.20)
0.25 (0.01)
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013)
8°
0°
0.25 (0.010)
0.19 (0.008)
1.27 (0.050)
0.40 (0.016)
1.27 (0.050)
5.20(0.205)
1
2
3
45
6
7
8
TYPICAL RECOMMENDED LAND PATTERN
2.20 (0.087)
0.60 (0.023)
For the most recent package outline drawing, see M8.15.
X9C102, X9C103, X9C104, X9C503
FN8222 Rev 4.00 Page 10 of 12
Jan 11, 2019
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
Unless otherwise specified, tolerance : Decimal ± 0.05
The pin #1 identifier may be either a mold or mark feature.
Interlead flash or protrusions shall not exceed 0.25mm per side.
Dimension does not include interlead flash or protrusions.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "A"
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
A
B
4
4
0.25 AMC B
C
0.10 C
5
ID MARK
PIN NO.1
(0.35) x 45°
SEATING PLANE
GAUGE PLANE
0.25
(5.40)
(1.50)
4.90 ± 0.10
3.90 ± 0.10
1.27 0.43 ± 0.076
0.63 ±0.23
4° ± 4°
DETAIL "A" 0.22 ± 0.03
0.175 ± 0.075
1.45 ± 0.1
1.75 MAX
(1.27) (0.60)
6.0 ± 0.20
Reference to JEDEC MS-012.
6.
SIDE VIEW “B”
For the most recent package outline drawing, see M8.15E.
X9C102, X9C103, X9C104, X9C503
FN8222 Rev 4.00 Page 11 of 12
Jan 11, 2019
Plastic Dual-In-Line Packages (PDIP)
D
L
A
eb
A1
NOTE 5
A2
SEATING
PLANE
L
N
PIN #1
INDEX
E1
12 N/2
b2
E
eB
eA
c
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
INCHES
TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20
A 0.210 0.210 0.210 0.210 0.210 MAX
A1 0.015 0.015 0.015 0.015 0.015 MIN
A2 0.130 0.130 0.130 0.130 0.130 ±0.005
b 0.018 0.018 0.018 0.018 0.018 ±0.002
b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015
c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002
D 0.375 0.750 0.750 0.890 1.020 ±0.010 1
E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010
E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2
e 0.100 0.100 0.100 0.100 0.100 Basic
eA 0.300 0.300 0.300 0.300 0.300 Basic
eB 0.345 0.345 0.345 0.345 0.345 ±0.025
L 0.125 0.125 0.125 0.125 0.125 ±0.010
N 8 14 16 18 20 Reference
Rev. C 2/07
NOTES:
17. Plastic or metal protrusions of 0.010” maximum per side are not included.
18. Plastic interlead protrusions of 0.010” maximum per side are not included.
19. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
20. Dimension eB is measured with the lead tips unconstrained.
21. 8 and 16 lead packages have half end-leads as shown.
For the most recent package outline drawing, see MDP0031.
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Colophon 7.2
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