LTM4653 EN55022B Compliant 58V, 4A Step-Down DC/DC Module Regulator FEATURES DESCRIPTION Complete Low EMI Switch Mode Power Supply n EN55022 Class B Compliant n Wide Input Voltage Range: 3.1V to 58V n Up to 4A Output Current n Output Voltage Range: 0.5V V OUT 0.94 * VIN n 1.67% Total DC Output Voltage Error Over Line, Load and Temperature (-40C to 125C) n Parallel and Current Share with Multiple LTM4653s n Analog Output Current Indicator n Programmable Input Voltage Limiting n Constant-Frequency Current Mode Control n Power Good Indicator and Programmable Soft-Start n Overcurrent/Overvoltage/Overtemperature Protection n 15mm x 9mm x 5.01mm BGA Package The LTM(R)4653 is an ultralow noise 58V, 4A DC/DC stepdown Module(R) regulator designed to meet the radiated emissions requirements of EN55022. Conducted emission requirements can be met by adding standard filter components. Included in the package are the switching controller, power MOSFETs, inductor, filters and supportcomponents. n APPLICATIONS Operating over an input voltage range of 3.1V to 58V, the LTM4653 supports an output voltage range of 0.5V to 94% of VIN, and a switching frequency range of 250kHz to 3MHz (400kHz default), each set by a single resistor. For high load currents, the LTM4653 can be paralleled in PolyPhase(R) operation and synchronized to an external clock. Only the bulk input and output filter capacitors are needed to finish the design. The LTM4653 is offered in a 15mm x 9mm x 5.01mm BGA package with SnPb or RoHS compliant terminalfinish. Avionics, Industrial Control and Test Equipment n Video, Imaging and Instrumentation n 48V Telecom and Network Power Supplies n RF Systems n All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5847554, 6580258. TYPICAL APPLICATION 4A, 24V Output Low EMI DC/DC Module Regulator with Analog Output Current Indicator IOUT 4.7F VIN VOUT SVIN VOSNS LOAD VD 4.7F INTVCC VINREG 10nF 499 124k 10F x2 SGND RUN PGND LTM4653 COMPa IMONa IMONb fSET GND ISETa ISETb 4653 TA01a 481k 70 24VOUT, UP TO 4A ANALOG OUTPUT CURRENT INDICATOR VIMON = 0.25 * IOUT PINS NOT USED IN THIS CIRCUIT: CLKIN, PGOOD, COMPb PGDFB, SW, EXTVCC TEMP+, TEMP-, NC 60 AMPLITUDE (dBV/m) VIN 28V TO 58V Radiated Emission Scan in a 10m Chamber LTM4653 Delivering 24VOUT at 3.5A, from 48VIN MEAS DIST 10m SPEC DIST 10m 50 40 30 20 10 [1] HORIZONTAL [2] VERTICAL QPK LIMIT + FORMAL 0 -10 30 130 230 330 730 630 430 530 FREQUENCY (MHz) 830 930 1000 4653 TA01b Rev. A Document Feedback For more information www.analog.com 1 LTM4653 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) (All Voltages Relative to VOUT- Unless Otherwise Indicated) Terminal Voltages VIN, VD, SVIN, SW, ISETa, VOUT, VOSNS......-0.3V to 60V GND, ISETb, EXTVCC.............................. -0.3V to 28V RUN..................................... GND-0.3V to PGND+60V INTVCC, PGDFB, VINREG, COMPa, COMPb, IMONa, IMONb ......................................... -0.3V to 4V fSET.................................................... -0.3V to INTVCC CLKIN, PGOOD (Relative to GND) ............ -0.3V to 6V Terminal Currents INTVCC Peak Output Current (Note 8).................30mA TEMP+...................................................-1mA to 10mA TEMP-..................................................-10mA to 1mA Temperatures Internal Operating Temperature Range (Note 2).............................................. -40C to 125C Storage Temperature Range............... -55C to 125C Peak Solder Reflow Package Body Temperature ............................................ 245C 1 2 C D CLKIN 7 PGOOD PGDFB VINREG GND ISETb fSET SGND NC ISETa EXTVCC RUN INTVCC G J 6 PGND IMONb IMONa SVIN COMPb COMPa H 5 VD NC E F TOP VIEW 4 VIN A B 3 VOSNS SGND SW TEMP+ TEMP- TEMP+ TEMP- PGND K NC VOUT L BGA PACKAGE 77-PIN (15mm x 9mm x 5.01mm) TJ(MAX) = 125C; JA = 15.5C/W; JCtop = 20.6C/W; JCbot = 5.1C/W; WEIGHT = 1.8 GRAMS NOTES: 1) VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS. 2) JA VALUE IS OBTAINED WITH DEMO BOARD. 3) REFER TO APPLICATION INFORMATION SECTION FOR LAB MEASUREMENT AND DERATING INFORMATION. ORDER INFORMATION PART MARKING* PART NUMBER PAD OR BALL FINISH LTM4653EY#PBF SAC305 (RoHS) LTM4653IY#PBF SAC305 (RoHS) LTM4653IY DEVICE FINISH CODE PACKAGE TYPE MSL RATING e1 LTM4653Y SnPb (63/37) e1 -40C to 125C BGA 3 e0 * Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609. TEMPERATURE RANGE (SEE NOTE 2) -40C to 125C -40C to 125C * Recommended LGA and BGA PCB Assembly and Manufacturing Procedures * LGA and BGA Package and Tray Drawings 2 Rev. A For more information www.analog.com LTM4653 ELECTRICAL CHARACTERISTICS l denotes the specifications which apply over the specified internal The operating temperature range (Note 2). TA = 25C, Test Circuit, VIN = SVIN = 48V, EXTVCC = 24V, RUN = 3.3V, RISET = 480k, RfSET = 57.6k, fSW = 1.5MHz (CLKIN driven with 1.2MHz clock signal) unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN SVIN(DC), VIN(DC) Input DC Voltage l 3.1 VOUT(RANGE) Range of Output Voltage Regulation 0.5V ISETa - SGND 0.94VIN, IOUT = 0A (See Note 6) l 0.5 VOUT(24VDC) Output Voltage Total Variation with Line and Load at VOUT = 24V 28V VIN 58V, 0A IOUT 4A, CINH = 4.7F, CD = 4.7F, COUTH = 2 x 47F, CLKIN driven with 1.5MHz Clock l 23.6 VOUT(0.5VDC) Output Voltage Total Variation with Line and Load at VOUT = 0.5V Measuring VOSNS - ISETa 3.1V VIN 13.2V, 0A IOUT 4A, CINH = 4.7F, CD = 4.7F, COUTH = 2 x 47F, ISETa = 500mV, RfSET = N/U (Note 5) l l l l TYP MAX 58 UNITS V 0.94VIN V 24 24.4 V -15 0 15 mV 2.4 150 2.85 2.6 250 3.1 2.9 V V mV 64 68 Input Specifications VIN(UVLO) SVIN Undervoltage Lockout Threshold SVIN Rising SVIN Falling Hysteresis VIN(OVLO) SVIN Overvoltage Lockout Rising (Note 4) VIN(HYS) SVIN Overvoltage Lockout Hysteresis (Note 4) IINRUSH(VIN) Input Inrush Current at Start-Up CINH = 4.7F, CD = 4.7F, COUTH = 2 x 47F; IOUT = 0A, ISETa Electrically Connected to ISETb 300 IQ(SVIN) Input Supply Bias Current Shutdown, RUN = GND RUN = VIN 16 450 IS(VIN, FCM) Input Supply Current CLKIN Open Circuit, IOUT = 4A 2.1 A IS(VIN, SHUTDOWN) Input Supply Current in Shutdown Shutdown, RUN = GND 4 A 2 V 4 V mA 30 A A Output Specifications IOUT VOUT Output Continuous Current Range (Note 3) 0 4 A VOUT(LINE)/VOUT Line Regulation Accuracy IOUT = 0A, 28V VIN 58V l 0.05 0.1 % VOUT(LOAD)/VOUT Load Regulation Accuracy VIN = 48V, 0A IOUT 4A l VOUT(AC) Output Voltage Ripple, VOUT VIN = 12V, ISETa = 5V 0.05 0.75 fs VOUT Ripple Frequency ISETa = 5V, RfSET = 57.6k, CLKIN Open Circuit l VOUT(START) Turn-On Overshoot tSTART Turn-On Start-Up Time Delay Measured from VIN Toggling from 0V to 48V to PGOOD Exceeding 3V; PGOOD Having a 100k Pull-Up to 3.3V, VPGFB Resistor-Divider Network as Shown in Test Circuit, RISETa = 480k, ISETa Electrically Connected to ISETb and CLKIN Driven with 1.5MHz Clock l VOUT(LS) Peak Output Voltage Deviation for Dynamic Load Step IOUT: 0A to 2A and 2A to 0A Load Steps in 1s, COUTH= 47F x 2 400 mV tSETTLE Settling Time for Dynamic Load Step IOUT: 0A to 2A and 2A to 0A Load Steps in 1s, COUTH = 47F x 2 50 s IOUT(OCL) IOUT- Output Current Limit 5.5 A 2 1.7 1.95 2.2 8 4 % mVP-P MHz mV 9 ms Control Section IISETa Reference Current of ISETa Pin VISETa = 0.5V, 3.1V VIN 13.2V VISETa = 24V, 28V VIN 58V IVOSNS VOSNS Leakage Current VIN = SVIN = RUN = ISETa = 58V 600 A tON(MIN) Minimum On-Time (Note 4 ) 60 ns l l 49.3 49 50 50 50.7 51 A A Rev. A For more information www.analog.com 3 LTM4653 ELECTRICAL CHARACTERISTICS l denotes the specifications which apply over the specified internal The operating temperature range (Note 2). TA = 25C, Test Circuit, VIN = SVIN = 48V, EXTVCC = 24V, RUN = 3.3V, RISET = 480k, RfSET = 57.6k, fSW = 1.5MHz (CLKIN driven with 1.2MHz clock signal) unless otherwise noted. SYMBOL PARAMETER CONDITIONS VRUN RUN Turn-On/-Off Thresholds RUN Input Turn-On Threshold, RUN Rising RUN Hysteresis l IRUN RUN Leakage Current RUN = 3.3V l VIN = 12V, ISETa = 5V, and: fSET Open Circuit RfSET = 57.6k (See fs Specification) l MIN TYP MAX UNITS 1.08 1.2 130 1.32 V mV 0.1 50 nA 400 1.95 440 kHz MHz 550 3 kHz MHz 0.4 V V Oscillator and Phase-Locked Loop (PLL) fOSC fSYNC Oscillator Frequency Accuracy PLL Synchronization Capture Range VIN = 12V, ISETa = 5V, CLKIN Driven with a GNDReferred Clock Toggling from 0.4V to 1.2V and Having a Clock Duty Cycle: From 10% to 90%; fSET Open Circuit From 40% to 60%; RfSET = 57.6k VCLKIN CLKIN Input Threshold VCLKIN Rising VCLKIN Falling ICLKIN CLKIN Input Current VCLKIN = 5V VCLKIN = 0V 360 250 1.3 1.2 -20 230 -5 500 A A Power Good Feedback Input and Power Good Output OVPGDFB Output Overvoltage PGOOD Upper Threshold PGDFB Rising l 620 645 675 mV UVPGDFB Output Undervoltage PGOOD Lower Threshold PGDFB Falling l 525 555 580 mV VPGDFB PGOOD Hysteresis PGDFB Returning RPGDFB Resistor Between PGDFB and SGND RPGOOD PGOOD Pull-Down Resistance VPGOOD = 0.1V, VPGDFB < UVPGDFB or VPGDFB > OVPGDFB IPGOOD(LEAK) PGOOD Leakage Current VPGOOD = 3.3V, UVPGDFB < VPGDFB < OVPGDFB tPGOOD(DELAY) PGOOD Delay PGOOD Low to High (Note 4) PGOOD High to Low (Note 4) 8 4.94 mV 4.99 5.04 k 700 1500 0.1 1 A 16/fSW(HZ) 64/fSW(HZ) s s Current Monitor and Input Voltage Regulation Pins hIMONa IOUT/IIMONa Ratio of VOUT Output Current to IIMONa Current, IOUT = 4A l IOS(IMON) IMONa Offset Current IIMONa at IOUT = 0A IMONb Resistor Resistor Between IMONb and SGND VIMONa IMONa Servo Voltage IMONa Voltage During Output Current Regulation VVINREG VINREG Servo Voltage VINREG Voltage During Output Current Regulation IVINREG VINREG Leakage Current VINREG = 2V VINTVCC Channel Internal VCC Voltage, No INTVCC Loading (IINTVCC = 0mA) 3.6V SVIN 58V, EXTVCC = Open Circuit 5V SVIN 58V, 3.2V EXTVCC 26.5V VEXTVCC(TH) EXTVCC Switchover Voltage (Note 4) VINTVCC(LOAD)/ VINTVCC INTVCC Load Regulation 0mA IINTVCC 30mA 36 40 44 5 A 9.8 10 10.2 k l 1.9 2.0 2.1 V l 1.8 2.0 2.2 V -5 1 k nA INTVCC Regulator 4 3.15 2.85 3.4 3.0 3.65 3.15 3.15 -2 0.5 V V V 2 % Rev. A For more information www.analog.com LTM4653 ELECTRICAL CHARACTERISTICS l denotes the specifications which apply over the specified internal The operating temperature range (Note 2). TA = 25C, Test Circuit, VIN = SVIN = 48V, EXTVCC = 24V, RUN = 3.3V, RISET = 480k, RfSET = 57.6k, fSW = 1.5MHz (CLKIN driven with 1.2MHz clock signal) unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Temperature Sensor VTEMP Temperature Sensor Forward Voltage, ITEMP+ = 100A and ITEMP- = -100A at TA = 25C VTEMP+ - VTEMP- 0.6 V TCV(TEMP) VTEMP Temperature Coefficient -2.0 mV/C Note 1: Stresses beyond those listing under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating conditions for extended periods may affect device reliability and lifetime. Note 2: The LTM4653 is tested under pulsed load conditions such that TJ TA. The LTM4653E is guaranteed to meet performance specifications over the 0C to 125C internal operating temperature range. Specifications over the full -40C to 125C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4653I is guaranteed to meet specifications over the full internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: See output current derating curves for different VIN, VOUT, and TA, located in the Applications Information section. Note 4: Minimum on-time, VIN Overvoltage Lockout and Overvoltage Lockout Hysteresis, and EXTVCC Switchover Threshold are tested at wafersort. Note 5: To ensure minimum on time criteria is met, VOUT(0.5VDC) high-line regulation is tested at 13.2VIN, with fSET and CLKIN open circuit. See the Applications Information section. Note 6. See Applications Information Section for Dropout Criteria. Note 7. This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 8. The INTVCC Abs Max peak output current is specified as the sum of current drawn by circuits internal to the module biased off of INTVCC and current drawn by external circuits biased off of INTVCC. See the Applications Information section. Rev. A For more information www.analog.com 5 LTM4653 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current at 5VIN, Forced Continuous Mode TA = 25C, unless otherwise noted. Efficiency vs Load Current at 12VIN, Forced Continuous Mode 95 95 90 90 85 85 Efficiency vs Load Current at 15VIN, Forced Continuous Mode 100 95 80 3.3VOUT, 400kHz 2.5VOUT, 400kHz 1.8VOUT, 400kHz 1.5VOUT, 400kHz 1.2VOUT, 400kHz 1.0VOUT, 400kHz 75 70 65 0.5 1.0 1.5 2.0 2.5 80 75 70 3.0 LOAD CURRENT (A) 3.5 65 0.5 4.0 5.0VOUT, 400kHz 3.3VOUT, 400kHz 2.5VOUT, 400kHz 1.8VOUT, 400kHz 1.5VOUT, 400kHz 1.0 1.5 2.0 3.0 3.5 75 12VOUT, 500kHz 5.0VOUT, 450kHz 3.3VOUT, 400kHz 2.5VOUT, 400kHz 1.8VOUT, 400kHz 1.5VOUT, 400kHz 70 65 1.2VOUT, 400kHz 1.0VOUT, 400kHz 2.5 80 60 4.0 0.5 95 95 95 90 90 90 70 65 60 55 0.5 1.0 1.5 2.0 80 75 70 15VOUT, 750kHz 12VOUT, 800kHz 5.0VOUT, 550kHz 3.3VOUT, 400kHz 2.5VOUT, 400kHz 1.8VOUT, 400kHz 1.5VOUT, 400kHz 1.2VOUT, 400kHz 1.0VOUT, 400kHz 2.5 3.0 3.5 4.0 24VOUT, 1.2MHz 15VOUT, 1.2MHz 12VOUT, 1.1MHz 5VOUT, 575kHz 65 60 55 0.5 1.0 1.5 2.0 3.3VOUT, 400kHz 2.5VOUT, 400kHz 1.8VOUT, 400kHz 1.5VOUT, 400kHz 2.5 3.0 3.5 3.3V Transient Response, 48VIN 4.0 4653 G03 Efficiency vs Load Current at 48VIN, Forced Continuous Mode 4.0 65 60 0.5 1.5 2.0 2.5 3.0 3.5 4.0 4653 G06 1V Transient Response, 24VIN VOUT 100mV/DIV AC-COUPLED VOUT 50mV/DIV AC-COUPLED IOUT 2A/DIV IOUT 2A/DIV IOUT 2A/DIV 4653 G08 1.0 LOAD CURRENT (A) 12V Transient Response, 48VIN 40s/DIV FIGURE 32 CIRCUIT, 48VIN, CINH = CD = 4.7F, COUT = 2 x 22F, RfSET = 124k, RISET = 240k, CTH = 10nF, RTH = 562, REXTVCC = 49.9, CEXTVCC = 1F, 2A to 4A LOAD STEP AT 2A/s 24VOUT, 1.5MHz 15VOUT, 1.4MHz 12VOUT, 1.2MHz 5.0VOUT, 600kHz 3.3VOUT, 400kHz 2.5VOUT, 400kHz 70 VOUT 50mV/DIV AC-COUPLED 6 3.5 75 4653 G05 4653 G04 4653 G07 3.0 80 LOAD CURRENT (A) LOAD CURRENT (A) 40s/DIV FIGURE 32 CIRCUIT, 48VIN, CINH = CD = 4.7F, COUT = 2 x 100F, RfSET = N/A, RISET = 66.5k, CTH = 10nF, RTH = 604, REXTVCC = N/A, CEXTVCC = N/A, 2A to 4A LOAD STEP AT 2A/s 2.5 85 85 EFFICIENCY (%) EFFICIENCY (%) 100 75 2.0 LOAD CURRENT (A) 100 80 1.5 1.2VOUT, 400kHz 1.0VOUT, 400kHz 4653 G02 Efficiency vs Load Current at 36VIN, Forced Continuous Mode 85 1.0 LOAD CURRENT (A) 4653 G01 Efficiency vs Load Current at 24VIN, Forced Continuous Mode EFFICIENCY (%) 85 EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%) 90 40s/DIV FIGURE 32 CIRCUIT, 24VIN, CINH = CD = 4.7F, COUT = 3 x 100F, RfSET = N/A, RISET = 20k, CTH = 6.8nF, RTH = 681, REXTVCC = N/A, CEXTVCC = N/A, 2A to 4A LOAD STEP AT 2A/s 4653 G09 Rev. A For more information www.analog.com LTM4653 TYPICAL PERFORMANCE CHARACTERISTICS Start-Up, No Load Start-Up, 4A Load RUN 2V/DIV RUN 2V/DIV VOUT 5V/DIV VOUT 5V/DIV PGOOD 2V/DIV PGOOD 2V/DIV 2ms/DIV FIGURE 32 CIRCUIT, 48VIN, CINH = CD = 4.7F, COUT = 2 x 22F, RfSET = 124k, RISET = 240k, RPGDFB = 95.3k, CTH = 10nF, RTH = 562, REXTVCC = 49.9, CEXTVCC = 1F, NO LOAD TA = 25C, unless otherwise noted. 4653 G10 Start-Up, Pre-Bias RUN 2V/DIV VOUT 5V/DIV IDIODE 1mA/DIV PGOOD 2V/DIV 2ms/DIV FIGURE 32 CIRCUIT, 48VIN, CINH = CD = 4.7F, COUT = 2 x 22F, RfSET = 124k, RISET = 240k, RPGDFB = 95.3k, CTH = 10nF, RTH = 562, REXTVCC = 49.9, CEXTVCC = 1F, 3 RESISTIVE LOAD Short Circuit, No Load 2ms/DIV FIGURE 32 CIRCUIT, 48VIN, CINH = CD = 4.7F, COUT = 2 x 22F, RfSET = 124k, RISET = 240k, RPGDFB = 95.3k, CTH = 10nF, RTH = 562, REXTVCC = 49.9, CEXTVCC = 1F, VOUT PRE-BIASED TO 5V THROUGH 1N4148 DIODE 4653 G12 Short Circuit, 4A Load VOUT 5V/DIV VOUT 5V/DIV IIN 1A/DIV IIN 1A/DIV 10s/DIV FIGURE 32 CIRCUIT, 48VIN, CINH = CD = 4.7F, COUT = 2 x 22F, RfSET = 124k, RISET = 240k, RPGDFB = 95.3k, CTH = 10nF, RTH = 562, REXTVCC = 49.9, CEXTVCC = 1F, NO LOAD PRIOR TO APPLICATION OF OUTPUT SHORT-CIRCUIT 4653 G11 4653 G13 10s/DIV FIGURE 32 CIRCUIT, 48VIN, CINH = CD = 4.7F, COUT = 2 x 22F, RfSET = 124k, RISET = 240k, RPGDFB = 95.3k, CTH = 10nF, RTH = 562, REXTVCC = 49.9, CEXTVCC = 1F, 3 RESISTIVE LOAD PRIOR TO APPLICATION OF OUTPUT SHORT-CIRCUIT 4653 G14 Rev. A For more information www.analog.com 7 LTM4653 PIN FUNCTIONS PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG Module PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY. VIN (A1-A3, B3): Power Input Pins. Apply input voltage and input decoupling capacitance directly between VIN and a ground (PGND) plane. VD (A4, B4, C4): Drain of the Converter's Primary Switching MOSFET. Apply at minimum one 4.7F high frequency ceramic decoupling capacitor directly from VD to PGND. Give this capacitor higher layout priority (closer proximity to the module) than any VIN decouplingcapacitors. SVIN (C3): Input Voltage Supply for Small-Signal Circuits. SVIN is the input to the INTVCC LDO. Connect SVIN directly to VIN. No decoupling capacitor is needed on this pin. PGND (A5, B5, C5, D5, E5, F5, G4-5, H3, H5, J3-5, K4-5, L4-5): Power Ground Pins of the LTM4653. Connect all pins to the application's PGND plane. VOUT (K1-3, L1-3): Power Output Pins of the LTM4653. Connect all pins to the application's power VOUT plane. Apply the output filter capacitors and the output load between a power VOUT plane and the application's PGNDplane. GND (D4): Ground Pin of the LTM4653. Electrically connect to the application's PGND plane. VOSNS (G1, H1): Output Voltage Sense and Feedback Signal. Connect VOSNS to VOUT at the point of load (POL). Pins G1 and H1 are electrically connected to each other internal to the module, and thus it is only necessary to connect one VOSNS pin to VOUT at the POL. The remaining VOSNS pin can be used for redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. SGND (E4, G2, H2): Signal Ground Pins of the LTM4653. Connect Pin H2 to PGND directly under the LTM4653. The SGND pins at locations E4 and G2 are electrically connected to each other internal to the module, and thus it is only necessary to connect one SGND pin to PGND under the module. The remaining SGND pins can be used for redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. 8 RUN (F4): Run Control Pin. A voltage above 1.2V commands the Module to regulate its output voltage. Undervoltage lockout (UVLO) can be implemented by connecting RUN to the midpoint node formed by a resistor-divider between VIN and GND. RUN features 130mV of hysteresis. See the Applications Information section. INTVCC (G3): Internal Regulator, 3.3V Nominal Output. Internal control circuits and MOSFET-drivers derive power from INTVCC bias. When operating 3.1V < SVIN 58V, an LDO generates INTVCC from SVIN when RUN is logic high (RUN > 1.2V). No external decoupling is required. When RUN is logic low (RUN - GND < 1.2V), the INTVCC LDO is off, i.e., INTVCC is unregulated. (Also see EXTVCC.) EXTVCC (F3): External Bias, Auxiliary Input to the INTVCC Regulator. When EXTVCC exceeds 3.2V and SVIN exceeds 5V, the INTVCC LDO derives power from EXTVCC bias instead of the SVIN path. This technique can reduce LDO losses considerably, resulting in a corresponding reduction in module junction temperature. For applications in which 4V VOUT 26.5V, connect EXTVCC to VOUT through a resistor. (See the Applications Information section for resistor value.) When taking advantage of this EXTVCC feature, locally decouple EXTVCC to PGND with a 1F ceramic--otherwise, leave EXTVCC open circuit. ISETb (F1): 1.5nF Soft-Start Capacitor. Connect ISETb to ISETa to achieve default soft-start characteristics, if desired. See ISETa. ISETa (F2): Accurate 50A Current Source. Positive input to the error amplifier. Connect a resistor (RISET) from this pin to SGND to program the desired LTM4653 output voltage, VOUT = RISET * 50A. A capacitor can be connected from ISETa to SGND to soft-start the output voltage and reduce start-up inrush current. Connect ISETa to ISETb in order to achieve default soft-start, if desired. (See ISETb.) In addition, the output of the LTM4653 can track a voltage applied between the ISETa pin and the SGND pins. (See the Applications Information section.) Rev. A For more information www.analog.com LTM4653 PIN FUNCTIONS PGOOD (D1): Power Good Indicator, Open-Drain Output Pin. PGOOD is high impedance when PGDFB is within approximately 7.5% of 0.6V. PGOOD is pulled to GND when PGDFB is outside this range. PGDFB (D2): Power Good Feedback Programming Pin. Connect PGDFB to VOSNS through a resistor, RPGDFB. RPGDFB configures the voltage threshold of VOUT for which PGOOD toggles its state. If the PGOOD feature is used, set RPGDFB to: V R PGDFB = OUT - 1 * 4.99k 0.6V otherwise, leave PGDFB open circuit. A small filter capacitor (220pF) internal to the LTM4653 on this pin provides high frequency noise immunity for the PGOOD output indicator. fSET (E3): Oscillator Frequency Programming Pin. The default switching frequency of the LTM4653 is 400kHz. Often, it is necessary to increase the programmed frequency by connecting a resistor between fSET and SGND. (See the Applications Information section.) Note that the synchronization range of CLKIN is approximately 40% of the oscillator frequency programmed by the fSET pin. CLKIN (B1): Mode Select and Oscillator Synchronization Input. Leave CLKIN open circuit for forced continuous mode operation. Alternatively, this pin can be driven to synchronize the switching frequency of the LTM4653 to a clock signal. In this condition, the LTM4653 operates in forced continuous mode and the cycle-by-cycle turnon of the primary power MOSFET MT is coincident with the rising edge of the clock applied to CLKIN. Note the synchronization range of CLKIN is approximately 40% of the oscillator frequency programmed by the fSET pin. (See the Applications Information section.) COMPa (E2): Current Control Threshold and Error Amplifier Compensation Node. The trip threshold of LTM4653's current comparator increases with a corresponding rise in COMPa voltage. A small filter cap (10pF) internal to the LTM4653 on this pin introduces a highfrequency roll-off of the error-amplifier response, yielding good noise rejection in the control-loop. COMPa is often electrically connected to COMPb in one's application, thus applying default loop compensation. Loop compensation (a series resistor-capacitor) can be applied externally to COMPa if desired or needed, instead. (See COMPb.) COMPb (E1): Internal Loop Compensation Network. For most applications, the internal, default loop compensation of the LTM4653 is suitable to apply "as is", and yields very satisfactory results: apply the default loop compensation to the control loop by simply connecting COMPa to COMPb. When more specialized applications require a personal touch to the optimization of control loop response, this can be accomplished by connecting a series resistor-capacitor network from COMPa to SGND-- and leaving COMPb open circuit. VINREG (D3): Input Voltage Regulation Programming Pin. Optionally connect this pin to the midpoint node formed by a resistor-divider between VD and SGND. When the voltage on VINREG falls below approximately 2V, a VINREG control loop servos VOUT to decrease the power inductor current and thus regulate VINREG at 2V. (See the Applications Information section.) If this input voltage regulation feature is not desired, connect VINREG to INTVCC. IMONa (C2): Power Inductor Current Analog Indicator Pin and Current Limit Programming Pin. The current flowing out of this pin is equal to 1/40,000 of the average power inductor current. To construct a voltage (VIMONa) that is proportional to the power inductor current, optionally apply a parallel resistor-capacitor network to this pin and terminate it to SGND. IMONa can be connected to IMONb if the default resistor-capacitor termination network provided by IMONb is desired: 1V at full scale (4A) load current. (See IMONb.) If this analog indicator feature is not desired, connect IMONa to SGND. If IMONa ever exceeds a trip threshold of approximately 2V, an IMON control loop servos VOUT to decrease power inductor current and thus regulate IMONa at 2V. In this manner, the average current limit inception threshold of the LTM4653 can be configured. (See the Applications Information section.) Rev. A For more information www.analog.com 9 LTM4653 PIN FUNCTIONS IMONb (C1): Power Inductor Analog Indicator Current Default Termination R-C Network. A 10k resistor in parallel with a 10nF capacitor and terminating to SGND connect to this pin. Connect IMONb to IMONa to achieve default power inductor analog indicator current characteristics: 1V at full scale (4A) load current. (See IMONa.) TEMP+ (J1, J6): Temperature Sensor, Positive Input. Emitter of a 2N3906-genre PNP bipolar junction transistor (BJT). Optionally interface to temperature monitoring circuitry such as LTC(R)2997, LTC2990, LTC2974 or LTC2975. Otherwise leave electrically open. Pins J1 and J6 are electrically connected together internal to the LTM4653, and thus it is only necessary to connect one TEMP+ pin to monitoring circuitry. The remaining TEMP+ pin can be used for redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. TEMP- (J2, J7): Temperature Sensor, Negative Input. Collector and base of a 2N3906-genre PNP bipolar junction transistor (BJT). Optionally interface to temperature monitoring circuitry such as LTC2997, LTC2990, LTC2974 or LTC2975. Otherwise leave electrically open. Pins J2 and J7 are electrically connected together internal to the LTM4653, and thus it is only necessary to connect one TEMP- pin to monitoring circuitry. The remaining TEMP- pin can be used for redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. SW (H4): Switching Node of Switching Converter Stage. Used for test purposes. May be routed a short distance with a thin trace to a local test point to monitor switching action of the converter, if desired, but do not route near any sensitive signals; otherwise, leave electrically opencircuit. NC (A6-7, B2, B6-7, C6-7, D6-7, E6-7, F6-7, G6-7, H6-7, K6-7, L6-7): No connect pins, i.e., pins with no internal connection. The NC pins predominantly serve to provide improved mounting of the module to the board. In one's layout, NC pins are permitted to remain electrically unconnected or can be connected as desired, e.g., connected to a GND plane for heat-spreading purposes and/or to facilitate routing. 10 Rev. A For more information www.analog.com For more information www.analog.com SGND IMONb IMONa fSET VINREG INTVCC COMPb COMPa ISETb ISETa 10k 1.5nF 10nF 1F 10k 10nF 249k 10pF + - IL / 40000 COMP BUFFER 2V 100 GND PGOOD LOGIC + - 50A ERROR AMPLIFIER TO CURRENT COMPARATORS, PWM, and FET-DRIVERS POWER CONTROL AND ANAOLG CIRCUITS 0.1F 1 *SEE APPLICATIONS INFORMATION SECTION FOR MINIMUM ON-TIME AND DROPOUT CRITERIA 400kHz DEFAULT RISET RISET = VOUT 50A EXTVCC CLKIN RUN + - + - RUN - GND: >1.2VTYP = ON <1.07VTYP = OFF 4.99k 220pF MB MT 4H (CENTRALLYLOCATED PNP TEMPERATURE SENSOR) 0.1F 400nH BEAD 4653 BD 0.1F + TEMP- TEMP+ PGDFB PGOOD SGND PGND VOSNS VOUT SW PGND VD VIN SVIN RPGDFB CINL COUTH LOAD Hi-Z WHEN VPGDFB-SGND IS WITHIN 0.6V7.5% COUT CD 4.7F CINH + LOAD-LOCAL MLCCs (HIGH-FREQUENCY DECOUPLING) VOUT DOWN TO 0.5V UP TO 0.94 * VIN* UP TO 4A VIN 3.1V TO 58V LTM4653 SIMPLIFIED BLOCK DIAGRAM Rev. A 11 LTM4653 TEST CIRCUIT VIN 28V TO 58V CINH 4.7F NC VIN SW SVIN VOUT VOSNS LOAD RUN GND CTH 0.1F RTH 499 LTM4653 COUTL 68F PGND VD INTVCC VINREG COMPa COMPb fSET + SGND CLKIN CD 4.7F x2 COUTH 27F 24VOUT, UP TO 4A ISETa PGDFB PGOOD EXTVCC TEMP+ TEMP- IMONa ISETb IMONb RPGDFB 196k 4653 TC01 RfSET 57.6k RISET 480k DECOUPLING REQUIREMENTS TA = 25C. Refer to Test Circuit APPLICATION SYMBOL PARAMETER Test Circuit CINH, CD External High Frequency Input Capacitor Requirement, 28V VIN 58V, VOUT = 24V IOUT = 4A 9.4 F COUTH External High Frequency Output Capacitor Requirement 28V VIN 58V, VOUT = 24V IOUT = 4A 22 F 12 CONDITIONS MIN TYP MAX UNITS Rev. A For more information www.analog.com LTM4653 OPERATION Power Module Description The LTM4653 is a non-isolated switch mode DC/DC stepdown power supply. It can provide up to 4A output current with a few external input and output capacitors. Set by a single resistor, RISET, the LTM4653 regulates a positive output voltage, VOUT. VOUT can be set to as low as 0.5V to as high as 0.94VIN. The LTM4653 operates from a positive input supply rail, VIN, between 3.1V and 58V. The typical application schematic is shown in Figure32. The LTM4653 contains an integrated constant-frequency current mode regulator, power MOSFETs, power inductor, EMI filter and other supporting discrete components. The nominal switching frequency range is from 400kHz to 3MHz, and the default operating frequency is 400kHz. It can be externally synchronized to a clock, from 250kHz to 3MHz. See the Applications Information section. The LTM4653 supports internal and external control loop compensation. Internal loop compensation is selected by connecting the COMPa and COMPb pins. Using internal loop compensation, the LTM4653 has sufficient stability margins and good transient performance with a wide range of output capacitors--even ceramic-only output capacitors. For external loop compensation, see the Applications Information section. LTpowerCAD(R) is available for transient load step and stability analysis. Input filter and noise cancellation circuitry reduces noise-coupling to the module's inputs and outputs, ensuring the module's electromagnetic interference (EMI) meets the limits of EN55022 Class B (see Figure6 to Figure8). Pulling the RUN pin below 1.2V forces the LTM4653 into a shutdown state. A capacitor can be applied from ISETa to SGND to program the output voltage ramp-rate; or, the default LTM4653 ramp-rate can be set by connecting ISETa to ISETb; or, voltage tracking can be implemented by interfacing rail voltages to the ISETa pin. See the Applications Information section. Multiphase operation can be employed by applying an external clock source to the LTM4653's synchronization input, the CLKIN pin. See the Typical Applications section. LDO losses within the module are reduced by connecting EXTVCC to VOUT through an RC-filter or by connecting EXTVCC to a suitable voltage source. IMONa is an analog output current indicator pin. It sources a current proportional to the LTM4653's load current. When IMONa is electrically connected to IMONb, the voltage on the IMONa/IMONb node is proportional to load current--with 1V corresponding to 4A load. IMONa can be interfaced to an external parallel-RC network instead of the one provided by IMONb. If IMONa ever exceeds 2V, a servo loop reduces the LTM4653's output current in order to keep IMONa at or below 2V. Through this servo mechanism, a parallel RC network can be connected to IMONa to implement an average current limit function--if desired. When the feature is not needed, connect IMONa to SGND. The LTM4653 also features a spare control pin called VINREG, with a 2V servo threshold, which can be used to reduce the input current draw during input line sag ("brownout") conditions. Connect VINREG to INTVCC when this feature is not needed. TEMP+ and TEMP- pins give access to a diode-connected PNP transistor, making it possible to monitor the LTM4653's internal temperature--if desired. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table7 and the Test Circuit for recommended external component values. VIN to VOUT Step-Down Ratios There are restrictions on the VIN to VOUT step-down ratio that the LTM4653 can achieve. The maximum duty cycle of the LTM4653 is 96% typical. The VIN to VOUT minimum dropout voltage is a function of load current when operating in high duty cycle applications. As an example, VOUT(24VDC) from the Electrical Characteristics table highlights the LTM4653's ability to regulate 24VOUT at up to 4A from 28VIN, when running at a switching frequency, fSW, of 1.5MHz. At very low duty cycles, the LTM4653's on-time of MT each switching cycle should be designed to exceed the LTM4653 control loop's specified minimum on-time of 60ns, tON(MIN), (guardband to 90ns), i.e.: D fSW > TON(MIN) Rev. A For more information www.analog.com 13 LTM4653 OPERATION where D (unitless) is the duty-cycle of MT, given by: V D = OUT VIN In rare cases where the minimum on-time restriction is violated, the frequency of the LTM4653 automatically and gradually folds back down to approximately one-fifth of its programmed switching frequency to allow VOUT to remain in regulation. See the Frequency Adjustment section. Be reminded of Notes 2, 3 and 5 in the Electrical Characteristics section regarding output current guidelines. transient effects during output load changes. The bulk capacitor can be a switcher-rated aluminum electrolytic capacitor or a Polymer capacitor. Suggested values for CD and CINH are found in Table7. A final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the LTM4653's VIN, SVIN, and VD pins. A ceramic input capacitor combined with trace or cable inductance forms a high Q (underdamped) tank circuit. If the LTM4653 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the device's rating. This situation is easily avoided; see the Hot-Plugging Safely section. Input Capacitors Output Capacitors The LTM4653 achieves low input conducted EMI noise due to tight layout and high-frequency bypassing of MOSFETs MT and MB within the module itself. A small filter inductor (400nH) is integrated in the input line (from VIN to VD), providing further noise attenuation--again, local to the switching MOSFETs. The VD and VIN pins are available for external input capacitors--CD and CINH--to form a high-frequency filter. As shown in the Simplified Block Diagram, the ceramic capacitor CD on the LTM4653's VD pins handles the majority of the RMS current into the DC/ DC converter power stage and requires careful selection, for that reason. Output capacitors COUTH and COUTL are applied to VOUT of the LTM4653. Sufficient capacitance and low ESR are called for, to meet the output voltage ripple, loop stability, and transient requirements. COUTL can be a low ESR tantalum or polymer capacitor. COUTH is a ceramic capacitor. The typical output capacitance is 22F (type X5R material, or better), if ceramic-only output capacitors are used. See Figure6 to Figure8 for demonstration of LTM4653's EMI performance, meeting the radiated emissions requirements of EN55022B. The input capacitance, CD, is needed to filter the pulsed current drawn by MT. To prevent excessive voltage sag on VD, a low-effective series resistance (low-ESR, such as an X7R ceramic) input capacitor should be used, sized appropriately for the maximum CD RMS ripple current: ICD(RMS) = IOUT(MAX) % * D * (1- D) where % is the estimated efficiency of the power module. (See Typical Performance Characteristics graphs.) Several capacitors may be paralleled to meet the application's target size, height, and CD RMS ripple current rating. For lower input voltage applications, sufficient bulk input capacitance is needed to counteract line sag and 14 Table7 shows a matrix of suggested output capacitors optimized for 2A transient step-loads applied at 2A/s. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. The LTpowerCAD design tool is available for transient and stability analysis. Stability criteria are considered in the Table7 matrix, and LTpowerCAD is available for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. LTpowerCAD can be used to calculate the output ripple reduction as the number of implemented phases increases by N times. External loop compensation can be applied to COMPa if needed, for transient response optimization. Forced Continuous Operation Leave the CLKIN pin open circuit to command the LTM4653 for forced continuous operation. In this mode, the control loop is allowed to command the inductor peak Rev. A For more information www.analog.com LTM4653 OPERATION Output Voltage Programming, Tracking and Soft-Start The LTM4653 regulates its output voltage, VOUT, according to the differential voltage present across ISETa and SGND. In most applications, the output voltage is set by simply connecting a resistor, RISET, from ISETa to SGND, according to: RISET = VOUT t - *C R VOUT (t) = IISETa * RISET * 1- e ISET SS The soft-start time, tSS, is defined as the time it takes for VOUT to ramp from 0V to 90% of its final value: or The default switching frequency (fSW) of the LTM4653 is 400kHz. This is suitable for low-VIN (VIN 5V) applications and low-VOUT (VOUT 3.3V) applications. For a practical design, the LTM4653's inductor ripple current (IPK-PK) is suggested to be less than ~2APK-PK. Choose fSW according to: t SS = -RISET * C SS *In (1- 0.9) t SS = 2.3 * RISET * C SS A default value of CSS = 1.5nF can be implemented by connecting ISETa to ISETb. For other ramp-up rates, connect an external CSS capacitor parallel to RISET. When starting up into a pre-biased VOUT, the LTM4653 stays in a sleep mode, keeping MT and MB off until VISETa equals VOSNS--after which, the DC/DC converter commences switching action and VOUT is ramped according to the voltage commanded by ISETa. Since the LTM4653 control loop servos its VOSNS voltage to match that of ISETa's, the LTM4653's output can be configured to track any voltage applied to ISETa, referenced to SGND. fSW = VOUT * (1- D ) L * IPK-PK where the value of LTM4653's power inductor, L, is 4H. To avoid cycle-skipping, impose restrictions on fSW, to ensure minimum on time criteria is met: 50A Since the LTM4653 control loop servos its output voltage according to the voltage between ISETa and SGND: placing a capacitor, CSS, parallel to RSET configures the ramp-up rate of ISETa and thus VOUT. In the time domain, the output voltage ramp-up after the RUN pin is toggled from low to high (t = 0s) is given by: Frequency Adjustment fSW < D TON(MIN) The LTM4653's minimum on-time, tON(MIN), is specified as 60ns. For a practical design, it is recommended to guardband to 90ns. To configure the LTM4653 for a higher switching frequency than its default of 400kHz, apply a resistor, RfSET, between the fSET pin and SGND. RfSET is given (in M) by: R fSET (M ) = 1 10pF *[fSW (MHz) - 0.4(MHz)] The relationship of RfSET to programmed fSW is shown in Figure1. See Table7 for recommended fSW and corresponding RfSET values for various combinations of VIN and VOUT. PROGRAMMED SWITCHING FREQUENCY (MHz) current to approximately -1A, allowing for significant negative average current. Clocking the CLKIN pin at a frequency within 40% of the target switching frequency commanded by the fSET pin synchronizes MT's turn-on to the rising edge of the CLKIN pin. 10 RfSET NOT USED 1 0.1 10 100 1k RfSET (k) 10k 4653 F01 Figure1. Relationship Between RfSET and Target fSW Rev. A For more information www.analog.com 15 LTM4653 APPLICATIONS INFORMATION Power Module Protection VSUPPLY The LTM4653's current mode control architecture provides fast cycle-by-cycle current limit in an overcurrent condition, as shown in the Typical Performance Characteristics section. If the output voltage collapses sufficiently due to an overload or short-circuit condition, minimum on-time will be violated and the internal oscillator will then fold-back automatically to one-fifth of the LTM4653's programmed switching frequency--thereby reducing the output current and affording the load a chance to recover. The LTM4653 features input overvoltage shutdown protection: when VIN > 68V, switching action ceases (with 4V of hysteresis)--however, be advised that this protection is only active outside the LTM4653's safe operating area (see Note 1 and Note 4 of the Electrical Characteristicstable). The LTM4653 ceases switching action if internal temperatures exceed 165C. The control IC resumes operation after a 10C cool-down hysteresis. Note that these typical parameters are based on measurements in a lab oven and are not production tested. This overtemperature protection is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this overtemperature protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. The LTM4653 does not feature any specialized output overvoltage protection beyond what is inherent to the control loop's servo mechanism. RUN Pin Enable The RUN pin is used to enable the power module or sequence the power module. The threshold is 1.2V. The RUN pin can be used to provide an undervoltage lockout (UVLO) function by connecting a resistor divider from the input supply to the RUN pin, as shown in Figure2. Undervoltage lockout keeps the LTM4653 in shutdown until the supply input voltage is above a certain voltage programmed by the user. The RUN pin hysteresis voltage 16 RA RUN PIN RB 4653 F02 Figure2. Undervoltage Lockout Resistive Divider prevents noise from falsely tripping UVLO. Resistors are chosen by first selecting RB (refer to Figure2). Then: VIN(ON) R A = RB * - 1 1.2V where VIN(ON) is the input voltage at which the undervoltage lockout is overcome and the supply turns on. RA may be replaced with a hardwired connection from VD to RUN. The VIN turn-off voltage, VIN(OFF) is given by: R VIN(OFF) = 1.07V * A + 1 RB If UVLO is not needed, RUN can be connected to LTM4653's VD or VIN pins. When RUN is below its threshold, UVLO is engaged, MT and MB are turned off, INTVCC ceases to be regulated, and ISETa is discharged to SGND by internal circuitry. Loop Compensation External loop compensation may be preferred for some applications and can be implemented easily, as follows: leave COMPb open circuit; connect a series-RC network (RTH and CTH) from COMPa to SGND; in some instances, connect a capacitor (CTHP) from COMPa to SGND (paralleling the RTH-CTH series-RC network). See Table7 for suggested input and output capacitances for a variety of operating conditions. Additionally, the LTpowerCAD design tool is available for transient and stability analysis. Rev. A For more information www.analog.com LTM4653 APPLICATIONS INFORMATION Hot-Plugging Safely The small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitors (CD and CINH) of the LTM4653. However, these capacitors can cause problems if the LTM4653 is plugged into a live supply (see Analog Devices Application Note 88 for a complete discussion). The low loss ceramic capacitor combined with stray inductance in series with the power source forms an under damped tank circuit, and the voltage at the VIN pin of the LTM4653 can ring to twice the nominal input voltage, possibly exceeding the LTM4653's rating and damaging the part. If the input supply is poorly controlled or the user will be plugging the LTM4653 into an energized supply, the input network should be designed to prevent this overshoot by introducing a damping element into the path of current flow. This is often done by adding an inexpensive electrolytic bulk capacitor (CINL) across the input terminals of the LTM4653. The selection criteria for CINL calls for: an ESR high enough to damp the ringing; a capacitance value several times larger than CINH. CINL does not need to be located physically close to the LTM4653; it should be located close to the application board's input connector,instead. taken to prevent current flow through the internal body diode. Simple solutions would be placing a Schottky diode in series with the supply (Figure3), or placing a Schottky diode from VOUT to SVIN/VIN (Figure4). Applications with loads that experience large load-step release, load dump or other mechanisms that invoke reverse energy flow in the Figure3 circuit may need a suitably-rated Zener diode protection clamp, to limit the resulting transient voltage rise on SVIN/VIN and CIN. VIN VIN SVIN CIN 4.7F 4653 F03 Figure3. Schottky Diode in Series with the Supply VIN VIN VOUT VOUT SVIN Input Disconnect/Input Short Considerations If at any point the input supply is removed with the output voltage still held high through its capacitor, power will be drawn from the output capacitor to power the module, until the output voltage drops below the minimum SVIN/ VIN requirements of the module. LTM4653 OPT C IN 4.7F LTM4653 COUT 47F 4653 F04 Figure4. Schottky Diode from VOUT to VIN However, if the SVIN/VIN pins are grounded while the output is held high, regardless of the RUN state, parasitic body diodes inside the LTM4653 will pull current from the output through the VOUT pins. Depending on the size of the output capacitor and the resistivity of the short, high currents may flow through the internal body diode, and cause damage to the part. If discharge of SVIN/VIN by the input source is possible, preventative measures should be Rev. A For more information www.analog.com 17 LTM4653 APPLICATIONS INFORMATION INTVCC and EXTVCC Connection When RUN is logic high, an internal low dropout regulator regulates an internal supply, INTVCC, that powers the control circuitry for driving LTM4653's internal MOSFETs. INTVCC is regulated at 3.3V. In this manner, the LTM4653's INTVCC is directly powered from SVIN, by default. The gate driver current through the LDO is about 20mA for a typical 1MHz application. The internal LDO power dissipation can be calculated as: PLDO _ LOSS(INTVCC) = 20mA * (SVIN - 3V) The LDO draws current off of EXTVCC instead of SVIN when EXTVCC is higher than 3.2V and SVIN is above 5V. For output voltages of 4V and higher, EXTVCC can be connected to VOUT through an RC-filter. When the internal LDO derives power from EXTVCC instead of SVIN, the internal LDO power dissipation is: PLDO _ LOSS(EXTVCC) = 20mA * (VOUT - 3V) The recommended value of the resistor between VOUT and EXTVCC is roughly VOUT * 4/V. This resistor, REXTVCC, must be rated to continually dissipate (0.02A) * REXTVCC. The primary purpose of this resistor is to prevent EXTVCC overstress under a fault condition. For example, when an inductive short-circuit is applied to the module's output, VOUT may be briefly dragged below PGND--forward biasing the PGND-to-EXTVCC body diode. This resistor limits the magnitude of current flow in EXTVCC. Bypass EXTVCC with 1F of X5R (or better) MLCC. Multiphase Operation Multiple LTM4653 devices can be paralleled for higher output current applications. For lowest input and output voltage and current ripples, it is advisable to synchronize paralleled LTM4653s to an external clock (within 40% of the target switching frequency set by fSET--see Test Circuit 1). See Figure34 for an example of a synchronizing circuit. LTM4653 modules can be paralleled without synchronizing circuits: just be aware that some beat-frequency ripple will be present in the output voltage and reflected input 18 current by virtue of the fact that such modules are not operating at identical, synchronized switchingfrequencies. The LTM4653 device is an inherently current mode controlled device, so parallel modules will have good current sharing's shown in Figure35. This helps balance the thermals on the design. To parallel LTM4653s, connect the respective COMPa, ISETa, and VOSNS pins of each LTM4653 together to share the current evenly. In addition, tie the respective RUN pins of paralleled LTM4653 devices together, to ensure proper start-up and shutdown behavior. Figure34 shows a schematic of LTM4653 devices operating in parallel. Note that for parallel applications, VOUT can be set by a single, common resistor on the ISETa net: RISET = VOUT 50A * N where N is the number of LTM4653 modules in parallel configuration. Depending on the duty cycle of operation, the output voltage ripple achieved by paralleled, synchronized LTM4653 modules may be considerably smaller than what is yielded by a single-phase solution. Application Note 77 provides a detailed explanation of multiphase operation (relevant to parallel LTM4653 applications) pertaining to noise reduction and output and input ripple current cancellation. Regardless of ripple current cancellation, it remains important for the output capacitance of paralleled LTM4653 applications to be designed for loop stability and transient response. LTpowerCAD is available for such analysis. Figure5 illustrates the RMS ripple current reduction as a function of the number of interleaved (paralleled and synchronized) LTM4653 modules--derived from Application Note 77. Radiated EMI Noise The generation of radiated EMI noise is an inherent disadvantage of switching regulators. Fast switching turnon and turn-off of the power MOSFETs--necessary Rev. A For more information www.analog.com LTM4653 APPLICATIONS INFORMATION for achieving high efficiency--create high-frequency (~30MHz+) l/t changes within DC/DC converters. This activity tends to be the dominant source of high-frequency EMI radiation in such systems. The high level of device integration within LTM4653--including optimized gatedriver and critical front-end filter inductor--delivers low radiated EMI noise performance. Figure6 to Figure8 show typical examples of LTM4653 meeting the radiated emission limits established by EN55022 Class B. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section of this data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a Module package mounted to a hardware test board. The motivation for providing these thermal coefficients is found in JESD51-12 ("Guidelines for Reporting and Using Electronic Package Thermal Information"). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the Module regulator's thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are, in and of themselves, not relevant to providing guidance of thermal performance; instead, the derating curves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to one's application-usage, and can be adapted to correlate thermal performance to one's ownapplication. The Pin Configuration section gives four thermal coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below: 1.JA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as "still air" although natural convection causes the air to move. This value is determined with the part mounted to a JESD51-9 defined test board, which does not reflect an actual application or viable operating condition. 2.JCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical Module regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don't generally match the user's application. 3.JCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical Module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of JCbottom, this value may be useful for comparing packages but the test conditions don't generally match the user's application. 4.JB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the Module regulator and into the board, and is really the sum of the JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD51-9. Rev. A For more information www.analog.com 19 LTM4653 APPLICATIONS INFORMATION 0.60 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.55 0.50 RMS INPUT RIPPLE CURRENT DC LOAD CURRENT 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY CYCLE 4653 F05 Figure5. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six LTM4653s (Phases) AMPLITUDE (dBV/m) 60 70 MEAS DIST 10m SPEC DIST 10m 50 40 30 20 10 130 230 330 730 630 430 530 FREQUENCY (MHz) 830 AMPLITUDE (dBV/m) 60 930 1000 20 [1] HORIZONTAL [2] VERTICAL QPK LIMIT + FORMAL -10 30 130 230 330 4653 F06 730 630 430 530 FREQUENCY (MHz) 830 930 1000 4653 F07 Figure7. Radiated Emissions Scan of the LTM4653 Producing 24VOUT at 3.5A, from 48VIN. DC2327A Hardware. fSW = 1.2MHz. Measured in a 10m Chamber. Peak Detect Method MEAS DIST 10m SPEC DIST 10m 50 40 30 20 10 [1] HORIZONTAL [2] VERTICAL QPK LIMIT + FORMAL 0 -10 30 20 40 30 0 Figure6. Radiated Emissions Scan of the LTM4653. Producing 24VOUT at 4A, from 29.5VIN. DC2327A Hardware. fSW = 1.2MHz. Measured in a 10m Chamber. Peak Detect Method 70 50 10 [1] HORIZONTAL [2] VERTICAL QPK LIMIT + FORMAL 0 -10 30 MEAS DIST 10m SPEC DIST 10m 60 AMPLITUDE (dBV/m) 70 130 230 330 730 630 430 530 FREQUENCY (MHz) 830 930 1000 4653 F08 Figure8. Radiated Emissions Scan of the LTM4653. Producing 12VOUT at 3A, from 58VIN. DC2327A Hardware. fSW = 1.2MHz. Measured in a 10m Chamber. Peak Detect Method For more information www.analog.com Rev. A LTM4653 APPLICATIONS INFORMATION A graphical representation of the aforementioned thermal resistances is given in Figure9; blue resistances are contained within the Module regulator, whereas green resistances are external to the Module package. As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a Module regulator. For example, in normal board-mounted applications, never does 100% of the device's total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the Module package--as the standard defines for JCtop and JCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package--granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. Within the LTM4653, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity-- but also not ignoring practical realities--an approach has Module DEVICE been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4653 and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD51-9 and JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4653 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with well-correlated JESD51-12-defined values provided in the Pin Configuration section of this data sheet. JA JUNCTION-TO-AMBIENT RESISTANCE JCtop JUNCTION-TO-CASE (TOP) RESISTANCE CASE (TOP)-TO-AMBIENT RESISTANCE JUNCTION AMBIENT JCbot JUNCTION-TO-CASE (BOTTOM) RESISTANCE CASE (BOTTOM)-TO-BOARD RESISTANCE BOARD-TO-AMBIENT RESISTANCE 4653 F09 Figure9. Graphical Representation of JESD51-12 Thermal Coefficients Rev. A For more information www.analog.com 21 LTM4653 APPLICATIONS INFORMATION The 1V, 5V, and 15V and 24V power loss curves in Figure10, Figure11 and Figure12 respectively can be used in coordination with the load current derating curves in Figure13 to Figure30 for calculating an approximate JA thermal resistance for the LTM4653 with various heat sinking and air flow conditions. These thermal resistances represent demonstrated performance of the LTM4653 on DC2327A hardware; a 4-layer FR4 PCB measuring 99mm x 133mm x 1.6mm using outer and inner copper weights of 2oz and 1oz, respectively. The power loss curves are taken at room temperature, and are increased with multiplicative factors with ambient temperature. These approximate factors are listed in Table1. (Compute the factor by interpolation, for intermediate temperatures.) The derating curves are plotted with the LTM4653's output initially sourcing 4A and the ambient temperature at 20C. The output voltages are 1V, 5V, 15V and 24V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. In all derating curves, the switching frequency of operation follows guidance provided by Table7. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without air flow, and with and without a heat sink attached with thermally conductive adhesive tape. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 120C maximum while lowering output current or power while increasing ambient temperature. The decreased output current decreases the internal module loss as ambient temperature is increased. The monitored junction temperature of 120C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example 22 in Figure27, the load current is derated to 2.5A at 70C ambient with 200LFM airflow and no heat sink and the room temperature (25C) power loss for this 48VIN to 24VOUT at 2.5AOUT condition is 3.9W. A 4.5W loss is calculated by multiplying the 3.9W room temperature loss from the 48VIN to 24VOUT power loss curve at 2.5A (Figure12), withthe 1.15 multiplying factor at 70C ambient (from Table1). If the 70C ambient temperature is subtracted from the 120C junction temperature, then the difference of 50C divided by 4.5W yields a thermal resistance, JA, of 11.1C/W--in good agreement with Table4. Tables 2, 3 and 4 provide equivalent thermal resistances for 1V, 5V and 15V and 24V outputs with and without air flow and heat sinking. The derived thermal resistances in Tables 2, 3 and 4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with ambient temperature multiplicative factors from Table1. Table1. Power Loss Multiplicative Factors vs Ambient Temperature AMBIENT TEMPERATURE POWER LOSS MULTIPLICATIVE FACTOR Up to 40C 1.00 50C 1.05 60C 1.10 70C 1.15 80C 1.20 90C 1.25 100C 1.30 110C 1.35 120C 1.40 Rev. A For more information www.analog.com LTM4653 APPLICATIONS INFORMATION Table2. 1V Output DERATING CURVE Figure13, Figure14, Figure15 Figure13, Figure14, Figure15 Figure13, Figure14, Figure15 Figure16, Figure17, Figure18 Figure16, Figure17, Figure18 Figure16, Figure17, Figure18 VIN (V) 5, 12, 24 5, 12, 24 5, 12, 24 5, 12, 24 5, 12, 24 5, 12, 24 POWER LOSS CURVE Figure10, Figure11 Figure10, Figure11 Figure10, Figure11 Figure10, Figure11 Figure10, Figure11 Figure10, Figure11 AIRFLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink JA (C/W) 13.9 11.4 10.7 13.3 11.0 10.3 VIN (V) 12, 24, 48 12, 24, 48 12, 24, 48 12, 24, 48 12, 24, 48 12, 24, 48 POWER LOSS CURVE Figure10, Figure11, Figure12 Figure10, Figure11, Figure12 Figure10, Figure11, Figure12 Figure10, Figure11, Figure12 Figure10, Figure11, Figure12 Figure10, Figure11, Figure12 AIRFLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink JA (C/W) 13.9 11.4 10.7 13.3 11.0 10.3 VIN (V) 24, 48 24, 48 24, 48 24, 48 24, 48 24, 48 POWER LOSS CURVE Figure11, Figure12 Figure11, Figure12 Figure11, Figure12 Figure11, Figure12 Figure11, Figure12 Figure11, Figure12 AIRFLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink JA (C/W) 13.9 11.4 10.7 13.3 11.0 10.3 Table3. 5V Output DERATING CURVE Figure19, Figure20, Figure21 Figure19, Figure20, Figure21 Figure19, Figure20, Figure21 Figure22, Figure23, Figure24 Figure22, Figure23, Figure24 Figure22, Figure23, Figure24 Table4. 15V and 24V Output DERATING CURVE Figure25, Figure26, Figure27 Figure25, Figure26, Figure27 Figure25, Figure26, Figure27 Figure28, Figure29, Figure30 Figure28, Figure29, Figure30 Figure28, Figure29, Figure30 Table5. Heat Sink Manufacturer (Thermally Conductive Adhesive Tape Pre-Attached) HEAT SINK MANUFACTURER PART NUMBER WEBSITE Cool Innovations 3-0504035UT411 www.coolinnovations.com Table6. Thermally Conductive Adhesive Tape Vendor THERMALLY CONDUCTIVE ADHESIVE TAPE MANUFACTURER PART NUMBER WEBSITE Chomerics T411 www.chomerics.com Rev. A For more information www.analog.com 23 LTM4653 APPLICATIONS INFORMATION Table7. LTM4653 Output Voltage Response vs Component Matrix. Performance of Figure32 Circuit with Values Here Indicated. Load-Stepping from 2A to 4A Load Current, at 2A/s. Typical Measured Values COUTH VENDORS PART NUMBER COUTH VENDORS PART NUMBER AVX 12066D107MAT2A (100F, 6.3V, 1206 Case Size) AVX 12105D106MAT2A (10F, 50V, 1210 Case Size) Murata GRM31CR60J107M (100F, 6.3V, 1206 Case Size) Murata GRM32ER61H106M (10F, 50V, 1210 Case Size) Taiyo Yuden JMK316BBJ107MLHT (100F, 6.3V, 1206 Case Size) Taiyo Yuden UMK325BJ106M (10F, 50V, 1210 Case Size) TDK C3216X5R0J107M (100F, 6.3V, 1206 Case Size) TDK C3225X5R1H106M (10F, 50V, 1210 Case Size) AVX 1210YD476MAT2A (47F, 16V, 1210 Case Size) CINH/CD VENDORS PART NUMBER Murata GRM32ER61C476M (47F, 16V, 1210 Case Size) Murata GRM32ER71K475M (4.7F, 80V, 1210 Case Size) Taiyo Yuden EMK325BJ476MM (47F, 16V, 1210 Case Size) AVX 12065C475MAT2A (4.7F, 50V, 1206 Case Size) AVX 12103D226MAT2A (22F, 25V, 1210 Case Size) Murata GRM31CR71H475M (4.7F, 50V, 1206 Case Size) Taiyo Yuden TMK325BJ226MM (22F, 25V, 1210 Case Size) Taiyo Yuden UMK316AB7475ML (4.7F, 50V, 1206 Case Size) TDK C3225X5R1E226M (22F, 25V, 1210 Case Size) TDK C3216X5R1H475M (4.7F, 50V, 1206 Case Size) VIN (V) CINH CD COUTH RTH () CTH (nF) RISET (k) RPGDFB (k) fSW (kHz) RfSET (k) REXTVCC () LOAD STEP TRANSIENT DROOP (mV) 1 5 4.7F 4.7F 100F x 3 681 6.8 20 3.32 400 N/A N/A 70 145 55 1 12 4.7F 4.7F 100F x 3 681 6.8 20 3.32 400 N/A N/A 70 145 50 1 24 4.7F 4.7F 100F x 3 681 6.8 20 3.32 400 N/A N/A 70 145 50 1.2 5 4.7F 4.7F 100F x 3 665 6.8 24 4.99 400 N/A N/A 70 145 50 1.2 12 4.7F 4.7F 100F x 3 665 6.8 24 4.99 400 N/A N/A 70 145 50 1.2 24 4.7F 4.7F 100F x 3 665 6.8 24 4.99 400 N/A N/A 70 145 50 1.5 5 4.7F 4.7F 100F x 3 665 6.8 30.1 7.5 400 N/A N/A 70 145 50 1.5 12 4.7F 4.7F 100F x 3 665 6.8 30.1 7.5 400 N/A N/A 70 145 50 1.5 24 4.7F 4.7F 100F x 3 665 6.8 30.1 7.5 400 N/A N/A 70 145 50 1.5 36 4.7F 4.7F 100F x 3 665 6.8 30.1 7.5 400 N/A N/A 70 145 50 1.8 5 4.7F 4.7F 100F x 3 665 8.2 36 10 400 N/A N/A 70 145 50 1.8 12 4.7F 4.7F 100F x 3 665 8.2 36 10 400 N/A N/A 70 145 50 1.8 24 4.7F 4.7F 100F x 3 665 8.2 36 10 400 N/A N/A 70 145 50 1.8 36 4.7F 4.7F 100F x 3 665 8.2 36 10 400 N/A N/A 70 145 50 2.5 5 4.7F 4.7F 100F x 3 649 8.2 50 15.8 400 N/A N/A 70 145 50 2.5 12 4.7F 4.7F 100F x 3 649 8.2 50 15.8 400 N/A N/A 70 145 50 2.5 24 4.7F 4.7F 100F x 3 649 8.2 50 15.8 400 N/A N/A 70 145 50 2.5 36 4.7F 4.7F 100F x 3 649 8.2 50 15.8 400 N/A N/A 70 145 50 2.5 48 4.7F 4.7F 100F x 3 649 8.2 50 15.8 400 N/A N/A 70 145 50 3.3 5 4.7F 4.7F 100F x 2 604 10 66.5 22.6 400 N/A N/A 90 190 50 3.3 12 4.7F 4.7F 100F x 2 604 10 66.5 22.6 400 N/A N/A 90 190 50 3.3 24 4.7F 4.7F 100F x 2 604 10 66.5 22.6 400 N/A N/A 90 185 50 3.3 36 4.7F 4.7F 100F x 2 604 10 66.5 22.6 400 N/A N/A 90 180 50 3.3 48 4.7F 4.7F 100F x 2 604 10 66.5 22.6 400 N/A N/A 90 180 50 5 12 4.7F 4.7F 47F x 2 499 10 100 36.5 400 N/A 20 130 260 45 5 24 4.7F 4.7F 47F x 2 499 10 100 36.5 550 665 20 130 260 45 5 36 4.7F 4.7F 47F x 2 499 10 100 36.5 575 576 20 130 260 45 5 48 4.7F 4.7F 47F x 2 499 10 100 36.5 600 499 20 130 260 45 12 15 4.7F 4.7F 22F x 2 499 10 240 95.3 500 1000 49.9 170 350 40 12 24 4.7F 4.7F 22F x 2 499 10 240 95.3 800 249 49.9 170 350 40 12 36 4.7F 4.7F 22F x 2 499 10 240 95.3 1100 143 49.9 170 350 40 12 48 4.7F 4.7F 22F x 2 499 10 240 95.3 1200 124 49.9 170 350 40 15 24 4.7F 4.7F 22F x 2 499 10 301 121 750 287 60.4 170 350 40 15 36 4.7F 4.7F 22F x 2 499 10 301 121 1200 124 60.4 170 350 40 15 48 4.7F 4.7F 22F x 2 499 10 301 121 1400 100 60.4 170 350 40 24 36 4.7F 4.7F 10F x 2 499 10 481 196 1200 124 100 220 430 35 24 48 4.7F 4.7F 10F x 2 499 10 481 196 1500 90.9 100 220 440 35 VOUT (V) 24 LOAD STEP PK-PK RECOVERY DEVIATION TIME (mV) (s) Rev. A For more information www.analog.com LTM4653 APPLICATIONS INFORMATION--DERATING CURVES 2.0 7.0 15VOUT, 750kHz 12VOUT, 800kHz 5.0VOUT, 550kHz 3.3VOUT, 400kHz 2.5VOUT, 400kHz 1.8VOUT, 400kHz 1.5VOUT, 400kHz 1.2VOUT, 400kHz 1.0VOUT, 400kHz 3.5 3.0 POWER LOSS (W) 2.5 POWER LOSS (W) 4.0 5.0VOUT, 400kHz 3.3VOUT, 400kHz 2.5VOUT, 400kHz 1.8VOUT, 400kHz 1.5VOUT, 400kHz 1.2VOUT, 400kHz 1.0VOUT, 400kHz 1.5 1.0 2.5 2.0 1.5 1.0 0.5 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT CURRENT (A) 3.5 0.0 0.0 4.0 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT CURRENT (A) 3.0 2.0 0.0 0.0 4.0 3.5 3.5 2.0 1.5 1.0 OLFM 200LFM 400LFM 0.0 20 40 2.5 2.0 1.5 1.0 OLFM 200LFM 400LFM 0.5 60 80 100 AMBIENT TEMPERATURE (C) 0.0 120 MAXIMUM LOAD CURRENT (A) 3.5 3.0 20 40 80 100 AMBIENT TEMPERATURE (C) 4653 F13 Figure13. 5V to 1VOUT Derating Curve, No Heat Sink 1.0 0.0 120 0.5 0.0 20 40 3.0 2.5 2.0 1.5 OLFM 200LFM 400LFM 0.5 60 80 100 AMBIENT TEMPERATURE (C) 120 4653 F16 Figure16. 5V to 1VOUT Derating Curve, with BGA Heat Sink MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) 3.5 1.0 0.0 20 40 20 80 100 AMBIENT TEMPERATURE (C) 60 80 100 120 4653 F15 3.0 2.5 2.0 1.5 1.0 OLFM 200LFM 400LFM 0.5 60 40 Figure15. 24V to 1VOUT Derating Curve, No Heat Sink 3.5 OLFM 200LFM 400LFM 4653 F12 AMBIENT TEMPERATURE (C) 3.5 1.0 4.0 OLFM 200LFM 400LFM 4653 F14 4.0 1.5 3.5 1.5 4.0 2.0 3.0 2.0 4.0 2.5 2.5 2.5 Figure14. 12V to 1VOUT Derating Curve, No Heat Sink 3.0 2.0 3.0 0.5 60 1.5 Figure12. 48VIN Power Loss Curve 4.0 2.5 1.0 OUTPUT CURRENT (A) 4.0 3.0 0.5 4653 F11 Figure11. 24VIN Power Loss Curve MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) 4.0 4.0 0.5 MAXIMUM LOAD CURRENT (A) 0.5 4653 F10 Figure10. 12VIN Power Loss Curve 5.0 1.0 0.5 0.0 0.0 24VOUT, 1.5MHz 15VOUT, 1.4MHz 12VOUT, 1.2MHz 5.0VOUT, 600kHz 3.3VOUT, 400kHz 2.5VOUT, 400kHz 6.0 POWER LOSS (W) 3.0 See Table1 for fSW and REXTVCC. 120 4653 F17 Figure17. 12V to 1VOUT Derating Curve, with BGA Heat Sink 0.0 20 40 60 80 100 AMBIENT TEMPERATURE (C) 120 4653 F18 Figure18. 24V to 1VOUT Derating Curve, with BGA Heat Sink Rev. A For more information www.analog.com 25 LTM4653 4.0 4.0 3.5 3.5 3.5 3.0 2.5 2.0 1.5 1.0 OLFM 200LFM 400LFM 0.5 0.0 20 40 3.0 2.5 2.0 1.5 1.0 80 100 AMBIENT TEMPERATURE (C) 0.0 120 40 3.0 2.5 2.0 1.5 1.0 60 80 100 0.0 120 3.5 3.5 3.5 1.0 OLFM 200LFM 400LFM 0.5 0.0 20 40 3.0 2.5 2.0 1.5 1.0 OLFM 200LFM 400LFM 0.5 60 80 100 AMBIENT TEMPERATURE (C) 0.0 120 MAXIMUM LOAD CURRENT (A) 4.0 1.5 20 40 80 100 AMBIENT TEMPERATURE (C) 4653 F22 Figure22. 12V to 5VOUT Derating Curve, with BGA Heat Sink 1.0 0.0 120 0.5 0.0 20 40 60 80 100 120 4653 F25 Figure25. 24V to 15VOUT Derating Curve, No Heat Sink MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) 2.5 2.0 1.5 1.0 OLFM 200LFM 400LFM 0.5 AMBIENT TEMPERATURE (C) 26 3.0 0.0 20 40 80 100 AMBIENT TEMPERATURE (C) 120 4653 F26 Figure26. 48V to 15VOUT Derating Curve, No Heat Sink 60 80 100 120 4653 F24 3.0 2.5 2.0 1.5 1.0 OLFM 200LFM 400LFM 0.5 60 40 Figure24. 48V to 5VOUT Derating Curve, with BGA Heat Sink Figure23. 24V to 5VOUT Derating Curve, with BGA Heat Sink 3.5 OLFM 200LFM 400LFM 20 AMBIENT TEMPERATURE (C) 3.5 1.0 4653 F21 OLFM 200LFM 400LFM 4653 F23 3.5 1.5 120 1.5 4.0 2.0 100 2.0 4.0 2.5 80 2.5 4.0 3.0 60 3.0 0.5 60 40 Figure21. 48V to 5VOUT Derating Curve, No Heat Sink 4.0 2.0 20 AMBIENT TEMPERATURE (C) 4.0 2.5 OLFM 200LFM 400LFM 4653 F20 Figure20. 24V to 5VOUT Derating Curve, No Heat Sink 3.0 See Table1 for fSW and REXTVCC. 0.5 AMBIENT TEMPERATURE (C) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) 20 4653 F19 Figure19. 12V to 5VOUT Derating Curve, No Heat Sink MAXIMUM LOAD CURRENT (A) OLFM 200LFM 400LFM 0.5 60 MAXIMUM LOAD CURRENT (A) 4.0 MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) APPLICATIONS INFORMATION--DERATING CURVES 0.0 20 40 60 80 100 AMBIENT TEMPERATURE (C) 120 4653 F27 Figure27. 48V to 24VOUT Derating Curve, No Heat Sink Rev. A For more information www.analog.com LTM4653 4.0 4.0 3.5 3.5 3.5 3.0 2.5 2.0 1.5 1.0 OLFM 200LFM 400LFM 0.5 0.0 20 40 3.0 2.5 2.0 1.5 1.0 OLFM 200LFM 400LFM 0.5 60 80 100 AMBIENT TEMPERATURE (C) 120 0.0 20 40 See Table1 for fSW and REXTVCC. 3.0 2.5 2.0 1.5 1.0 OLFM 200LFM 400LFM 0.5 60 80 100 AMBIENT TEMPERATURE (C) 4653 F28 Figure28. 24V to 15VOUT Derating Curve, with BGA Heat Sink MAXIMUM LOAD CURRENT (A) 4.0 MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) APPLICATIONS INFORMATION--DERATING CURVES 120 4653 F29 Figure29. 48V to 15VOUT Derating Curve, with BGA Heat Sink 0.0 20 40 60 80 100 AMBIENT TEMPERATURE (C) 120 4653 F30 Figure30. 48V to 24VOUT Derating Curve, with BGA Heat Sink APPLICATIONS INFORMATION Safety Considerations The LTM4653 does not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect the unit from catastrophicfailure. The fuse or circuit breaker, if used, should be selected to limit the current to the regulator in case of a MT MOSFET fault. If MT fails, the system's input supply will source very large currents to VOUT through MT. This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be used as a secondary fault protector in this situation. The LTM4653 does feature overcurrent and overtemperature protection. Layout Checklist/Example The high integration of LTM4653 makes the PCB board layout straightforward. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. * Place high frequency ceramic input and output capacitors next to the VIN, VD, PGND and VOUT pins to minimize high frequency noise. * Place a dedicated power ground layer underneath the LTM4653. * To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. * Do not put vias directly on pads, unless they are capped or plated over. * Use a separate SGND copper plane for components connected to signal pins. Connect SGND to PGND directly under the module. * For parallel module applications, connect the VOUT, VOSNS, RUN, ISETa, COMPa and PGOOD pins together as shown in Figure34. * Bring out test points on the signal pins for monitoring. Figure31 gives a good example of the recommended LTM4653 layout. * Use large PCB copper areas for high current paths, including VIN, PGND and VOUT. Doing so helps to minimize the PCB conduction loss and thermal stress. Rev. A For more information www.analog.com 27 LTM4653 APPLICATIONS INFORMATION GND VIN GND VOUT 4653 F31 Figure31. Recommend PCB Layout, Package Top View TYPICAL APPLICATIONS VIN 48V CINH 4.7F CD 4.7F VIN NC SW SVIN LOAD VD SGND RUN GND LTM4653 INTVCC VINREG CTH 10nF RTH 499 COMPa COMPb fSET ISETa PGDFB PGOOD TEMP+ TEMP- EXTVCC IMONa ISETb IMONb COUTH 10F x2 INTVCC PGND CLKIN INTVCC 24VOUT, UP TO 4A VOUT VOSNS RPGDFB 196k RPGDPUP 100k REXTVCC 100 0.1F D+ 470pF D- CEXTVCC 1F VCC VREF LTC2997 GND VPTAT 4mV/K 4653 F32 RfSET 90.9k RISET 481k OPTIONAL ANALOG OUTPUT TEMPERATURE INDICATOR Figure32. 4A, 24V Output DC/DC Module Regulator 28 Rev. A For more information www.analog.com LTM4653 TYPICAL APPLICATIONS RUN 5V/DIV VOUT 10V/DIV PGOOD 5V/DIV 4653 F33 1ms/DIV Figure33. Start-Up Waveforms at 48VIN, Figure32 Circuit IOUT1 VIN 48V CINH 4.7F CD 4.7F NC VIN SW SVIN U1 LTM4653 INTVCC COMPa RSET 66.5k OUT1 SET OUT2 GND MOD RPGDFB1 INTVCC1 196k RPGDPUP 100k PGOOD REXTVCC 100 TEMP+ TEMP- COMPb V+ PGND PGDFB PGOOD EXTVCC VINREG fSET 24VOUT UP TO 8A SGND CLKIN LTC6908-1 COUT 22F x2 LOAD VD RUN GND INTVCC1 VOUT VOSNS CEXTVCC 1F IMONa ISETa ISETb NC SW IMONb RfSET1 90.9k ANALOG OUTPUT CURRENT INDICATOR VIMON = 0.125 * (IOUT1 + IOUT2) IOUT2 0.1F CINH 4.7F VIN SVIN VD CD 4.7F SGND RUN GND CLKIN PGND U2 LTM4653 INTVCC PGDFB PGOOD VINREG CTH 10nF RTH 499 COMPb RfSET 90.9k RPGDFB2 196k REXTVCC 100 EXTVCC COMPa fSET VOUT VOSNS ISETa ISETb TEMP+ TEMP- IMONa IMONb RISET 240k CEXTVCC 1F 4653 F34 Figure34. 24V Output at Up to 8A from 48V Input, 2-Phase Parallel with Analog Output Current Indicator Rev. A For more information www.analog.com 29 LTM4653 TYPICAL APPLICATIONS MODULE OUTPUT CURRENT (A) 5 4 3 2 1 0 -1 U1 U2 0 1 2 3 4 5 6 TOTAL OUTPUT CURRENT (A) 7 8 4653 F35 Figure35. Current Sharing Performance of LTM4653s in Figure34 Circuit RUN 5V/DIV VOUT 5V/DIV VOUT- 5V/DIV PGOOD 5V/DIV 2ms/DIV 4653 F36 Figure36. Concurrent 12V Supply, Output Voltage Start-Up Waveforms, Figure37 Circuit 30 Rev. A For more information www.analog.com LTM4653 PACKAGE PHOTOGRAPH PACKAGE DESCRIPTION Table8. LTM4653 Component BGA Pinout PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 VIN B1 CLKIN C1 IMONb D1 PGOOD E1 COMPb F1 ISETb A2 VIN B2 NC C2 IMONa D2 PGDFB E2 COMPa F2 ISETa A3 VIN B3 VIN C3 SVIN D3 VINREG E3 fSET F3 EXTVCC A4 VD B4 VD C4 VD D4 GND E4 SGND F4 RUN A5 PGND B5 PGND C5 PGND D5 PGND E5 PGND F5 PGND A6 NC B6 NC C6 NC D6 NC E6 NC F6 NC A7 NC B7 NC C7 NC D7 NC E7 NC F7 NC PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 VOSNS H1 VOSNS J1 TEMP+ K1 VOUT L1 VOUT G2 SGND H2 SGND J2 TEMP- K2 VOUT L2 VOUT G3 INTVCC H3 PGND J3 PGND K3 VOUT L3 VOUT G4 PGND H4 SW J4 PGND K4 PGND L4 PGND G5 PGND H5 PGND J5 PGND K5 PGND L5 PGND K6 NC L6 NC K7 NC L7 NC G6 NC H6 NC J6 TEMP+ G7 NC H7 NC J7 TEMP- Rev. A For more information www.analog.com 31 0.630 0.025 O 77x SUGGESTED PCB LAYOUT TOP VIEW 2.540 PACKAGE TOP VIEW 1.270 4 0.3175 0.000 0.3175 PIN "A1" CORNER E 1.270 aaa Z 2.540 Y For more information www.analog.com 6.350 5.080 3.810 2.540 1.270 0.000 1.270 2.540 3.810 5.080 6.350 D X aaa Z SYMBOL A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee b1 DETAIL A NOM 5.01 0.60 4.41 0.75 0.63 15.00 9.00 1.27 12.70 7.62 0.41 4.00 BALL DIMENSION PAD DIMENSION BALL HT NOTES DETAIL B PACKAGE SIDE VIEW MAX 5.21 0.70 4.51 0.90 0.66 DIMENSIONS A A2 SUBSTRATE THK 0.46 MOLD CAP HT 4.05 0.15 0.10 0.20 0.30 0.15 TOTAL NUMBER OF BALLS: 77 0.36 3.95 MIN 4.81 0.50 4.31 0.60 0.60 H1 SUBSTRATE A1 ddd M Z X Y eee M Z DETAIL B H2 MOLD CAP ccc Z Ob (77 PLACES) // bbb Z (Reference LTC DWG# 05-08-1826 Rev O) Z 32 Z BGA Package 77-Lead (15.00mm x 9.00mm x 5.01mm) F e 7 5 4 3 2 1 DETAIL A PACKAGE BOTTOM VIEW 6 G L K J H G F E D C B A PIN 1 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 4 TRAY PIN 1 BEVEL COMPONENT PIN "A1" 6 ! BGA 77 0417 REV O PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX Module PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG Module PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY 5. PRIMARY DATUM -Z- IS SEATING PLANE BALL DESIGNATION PER JESD MS-028 AND JEP95 3 2. ALL DIMENSIONS ARE IN MILLIMETERS 6 SEE NOTES NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 b 3 SEE NOTES LTM4653 PACKAGE DESCRIPTION Rev. A 3.810 3.810 LTM4653 REVISION HISTORY REV DATE DESCRIPTION A 02/20 Added Input Disconnect/Input Short Considerations section Corrected resistor value to 100k from 100 PAGE NUMBER 17 29, 34 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No licenseFor is granted implication www.analog.com or otherwise under any patent or patent rights of Analog Devices. more by information 33 LTM4653 TYPICAL APPLICATION IOUT VIN 15V TO 46V CINH1 4.7F RA 105k CD1 4.7F VIN NC GND SGND PGND U1 LTM4653 RPGDFB1 INTVCC1 95.3k RPGDPUP 100k PGDFB PGOOD EXTVCC REXTVCC1 TEMP+ 49.9 C EXTVCC1 TEMP- 1F IMONa INTVCC VINREG RTH 499 COMPa COMPb fSET ISETa CINOUT 4.7F CDGND 4.7F VIN NC IMONb PGOOD ANALOG OUTPUT CURRENT INDICATOR, VIMON = 0.25 * IOUT RISET1 240k SW SVIN PGOOD GNDSNS GND VD PGND U2 LTM4651 CD2 4.7F RB 10k ISETb CSS 10nF RfSET1 124k CINH2 4.7F COUTH 22F x2 LOAD VD CLKIN CTH 10nF VOUT 12V UP TO 4A VOUT VOSNS SVIN RUN INTVCC1 SW RUN CLKIN INTVCC fSET VOUT- SVOUT- PGDFB VINREG COMPa COMPb D1* LOAD COUT2 22F RPGDFB2 95.3k REXTVCC2 49.9 EXTVCC TEMP+ RTRACK 10k TEMP- ISETa ISETb RfSET2 124k VOUT- -12V UP TO 3.25A CEXTVCC2 1F RISET2 240k||10k *D1: CENTRAL SEMI P/N CMMSH1-40L 4653 F37 Figure37. Concurrent 12V Supply. See Figure36 for Output Voltage Start-Up Waveforms RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4651 EN55022B Compliant, 58VIN, 24W Inverting-Output Module Regulator 3.6V VIN 58V, -26.5V VOUT -0.5V, IOUT 4A. 15mm x 9mm x 5.01mm BGA LTM8045 SEPIC or Inverting Module DC/DC Converter 2.8V VIN 18V, 2.5V VOUT 15V. IOUT(DC) 700mA. 6.25mm x 11.25mm x 4.92mm BGA LTM8049 Dual, SEPIC and/or Inverting Module DC/DC Converter 2.6V VIN 20V, 2.5V VOUT 24V. IOUT(DC) 1A/Channel. 9mm x 15mm x 2.42mm BGA LTM8071 60V, 5A Step-Down Module Regulator 3.6V VIN 60V, 0.97V VOUT 15V, 9mm x11.25mm x 3.32mm BGA LTM8073 60V, 3A Step-Down Module Regulator 3.4V VIN 60V, 0.8V VOUT 15V. 6.25mm x 9mm x 3.32mm BGA LTM8064 58V, 6A CVCC Step-Down Module Regulator 6V VIN 58V, 1.2V VOUT 36V. 11.9mm x 16mm x 4.92mm BGA LTM4613 EN55022B Compliant, 36V, 8A Module Regulator 5V VIN 36V, 3.3V VOUT 15V. 15mm x 15mm x 4.32mm LGA, and 15mm x 15mm x 4.92mm BGA 34 Rev. A 02/20 www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2018-2020