Low Cost, Dual, High Current Output
Line Driver with Shutdown
ADA4311-1
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
High speed
−3 dB bandwidth: 310 MHz, G = +5, RLOAD = 50 Ω
Slew rate: 1050 V/μs, RLOAD = 50 Ω
Wide output swing
20.6 V p-p differential, RLOAD of 100 Ω from 12 V supply
High output current
Low distortion
−98 dBc typical at 1 MHz, VOUT = 2 V p-p, G = +5, RLOAD = 100 Ω
−72 dBc typical at 10 MHz, VOUT = 2 V p-p, G = +5, RLOAD = 100 Ω
Power management and shutdown
Control inputs CMOS level compatible
Shutdown quiescent current: 1 mA/amplifier
Selectable quiescent current: 1 mA to 11.8 mA/amplifier
APPLICATIONS
Home networking line drivers
Twisted pair line drivers
Power line communications (PLC)
Video line drivers
ARB line drivers
I/Q channel amplifiers
PIN CONFIGURATION
NC = NO CONNECT
+V
S1
NC
2
OUT A
3
–IN A
4
+IN A
5
OUT B
10
–IN B
9
+IN B
8
PD1
7
PD0
6
A
DA4311-1
06940-001
Figure 1. Thermally Enhanced, 10-Lead MINI_SO_EP
TYPICAL APPLICATION
V
MID
*
ADA4311-1
ADA4311-1
1/2
1/2
*V
MID =
V
CC –
GND
2
06940-002
Figure 2. Typical PLC Driver Application
GENERAL DESCRIPTION
The ADA4311-1 is comprised of two high speed, current
feedback operational amplifiers. The high output current, high
bandwidth, and fast slew rate make it an excellent choice for
broadband applications requiring high linearity performance
while driving low impedance loads.
The ADA4311-1 incorporates a power management function
that provides shutdown capabilities and the ability to optimize
the quiescent current of the amplifiers. The CMOS-compatible,
power-down control pins (PD1 and PD0) enable the ADA4311-1
to operate in four different modes: full power, medium power,
low power, and complete power-down. In power-down mode, the
quiescent current drops to only 1.0 mA/amplifier, while the outputs
go to a high impedance state.
The ADA4311-1 is available in a thermally enhanced, 10-lead
MSOP with an exposed paddle for improved thermal conduction.
The ADA4311-1 is rated to work in the extended industrial
temperature range of −40°C to +85°C.
ADA4311-1
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
Typical Application........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Application Information................................................................ 11
Feedback Resistor Selection...................................................... 11
Power Control Modes of Operation ........................................ 11
Exposed Thermal Pad Connections ........................................ 11
Powerline Application ............................................................... 11
Board Layout............................................................................... 12
Power Supply Bypassing ............................................................ 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
8/07—Revision 0: Initial Version
ADA4311-1
Rev. 0 | Page 3 of 16
SPECIFICATIONS
VS = 12 V, RF = 499 Ω (@ TA = 25°C, G = +5, RL = 100 Ω to VS/2), unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VOUT = 0.1 V p-p, PD1 = 0, PD0 = 0, RLOAD = 50 Ω 310 MHz
V
OUT = 0.1 V p-p, PD1 = 0, PD0 = 1, RLOAD = 50 Ω 220 MHz
V
OUT = 0.1 V p-p, PD1 = 1, PD0 = 0, RLOAD = 50 Ω 140 MHz
Full Power Bandwidth VOUT = 10.2 V p-p, PD1 = 0, PD0 = 0, RLOAD = 50 Ω 12.9 MHz
Slew Rate VOUT = 2 V p-p, PD1 = 0, PD0 = 0 1050 V/μs
V
OUT = 2 V p-p, PD1 = 0, PD0 = 1 1050 V/μs
V
OUT = 2 V p-p, PD1 = 1, PD0 = 0 1000 V/μs
NOISE/DISTORTION PERFORMANCE
Differential Distortion (Worst
Harmonic)
fC = 1 MHz, VOUT = 2 V p-p
PD1 = 0, PD0 = 0 −98 dBc
PD1 = 0, PD0 = 1 −95 dBc
PD1 = 1, PD0 = 0 −86 dBc
f
C = 10 MHz, VOUT = 2 V p-p
PD1 = 0, PD0 = 0 −72 dBc
PD1 = 0, PD0 = 1 −63 dBc
PD1 = 1, PD0 = 0 −52 dBc
f
C = 20 MHz, VOUT = 2 V p-p
PD1 = 0, PD0 = 0 −56 dBc
PD1 = 0, PD0 = 1 −49 dBc
PD1 = 1, PD0 = 0 −43 dBc
Input Voltage Noise f = 100 kHz 2.4 nV/√Hz
Input Current Noise f = 100 kHz 17 pA/√Hz
DC PERFORMANCE
Input Offset Voltage −3 +1 +3 mV
Input Bias Current
Noninverting Input −9 −2 +3 μA
Inverting Input −4 +4.5 +16 μA
Open-Loop Transimpedance RLOAD = 50 Ω 4 14 MΩ
R
LOAD = 100 Ω 15 35 MΩ
Common-Mode Rejection 57 62 dB
INPUT CHARACTERISTICS
Input Resistance +IN, f < 100 kHz 500 kΩ
OUTPUT CHARACTERISTICS
Single-Ended, +Swing RLOAD = 50 Ω 11 11.1 VP
Single-Ended, −Swing RLOAD = 50 Ω 0.9 1 VP
Single-Ended, +Swing RLOAD = 100 Ω 11 11.1 VP
Single-Ended, −Swing RLOAD = 100 Ω 0.8 0.9 VP
Differential Swing RLOAD = 100 Ω 20.2 20.6 V p-p
POWER SUPPLY
Single Supply 12 V
Supply Current PD1 = 0, PD0 = 0 10.5 11.8 13 mA/amp
PD1 = 0, PD0 = 1 7 7.9 9 mA/amp
PD1 = 1, PD0 = 0 4.3 5.2 6.3 mA/amp
PD1 = 1, PD0 = 1 0.9 1.3 mA/amp
ADA4311-1
Rev. 0 | Page 4 of 16
Parameter Test Conditions/Comments Min Typ Max Unit
POWER-DOWN PINS
PD1, PD0 Threshold Referenced to GND 1.5 V
High Level Input Voltage, VIH 2 5 V
Low Level Input Voltage, VIL 0 0.8 V
PD1, PD0 = 0 Pin Bias Current PD1 or PD0 = 0 V −1.5 −0.2 +1.5 μA
PD1, PD0 = 1 Pin Bias Current PD1 or PD0 = 3 V 40 63 80 μA
Enable/Disable Time 130/116 ns
Power Supply Rejection Ratio −63 −70 dB
ADA4311-1
Rev. 0 | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage 13.6 V
Power Dissipation (TJMAX − TA)/θJA
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
Thermal resistance (θJA) is specified for the worst-case conditions,
that is, θJA is specified for device soldered in circuit board for
surface-mount packages.
Table 3.
Package Type θJA Unit
10-Lead MINI_SO_EP 44 °C/W
Maximum Power Dissipation
The maximum safe power dissipation for the ADA4311-1 is
limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the amplifiers. Exceeding a junction temperature of
150°C for an extended period can result in changes in silicon
devices, potentially causing degradation or loss of functionality.
Figure 3 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the 10-lead
MINI_SO_EP (44°C/W) on a JEDEC standard 4-layer board.
θJA values are approximations.
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (W)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–35 –15 5 25 45 65 85
MINI_SO_EP-10
06940-003
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ADA4311-1
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
+V
S1
NC
2
OUT A
3
–IN A
4
+IN A
5
OUT B
10
–IN B
9
+IN B
8
PD1
7
PD0
6
A
DA4311-1
06940-004
Figure 4. Pin Configuration
Table 4. Pin Function Description
Pin No. Mnemonic Description
1 +VSPositive Power Supply Input.
2 NC No Connection.
3 OUT A Amplifier A Output.
4 −IN A Amplifier A Inverting Input.
5 +IN A Amplifier A Noninverting Input.
6 PD0 Power Dissipation Control.
7 PD1 Power Dissipation Control.
8 +IN B Amplifier B Noninverting Input.
9 −IN B Amplifier B Inverting Input.
10 OUT B Amplifier B Output.
11 (Exposed Paddle) GND Ground (Electrical Connection Required).
ADA4311-1
Rev. 0 | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
–18
–15
–12
–9
–6
–3
0
3
6
9
1 10 100 1000
G = +5
G = +10
G = +20
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
VOUT = 100mV p-p
RL = 50
PD1, PD0 = 0, 0
06940-005
Figure 5. Small Signal Frequency Response for Various Closed-Loop Gains
1 10 100 1000
–24
–21
–18
–15
–12
–9
–6
–3
0
3
6
9
FREQUENCY (MHz)
GAIN (dB)
V
OUT
= 100mV p-p
R
L
= 50
G = +5 PD1, PD0 = 0, 0
PD1, PD0 = 0, 1
PD1, PD0 = 1, 0
06940-006
Figure 6. Small Signal Frequency Response for Various Modes
OUTPUT (V)
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20 G = +5
R
L
= 50
10ns/DIV
06940-010
Figure 7. Small Signal Transient Response
–120
–50
FREQUENCY (MHz)
HARMONIC DISTORTION (dBc)
–130
–100
–90
–80
–70
–60
–
40
0.1 110
–110
100
V
OUT
= 2V p-p
R
L
= 100
G = +5
PD1, PD0 = 0, 0
PD1, PD0 = 0, 1
PD1, PD0 = 1, 0
HD2
HD3
06940-008
Figure 8. Differential Harmonic Distortion vs. Frequency
06940-021
OUTPUT VOLTAGE (V p-p)
HARMONIC DISTORTION (dBc)
–120
–110
–100
–90
–80
–70
–
60
0.1 1 10
HD2
HD3
f = 5MHz
R
L
= 100
G = +5
Figure 9. Differential Harmonic Distortion vs. Output Voltage
06940-022
LOAD RESISTANCE ()
HARMONIC DISTORTION (dBc)
10 100 1000
–110
–100
–90
–80
–70
–60
–50
–
40
HD2
HD3
V
OUT
= 2V p-p
f = 5MHz
G = +5
Figure 10. Differential Harmonic Distortion vs. Load Resistance
ADA4311-1
Rev. 0 | Page 8 of 16
FREQUENCY (Hz)
TRANSIMPEDANCE ()
PHASE (Degrees)
100 1k 10k 100k 1M 10M 100M 1G
–270
–225
–180
–135
–90
–45
0
R
L
= 100
06940-007
100
1k
10k
100k
1M
10M
100M
MAGNITUDE
PHASE
Figure 11. Open-Loop Transimpedance and Phase vs. Frequency
COMMON-MODE REJECTION (dB)
–70
–50
–40
–30
–20
0
–60
–10
FREQUENCY (MHz)
0.01 0.1 1 10 100 1000
PD1, PD0 = 0, 0
R
L
= 100
0
6940-011
Figure 12. Common-Mode Rejection vs. Frequency
–70
–50
–40
–30
–
10
–60
–20
+PSR
FREQUENCY (MHz)
POWER SUPPLY REJECTION (dB)
0.01 0.1 1 10 100 1000
PD1, PD0 = 0, 0
R
L
= 100
06940-012
Figure 13. Power Supply Rejection vs. Frequency
FREQUENCY (MHz)
OUTPUT IMPEDANCE ()
0.01
0.1
1
10
100
1000
0.01 0.1 1 10 100 1000
PD1, PD0 = 0, 0
0
6940-013
Figure 14. Closed-Loop Output Impedance vs. Frequency
06940-015
FREQUENCY (MHz)
OUTPUT IMPEDANCE ()
1
10
100
1k
10k
100k
1M
0.01 0.1 1 10 100 1000
PD1, PD0 = 1, 1
Figure 15. Output Impedance vs. Frequency (Disabled)
0
6940-009
FREQUENCY (Hz)
VOLTAGE NOISE (nV/ Hz)
1
10
100
10 100 1k 10k 100k 1M 10M 100M 1G
Figure 16. Voltage Noise vs. Frequency
ADA4311-1
Rev. 0 | Page 9 of 16
FREQUENCY (MHz)
FEEDTHROUGH (dB)
–100
–80
–60
–40
–
20
101 100 1000
PD1, PD0 = 1, 1
06940-014
Figure 17. Feedthrough vs. Frequency
06940-016
VOLTAGE (V)
8
VOUT
0
1
2
3
4
5
6
7
V
PD1
, V
PD0
TIME (1s/DIV)
0123456
Figure 18. Power-Down Turn On/Turn Off
FREQUENCY (Hz)
–100
–80
–60
–40
0
CROSSTALK (dB)
–20
0.1 1 10 100 1000
06940-017
Figure 19. Crosstalk vs. Frequency
06940-020
LOAD ()
V
OUT
(p-p)
6
7
8
9
10
11
12
30 100 1000
Figure 20. Single-Ended Output Swing vs. Load
ADA4311-1
Rev. 0 | Page 10 of 16
THEORY OF OPERATION
The ADA4311-1 is a dual-current feedback amplifier with high
output current capability. With a current feedback amplifier, the
current into the inverting input is the feedback signal, and the
open-loop behavior is that of a transimpedance, dVO/dIIN or TZ.
The open-loop transimpedance is analogous to the open-loop
voltage gain of a voltage feedback amplifier. Figure 21 shows a
simplified model of a current feedback amplifier. Because RIN is
proportional to 1/gm, the equivalent voltage gain is TZ × gm,
where gm is the transconductance of the input stage. Basic
analysis of the follower with gain circuit yields
()
()
FIN
Z
Z
IN
OUT
RRGsT
sT
G
V
V
+×+
×=
where:
G
F
R
R
G+= 1
50
1≈=
m
IN g
R
Because G × RIN << RF for low gains, a current feedback amplifier
has relatively constant bandwidth vs. gain, the 3 dB point being
set when |TZ| = RF.
For a real amplifier, there are additional poles that contribute
excess phase, and there is a value for RF below which the amplifier
is unstable. Tolerance for peaking and desired flatness determines
the optimum RF in each application.
R
F
V
OUT
R
G
R
N
V
IN
R
IN
I
IN
T
Z
0
6940-018
Figure 21. Simplified Block Diagram
ADA4311-1
Rev. 0 | Page 11 of 16
APPLICATION INFORMATION
FEEDBACK RESISTOR SELECTION
The feedback resistor has a direct impact on the closed-loop
bandwidth and stability of the current feedback op amp.
Reducing the resistance below the recommended value can
make the amplifier response peak and even become unstable.
Increasing the size of the feedback resistor beyond the recom-
mended value reduces the closed-loop bandwidth. Table 5
provides a convenient reference for quickly determining the
feedback and gain resistor values, and the corresponding
bandwidth, for common gain configurations. The recommended
feedback resistor value for the ADA4311-1 is 499 Ω.
Table 5. Recommended Values and Frequency Performance1
Gain RF (Ω) RG (Ω) −3 dB SS BW (MHz)
+5 499 124 310
+5 1 k 250 220
+10 499 55.4 175
+20 499 26.1 84
1 Conditions: VS = ±12 V, TA = 25°C, RL = 50 Ω, PD1, PD0 = 0, 0.
POWER CONTROL MODES OF OPERATION
The ADA4311-1 features four power modes: full power, ¾
power, ½ power, and shutdown. The power modes are controlled
by two logic pins, PD0 and PD1. The power-down control pins
are compatible with standard 3 V and 5 V CMOS logic. Table 6
shows the various power modes and associated logic states. In
the power-down mode, the output of the amplifier goes into a
high impedance state.
Table 6. Power Modes
PD1 PD0 Power Mode
Total Supply
Current (mA)
Output
Impedance
Low Low Full Power 23.6 Low
Low High ¾ Power 15.8 Low
High Low ½ Power 10.4 Low
High High Power-Down 1.8 High
EXPOSED THERMAL PAD CONNECTIONS
The exposed thermal pad on the 10-lead MSOP is both the
reference for the PD pins and the only electrical connection for
the negative supply voltage. Therefore, in the 10-lead MSOP,
the ADA4311-1 can only be used on a single supply. The exposed
thermal pad must be connected to ground. Failure to do so
renders the part inoperable.
A requirement for this package is that the thermal pad be
connected to a solid plane with low thermal resistance, ensuring
adequate heat transfer away from the die and into the board.
POWERLINE APPLICATION
Applications (that is, powerline AV modems) requiring greater
than 10 dBm peak power should consider using an external
line driver, such as the ADA4311-1. Figure 22 shows an example
interface between the TxDAC® output and the ADA4311-1 biased
for single-supply operation. The peak-to-peak differential
output voltage swing of the TxDAC should be limited to
2 V p-p, with the gain of the ADA4311-1 configured to realize
the additional voltage gain required by the application. A low-
pass filter should be considered to filter the DAC images
inherent in the signal reconstruction process. In addition, dc
blocking capacitors are required to level-shift the output signal
of the TxDAC to the common-mode level of the ADA4311-1
(that is, VMID = VCC − GND/2).
0.1µF
R
SET
REFIO
IOUTP+
IOUTP–
0dB TO –7.5dB
OPTIONAL
LCLPF
V
MID
TxDISABLE
ADA4311-1
ADA4311-1
1/2
1/2
REFADJ
TxDAC
06940-019
Figure 22. TxDAC Output Directly via Center-Tap Transformer
ADA4311-1
Rev. 0 | Page 12 of 16
BOARD LAYOUT
As is the case with all high speed applications, careful attention
to printed circuit board (PCB) layout details prevents associated
board parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the
board to provide a low impedance return path. Removing the
ground plane on all layers from the area near the input and
output pins reduces stray capacitance, particularly in the area of
the inverting inputs. Signal lines connecting the feedback and
gain resistors should be as short as possible to minimize the
inductance and stray capacitance associated with these traces.
Termination resistors and loads should be located as close as
possible to their respective inputs and outputs. Input and
output traces should be kept as far apart as possible to minimize
coupling (crosstalk) though the board. Wherever there are
complementary signals, a symmetrical layout should be provided
to the extent possible to maximize balanced performance.
When running differential signals over a long distance, the
traces on the PCB should be close. Doing this reduces the
radiated energy and makes the circuit less susceptible to RF
interference. Adherence to stripline design techniques for long
signal traces (greater than about 1 inch) is recommended.
For more information on high speed board layout, see A
Practical Guide to High-Speed Printed-Circuit-Board Layout.
POWER SUPPLY BYPASSING
The ADA4311-1 operates on supplies from 6 V to 12 V. The
ADA4311-1 circuit should be powered with a well-regulated
power supply. Careful attention must be paid to decoupling the
power supply. High quality capacitors with low equivalent series
resistance (ESR), such as multilayer ceramic capacitors (MLCCs),
should be used to minimize supply voltage ripple and power
dissipation. In addition, 0.1 µF MLCC decoupling capacitors
should be located no more than ⅛-inch away from each of the
power supply pins. A large, usually tantalum, 10 µF capacitor is
required to provide good decoupling for lower frequency signals
and to supply current for fast, large signal changes at the
ADA4311-1 outputs. Bypassing capacitors should be laid out
in such a manner as to keep return currents away from the
inputs of the amplifiers, which minimizes any voltage drops that
can develop due to ground currents flowing through the ground
plane. A large ground plane also provides a low impedance path
for the return currents.
ADA4311-1
Rev. 0 | Page 13 of 16
OUTLINE DIMENSIONS
*COMPLIANT TO JEDEC STANDARDS MO-187-BA-T
EXCEPT FOR EXPOSED PAD DIMENSIONS.
073007-B
0.70
0.55
0.40
8°
0°
0.94
0.86
0.78
SEATING
PLANE
1.10 MAX
0.15
0.10
0.05
0.30
0.23
0.15
5.05
4.90
4.75
*2.27
2.17
2.07
*1.83
1.73
1.63
3.10
3.00
2.90
3.10
3.00
2.90
10 6
5
1
0.50 BSC 0.50 BSC
PIN 1
INDICATOR
C
OPLANARITY
0.10
0.23
0.18
0.13
TOP
VIEW
BOTTOM VIEW
EXPOSED
PAD
Figure 23. 10-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP]
(RH-10-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description
Package
Option Branding
ADA4311-1ARHZ1−40°C to +85°C 10-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] RH-10-1 1A
ADA4311-1ARHZ-RL1−40°C to +85°C 10-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] RH-10-1 1A
ADA4311-1ARHZ-R71−40°C to +85°C 10-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] RH-10-1 1A
1 Z = RoHS Compliant Part.
ADA4311-1
Rev. 0 | Page 14 of 16
NOTES
ADA4311-1
Rev. 0 | Page 15 of 16
NOTES
ADA4311-1
Rev. 0 | Page 16 of 16
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06940-0-8/07(0)
