Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMC567 SNOSBY1C - JUNE 1999 - REVISED DECEMBER 2015 LMC567 Low-Power Tone Decoder 1 Features 3 Description * * * * * * * * * * The LMC567 device is a low-power, general-purpose LMCMOS tone decoder which is functionally similar to the industry standard LM567. The device consists of a twice frequency voltage-controlled oscillator (VCO) and quadrature dividers which establish the reference signals for phase and amplitude detectors. 1 Functionally Similar to LM567 2-V to 9-V Supply Voltage Range Low Supply Current Drain No Increase in Current With Output Activated Operates to 500-kHz Input Frequency High Oscillator Stability Ground-Referenced Input Hysteresis Added to Amplitude Comparator Out-of-Band Signals and Noise Rejected 20-mA Output Current Capability 2 Applications * * * * * * * Touch-Tone Decoding Precision Oscillators Frequency Monitoring and Control Wide-Band FSK Demodulation Ultrasonic Controls Carrier Current Remote Controls Communications Paging Decoders The phase detector and VCO form a phase-locked loop (PLL) which locks to an input signal frequency which is within the control range of the VCO. When the PLL is locked and the input signal amplitude exceeds an internally pre-set threshold, a switch to ground is activated on the output pin. External components set up the oscillator to run at twice the input frequency and determine the phase and amplitude filter time constants. Device Information PART NUMBER LMC567 PACKAGE SOIC (8) (1) BODY SIZE (NOM) 4.90 mm x 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Diagram 1 8 Amplitude Detector 2 7 /2 3 /2 6 Phase Detector VCO 4 5 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMC567 SNOSBY1C - JUNE 1999 - REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 4 4 4 4 6 Absolute Maximum Ratings ...................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. 8 Parameter Measurement Information .................. 7 9 Detailed Description .............................................. 8 8.1 Test Circuit ................................................................ 7 9.1 Overview ................................................................... 8 9.2 Functional Block Diagram ......................................... 8 9.3 Feature Description................................................... 8 9.4 Device Functional Modes.......................................... 9 10 Application and Implementation........................ 10 10.1 Application Information.......................................... 10 10.2 Typical Application ............................................... 10 11 Power Supply Recommendations ..................... 12 12 Layout................................................................... 12 12.1 Layout Guidelines ................................................. 12 12.2 Layout Example ................................................... 12 13 Device and Documentation Support ................. 13 13.1 13.2 13.3 13.4 13.5 Device Support .................................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 13 13 13 13 13 14 Mechanical, Packaging, and Orderable Information ........................................................... 13 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (April 2013) to Revision C * Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1 Changes from Revision A (April 2013) to Revision B * 2 Page Page Changed layout of National Data Sheet to TI format ............................................................................................................. 9 Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC567 LMC567 www.ti.com SNOSBY1C - JUNE 1999 - REVISED DECEMBER 2015 5 Device Comparison Table DEVICE NUMBER DESCRIPTION LMC567 Low power tone decoder General-purpose tone decoder with half oscillator frequency than LMC567 LM567, LM567C 6 Pin Configuration and Functions D Package 8-Pin SOIC Top View 1 8 2 7 3 6 4 5 Pin Functions PIN NAME NO. TYPE (1) DESCRIPTION GND 7 PWR IN 3 I Device input LF_CAP 2 I Loop filter capacitor terminal OF_CAP 1 I Output filter capacitor terminal OUT 8 O Device output T_CAP 5 I Timing capacitor connection terminal T_RES 6 I Timing resistor connection terminal VCC 4 PWR (1) Ground connection Voltage supply connection I = input, O = output, PWR = power Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC567 3 LMC567 SNOSBY1C - JUNE 1999 - REVISED DECEMBER 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT Input voltage IN 2 Vp-p Supply voltage VCC 10 Output voltage OUT 13 V Output current OUT 30 mA Package dissipation V 500 mW Operating temperature, TA -25 125 C Storage temperature, Tstg -55 150 C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. 7.2 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC Supply voltage FIN Input frequency TA Operating temperature MIN MAX 2 9 UNIT V 1 500 Hz -25 125 C 7.3 Thermal Information LMC567 THERMAL METRIC (1) D (SOIC) UNIT 8 PINS RJA Junction-to-ambient thermal resistance 111.8 C/W RJC(top) Junction-to-case (top) thermal resistance 59.2 C/W RJB Junction-to-board thermal resistance 52.2 C/W JT Junction-to-top characterization parameter 13.5 C/W JB Junction-to-board characterization parameter 51.7 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.4 Electrical Characteristics Test Circuit, TA = 25C, Vs = 5 V, RtCt #2, Sw. 1 Pos. 0, and no input, unless otherwise noted. PARAMETER I4 Power supply current TEST CONDITIONS RtCt #1, quiescent or activated MIN TYP MAX UNIT 0.5 0.8 mAdc 0.8 1.3 Vs = 2 V 0.3 Vs = 5 V Vs = 9 V V3 Input D.C. bias 0 R3 Input resistance 40 I8 Output leakage 1 f0 Center frequency, Fosc / 2 Vs = 2 V RtCt #2, measure oscillator Frequency and divide by 2 4 Center frequency shift with supply f0 |9 V f0 |2 V 7 f0 |5 V Vs = 5 V u 100 Submit Documentation Feedback k 100 nAdc 113 kHz 2 %/V 98 92 Vs = V f0 mVdc 103 105 1 (1) Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC567 LMC567 www.ti.com SNOSBY1C - JUNE 1999 - REVISED DECEMBER 2015 Electrical Characteristics (continued) Test Circuit, TA = 25C, Vs = 5 V, RtCt #2, Sw. 1 Pos. 0, and no input, unless otherwise noted. PARAMETER Vin Input threshold TEST CONDITIONS Set input frequency equal to f0 measured above. Increase input level until pin 8 goes low. Vin Input hysteresis Starting at input threshold, decrease input level until pin 8 goes high. V8 Output sat voltage Input level > threshold Choose RL for specified I8. Largest detection L.D.B.W. bandwidth BW Bandwidth skew MIN TYP MAX Vs = 2 V 11 20 27 Vs = 5 V 17 30 45 mVrms Vs = 9 V 45 1.5 I8 = 2 mA 0.06 I8 = 20 mA 0.7 Measure Fosc with Sw. 1 in Vs = 2 V Pos. 0, 1, and 2; Vs = 5 V FOSC |P2 FOSC |P1 L.D.B.W u 100 FOSC |P0 (2) Vs = 9 V Skew FOSC |P2 FOSC |P1 * 1 u 100 2 F | OSC P0 (c) UNIT mVrms 0.15 7% 11% 15% 11% 14% 17% Vdc 15% 0% 1.0% (3) fmax Highest center frequency RtCt #3 Measure oscillator frequency and divide by 2. Vin Input threshold at fmax Set input frequency equal to fmax measured above. Increase input level until pin 8 goes low. 700 kHz 35 mVrms Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC567 5 LMC567 SNOSBY1C - JUNE 1999 - REVISED DECEMBER 2015 www.ti.com 7.5 Typical Characteristics 6 Figure 1. Supply Current vs Operating Frequency Figure 2. Bandwidth vs Input Signal Level Figure 3. Largest Detection Bandwidth vs Temperature Figure 4. Bandwidth as a Function of C2 Figure 5. Frequency Drift With Temperature Figure 6. Frequency Drift With Temperature Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC567 LMC567 www.ti.com SNOSBY1C - JUNE 1999 - REVISED DECEMBER 2015 8 Parameter Measurement Information All parameters are measured according to the conditions described in Specifications. 8.1 Test Circuit Figure 7 was used to make the measurements of the typical characteristics of the LMC567. Figure 7. LMC567 Test Circuit Table 1. Rt and Ct Values for the Test Circuit RtCt Rt Ct #1 100k 300 pF #2 10k 300 pF #3 5.1k 62 pF Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC567 7 LMC567 SNOSBY1C - JUNE 1999 - REVISED DECEMBER 2015 www.ti.com 9 Detailed Description 9.1 Overview The LMC567C is a low-power, general-purpose tone decoder with similar functionality to the industry standard LM567. The device requires external components set up the internal oscillator to run at twice the input frequency and determine the required filter constants. Internal VCO and Phase detector form a Phase-locked loop which locks to an input signal frequency that is established by external timing components. When PLL is locked, a switch to ground is activated in the output of the device. 9.2 Functional Block Diagram 1 8 Amplitude Detector 2 7 /2 3 /2 6 Phase Detector VCO 4 5 9.3 Feature Description 9.3.1 Oscillator The voltage-controlled oscillator (VCO) on the LMC567 must be set up to run at twice the frequency of the input signal tone to be decoded. The center frequency of the VCO is set by timing resistor Rt and timing capacitor Ct connected to pins 5 and 6 of the IC. The center frequency as a function of Rt and Ct is given by Equation 4: FOSC # 1 Hz 1.4 RtCt (4) Because this causes an input tone of half Fosc to be decoded by Equation 5, FINPUT # 1 Hz 2.8 RtCt (5) Equation 5 is accurate at low frequencies; however, above 50 kHz (Fosc = 100 kHz), internal delays cause the actual frequency to be lower than predicted. The choice of Rt and Ct is a tradeoff between supply current and practical capacitor values. An additional supply current component is introduced in Equation 6 due to Rt being switched to Vs every half cycle to charge Ct: Is due to Rt = Vs/(4Rt) (6) Thus the supply current can be minimized by keeping Rt as large as possible (see Figure 1). However, the desired frequency dictates an RtCt product such that increasing Rt requires a smaller Ct. Below Ct = 100 pF, circuit board stray capacitances begin to play a role in determining the oscillation frequency which ultimately limits the minimum Ct. To allow for IC and component value tolerances, the oscillator timing components requires a trim. This is generally accomplished by using a variable resistor as part of Rt, although Ct could also be padded. The amount of initial frequency variation due to the LMC567 itself is given in the Electrical Characteristics; the total trim range must also accommodate the tolerances of Rt and Ct. 8 Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC567 LMC567 www.ti.com SNOSBY1C - JUNE 1999 - REVISED DECEMBER 2015 Feature Description (continued) 9.3.2 Input The input pin 3 is internally ground-referenced with a nominal 40-k resistor. Signals which are already centered on 0 V may be directly coupled to pin 3; however, any DC potential must be isolated through a coupling capacitor. Inputs of multiple LMC567 devices can be paralleled without individual DC isolation. 9.3.3 Loop Filter Pin 2 is the combined output of the phase detector and control input of the VCO for the phase-locked loop (PLL). Capacitor C2 in conjunction with the nominal 80-k pin 2 internal resistance forms the loop filter. For small values of C2, the PLL has a fast acquisition time and the pull-in range is set by the built in VCO frequency stops, which also determines the largest detection bandwidth (LDBW). Increasing C2 results in improved noise immunity at the expense of acquisition time, and the pull-in range begins to become narrower than the LDBW (see Figure 4). However, the maximum hold-in range always equal the LDBW. 9.3.4 Output Filter Pin 1 is the output of a negative-going amplitude detector which has a nominal 0 signal output of 7/9 Vs. When the PLL is locked to the input, an increase in signal level causes the detector output to move negative. When pin 1 reaches 2/3 Vs, the output is activated (see Output). Capacitor C1 in conjunction with the nominal 40-k pin 1 internal resistance forms the output filter. The size of C1 is a tradeoff between slew rate and carrier ripple at the output comparator. Low values of C1 produce the least delay between the input and output for tone burst applications, while larger values of C1 improve noise immunity. Pin 1 also provides a means for shifting the input threshold higher or lower by connecting an external resistor to supply or ground. However, reducing the threshold using this technique increases sensitivity to pin 1 carrier ripple and also results in more part to part threshold variation. 9.3.5 Output The output at pin 8 is an N-channel FET switch to ground which is activated when the PLL is locked and the input tone is of sufficient amplitude to cause pin 1 to fall below 2/3 Vs. Apart from the obvious current component due to the external pin 8 load resistor, no additional supply current is required to activate the switch. The ONresistance of the switch is inversely proportional to supply; thus the sat voltage for a given output current increases at lower supplies. 9.4 Device Functional Modes 9.4.1 Operation as LM567 The LMC567 low power tone decoder can be operated at supply voltages of 2 V to 9 V and at input frequencies ranging from 1 Hz up to 500 kHz. The LMC567 can be directly substituted in most LM567 applications with the following provisions: 1. Oscillator timing capacitor Ct must be halved to double the oscillator frequency relative to the input frequency (see Oscillator). 2. Filter capacitors C1 and C2 must be reduced by a factor of 8 to maintain the same filter time constants. 3. The output current demanded of pin 8 must be limited to the specified capability of the LMC567. Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC567 9 LMC567 SNOSBY1C - JUNE 1999 - REVISED DECEMBER 2015 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information These typical connection diagrams highlight the required external components and system level connections for proper operation of the device in several popular use cases. Any design variation can be supported by TI through schematic and layout reviews. Visit support.ti.com for additional design assistance. Also, join the audio amplifier discussion forum at e2e.ti.com. 10.2 Typical Application Figure 8. LMC567 Application Schematic 10.2.1 Design Requirements For this design example, use the parameters listed in Table 2. Table 2. Design Parameters DESIGN PARAMETER 10 EXAMPLE VALUE Supply voltage 2 V to 9 V Input voltage 20 mVRMS to (VCC + 0.5) Input frequency 1 Hz to 500 KHz Output current maximum 30 mA Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC567 LMC567 www.ti.com SNOSBY1C - JUNE 1999 - REVISED DECEMBER 2015 10.2.2 Detailed Design Procedure 10.2.2.1 Timing Components As VCO frequency (FOSC) runs at twice the frequency of the input tone, the desired input detection frequency can be defined by Equation 7: FINPUT 2 FOSC (7) The central frequency of the oscillator is set by timing capacitor and resistor. The timing capacitor value (CT) must be set in order to calculate the timing resistor value (RT). This is given by Equation 8: 1 RT | 1.4 FOSCCT (8) So, in order to found the required component values to set the detection frequency Equation 9: 1 RT | 2.8 FINPUT CT (9) This approximation is valid with lower frequencies; considerations must be taken when using higher frequencies. More information on this can be found in Oscillator. 10.2.2.2 Bandwidth Detection bandwidth is represented as a percentage of FOSC. It can be approximated as a function of FOSC x C2 following the behavior indicated in Figure 4. More information on this can be found in Loop Filter. 10.2.2.3 Output Filter The size of the output filter capacitor C1 is a tradeoff between slew rate and carrier ripple. More information on this can be found in Output Filter. 10.2.2.4 Supply Decoupling The decoupling of supply pin 4 becomes more critical at high supply voltages with high operating frequencies, requiring C4 to be placed as close as possible to pin 4. 10.2.3 Application Curve SPACE IN (PIN 3) OUT (PIN 8) Figure 9. Frequency Detection Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC567 11 LMC567 SNOSBY1C - JUNE 1999 - REVISED DECEMBER 2015 www.ti.com 11 Power Supply Recommendations The LMC567 is designed to operate with an input power supply range between 2 V and 9 V. Therefore, the output voltage range of power supply must be within this range and well regulated. The current capability of upper power must not exceed the maximum current limit of the power switch. Because the operating frequency of the device could be very high for some applications, the decoupling of power supply becomes critical, so is required to place a proper decoupling capacitor as close as possible to VCC pin. Low equivalent-seriesresistance (ESR) ceramic capacitor, typically 0.1 F, is typically used. This capacitor must be placed within 2 mm of the supply pin. 12 Layout 12.1 Layout Guidelines The VCC pin of the LM567 must be decoupled to ground plane as the device can work with high switching speeds. The decoupling capacitor must be placed as close as possible to the device. Traces length for the timing and external filter components must be kept at minimum in order to avoid any possible interference from other close traces. 12.2 Layout Example Short traces to external components C1 C2 CIN IN Vcc 0.1F Vcc 1 8 2 7 RL OUT LMC567 3 6 RT 4 5 Decoupling capacitor placed as close as possible to the device CT Ground Plane that gives low impedance return path Top Layer Ground Plane Top Layer Traces Pad to Top Layer Ground Plane Connection to Power Supply Figure 10. LMC567 Board Layout 12 Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC567 LMC567 www.ti.com SNOSBY1C - JUNE 1999 - REVISED DECEMBER 2015 13 Device and Documentation Support 13.1 Device Support 13.1.1 Development Support For development support, see the following: support.ti.com 13.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC567 13 PACKAGE OPTION ADDENDUM www.ti.com 27-Oct-2016 PACKAGING INFORMATION Orderable Device Status (1) LMC567CMX/NOPB ACTIVE Package Type Package Pins Package Drawing Qty SOIC D 8 2500 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM Op Temp (C) Device Marking (4/5) -25 to 100 LMC 567CM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 27-Oct-2016 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-May-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device LMC567CMX/NOPB Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 5.4 2.0 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 4-May-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC567CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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